JP2017054842A - Wiring board, semiconductor device, and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board, a semiconductor device, and a semiconductor package having a high cooling performance.SOLUTION: A wiring board according to an embodiment comprises: an insulation substrate configured by a ceramic material, and on whose one principal surface a wiring layer for mounting components is formed; and a base plate arranged at the other side of the insulation substrate, and that has a projection protruded outward from an outer peripheral edge of the insulation substrate, and that has a thickness larger than that of the insulation substrate.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a wiring board, a semiconductor device, and a semiconductor package.

  The semiconductor package includes, for example, a semiconductor circuit substrate and a sealing member that seals the semiconductor circuit substrate. The semiconductor circuit board is, for example, a conductive base material including an insulating base material such as ceramic or resin and a metal foil fixed on both sides or one side of the insulating base material, and a semiconductor fixed to one conductive base material with solder or the like. A circuit including a chip and the like.

  For example, a power semiconductor chip such as an insulated gate bipolar transistor (IGBT) generates heat by switching. Therefore, the semiconductor circuit board is cooled by being fixed in contact with the heat sink via a diffusion plate that diffuses heat.

  In recent years, when power semiconductors switch at high speeds under high voltage and large current, the amount of heat generated is increased by switching at high speeds under large currents. Therefore, heat dissipation and cooling performance are improved for semiconductor circuits including power semiconductors. Is desired.

  In addition, with the practical application of hybrid cars and electric vehicles, power semiconductor packages are desired to be reduced in size, weight, and cost.

JP 2002-329938 A JP 2002-315358 A

The cooling performance of the semiconductor circuit board depends on the thermal resistance (package thermal resistance) between the semiconductor element and the cooling surface and the thermal resistance (heat transfer) between the cooling surface and the cooling medium.
For example, if the configuration interposed between the semiconductor element and the cooling surface is reduced, the package thermal resistance can be reduced, which is advantageous for improving the cooling performance. In a general semiconductor module cooling method, a module heat sink and a heat sink are adhered and bonded together by silicon grease or the like. In such a configuration, since there are many intervening materials and there is a material having a large thermal resistance called silicon grease, it is difficult to obtain high cooling performance.

  An object of an embodiment of the present invention is to provide a wiring board having a high cooling performance and a semiconductor package including the wiring board.

  The wiring board according to the embodiment is made of a ceramic material, and is disposed on the other side of the insulating substrate, the insulating substrate having a wiring layer formed on one main surface, and protrudes outward from the outer peripheral edge of the insulating substrate. And a base plate having a protruding portion.

1 is a perspective view illustrating a configuration of a semiconductor package according to a first embodiment. II-II sectional drawing of FIG. 1 which shows the structure of the semiconductor package. The bottom view of the semiconductor package. The perspective view of the semiconductor package. Explanatory drawing which shows the manufacturing process of the semiconductor package. The top view which shows the structure of the semiconductor package which concerns on 2nd Embodiment. Sectional drawing which shows the structure of the semiconductor package. The perspective view which shows the structure of the semiconductor package which concerns on 3rd Embodiment. The perspective view which shows the structure of the semiconductor package which concerns on 4th Embodiment. Sectional drawing which shows the structure of the semiconductor package which concerns on the same embodiment.

[First embodiment]
Hereinafter, the semiconductor device 1 including the wiring substrate 10 and the wiring substrate 10 according to the embodiment will be described with reference to FIGS. 1 to 4. In each figure, the structure is appropriately enlarged, reduced, or omitted for explanation.

  FIG. 1 is a perspective view of a semiconductor package 100 including the wiring substrate 10 and the semiconductor device 1 according to the first embodiment as viewed from above, and FIG. 2 is a cross-sectional view taken along the line II-II in FIG. 3 is a bottom view of the semiconductor package 100, and FIG. 4 is a perspective view of the semiconductor package 100 as viewed from below. In FIG. 1, the sealing structure 30 is omitted. FIG. 5 is an explanatory view showing a manufacturing process of the semiconductor package 100.

  As shown in FIGS. 1 to 4, the semiconductor device 1 includes a wiring board 10, a semiconductor chip 20 as a semiconductor element provided on the wiring board 10, a sealing structure portion 30 that seals the semiconductor chip 20, It has.

  The semiconductor package 100 of the present embodiment includes the semiconductor device 1 and a cooling structure 40 provided on the other side of the wiring substrate 10 of the semiconductor device 1.

  The wiring substrate 10 is an insulating substrate 11 serving as a substrate portion, a wiring pattern 12 formed on one main surface of the insulating substrate 11 on which components are mounted, and a base plate provided on the other main surface side of the insulating substrate 11. 13.

  The insulating substrate 11 is formed of a ceramic material, and is configured in a rectangular plate shape having a first surface 11a on one side on which the semiconductor chip 20 is mounted and a second surface 11b on the other side.

The insulating substrate 11 is formed by sintering a powdery material into a sheet. In the present embodiment, the insulating substrate 11 is formed of a ceramic sheet such as silicon nitride (SiN) or alumina (Al ₂ O ₃ ). A plurality of sheets can be stacked and formed. For example, silicon nitride has high strength and a low coefficient of linear expansion, so that it is difficult to deform even in a high temperature environment. Silicon nitride has a higher thermal conductivity than alumina or resin. The insulating substrate 11 is made of ceramic. For this reason, it is hard to corrode, and since it has high hardness and strength, it has sufficient resistance to an increase in the flow rate of the cooling medium and a boiling phenomenon.

  For example, the thickness of the insulating substrate 11, that is, the dimension in the Z direction is configured to be about 0.3 mm to 1 mm. In this embodiment, it is 0.5 mm or less.

  The wiring pattern 12 is a wiring layer formed by patterning a conductive material such as copper or aluminum used for circuit wiring. For example, in the wiring pattern 12, for example, a copper pad is directly bonded to the insulating substrate 11 by so-called DBC bonding, or a copper pad is welded on the insulating substrate 11.

  The wiring pattern 12 also functions as a heat spreader for transferring heat generated in the semiconductor chip 20 in the direction of the substrate surface of the insulating substrate 11, that is, in the direction orthogonal to the stacking direction of the semiconductor chip 20 and the insulating substrate 11. .

  As shown in FIG. 1, in the embodiment, the wiring pattern 12 includes an emitter wiring pattern 12a for connecting an emitter electrode and a collector wiring pattern 12b for connecting a collector electrode. A semiconductor chip 20 is disposed on the collector wiring pattern 12b. A bonding wire 16 connected to the lead terminal 15 that is a signal pin is bonded to the edge portion on the one end side in the Y direction of the collector wiring pattern 12b. A collector terminal 18b is connected to the edge of the collector wiring pattern 12b on the other end side in the Y direction.

  The lead terminal 15, the emitter bridge 17, the emitter terminal 18a, and the collector terminal 18b are connecting members configured in a strip shape from a conductive material, and electrically join a plurality of electrodes and terminals.

  For example, in the manufacturing process, the lead terminal 15, the emitter terminal 18 a, and the collector terminal 18 b are disposed as a part of the lead frame 50 disposed on the outer periphery of the wiring substrate 10. The lead frame 50 includes an emitter terminal 18 a, a collector terminal 18 b, a lead terminal 15, and a rectangular frame portion that is disposed outward from the outer periphery of the base plate 13. The lead frame 50 is cut in the manufacturing process and removed leaving the portions of the lead terminal 15 and the terminals 18a and 18b.

  An emitter bridge 17 bonded to the upper surface of the semiconductor chip 20 is connected to the emitter wiring pattern 12a. That is, the emitter bridge 17 includes the upper surface of the IGBT chip 21 and the FRD (Fast Recovery Diode) chip 22 that are arranged side by side, and the upper surface of the emitter wiring pattern 12a that is adjacent to the FRD chip 22 in the Y direction. It is configured in an L shape corresponding to the region.

  Junction sites formed respectively at the two ends and the bent sites of the emitter bridge 17 are bonded to the emitter electrode disposed on the upper surfaces of the IGBT chip 21 and the FRD chip 22 and the emitter wiring pattern 12a, respectively.

  An emitter terminal 18a is connected to the emitter wiring pattern 12a.

  The base plate 13 is formed of, for example, a metal material that is a conductive material, and is configured in a plate shape having a first surface 13a bonded to the insulating substrate 11 and a second surface 13b facing the first surface 13a. Has been. For example, in the embodiment, the base plate 13 is made of a copper plate.

  For example, the thickness of the base plate 13, that is, the dimension in the Z direction is configured to be about 3 mm to 5 mm. The base plate 13 is directly bonded to the insulating substrate 11 by DBC (Direct Plated Copper) bonding.

  The base plate 13 includes a protruding portion 13 c that protrudes outward from the outer peripheral edge of the insulating substrate 11 at the outer peripheral portion thereof. That is, the base plate 13 has the insulating substrate 11 disposed at the central portion on the upper surface thereof. The outer peripheral portion of the base plate 13 protrudes outward from the outer peripheral edge of the insulating substrate 11 and constitutes a protruding portion 13 c that is exposed without being covered by the insulating substrate 11.

  In the outer peripheral portion of the base plate 13, a notch portion 13 d that is recessed toward the center in the surface direction of the insulating substrate is formed at a predetermined location. The notch 13d is disposed at a portion where various terminals such as a signal connection lead terminal 15, an emitter terminal 18a, and a collector terminal 18b are arranged, and these terminals 15, 18a, 18b are prevented from contacting the base plate 13. doing.

  In FIG. 1, the base plate 13 is formed with notches 13d at two locations on both end edges in the Y direction, and protruding portions 13c are formed at the remaining portions.

  The protruding portion 13c serves as a holding allowance for the mold 60 during molding, for example. Further, the protruding portion 13c functions as an attachment portion for fixing the cooling structure portion 40.

  Specifically, a mounting hole 13e penetrating in the Z direction, which is the thickness direction, is formed in the protruding portion 13c. The cooling structure 40 is attached to the base plate 13 by a fastening member 19 such as a screw in the attachment hole 13e.

  The semiconductor chip 20 is bonded to the wiring pattern 12 on the wiring substrate 10 by, for example, solder. As the semiconductor chip 20, various semiconductor chips 20 used in electric circuits such as IGBTs, FETs (Field-Effect Transistors), GTOs (Gate Turn-Off Thyristors), semiconductor switches such as transistors, and diodes can be used.

  For example, in the present embodiment, as the semiconductor chip 20, the IGBT chip 21 and the FRD chip 22, which are switching elements, are arranged side by side in the X direction on the insulating substrate. The outer shape of the IGBT chip 21 and the FRD chip 22 is configured in a rectangular plate shape, for example.

  The IGBT chip 21 and the FRD chip 22 have a collector electrode and an emitter electrode as electrodes on both main surfaces, respectively. For example, in the embodiment, an emitter electrode is formed on the upper surface and a collector electrode is formed on the lower surface.

  The emitter electrode of the FRD chip 22 and the emitter electrode of the IGBT chip 21 are electrically connected to the emitter wiring pattern 12 via the emitter bridge 17.

  The collector electrode is bonded to the collector wiring pattern 12 formed on the lower side of the chip.

  The cooling structure 40 includes a cooling jacket 41 disposed to face the base plate 13 and a rectifying guide 42 formed integrally with the second surface 13 b of the base plate 13.

  The rectifying guide 42 includes a plurality of rectifying units 42 a configured on the second surface 13 b of the base plate 13. The rectifying unit 42a is configured in various shapes such as a fin shape, a column shape, a pin shape, and a wall shape.

  The cooling jacket 41 includes a case portion 41a having a rectangular recess that forms a flow path that is a gap through which the cooling medium passes, and a plurality of attachment portions provided on the outer periphery of the case portion 41a. 41b, an inflow port 41c and an outflow port 41d for communicating the inside and outside of the case portion 41a.

  A ring groove in which the O-ring 43 is disposed is formed on the outer peripheral edge of the cooling jacket 41. The cooling jacket 41 is covered with the case portion 41a on the second surface 13b of the base plate 13 so as to cover the rectifying portion 42a, and the attachment portion 41b is attached to the base plate 13 with a fastening member such as a screw. A predetermined flow path that is sealed by an O-ring 43 disposed in the ring groove 41e is formed on the second surface 13b side.

  The sealing structure portion 30 is an insulator formed of, for example, a resin. The sealing structure unit 30 covers and seals the semiconductor chip 20 and the wiring pattern 12 of the semiconductor package 100 by, for example, molding or potting. The sealing structure portion 30 seals at least the semiconductor chip 20 to prevent the semiconductor chip 20 from coming into contact with water or air, and avoids deterioration of the semiconductor chip 20. The sealing structure unit 30 may be disposed so as to expose a part of the wiring pattern 12.

  In the semiconductor device 1 and the semiconductor package 100, the cooling structure 40 is cooled by the coolant flowing through the flow path formed in the cooling structure 40. The refrigerant flowing through the flow path is, for example, water, ethylene glycol or the like.

  A manufacturing process of the semiconductor package 100 configured as described above will be described.

  First, the wiring board 10 manufactured by the DBC process is prepared. The manufacturing process of the wiring board 10 includes, for example, directly bonding the insulating substrate 11 formed in a plate shape from a ceramic material on the base plate 13 formed in a predetermined shape having the fin-like rectifying portion 42a on the lower surface by DBC bonding. Then, the wiring pattern 12 is formed on the insulating substrate 11.

  The wiring substrate 10 may be manufactured by forming the wiring pattern 12 on the ceramic insulating substrate 11 in advance and then bonding the insulating substrate 11 directly on the base plate 13. Alternatively, the conductive substrate may be used as a pattern forming step. May be joined directly.

  The wiring board 10 is placed on a jig for reflow conveyance. The conveyance jig includes a guide pin for positioning inserted into a hole provided in the base plate 13, for example.

  The wiring board 10 is placed on a jig for reflow conveyance. The conveyance jig includes a guide pin for positioning inserted into a hole provided in the base plate 13, for example.

  Next, a solder sheet, a semiconductor chip 20 and a lead frame 50 are placed on a predetermined position on the wiring pattern 12 of the wiring substrate 10, and the solder sheet and the emitter bridge are further stacked, and then hydrogen / formic acid reflow is performed. Put in the furnace and solder.

  Then, by holding the lead frame 50 using a jig for fixing the frame and bonding a Cu ribbon or a bonding wire for electrode connection, the gate signal, temperature sense, and emitter sense of the plurality of semiconductor chips 20, The lead terminals 15 are connected to each other.

  Next, the wiring substrate 10 on which the semiconductor chip 20 is mounted is removed from the conveying jig together with the lead frame 50, and is set in a mold 60 of a molding apparatus, for example, as shown in FIG. A stop structure 30 is formed. The mold 60 includes a plurality of molds 61 and 62 that seal the outer periphery of the wiring board 10. An internal space having a predetermined shape corresponding to the shape of the sealing structure portion 30 formed on the wiring substrate 10 and the wiring substrate 10 is formed between the plurality of molds. In addition, the plurality of molds constituting the mold 60 are arranged such that terminals 15, 18 a, and 18 b are arranged on the outer edge portion of the mold 60 with the mold 60 closed, and the periphery thereof is sealed. have. The wiring board 10 is set on a jig 63 for avoiding mechanical interference with the rectifying unit 42a. The wiring substrate 10 is disposed in the inner space of the mold 60, and the mold 60 is closed and molded, whereby the sealing structure 30 is formed with a part of the terminals 15, 18a, and 18b exposed. The chip 20 and the wiring pattern 12 are covered and sealed. The sealing structure 30 may be formed by other processes such as a potting process in addition to the molding process.

  When forming the sealing structure portion 30, positioning and processing can be easily performed by pressing the protruding portion 13c with the processing device jig. Then, unnecessary portions on the outer periphery of the lead frame 50 are cut with a mold, whereby the semiconductor device 1 is completed.

  Further, the cooling jacket 41 is placed on the second surface 13 b of the base plate 13, the fastening member 19 is fastened at the mounting portion 41 b, and the semiconductor package 100 is completed by fixing to the base plate 13.

  In the semiconductor device 1 and the semiconductor package 100 configured as described above, the solder, the wiring pattern 12, and the insulation are provided between the semiconductor chip 20 that is a heat source and the cooling surface of the cooling structure 40 that contacts the cooling medium. A substrate 11 and a base plate 13 are provided.

  Therefore, the heat generated in the semiconductor chip 20 is transferred to the wiring pattern 12 and further transferred to the cooling structure 40 via the insulating substrate 11 and the base plate 13 and cooled by the cooling medium. Further, when a lead is connected to the wiring pattern 12, heat is generated at a connection portion between the lead and the wiring pattern 12 due to a current flowing from the lead to the wiring pattern 12. The heat generated between the lead and the wiring pattern 12 is transferred to the wiring pattern 12 and further transferred to the cooling structure 40 via the insulating substrate 11 and cooled by the cooling medium.

  The semiconductor device 1 and the semiconductor package 100 of the present embodiment are configured to include the semiconductor chip 20, the wiring pattern 12, and the sealing structure portion 30 on the wiring substrate 10, so that a joint portion by grease or solder can be provided. It is possible to realize a reduction in size, weight, and price as compared with a configuration having a large number. Further, since the insulating substrate 11 is made of a ceramic material, a high breakdown voltage can be secured, and performance suitable for mounting a power semiconductor element can be secured.

Further, the base plate 13 joined to the insulating substrate 11 is provided with a protruding portion 13c projecting outward from the insulating substrate 11, so that the assemblability is good. That is, it is possible to provide a holding allowance in the molding process, and it is possible to provide an attachment function with other structures, so that the assemblability is good.
[Second Embodiment]
Hereinafter, the wiring board 10, the semiconductor device 2, and the semiconductor package 200 according to the second embodiment will be described with reference to FIGS. FIG. 6 is a plan view showing the configuration of the semiconductor package 200 according to the second embodiment, and FIG. 7 is a side view showing the configuration of the semiconductor package 200. FIG. 8 is a perspective view showing a part of the semiconductor package 200.

  The semiconductor package 200 according to the second embodiment has a so-called 6-in-1 structure. The insulating substrate 11 is provided on one base plate 13, and the chip includes the IGBT chip 21 and the FRD chip 22 on the insulating substrate 11. There are multiple sets. Since the rest is the same as that of the semiconductor package 100 according to the first embodiment, in the semiconductor package 200 according to the second embodiment, the same components as those of the semiconductor package 100 are denoted by the same reference numerals, and redundant description is omitted. To do.

  As shown in FIGS. 6 to 8, the semiconductor package 200 of this embodiment includes the semiconductor device 2 and a cooling structure 40 provided on the other side of the wiring substrate 10 of the semiconductor device 2.

  The wiring substrate 10 of the semiconductor device 2 is provided with an insulating substrate 11 on a base plate 13.

  The base plate 13 has a rectangular shape that is long in one direction along the X axis in the drawing, and includes a plurality of cutout portions 13d on the outer periphery thereof.

  The insulating substrate 11 is formed in a rectangular shape that is smaller than the base plate 13 and long in one direction along the X axis in the figure. A plurality of collector wiring patterns 12 b and a plurality of emitter wiring patterns 12 a are formed on the insulating substrate 11 as the wiring patterns 12.

  In the present embodiment, six sets of chips each including two IGBT chips 21 and two FRD chips 22 are arranged side by side in the X direction. Two adjacent chip sets each correspond to one phase, and three-phase groups corresponding to the U phase, the V phase, and the W phase are arranged side by side in the X direction.

  The wiring pattern 12 has six rectangular collector wiring patterns 12b arranged in the X direction. Two IGBT chips 21 and two FRD chips 22 are arranged on each collector wiring pattern 12b. The collector wiring pattern 12b is continuously formed along the X direction on one end side in the Y direction of the semiconductor device 2, and is formed at a predetermined position between adjacent rectangular collector wiring patterns 12b.

  A bonding wire 16 connected to the lead terminal 15 is bonded to the edge of the collector wiring pattern 12b on the one end side in the Y direction. A collector terminal 18b connected to the lead frame 50 is connected to the edge of the collector wiring pattern 12b on the other end side in the Y direction.

  The six emitter wiring patterns 12a are formed side by side on a side of the rectangular collector wiring pattern 12b on which the semiconductor chip 20 is mounted and at predetermined positions on one end side in the Y direction of each collector wiring pattern 12b. An emitter bridge 17 bonded to the upper surface of the semiconductor chip 20 is connected to the emitter wiring pattern 12a.

  A pair of emitter terminals 18a connected to the lead frame 50 are connected to the emitter wiring pattern 12a.

  The lead terminal 15, the emitter bridge 17, the emitter terminal 18a, and the collector terminal 18b are formed in a strip shape or a pin shape from a conductive material, and electrically connect a plurality of electrodes and terminals.

  A lead frame 50 is provided on the outer periphery of the wiring board 10. The lead frame 50 is a rectangular frame that surrounds the wiring substrate 10 outside the outer periphery of the base plate 13. In the lead frame 50, a lead terminal 15 extending in the Y direction toward a predetermined wiring pattern 12 disposed on the inner side is provided in a frame portion on one end side in the Y direction. In the lead frame 50, a plurality of terminals 18a and 18b extending in the X direction toward the emitter wiring pattern 12a and the collector wiring pattern 12b are provided in a frame portion on one end side in the X direction. The lead frame 50 is cut in the manufacturing process leaving the portions of the various terminals 15, 18a, 18b.

  The IGBT chip 21 and the FRD chip 22 have a collector electrode and an emitter electrode as electrodes on both main surfaces, respectively. For example, in the embodiment, an emitter electrode is formed on the upper surface and a collector electrode is formed on the lower surface.

  The emitter electrode of the FRD chip 22 and the emitter electrode of the IGBT chip 21 are electrically connected to the emitter wiring pattern 12 via the emitter bridge 17.

  The collector electrode is bonded to the collector wiring pattern 12 formed on the lower side of the chip.

  The cooling structure portion 40 includes a case portion 41a that covers the second surface 13b of the base plate 13 via a predetermined flow path. The flow path is a space through which the cooling medium passes.

  The sealing structure portion 30 is an insulator formed of, for example, a resin. The sealing structure unit 30 covers and seals the semiconductor chip 20, the wiring pattern 12, and the like of the semiconductor package by, for example, molding or potting.

  In the semiconductor device 2 and the semiconductor package 200, the cooling structure 40 is cooled by the coolant flowing through the flow path formed in the cooling structure 40. The refrigerant flowing through the flow path is, for example, water, ethylene glycol or the like.

Also in the semiconductor device 2 and the semiconductor package 200 of the present embodiment, the same effects as those of the semiconductor device 1 and the semiconductor package 100 according to the first embodiment can be obtained.
[Third Embodiment]
Hereinafter, the semiconductor device 3 and the semiconductor package 300 according to the third embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a perspective view of the semiconductor device 3 according to the third embodiment, and FIG. 10 is a cross-sectional view of the semiconductor package 300. The semiconductor device 3 according to the present embodiment relates to the first embodiment in that the semiconductor device 3 includes a block-shaped emitter bridge 117 that connects electrodes instead of the emitter bridge 17 that is formed of a strip-shaped conductive ribbon that connects emitter electrodes. Although different from the semiconductor device 1, the other points are the same as those of the semiconductor device 1. Therefore, the same reference numerals are given to the same configurations as those of the semiconductor device 1 in this embodiment, and the description thereof is omitted.

  As shown in FIGS. 9 and 10, the semiconductor device 3 includes an emitter bridge 117 that connects the emitter electrodes. The emitter bridge 117 has, for example, a thickness dimension along the Z direction of 3 mm or more and 5 mm or less, and protrudes downward from an L-shaped base portion 117a that is bent at 90 degrees when viewed from above, and both ends and bent portions of the base portion 117a. Connecting portion 117b to be integrated. That is, the emitter bridge 117 corresponds to a region including the upper surfaces of the IGBT chip 21 and the FRD chip 22 that are arranged side by side, and the upper surface of the emitter wiring pattern 12a that is adjacent to the FRD chip 22 in the Y direction. It is configured in an L shape.

  The front end surfaces of the connecting portions 117b formed at the two ends and the three bent portions are respectively the two semiconductor chips 20 arranged side by side, that is, the emitter electrodes arranged on the upper surfaces of the IGBT chip 21 and the FRD chip 22, and the emitter The wiring pattern 12a and a bonding surface to be bonded to each other are formed.

  Other configurations are the same as those of the semiconductor device 1 according to the first embodiment.

  According to the present embodiment, the emitter bridge 117 disposed on the upper surface of the semiconductor chip 20 is configured in a block shape, so that the volume of the emitter bridge 117 can be increased to function as a heat mass. For this reason, high heat dissipation performance can be secured even from the upper surface side of the semiconductor chip 20.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage.

  For example, the cooling structure 40 may be omitted. Even in that case, the same effects as those of the wiring substrate 10 and the semiconductor package of the first embodiment described above can be obtained.

  Moreover, the structure of the cooling structure 40 is not limited to the above embodiment. For example, other shapes such as a plurality of columnar portions and a plurality of wall-shaped portions may be used. Moreover, the structure of the cooling structure 40 is not limited to the above embodiment. For example, other shapes such as a plurality of columnar portions and a plurality of wall-shaped portions may be used. Further, it is also possible to define the flow path by arranging a rubber member that elastically contacts the rectifying portion 42 a formed on the wiring board 10 side on the bottom surface of the case body 42, for example.

  In the first embodiment and the second embodiment, the sealing structure unit 30 may be disposed so as to cover the semiconductor chip 20 by exposing a part of the wiring pattern 12. Even in such a case, the same effects as those of the first and second embodiments described above can be obtained. The method for fixing the wiring board 10 to the flow path jacket 41 is not limited to the above-described method.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1, 2, 3, 4 ... Semiconductor device, 10 ... Wiring board, 11 ... Insulating board, 11a ... 1st surface, 11b ... 2nd surface, 12 ... Wiring pattern, 12a ... Emitter wiring pattern, 12b ... Collector wiring Pattern, 13 ... Base plate, 13a ... First surface, 13b ... Second surface, 13c ... Projection, 13d ... Notch, 13e ... Mounting hole, 15 ... Lead terminal (connection member), 16 ... Bonding wire (connection) Member), 17 ... emitter bridge (connection member), 18a ... emitter terminal (connection member), 18b ... collector terminal (connection member), 19 ... fastening member, 20 ... semiconductor chip, 21 ... IGBT chip, 22 ... FRD chip, DESCRIPTION OF SYMBOLS 30 ... Sealing structure part, 40 ... Cooling structure part, 41 ... Cooling jacket 41 ... Rectification guide, 42a ... Rectification part, 50 ... Lead frame, 100, 200, 300 ... Conductor package 117 ... emitter bridge, 117a ... base, 117b ... connection.

Claims (7)

An insulating substrate made of a ceramic material and having a wiring layer on which a component is mounted on one main surface;
A base plate disposed on the other side of the insulating substrate, having a protruding portion protruding outward from an outer peripheral edge of the insulating substrate, and having a thickness larger than that of the insulating substrate;
A wiring board comprising: The base plate is made of a metal material and directly bonded to the insulating substrate,
2. The protruding portion according to claim 1, wherein at least a part of the base plate protrudes outward from the insulating substrate in a plane direction intersecting with a stacking direction of the insulating substrate and the base plate. Wiring board. The wiring board according to claim 1 or 2,
A semiconductor chip disposed on the one wiring layer of the insulating substrate;
A sealing structure for sealing the semiconductor chip;
A semiconductor device comprising: A plurality of semiconductor chips each having an emitter electrode and a collector electrode on both main surfaces on the wiring layer,
The wiring layer comprises an emitter wiring pattern connected to the emitter electrode and a collector wiring pattern connected to the collector electrode,
4. The semiconductor device according to claim 3, further comprising: a plurality of electrodes made of a conductive material, each of which is formed on each of the plurality of semiconductor chips, and a connection member that connects the wiring pattern of the wiring layer.   5. The semiconductor device according to claim 4, wherein the connection member for connecting electrodes formed on the upper surfaces of the plurality of semiconductor chips is formed in a block shape having a thickness dimension of 3 mm or more and 5 mm or less. A semiconductor device according to any one of claims 3 to 5;
A cooling structure provided on the other side of the base plate.   The semiconductor package according to claim 6, further comprising a flow path jacket that is disposed opposite to the other surface of the base plate, forms a flow path between the cooling structure section and the base plate, and is attached to the protruding portion. .