JP2017050380A - Semiconductor device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can ease restrictions on arrangement of semiconductor elements and respond to a request such as size change while achieving reduction in manufacturing cost.SOLUTION: A semiconductor device 1A comprises: a substrate 100 which is composed of a semiconductor material and has a principal surface 101 and a rear face 102, which face the opposite direction in a thickness direction; a semiconductor element 300 arranged on the substrate 100; a conductive layer 200 which is conducted to the semiconductor element 300 and formed on the substrate 100; and an encapsulation resin 400 which covers the semiconductor element 300. On the substrate 100, a recess 105 which dents from the principal surface 101 and pierces the substrate 100 to the rear face 102 is formed; the semiconductor element 300 is mounted on the principal surface 101; and the conductive layer 200 is formed in a range from the principal surface 101 to the rear face 102 via the recess 105.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Various types of semiconductor devices having a specific function with respect to input / output of current from the outside have been proposed. Generally, in order to fulfill the function of this semiconductor device, semiconductor elements each constituting a part of an electric circuit are incorporated. Metal leads are used for the purpose of supporting the semiconductor elements and making them conductive with each other. The number, shape and size of these leads are determined according to the function, shape and size of the semiconductor element. The semiconductor element mounted on the lead is covered with a sealing resin. The sealing resin is for protecting a part of the semiconductor element and the lead. Such a semiconductor device is used by being mounted on a circuit board of an electronic device, for example. Patent Document 1 is given as a document related to the semiconductor device.

  Patent Document 1 discloses a semiconductor device in which a Hall element as a semiconductor element is mounted on a metal lead. When the semiconductor device is mounted on a circuit board or the like, the distance between the magnet arranged outside the semiconductor device (on the opposite side of the circuit board across the semiconductor device) and the magnetosensitive surface of the Hall element is shortened. It is requested to do. Further, the distance from the circuit board to the magnet can change in accordance with the change of the mounting target. Therefore, when the distance from the circuit board to the magnet changes, it is required to change the dimension in the thickness direction of the semiconductor device so as to be suitable for the distance.

  The lead is often formed by punching using a mold, for example. The technique using a mold has an advantage that the leads can be formed efficiently and accurately. On the other hand, when the size or function required for the semiconductor device is changed, it is necessary to change the size or shape of the lead. In order to realize this, it is compelled to make a new mold. Since the mold is relatively expensive, when the semiconductor device is produced in a small amount, the cost of the semiconductor device is increased. Further, the lead can be formed into a three-dimensional shape by arbitrarily drawing, but a certain degree of restriction is imposed.

JP 2002-368304 A

  The present invention has been conceived under the circumstances described above, and is a semiconductor that can relieve restrictions on the arrangement of semiconductor elements and can respond to requests for size change while reducing manufacturing costs. The main object is to provide a device. Moreover, this invention makes it a subject to manufacture such a semiconductor device appropriately and to make it function appropriately.

  A semiconductor device provided by the first aspect of the present invention has a main surface and a back surface facing opposite to each other in the thickness direction, a substrate made of a semiconductor material, a semiconductor element disposed on the substrate, A conductive layer formed on the substrate and electrically conductive to the semiconductor element; and a sealing resin covering the semiconductor element, wherein the substrate is formed with a recess recessed from the main surface and penetrating the back surface. The semiconductor element is mounted on the main surface, and the conductive layer is formed in a range extending from the main surface to the back surface via the recess.

  In a preferred embodiment of the present invention, the recess has an inclined surface connected to the main surface and inclined with respect to the main surface, and a bottom surface connected to the inclined surface, and the substrate includes the bottom surface. To the back surface.

  In a preferred embodiment of the present invention, the inclined surfaces are spaced apart from each other across the main surface in a first direction perpendicular to the thickness direction, and each of the inclined surfaces is in the first direction. The further away from the main surface, the closer to the bottom surface.

  In a preferred embodiment of the present invention, the substrate has an outer surface that is sandwiched between the main surface and the back surface in the thickness direction and intersects the back surface.

  In a preferred embodiment of the present invention, the outer surface has a rectangular ring shape when viewed in the thickness direction.

  In a preferred embodiment of the present invention, the bottom surface is surrounded by the outer surface as viewed in the thickness direction.

  In a preferred embodiment of the present invention, the bottom surface has a rectangular ring shape and surrounds the main surface when viewed in the thickness direction.

  In a preferred embodiment of the present invention, the sealing resin covers the entirety of the main surface, the inclined surface, and the bottom surface.

  In a preferred embodiment of the present invention, the sealing resin includes a resin main surface facing the same direction as the main surface, a resin side surface positioned between the resin main surface and the outer surface of the substrate, The outer side surface and the resin side surface are flush with each other.

  In a preferred embodiment of the present invention, the dimension from the main surface to the resin main surface in the thickness direction is smaller than the dimension from the back surface to the main surface in the thickness direction.

  In a preferred embodiment of the present invention, the penetrating portion is provided with a metal filling portion that fills at least the opening on the back surface side of the penetrating portion and is filled with a metal material.

  In a preferred embodiment of the present invention, the metal filling portion is filled in the entire penetration portion.

  In a preferred embodiment of the present invention, the metal filling portion has an end surface facing in the same direction as the back surface, and the end surface is flush with the back surface.

  In preferable embodiment of this invention, the said conductive layer has a coating | coated part which covers the said end surface of the said metal filling part.

  In a preferred embodiment of the present invention, the penetrating portion has a smaller cross-sectional dimension from the main surface side toward the back surface side.

  In a preferred embodiment of the present invention, the number of the through portions is plural.

  In a preferred embodiment of the present invention, the substrate is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface.

  In a preferred embodiment of the present invention, an insulating film formed on the back surface of the substrate is further provided, and the insulating film is interposed between the substrate and the conductive layer.

  In a preferred embodiment of the present invention, the semiconductor element is a Hall element.

  A method of manufacturing a semiconductor device provided by the second aspect of the present invention includes a step of forming a recess recessed from the main surface in a substrate material having a main surface and a back surface facing opposite sides in the thickness direction, A step of forming a conductive layer on the substrate material including the recess, a step of mounting the semiconductor element on the main surface, a step of forming a sealing resin covering the semiconductor element, and a position avoiding the main surface And cutting the substrate material along the thickness direction of the substrate material.

  In a preferred embodiment of the present invention, in the step of forming the recess, the first recess having an inclined surface connected to the main surface and inclined with respect to the main surface, and a bottom surface connected to the inclined surface. And a second recess recessed from the bottom surface, and after the step of forming the sealing resin and before the step of cutting the substrate material, the substrate material is transferred from the back surface to the second recess. A step of grinding until reaching the formation portion of the recess is provided.

  In a preferred embodiment of the present invention, in the step of cutting the substrate material, the substrate material is cut at the bottom surface.

  In a preferred embodiment of the present invention, in the step of forming the recesses, a plurality of recess-unformed regions arranged at intervals in a first direction perpendicular to the thickness direction of the substrate material are arranged in the main direction. In the step of mounting as a surface and mounting the semiconductor element, the step of mounting at least one semiconductor element in each of the recess-unformed regions and cutting the substrate material in the step of cutting the substrate material is adjacent to the first direction. The substrate material is cut between the recess-unformed regions.

  In a preferred embodiment of the present invention, a plurality of the recess-unformed regions are arranged at intervals in a second direction perpendicular to both the thickness direction and the first direction, and the substrate material is In the cutting step, the substrate material is cut between the recess-unformed regions adjacent in the second direction.

  In a preferred embodiment of the present invention, in the step of forming the sealing resin, in the step of covering the whole of the main surface, the inclined surface and the bottom surface with the sealing resin and cutting the substrate material. The sealing resin is cut together with the substrate material.

  In a preferred embodiment of the present invention, the substrate material is made of a single crystal of a semiconductor material.

  In a preferred embodiment of the present invention, the semiconductor material is Si.

  In a preferred embodiment of the present invention, the main surface is a (100) surface.

  In a preferred embodiment of the present invention, in the step of forming the recess, the first recess is formed by subjecting the main surface of the substrate material to anisotropic etching, and the second recess is the bottom surface. It is formed by performing anisotropic etching on.

  Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

It is a principal part top view which shows an example of the semiconductor device which concerns on this invention. It is sectional drawing which follows the II-II line | wire of FIG. FIG. 2 is a perspective view showing a substrate of the semiconductor device of FIG. 1. FIG. 3 is a partially enlarged view of FIG. 2. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a plan view of relevant parts showing one step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a plan view of relevant parts showing one step in a method for manufacturing the semiconductor device of FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a main part cross-sectional view showing a step of the method of manufacturing the semiconductor device in FIG. 1. FIG. 3 is a plan view of relevant parts showing one step in a method for manufacturing the semiconductor device of FIG. 1.

  Hereinafter, preferred embodiments of the present invention will be specifically described with reference to the drawings.

  1 and 2 show an example of a semiconductor device according to the present invention. The semiconductor device 1A of this embodiment includes a substrate 100, a conductive layer 200, a metal filling portion 240, a semiconductor element 300, a sealing resin 400, an insulating film 500, and a back electrode pad 600. In FIG. 1, the sealing resin 400 is omitted for convenience of understanding. FIG. 2 is a cross-sectional view in the yz plane along the line II-II in FIG. FIG. 3 is a perspective view showing the substrate 100. In FIG. 3, the sealing resin 400 is indicated by an imaginary line (two-dot chain line).

  The substrate 100 is a base for the semiconductor device 1 </ b> A, and includes a base material 103 and an insulating layer 104. The substrate 100 has a main surface 101, a back surface 102, four outer surfaces 106, a recess 105, and a through portion 107. The main surface 101 and the back surface 102 are opposite to each other in the z direction (thickness direction of the substrate), and the z direction corresponds to the thickness direction of the semiconductor device 1A (substrate 100). The substrate 100 has a rectangular shape when viewed in the z direction (viewed in the thickness direction of the substrate 100). The main surface 101 is located at the center of the substrate 100 when viewed in the z direction.

  The four outer surfaces 106 are sandwiched between the main surface 101 and the back surface 102 in the z direction (the thickness direction of the substrate 100), and all are connected to the back surface 102. Of these outer faces 106, two are facing away from each other in the x direction and the other two are facing away from each other in the y direction. Both the x direction and the y direction are perpendicular to the z direction. The y direction is perpendicular to the x direction. That is, the x direction, the y direction, and the z direction are perpendicular to each other. As shown in FIG. 2, the four outer surfaces 106 form a rectangular ring shape in a plan view (viewed in the thickness direction of the substrate 100).

  The base material 103 is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a single crystal of Si. The material of the base material 103 is not limited to Si, and may be any material that can form the concave portion 105 that satisfies the intention described later. The thickness of the substrate 100 is, for example, about 250 to 400 μm.

  FIG. 3 is a perspective view showing the substrate 100. In the present embodiment, the (100) surface of the base material 103 is employed as the main surface 101. The recess 105 is recessed from the main surface 101 toward the back surface 102.

  The recess 105 surrounds the main surface 101. The recess 105 has a bottom surface 111 and four inclined surfaces 112. The depth of the recess 105 (the distance between the main surface 101 and the bottom surface 111 in the thickness direction) is, for example, about 200 to 300 μm.

  Each inclined surface 112 is connected to the main surface 101 and is inclined with respect to the main surface 101. The four inclined surfaces 112 surround the main surface 101 in a plan view (view in the thickness direction of the substrate 100) and have a substantially trapezoidal shape with a portion in contact with the main surface 101 as an upper base. Two of the four inclined surfaces 112 are separated from each other across the main surface 101 in the y direction. Each of the two inclined surfaces 112 is displaced so as to approach the bottom surface 111 as the distance from the main surface 101 increases in the y direction. The other two of the four inclined surfaces 112 are separated from each other across the main surface 101 in the x direction. The other two inclined surfaces 112 are displaced so as to approach the bottom surface 111 as the distance from the main surface 101 increases in the x direction. In the present embodiment, the inclination angle of the inclined surface 112 with respect to the xy plane is about 55 °. The point that the inclined surface 112 is substantially trapezoidal and the inclination angle is 55 ° is derived from the fact that the (100) surface is adopted as the main surface 101.

  The bottom surface 111 is connected to the inclined surface 112. The bottom surface 111 has a rectangular ring shape when viewed in the thickness direction of the substrate 100, and surrounds the main surface 101 and the four inclined surfaces 112. The bottom surface 111 is also surrounded by the four outer surfaces 106 described above in a plan view.

  The penetrating portion 107 is recessed from the concave portion 105 toward the back surface 102, and penetrates a part of the substrate 100 from the bottom surface 111 to the back surface 102.

  In the present embodiment, the number of penetrating portions 107 is plural (for example, four). In the present embodiment, two through portions 107 are provided in two portions of the bottom surface 111 of the recess 105 that are separated in the y direction across the main surface 101. The depth of the penetrating portion 107 is, for example, about 10 to 50 μm. The maximum opening dimension of the through portion 107 in the thickness direction of the substrate 100 is, for example, about 10 to 50 μm. In the present embodiment, the through portion 107 has a rectangular shape when viewed in the thickness direction. In the present embodiment, the penetrating portion 107 has a smaller cross-sectional dimension from the main surface 101 side toward the back surface 102 side in the thickness direction.

  The through portion 107 has a through portion inner surface 108. The through portion inner surface 108 is inclined with respect to the thickness direction of the substrate 100. The through portion inner surface 108 has four flat surfaces. In the present embodiment, the penetrating portion inner surface 108 is connected to the bottom surface 111 and the back surface 102. The angle of the penetration part inner surface 108 with respect to a plane (xy plane) orthogonal to the thickness direction is about 55 °. This is because the (100) plane is adopted as the main surface 101. In the present embodiment, the back surface 102 side of the penetrating portion 107 is a flat opening 109 facing the thickness direction of the substrate 100.

The insulating layer 104 is formed on the substrate 100. The insulating layer 104 covers a portion of the substrate 100 that faces from the side opposite to the back surface 102. More specifically, the insulating layer 104 covers the main surface 101, the inclined surface 112, the bottom surface 111, and the through portion inner surface 108. The thickness of the insulating layer 104 is, for example, about 0.1 to 1.0 μm. The insulating layer 104 is made of, for example, SiO ₂ . The insulating layer 104 is formed by thermal oxidation, for example.

  The insulating layer 104 has a penetrating portion inner surface insulating portion 104A. The penetrating portion inner surface insulating portion 104 </ b> A is formed on the penetrating portion inner surface 108 of the penetrating portion 107. The penetrating portion inner surface insulating portion 104 </ b> A has an end surface 104 b facing the same direction as the back surface 102. The end surface 104b is flush with the back surface 102.

  The conductive layer 200 is mounted on the semiconductor element 300 and constitutes a current path that inputs and outputs to the semiconductor element 300. The conductive layer 200 is formed on the substrate 100 and is electrically connected to the semiconductor element 300. The conductive layer 200 is formed from the main surface 101 to the back surface 102 via the concave portion 105 and the penetrating portion 107 (the inclined surface 112 and the bottom surface 111 of the concave portion 105 and the penetrating portion inner surface 108 of the penetrating portion 107). In the present embodiment, as shown in FIG. 4, the conductive layer 200 has a structure in which a seed layer 201 and a plating layer 202 are laminated.

  The seed layer 201 is a so-called underlayer for forming a desired plating layer 202. The seed layer 201 is interposed between the base material 103 and the plating layer 202. The seed layer 201 is made of, for example, Ti or Cu. The seed layer 201 is formed by sputtering, for example. The thickness of the seed layer 201 is, for example, 1 μm or less.

  The plating layer 202 is formed, for example, by electrolytic plating using the seed layer 201. The plating layer 202 is made of, for example, a layer in which Cu, Ti, Ni, Cu, or the like is laminated. The thickness of the plating layer 202 is, for example, about 3 to 10 μm. The plating layer 202 is thicker than the seed layer 201.

  The conductive layer 200 includes element placement pads 210, communication paths 220, and back side pads 230.

  The element arrangement pad 210 is formed on the main surface 101. The element arrangement pad 210 is used for mounting the semiconductor element 300 on the main surface 101. In the present embodiment, a plurality of element placement pads 210 are provided so as to correspond to the plurality of through portions 107.

  The back side pad 230 is formed on the back side 102. The back surface side pad 230 is a part that becomes a base for forming a back surface electrode pad 600 described later. In the present embodiment, a plurality of back side pads 230 are provided so as to correspond to the plurality of through portions 107. In the present embodiment, the back surface side pad 230 covers an end surface 241 of the metal filling portion 240 described later.

  The communication path 220 is mainly formed in the recess 105. The communication path 220 is electrically connected to the element arrangement pad 210 and the back surface side pad 230. In FIG. 1, the conductive layer 200 is hatched.

  The metal filling part 240 is provided in the penetrating part 107. The metal filling portion 240 is made of a metal material having excellent conductivity, such as Cu. The metal filling part 240 is filled in at least a part of the penetrating part 107. The metal filling part 240 closes at least the opening 109 of the penetrating part 107. The metal filling part 240 may be filled in the entire penetration part 107. In the present embodiment, the metal filling portion 240 covers at least a part of the portion formed on the inner surface 108 of the through portion of the communication path 220. The metal filling portion 240 has an end surface 241 that faces the same direction as the back surface 102. The end surface 241 of the metal filling part 240 is flush with the back surface 102 of the substrate 100. In the metal filling portion 240, the dimension in the thickness direction of the substrate 100 is larger than the thickness of the conductive layer 200. In FIG. 1, the metal filling portion 240 is hatched.

  The insulating film 500 is formed on the back surface 102. The insulating film 500 is interposed between the substrate 100 and the conductive layer 200. In the present embodiment, the insulating film 500 covers the entire back surface 102. Further, the insulating film 500 covers the end face 104b of the penetrating portion inner surface insulating portion 104A. The insulating film 500 is formed by lamination with, for example, an insulating material. The insulating film 500 is formed, for example, by CVD (Chemical Vapor Deposition). The insulating film 500 is made of polyimide resin or benzocyclobutene resin.

  The back electrode pad 600 is formed on the back surface 102. The back electrode pad 600 is in contact with the conductive layer 200 and is electrically connected to the semiconductor element 300. The back electrode pad 600 has a structure in which, for example, a Ni layer, a Pd layer, and an Au layer are stacked in the order closer to the substrate 100. In the present embodiment, the back electrode pad 600 has a rectangular shape. The back electrode pad 600 is used for surface mounting the semiconductor device 1A on, for example, a circuit board of an electronic device (not shown).

  The semiconductor element 300 is supported on the main surface 101 and is mounted via solder 310 using a plurality of element arrangement pads 210. In the present embodiment, the semiconductor element 300 is a Hall element. With the Hall element, the semiconductor device 1A functions as a magnetic sensor. In the present embodiment, the Hall element is a GaAs Hall element. The GaAs type Hall element has an advantage that it is excellent in the linearity of the Hall voltage with respect to a change in magnetic flux and is hardly affected by a temperature change. On the lower surface of the semiconductor element 300 shown in FIG. 2, a magnetic sensitive surface (not shown) for detecting a magnetic flux change caused by a magnet disposed outside the semiconductor device 1A is formed.

  The sealing resin 400 covers the semiconductor element 300 and fills the recess 105. More specifically, the sealing resin 400 covers the entire main surface 101, the inclined surface 112, and the bottom surface 111. The sealing resin 400 is also filled in a space where the metal filling portion 240 does not exist in the through portion 107 connected to the recess 105.

  The sealing resin 400 has a resin main surface 401 and a resin side surface 402. The resin main surface 401 faces outward in the normal direction of the main surface 101. That is, the resin main surface 401 faces the same direction as the main surface 101. The resin main surface 401 has a rectangular shape when viewed in the z direction (viewed in the thickness direction of the substrate 100). The resin main surface 401 overlaps the substrate 100 in the thickness direction view. The dimension from the main surface 101 to the resin main surface 401 in the thickness direction of the substrate 100 is smaller than the dimension from the back surface 102 to the main surface 101 in the thickness direction of the substrate 100. The resin side surface 402 surrounds the periphery of the resin main surface 401 when viewed in the thickness direction of the substrate 100. In the present embodiment, the sealing resin 400 has four resin side surfaces 402 so as to correspond to the respective sides of the resin main surface 401. Each of the four resin side surfaces 402 is located between the resin main surface 401 and the outer surface 106 of the substrate 100 in the z direction (the thickness direction of the substrate 100). The resin side surface 402 is flush with the outer side surface 106 at the corresponding position. Examples of the material of the sealing resin 400 include an epoxy resin, a phenol resin, a polyimide resin, a polybenzoxazole (PBO) resin, and a silicone resin. The sealing resin 400 may be either a translucent resin or a non-translucent resin, but in the present embodiment, a non-translucent resin is preferable.

  Next, a method for manufacturing the semiconductor device 1A will be described below with reference to FIGS. In these drawings (excluding FIGS. 7, 10, and 25), a cross section in the yz plane along the line II-II in FIG. 1 is shown.

  First, as shown in FIG. 5, a substrate material 100 'is prepared. The substrate material 100 ′ is made of a single crystal of a semiconductor material, and in the present embodiment, is made of a Si single crystal. The thickness of the substrate material 100 ′ is, for example, about 300 to 450 μm. The substrate material 100 'is sized so that a plurality of substrates 100 of the semiconductor device 1A can be obtained. That is, the subsequent manufacturing process is premised on a method of manufacturing a plurality of semiconductor devices 1A in a lump. A method of manufacturing one semiconductor device 1A may be used, but considering industrial efficiency, a method of manufacturing a plurality of semiconductor devices 1A collectively is realistic.

The substrate material 100 ′ has a main surface 101 and a back surface 102 that face opposite sides in the z direction. In the present embodiment, a plane having a crystal orientation of (100) and a (100) plane are adopted as the main surface 101. Next, the mask layer 191 made of SiO ₂ is formed by oxidizing the main surface 101, for example. The thickness of the mask layer 191 is, for example, about 0.7 to 1.0 μm.

  Next, as shown in FIG. 6, the mask layer 191 is patterned by etching. Thereby, as shown in FIG. 7, the mask layer 191 remains in a plurality of regions separated from each other. The plurality of regions have a predetermined interval in each of the y direction perpendicular to the z direction (thickness direction of the substrate material 100 ′) and the x direction perpendicular to both the z direction and the y direction. They are spaced apart and arranged in a matrix on the xy plane. The plurality of regions which are the remaining mask layer 191 are each rectangular, and are finally set according to the shape and size of the portion remaining as the main surface 101.

  Next, as shown in FIG. 8, a first recess 110 is formed. The formation of the first recess 110 is performed by anisotropic etching using, for example, KOH. KOH is an example of an alkaline etching solution that can realize good anisotropic etching for a Si single crystal. By performing this anisotropic etching, a first recess 110 having a bottom surface 111 and an inclined surface 112 is formed. The first recess 110 is a portion that later becomes the recess 105. The angle formed by the inclined surface 112 with respect to the xy plane is about 55 °.

  Next, as shown in FIG. 9, the mask layer 191 is removed. The removal of the mask layer 191 is performed by etching using, for example, HF.

  Here, as can be understood by comparing FIGS. 7 and 10, the region covered with the mask layer 191 remains as the recess-unformed region 101 ′ (main surface 101). The recess-unformed region 101 ′ is arranged at a predetermined interval in each of the x direction and the y direction. The recess-unformed region 101 ′ is surrounded by four inclined surfaces 112 when viewed in the z direction (viewed in the thickness direction of the substrate material 100 ′). The recess-unformed region 101 ′ is surrounded by the bottom surface 111 when viewed in the thickness direction.

  Next, as shown in FIG. 11, a mask layer 192 is formed. The mask layer 192 is formed by oxidizing the entire portion of the substrate material 100 ′ opposite to the back surface 102. The thickness of the mask layer 192 is, for example, about 0.7 to 1.0 μm.

  Next, as shown in FIG. 12, the mask layer 192 is patterned by etching. Thereby, an opening is formed in the mask layer 192. The shape and size of the opening are set according to the shape and size of the penetrating portion 107 to be finally obtained. The opening is rectangular, for example.

  Next, as shown in FIG. 13, the second recess 120 is formed. In order to form the second recess 120, for example, the above-described anisotropic etching using KOH is performed. By performing this etching, the second recess 120 shown in FIG. 13 is formed. The second concave portion 120 is a portion that becomes the penetrating portion 107 through a subsequent process, and has a concave inner surface 121 and a concave bottom surface 122. The second recess 120 is recessed from the bottom surface 111 of the first recess 110. The second recess 120 has a rectangular shape as viewed in the thickness direction. The concave bottom surface 122 is perpendicular to the thickness direction. The angle formed by the recess inner surface 121 with respect to the xy plane is about 55 °.

  Next, as shown in FIG. 14, the mask layer 192 is removed. The mask layer 192 is removed by etching using, for example, HF.

Next, as shown in FIG. 15, an insulating layer 104 made of, for example, SiO ₂ is formed. The insulating layer 104 is formed by oxidizing the entire portion of the substrate material 100 ′ opposite to the back surface 102. Thereby, the insulating layer 104 having a thickness of, for example, about 0.7 to 1.0 μm is obtained.

  Next, as shown in FIG. 16, a conductive layer 200 (seed layer 201 and plating layer 202) is formed. The seed layer 201 is formed, for example, by performing patterning after performing sputtering using Cu. The plating layer 202 is formed by electrolytic plating using the seed layer 201, for example. As a result, a plated layer 202 made of a layer in which, for example, Cu, Ti, Ni, Cu, or the like is laminated is obtained. The seed layer 201 and the plating layer 202 are stacked to form the conductive layer 200. The plating layer 202 has a shape corresponding to the element arrangement pad 210 and the communication path 220 described above.

  Next, as shown in FIG. 17, a metal filling portion 240 is formed. The metal filling portion 240 is formed, for example, by electroless plating a metal such as Cu on the inner surface 121 of the second recess 120.

  Next, as shown in FIG. 18, the semiconductor element 300 is mounted on the recess-unformed region 101 ′ (main surface 101) of the substrate material 100 ′. For example, solder balls are formed on the semiconductor element 300. A flux is applied to the solder balls. The semiconductor element 300 is mounted using the adhesiveness of the flux. Then, the solder ball is melted in a reflow furnace and then cured, thereby completing the mounting of the semiconductor element 300 via the solder 310. In addition to the method of forming solder balls, a method of applying a solder paste to the element placement pads 210 of the conductive layer 200 may be employed.

  Next, as shown in FIG. 19, a sealing resin 400 is formed. The formation of the sealing resin 400 is, for example, filled with a resin material that has excellent permeability and is cured by light exposure so as to cover the main surface 101, the inclined surface 112, and the bottom surface 111 and cover the semiconductor element 300. This is done by curing.

  Next, as shown in FIG. 20, the substrate material 100 ′ is ground from the back surface 102. The back surface 102 is ground until reaching the metal filling portion 240. Thereby, the bottom part (end surface 241) of the metal filling part 240 is exposed. Further, the above-described second recess 120 becomes a penetrating portion 107 having a penetrating portion inner surface 108 and a flat opening 109 by grinding the bottom surface portion. At this time, the end surface 241 of the metal filling portion 240 exposed by grinding and the back surface 102 of the substrate material 100 ′ are flush with each other. Further, the metal filling part 240 closes the entire opening 109 of the through part 107.

  Next, as illustrated in FIG. 21, an insulating film 500 is formed on the back surface 102. The insulating film 500 is formed by patterning after an insulating material such as polyimide resin or benzocyclobutene resin is laminated by CVD.

  Next, as shown in FIG. 22, a conductive layer 200 (seed layer 201 and plating layer 202) is formed at appropriate positions on the back surface 102 (on the insulating film 500 and the metal filling portion 240). The seed layer 201 is formed, for example, by performing patterning after performing sputtering using Ti or Cu. The plating layer 202 is formed by electrolytic plating using the seed layer 201, for example. As a result, a plating layer 202 made of a layer in which, for example, Cu, Ti, Ni, Cu or the like is laminated is obtained. The seed layer 201 and the plating layer 202 form a conductive layer 200 by being laminated. At this time, the conductive layer 200 has a shape including the back-side pad 230, for example.

  Next, as shown in FIG. 23, a back electrode pad 600 is formed. The back electrode pad 600 is formed by electroless plating a metal such as Ni, Pd, or Au on the back side pad 230.

  Next, as shown in FIGS. 24 and 25, the substrate material 100 'and the sealing resin 400 are cut by, for example, a dicer Dc. Cutting by the dicer Dc is performed along cutting lines CL extending in the x direction and the y direction, respectively, when viewed in the z direction. In FIG. 25, only the substrate material 100 ′ and the semiconductor element 300 are shown, and other elements are omitted.

  At the time of cutting by the dicer Dc, the substrate material 100 ′ is cut at a position that avoids the recess-unformed region 101 ′ (main surface 101). Specifically, the substrate material 100 ′ is cut at the bottom surface 111 of the first recess 110, and between the recess-unformed regions 101 ′ adjacent in the y direction and between the recess-unformed regions 101 ′ adjacent in the x direction. Disconnect at. By performing such a cutting operation, the semiconductor device 1A shown in FIGS. 1 and 2 is obtained.

  Next, functions and effects of the semiconductor device 1A will be described.

  According to this embodiment, the semiconductor element 300 is mounted on the substrate 100 made of a semiconductor material and having irregularities. For this reason, it is not necessary to provide a lead for supporting the semiconductor element 300. Compared with the case where the leads are molded, the substrate 100 made of a semiconductor material is less expensive to change the shape. Therefore, the cost of the semiconductor device 1A can be reduced. In particular, when the semiconductor device 1A is produced in a small amount, the cost reduction effect is remarkable.

  The semiconductor element 300 is mounted at a position (main surface 101) avoiding the recess 105 of the substrate 100. On the opposite side of the substrate 100 from the back surface 102 in the thickness direction, the substrate 100 has a main surface 101 and a recess 105 and is uneven. The main surface 101 on which the semiconductor element 300 is mounted is the portion that protrudes most in the thickness direction of the substrate 100. Thus, when the semiconductor device 1A is mounted on, for example, a circuit board, the semiconductor element 300 is located away from the back surface 102 that is the mounting surface. Therefore, in the present embodiment, for the Hall element that is the semiconductor element 300, for example, a magnet disposed outside the semiconductor device 1A (on the side opposite to the circuit board across the semiconductor device 1A), and a magnetosensitive surface of the Hall element Can be shortened, and the sensitivity of the Hall element to changes in magnetic flux is improved.

  Even when the distance from the circuit board to the magnet is set to be relatively long, the semiconductor element 300 (hole) mounted on the main surface 101 is increased by increasing the dimension in the thickness direction of the board 100. The distance between the element) and the external magnet can be shortened.

  A recess 105 formed in the substrate 100 penetrates the back surface 102. The conductive layer 200 conducting to the semiconductor element 300 is formed in a range from the main surface 101 (element arrangement pad 210) to the back surface 102 (back surface side pad 230) via the recess 105 (communication path 220). Therefore, even when the thickness of the substrate 100 is changed, electrical conduction between the semiconductor element 300 and the back surface electrode pad 600 on the back surface 102 side is appropriately ensured by the conductive layer 200 formed mainly in the through-shaped recess 105. Can do. According to such a configuration, the degree of freedom of arrangement of the semiconductor element 300 is increased.

  As described above, the main surface 101 on which the semiconductor element 300 is mounted is the most protruding portion in the thickness direction of the substrate 100. According to such a configuration, when the semiconductor element 300 is mounted on the substrate 100, the interference between the device for mounting the semiconductor element 300 (for example, a suction collet) and the substrate 100, for example, compared to the case where the semiconductor element is accommodated in the recess. Thus, the semiconductor element 300 can be easily mounted on the substrate 100.

  Furthermore, according to the configuration in which the semiconductor element 300 is mounted on the convex main surface 101, the entire semiconductor element 300 can be more reliably covered when the sealing resin 400 is formed during the manufacture of the semiconductor device 1A. This is preferable in properly manufacturing the semiconductor device 1A.

  The sealing resin 400 covers the semiconductor element 300 and is filled in the recess 105. The recess 105 is recessed from the main surface 101. The recess 105 is constituted by an inclined surface 112 connected to the main surface 101 and a bottom surface 111 connected to the inclined surface 112. Then, the sealing resin 400 covers the entire main surface 101, the inclined surface 112, and the bottom surface 111 (that is, substantially the entire uneven portion of the substrate 100). According to such a configuration, the adhesion between the substrate 100 and the sealing resin 400 is enhanced, and the peeling or dropping of the sealing resin 400 is prevented.

  The bottom surface 111 forms a rectangular ring shape as viewed in the thickness direction of the substrate 100 and surrounds the main surface 101. The inclined surface 112 is interposed between the main surface 101 and the bottom surface 111. Such a configuration is suitable for increasing the area of the concavo-convex portion of the substrate 100 (that is, the contact area with the sealing resin 400), and for increasing the adhesion between the substrate 100 and the sealing resin 400. preferable.

  As described above, the bottom surface 111 of the recess 105 has a rectangular ring shape, and the peripheral edge of the concavo-convex portion (the opposite side of the back surface 102) of the substrate 100 is constituted by the bottom surface 111. When manufacturing the semiconductor device 1 </ b> A, the substrate material 100 ′ is cut only at the bottom surface 111. According to such a configuration, the semiconductor device 1A can be surely cut by a desired size. This is preferable in properly manufacturing the semiconductor device 1A.

  The semiconductor device according to the present invention is not limited to the above-described embodiment. The specific configuration of each part of the semiconductor device according to the present invention can be modified in various ways.

1A Semiconductor device 100 Substrate 100 ′ Substrate material 101 Main surface 101 ′ Recessed unformed region 102 Back surface 103 Base material 104 Insulating layer 104A Through portion inner surface insulating portion 104b End surface 105 Recessed portion 106 Outer side surface 107 Through portion 108 Through portion inner surface 109 1 recessed portion 111 bottom surface 112 inclined surface 120 second recessed portion 121 recessed portion inner surface 122 recessed portion bottom surface 200 conductive layer 201 seed layer 202 plated layer 210 element placement pad 220 communication path 230 back side pad (covering portion)
240 Metal Filled Portion 241 End Surface 300 Semiconductor Element 310 Solder 400 Sealing Resin 401 Resin Main Surface 402 Resin Side Surface 500 Insulating Film 600 Back Electrode Pad

Claims (31)

A substrate having a main surface and a back surface facing opposite sides in the thickness direction, and made of a semiconductor material;
A semiconductor element disposed on the substrate;
A conductive layer electrically connected to the semiconductor element and formed on the substrate;
Sealing resin covering the semiconductor element,
The substrate has a recess recessed from the main surface and penetrating through the back surface,
The semiconductor element is mounted on the main surface,
The said conductive layer is a semiconductor device currently formed in the range over the said back surface via the said recessed part from the said main surface. The recess has an inclined surface connected to the main surface and inclined with respect to the main surface, and a bottom surface connected to the inclined surface,
The semiconductor device according to claim 1, wherein the substrate has a through portion penetrating from the bottom surface to the back surface.   The inclined surfaces are spaced apart from each other across the main surface in a first direction perpendicular to the thickness direction, and each of the inclined surfaces approaches the bottom surface as the distance from the main surface increases in the first direction. The semiconductor device according to claim 2, wherein the semiconductor device is displaced.   The semiconductor device according to claim 2, wherein the substrate has an outer surface that is sandwiched between the main surface and the back surface in the thickness direction and intersects the back surface.   The semiconductor device according to claim 4, wherein the outer surface has a rectangular ring shape when viewed in the thickness direction.   The semiconductor device according to claim 5, wherein the bottom surface is surrounded by the outer surface as viewed in the thickness direction.   The semiconductor device according to claim 6, wherein the bottom surface has a rectangular ring shape and surrounds the main surface when viewed in the thickness direction.   The semiconductor device according to claim 4, wherein the sealing resin covers the entire main surface, the inclined surface, and the bottom surface. The sealing resin has a resin main surface facing the same direction as the main surface, and a resin side surface located between the resin main surface and the outer surface of the substrate,
The semiconductor device according to claim 8, wherein the outer side surface and the resin side surface are flush with each other.   The semiconductor device according to claim 9, wherein a dimension from the main surface to the resin main surface in the thickness direction is smaller than a dimension from the back surface to the main surface in the thickness direction.   The semiconductor device according to claim 2, wherein the penetrating portion is provided with a metal filling portion that closes at least the opening on the back surface side of the penetrating portion and is filled with a metal material.   The semiconductor device according to claim 11, wherein the metal filling portion is filled in the entire penetration portion. The metal filling portion has an end surface facing the same direction as the back surface,
The semiconductor device according to claim 12, wherein the end surface is flush with the back surface.   The semiconductor device according to claim 13, wherein the conductive layer has a covering portion that covers the end face of the metal filling portion.   The semiconductor device according to claim 11, wherein the penetrating portion has a smaller cross-sectional dimension from the main surface side toward the back surface side.   The electronic device according to claim 11, wherein the number of the through portions is plural.   The semiconductor device according to claim 2, wherein the substrate is made of a single crystal of a semiconductor material.   The semiconductor device according to claim 17, wherein the semiconductor material is Si.   The semiconductor device according to claim 18, wherein the main surface is a (100) surface. An insulating film formed on the back surface of the substrate;
The semiconductor device according to claim 1, wherein the insulating film is interposed between the substrate and the conductive layer.   The semiconductor device according to claim 1, wherein the semiconductor element is a Hall element. Forming a recess recessed from the main surface in a substrate material having a main surface and a back surface facing away from each other in the thickness direction;
Forming a conductive layer on the substrate material including the recess;
Mounting the semiconductor element on the main surface;
Forming a sealing resin covering the semiconductor element;
Cutting the substrate material along the thickness direction of the substrate material at a position avoiding the main surface;
A method for manufacturing a semiconductor device. In the step of forming the recess, a first recess having an inclined surface connected to the main surface and inclined with respect to the main surface, and a bottom surface connected to the inclined surface, and a second recess recessed from the bottom surface; , In order,
After the step of forming the sealing resin, and before the step of cutting the substrate material, the step of grinding the substrate material from the back surface until reaching the formation site of the second recess, 23. A method of manufacturing a semiconductor device according to 22.   24. The method of manufacturing a semiconductor device according to claim 23, wherein in the step of cutting the substrate material, the substrate material is cut at the bottom surface. In the step of forming the recess, a plurality of recess-unformed regions arranged at intervals in a first direction perpendicular to the thickness direction of the substrate material are left as the main surface,
In the step of mounting the semiconductor element, at least one of the semiconductor elements is mounted in each of the recess-unformed regions,
25. The method of manufacturing a semiconductor device according to claim 23, wherein in the step of cutting the substrate material, the substrate material is cut between the recess-unformed regions adjacent in the first direction. A plurality of the recess-unformed regions are arranged at intervals in a second direction that is perpendicular to both the thickness direction and the first direction,
26. The method of manufacturing a semiconductor device according to claim 25, wherein in the step of cutting the substrate material, the substrate material is cut between the recess-unformed regions adjacent in the second direction. In the step of forming the sealing resin, the entire main surface, the inclined surface and the bottom surface are covered with the sealing resin,
27. The method of manufacturing a semiconductor device according to claim 23, wherein, in the step of cutting the substrate material, the sealing resin is cut together with the substrate material.   28. The method of manufacturing a semiconductor device according to claim 23, wherein the substrate material is made of a single crystal of a semiconductor material.   30. The method of manufacturing a semiconductor device according to claim 28, wherein the semiconductor material is Si.   30. The method of manufacturing a semiconductor device according to claim 29, wherein the main surface is a (100) surface.   In the step of forming the concave portion, the first concave portion is formed by performing anisotropic etching on the main surface of the substrate material, and the second concave portion is subjected to anisotropic etching on the bottom surface. The method for manufacturing a semiconductor device according to claim 30, wherein the semiconductor device is formed by:

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