JP2017028486A - Piezoelectric device for high temperature - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technology capable of improving connection strength of an Al wire, in a piezoelectric device for high temperature use which is used in an environment at a temperature of 150°C or above and 300°C or below.SOLUTION: A piezoelectric device includes: an element mounting member 20 having a recessed space; a crystal vibration element and an IC chip mounted in the recessed space; and a lid member for sealing the recessed space. The piezoelectric device is used in an environment at a temperature of 150°C or above and 300°C or below. A pad 24 for an IC is provided in the recessed space, and the pad 24 for an IC and the IC chip are connected by an Al wire 52. The pad 24 for an IC includes: an Au layer 24a with which the Al wire 52 is in contact; and a Ni layer 24b as a metal layer under the Au layer. The film thickness ta of the Au layer 24a is 0.5 μm or more and 0.8 μm or less.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a high-temperature piezoelectric device such as a crystal oscillator that is used in an environment of 150 ° C. or higher and 300 ° C. or lower. In the present specification and claims, element names are indicated by element symbols.

  As a general piezoelectric device, a piezoelectric element and an IC chip are mounted in a recessed space of an element mounting member, the recessed space is sealed with a lid member, and an electrode of the IC chip is electrically connected to a pad in the recessed space by a wire. Is known (see Patent Document 1).

  In addition, as a general semiconductor device instead of a piezoelectric device, a pad made of an underlying Cu (copper) plating layer and an Au (gold) plating layer thereon is provided on the substrate. Are connected by an Al (aluminum) wire (see Patent Document 2).

  In the technique of Patent Document 2, the thickness of the Au plating layer is less than 0.5 μm in a pad that has a Cu—Au laminated structure and is bonded to an Al wire. As a result, Kirkendall voids generated between the Au plating layer and the Al wire under a high temperature environment (125 ° C. or lower) can be prevented, and the bondability between the wire and the pad is improved. This Kirkendall void is a deficient layer (void) generated in the Au plating layer because the diffusion rate of Au due to heat is significantly higher than that of other metals such as Al and Cu. When Kirkendall voids are generated, the Al wire easily peels from the Au plating layer.

JP 2013-239790 A JP 2003-059962 A

  However, since the technology of Patent Document 2 is 125 ° C. or lower even in a high temperature environment, the following problems occur in a high temperature piezoelectric device used in an environment of 150 ° C. or higher and 300 ° C. or lower.

  The number of pin holes in the Au layer increases as the film thickness of the Au layer decreases, and the number of pin holes in the Au layer decreases as the film thickness of the Au layer increases. Therefore, when the pad has a laminated structure of a base metal layer and an Au layer, and the Au layer is thinned to less than 0.5 μm, the base metal is exposed to the surface of the Au layer through the pin hole of the Au layer, so that the Al wire The connection strength is reduced. The base metal exposed on the surface of the Au layer acts to peel off the Al wire.

  Therefore, an object of the present invention is to provide a technique capable of improving the connection strength of an Al wire in a high-temperature piezoelectric device used in an environment of 150 ° C. or higher and 300 ° C. or lower.

  This inventor repeated experiment and consideration about the relationship between the film thickness of the Au layer and the connection strength of the Al wire in the high-temperature piezoelectric device, and obtained the following knowledge. When the thickness of the Au layer is less than 0.5 μm, the base metal is exposed to the surface of the Au layer through the pin hole of the Au layer, and the connection strength of the Al wire becomes below a practical level. On the other hand, if the thickness of the Au layer exceeds 0.8 μm, Kirkendall voids are generated in the Au layer, so that the connection strength of the Al wire becomes less than a practical level. The present invention has been made based on this finding.

That is, the high-temperature piezoelectric device according to the present invention is
An element mounting member having a recessed space, a piezoelectric element and an IC chip mounted in the recessed space, and a lid member that seals the recessed space, and is used in an environment of 150 ° C. or higher and 300 ° C. or lower. Piezoelectric devices for
The IC pad provided in the recess space and the IC chip are connected by an Al wire,
The IC pad includes an Au layer in contact with the Al wire and a metal layer below the Au layer,
The film thickness of the Au layer is 0.5 μm or more and 0.8 μm or less,
It is characterized by that.

  According to the present invention, in a high-temperature piezoelectric device used in an environment of 150 ° C. or higher and 300 ° C. or lower, the thickness of the Au layer in contact with the Al wire is 0.5 μm or more and 0.8 μm or less. Since both the exposure of the base metal to the surface and the generation of Kirkendall voids in the Au layer can be suppressed, the connection strength of the Al wire can be improved.

2 is an enlarged cross-sectional view of an IC pad and its periphery in the piezoelectric device of Embodiment 1. FIG. The piezoelectric device of Embodiment 1 is shown, FIG. 2 [A] is a top view, FIG. 2 [B] is the IIb-IIb sectional view taken on the line in FIG. 2 [A]. FIG. 2 is an exploded perspective view showing the piezoelectric device of Embodiment 1 with a part cut away.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention (hereinafter referred to as “embodiments”) will be described with reference to the accompanying drawings. In the present specification and drawings, the same reference numerals are used for substantially the same components. The shapes depicted in the drawings are drawn so as to be easily understood by those skilled in the art, and thus do not necessarily match the actual dimensions and ratios. “High-temperature piezoelectric device” is abbreviated as “piezoelectric device”.

  FIG. 1 is an enlarged cross-sectional view showing an IC pad and its periphery in the piezoelectric device according to the first embodiment. 2 shows the piezoelectric device of the first embodiment, FIG. 2 [A] is a plan view, and FIG. 2 [B] is a sectional view taken along the line IIb-IIb in FIG. 2 [A]. FIG. 3 is an exploded perspective view showing the piezoelectric device of Embodiment 1 with a part cut away. Hereinafter, description will be given with reference to FIGS.

  First, the configuration of the piezoelectric device 10 will be schematically described.

  The piezoelectric device 10 includes an element mounting member 20 having a recessed space 11, a crystal resonator element 40 and an IC chip 50 mounted in the recessed space 11, and a lid member 30 that seals the recessed space 11, and is 150 ° C. or higher. And it is used in an environment of 300 ° C. or lower. An IC pad 24 is provided in the recessed space 11, and the IC pad 24 and the IC chip 50 are connected by an Al wire 52. The IC pad 24 includes an Au layer 24a in contact with the Al wire 52 and a Ni (nickel) layer 24b as a metal layer therebelow. The film thickness ta of the Au layer 24a is not less than 0.5 μm and not more than 0.8 μm.

  As described above, the piezoelectric device 10 is a surface-mounted crystal oscillator including the crystal resonator element 40 as a piezoelectric element. Since the crystal oscillator serves as a reference clock signal source for the apparatus, higher reliability is required than other electronic components.

  The film thickness tb of the Ni layer 24b is, for example, 1 μm to 6 μm. The Au layer 24a and the Ni layer 24b are, for example, electroless plating films. As a method for forming the Au layer 24a and the Ni layer 24b, in addition to electroless plating, electrolytic plating, sputtering, vapor deposition, and the like can be given. The deposition method of the Au layer 24a and the deposition method of the Ni layer 24b may be the same or different. For patterning the Au layer 24a and the Ni layer 24b, for example, photolithography and etching, or a metal mask is used.

  The element mounting member 20 mounts the IC chip 50 and the crystal resonator element 40. The lid member 30 is provided on the element mounting member 20. The recessed space 11 is formed in the element mounting member 20 and accommodates the crystal resonator element 40 and the IC chip 50.

  The element mounting member 20 has a substrate portion 25 having a first bottom surface 211 on which the IC chip 50 is mounted and a second bottom surface 212 on which the IC pad 24 is mounted and is provided on the periphery of the substrate portion 25. The first frame portion 261, the third bottom surface 213 on which the crystal resonator element 40 is mounted, the second frame portion 262 provided on the periphery of the first frame portion 261, and the periphery of the second frame portion 262. And a third frame portion 263. A space surrounded by the substrate portion 25, the first frame portion 261, the second frame portion 262, and the third frame portion 263 is the recessed space 11.

  Next, the configuration of the piezoelectric device 10 will be described in more detail.

  In the piezoelectric device 10, the crystal vibration element 40 and the IC chip 50 are mounted on the element mounting member 20, and the element mounting member 20 and the lid member 30 are joined together by seam welding or glass sealing, thereby crystal vibration. The element 40 and the IC chip 50 are hermetically sealed in the recessed space 11.

  The crystal resonator element 40 includes a crystal piece 43 having an upper surface 41 and a lower surface 42 that are in a front / back relationship, and an electrode 44 that extends from the upper surface 41 to the lower surface 42 of the crystal piece 43. The crystal piece 43 is made of, for example, an AT cut plate. The electrode 44 consists of two insulated from each other, and is divided into an excitation electrode, a lead electrode, a pad electrode, etc., and extends from the upper surface 41 to the lower surface 42 across the side surface. The quartz crystal vibration element 40 is a thickness shear vibration element, but instead of this, a tuning fork type bending vibration element or a contour slip vibration element may be used.

  The substrate portion 25, the first frame portion 261, the second frame portion 262, and the third frame portion 263 constituting the element mounting member 20 are made of, for example, a laminated ceramic plate in which a plurality of green sheets are laminated and fired. The first frame portion 261 is provided on the periphery of the substrate portion 25, the second frame portion 262 is provided on the periphery of the first frame portion 261, and the third frame portion 263 is provided on the periphery of the second frame portion 262, respectively. It has been. The internal wiring (not shown) is made of, for example, a conductor pattern printed on a green sheet or a via hole conductor. The IC chip 50 is die-bonded to the first bottom surface 211 of the recessed space 11 with, for example, an adhesive. An IC pad 24 is provided on the second bottom surface 212, and an element pad 23 is provided on the third bottom surface 213.

  The element pad 23 is provided at a position facing the electrode 44 of the crystal resonator element 40 and is electrically connected to the electrode 44 by the conductive bonding material 27. The conductive bonding material 27 is a conductive adhesive such as silver paste, and has fluidity before curing. External connection terminals 29 for surface mounting are provided on the projecting end surfaces of the four corners of the substrate portion 25, respectively. Examples of the external connection terminal 29 include a frequency control terminal, a ground terminal, an output terminal, and a power supply voltage terminal. Note that the element pads 23, the IC pads 24, and the external connection terminals 29 are electrically connected to each other by internal wiring (not shown).

  The IC chip 50 is composed of an oscillation circuit of the crystal resonator element 40 and has an electrode 51 that is a connection terminal. The electrode 51 is made of, for example, an Al layer or an Au layer, and is electrically connected to the IC pad 24 via the Al wire 52. That is, the same number of electrodes 51 and IC pads 24 are provided. The Al wire 52 is literally made of Al, and both ends thereof are electrically connected to the electrode 51 and the IC pad 24, respectively. The connection method is wire bonding using ultrasonic waves.

  The lid member 30 is made of, for example, a metal such as Kovar or ceramics, and is a rectangular flat plate. The lid member 30 is joined to the element mounting member 20 by electric welding or glass sealing to hermetically seal the recessed space 11.

  Next, a method for assembling the piezoelectric device 10 will be described.

  First, the IC chip 50 is die bonded to the first bottom surface 211 of the recessed space 11. Subsequently, an Al wire 52 is wire-bonded to the electrode 51 of the IC chip 50 and the IC pad 24 on the second bottom surface 212. Subsequently, the electrode 44 of the crystal resonator element 40 is placed on the element pad 23 on the third bottom surface 212 via the conductive bonding material 27. Finally, the recessed space 11 of the element mounting member 20 is sealed with the lid member 30. Thereby, the piezoelectric device 10 is completed.

  Next, operations and effects of the piezoelectric device 10 will be described with reference to FIGS. 1 to 3.

  According to the first embodiment, in the high-temperature piezoelectric device 10 used in an environment of 150 ° C. or more and 300 ° C. or less, the film thickness ta of the Au layer 24a in contact with the Al wire 52 is 0.5 μm or more and 0.8 μm or less. As a result, both the exposure of the underlying Ni layer 24b to the surface of the Au layer 24a and the generation of Kirkendall voids in the Au layer 24a can be suppressed, so that the connection strength of the Al wire 52 can be improved. Therefore, the first embodiment is used in an environment of 150 ° C. or more and 300 ° C. or less, which is higher than the upper limit of the environmental temperature assumed to be used in the conventional piezoelectric device, that is, a hot spring excavator, an oil drilling drill, or the like. This is particularly effective for improving the connection strength of the Al wire 52 in an environment where a piezoelectric device is used.

  The reason why the film thickness ta of the Au layer 24a is 0.5 μm or more is that Ni can be prevented from being exposed to the surface of the Au layer 24a through the pinholes of the Au layer 24a. On the other hand, the reason why the film thickness ta of the Au layer 24a is set to 0.8 μm or less is that generation of Kirkendall voids in the Au layer 24a can be suppressed. This effect becomes even more remarkable when the film thickness ta of the Au layer 24a is 0.6 μm or more and 0.7 μm or less.

  In addition, by using the Ni layer 24b as the base metal layer, generation of Kirkendall voids in the Au layer 24a can be further suppressed. This is because Ni has an effect of shielding the diffusion of Au compared to Cu or the like (see, for example, paragraph 0013 of Patent Document 2). That is, if the base metal layer is, for example, a Cu layer, Au diffuses not only into the Al wire but also into the Cu layer, so that a Kirkendall void in the Au layer is likely to occur.

  In other words, the operation and effect of the piezoelectric device 10 are as follows.

  In the periphery of the diffusion layer of the Al wire 52 and the IC pad 24, voids may be generated due to the Kirkendall's effect because the diffusion rates of Al and Au are different. As a result, peeling occurs from the void portion, the connection strength between the Al wire 52 and the IC pad 24 cannot be ensured, and the Al wire 52 and the IC pad 24 may not be electrically connected. In particular, if the film thickness ta of the Au layer 24a is thick, the diffusion of Au is accelerated and voids are excessively generated.

  Therefore, in the first embodiment, by reducing the film thickness ta of the Au layer 24a, the Au diffusion rate in the diffusion layer is suppressed, and the occurrence of excessive voids is reduced. Then, by reducing the generation of voids due to the Kirkendall effect, peeling from the void portion is reduced, and the connection strength between the Al wire 52 and the IC pad 24 is ensured.

  Here, the reason why Kirkendall voids are more likely to occur when the Au layer is thickened (and conversely why Kirkendall voids are less likely to occur when the Au layer is thinned) is as follows. Can be considered.

  The phenomenon of Kirkendall voids in the Au layer also follows Fick's first law. Fick's first law is a basic law concerning the diffusion of a substance, and is a law that "the diffusion flux (diffusion rate) is proportional to the concentration gradient". Assuming the case of diffusion only in one dimension, Fick's first law is given by the following equation.

J = −D (dc / dx) (1)
J is the diffusion flux (diffusion rate), D is the diffusion coefficient, c is the concentration, and x is the position.

  At the boundary (x = 0) between the Au layer and the Al wire, Au atoms diffuse into the Al wire with time. Here, as the film thickness of the Au layer increases, Au atoms continue to be supplied to the boundary (x = 0) over time, so the concentration gradient (dc / dx) of Au atoms at the boundary (x = 0) is It remains large. As a result, the thicker the Au layer is, the more difficult it is to reduce the diffusion rate of Au atoms, so that Kirkendall voids are more likely to occur.

  The present invention has been described above with reference to the above embodiment, but the present invention is not limited to the above embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention. In addition, the present invention includes a combination of some or all of the configurations of the above embodiments as appropriate.

  The present invention can be used for a piezoelectric device including a piezoelectric element made of crystal or ceramics, and is particularly suitable for a crystal oscillator used in a hot spring excavator, an oil drilling drill, or the like.

10 Piezoelectric devices (piezoelectric devices for high temperatures)
DESCRIPTION OF SYMBOLS 11 Recessed space 20 Element mounting member 211 1st bottom face 212 2nd bottom face 213 3rd bottom face 23 Element pad 24 IC pad 24a Au layer ta Au layer film thickness 24b Ni layer tb Ni layer film thickness 25 Substrate part 261 1st One frame part 262 Second frame part 263 Third frame part 27 Conductive bonding material 29 External connection terminal 30 Lid member 40 Crystal vibration element (piezoelectric element)
41 Upper surface 42 Lower surface 43 Crystal piece 44 Electrode 50 IC chip 51 Electrode 52 Al wire

Claims (3)

An element mounting member having a recessed space, a piezoelectric element and an IC chip mounted in the recessed space, and a lid member that seals the recessed space, and is used in an environment of 150 ° C. or higher and 300 ° C. or lower. Piezoelectric devices for
The IC pad provided in the recess space and the IC chip are connected by an Al wire,
The IC pad includes an Au layer in contact with the Al wire and a metal layer below the Au layer,
The film thickness of the Au layer is 0.5 μm or more and 0.8 μm or less,
A high-temperature piezoelectric device characterized by that. The thickness of the Au layer is 0.6 μm or more and 0.7 μm or less,
The high-temperature piezoelectric device according to claim 1. The metal layer is a Ni layer;
The high-temperature piezoelectric device according to claim 1 or 2.

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