JP2017011111A - Semiconductor device, display device and electronic apparatus - Google Patents

Abstract

In a semiconductor device having a low concentration implantation region, a characteristic drop in the low concentration implantation region is suppressed. A first insulating layer, a semiconductor layer, a gate insulating layer, and a gate electrode are formed in order from a substrate side, a first blocking layer, a second blocking layer, and a second blocking layer. The semiconductor layer 10 includes a source region 5, a channel region 9, a drain region 6, a first low concentration implantation region 7 and a drain region 6 provided in contact with each other between the source region 5 and the channel region 9 and a channel. A second low concentration implantation region 8 is provided between and in contact with the region 9. The first blocking layer 11 is provided on the first low concentration implantation region 7, the second blocking layer 12 is provided on the second low concentration implantation region 8, and the first blocking layer 11 and the second blocking layer are provided. The mobility of mobile ions at 12 is smaller than the mobility of mobile ions in the gate insulating layer. [Selection] Figure 1

Description

  The present invention relates to a semiconductor device, a display device, and an electronic device.

  In a display device such as a liquid crystal display device, an organic EL display device, and electronic paper, a semiconductor substrate including a TFT (Thin Film Transistor) is often used as a switching element for controlling image display and the like.

  Although the display portion of these display devices can be made thin by using TFT, the characteristics of TFT may change over time when mobile ions such as alkali metal exist in the semiconductor substrate. It is known that there is. For this reason, in the manufacture of such a semiconductor substrate, close attention is paid to alkali metals, and measures are often taken to prevent alkali contamination.

  For example, in Patent Document 1, by providing a substrate (base material) with a blocking film such as a silicon nitride film (SiN film), even when the base material itself is contaminated with mobile ions, the semiconductor layer is applied to the semiconductor layer. It is described that mobile ions are prevented from diffusing.

JP 2001-26462 A

  However, the countermeasure described in Patent Document 1 has a problem that diffusion of mobile ions cannot be prevented when mobile ions are present in a portion other than the substrate (base material). As a specific example, when a TFT has a low concentration implantation region (LDD region), if mobile ions are accumulated in the LDD region or in the vicinity of the LDD region, the LDD region and the vicinity of the LDD region The resistance value fluctuates, thereby reducing the on-current of the TFT. As a result, the characteristics of the TFT change.

  SUMMARY An advantage of some aspects of the invention is to solve at least one of the problems and problems described above, and the following application examples or embodiments can be adopted.

[Application Example 1]
One semiconductor device according to the present invention includes a substrate, a first insulating layer formed on the substrate, a semiconductor layer formed on the first insulating layer, and a gate insulating formed on the semiconductor layer. A semiconductor layer comprising: a layer; a gate electrode formed on the gate insulating layer; a first blocking layer; and a second blocking layer. The semiconductor layer includes a source region, a channel region, a drain region, and the source region. And a first low concentration implantation region provided in contact with each other between the drain region and the channel region, and a second low concentration implantation region provided in contact with each other between the drain region and the channel region. The first blocking layer is provided between the gate insulating layer and the first low concentration implantation region, and the second blocking layer includes the gate insulating layer and the second low concentration implantation region. Between Is the mobility of the mobile ions in the mobility and the second blocking layer of the mobile ions in the first blocking layer is characterized by less than the mobility of the mobile ions in the gate insulating layer.

  According to this configuration, the first blocking layer and the second blocking layer suppress the intrusion of movable ions into the first low concentration implantation region and the second low concentration implantation region. It is possible to suppress a change in resistance in the second low concentration implantation region. As a result, a change in on-current in the first low-concentration implantation region and the second low-concentration implantation region can be prevented, and a change in characteristics of the semiconductor device can be suppressed.

[Application Example 2]
In one semiconductor device according to the present invention, the first blocking layer and the second blocking layer include silicon oxynitride, silicon nitride, aluminum oxide, tantalum oxide, tantalum nitride, and tantalum acid. At least one of nitride, titanium oxide, titanium nitride, and titanium oxynitride is preferably the main material.

  According to this configuration, by using at least one of these materials as a main material, the mobility of mobile ions in the first blocking layer and the second blocking layer is formed using a commonly used material. The mobility of mobile ions in the insulating layer can be smaller.

[Application Example 3]
In one semiconductor device according to the present invention, it is preferable that each of the first blocking layer and the second blocking layer has a thickness of 10 nm to 500 nm.

  According to this configuration, by setting the thickness of the first blocking layer and the second blocking layer within the above range, the first low-concentration implantation region and the second low-concentration region can be obtained without increasing the size of the semiconductor device. The increase in resistance in the concentration implantation region can be suppressed.

[Application Example 4]
In the semiconductor device according to the present invention, it is preferable that the semiconductor device further includes a third blocking layer formed between the substrate and the first insulating layer.

  According to this configuration, it is possible to reduce the influence of the mobile ions on the semiconductor layer by delaying the propagation of the mobile ions from the substrate side to the semiconductor layer.

[Application Example 5]
In the semiconductor device according to the present invention, a second insulating layer is provided on the gate insulating layer and the gate electrode, and a fourth blocking layer is provided on the second insulating layer. preferable.

  According to this configuration, it is possible to reduce the influence of mobile ions on the semiconductor layer by delaying the propagation of mobile ions from the upper side of the fourth blocking layer.

[Application Example 6]
Another semiconductor device according to the present invention includes a substrate, a first insulating layer formed on the substrate, a gate electrode formed on the first insulating layer, the first insulating layer, and the first insulating layer. A gate insulating layer formed on the gate electrode; a first blocking layer formed on a part of the gate insulating layer; a second blocking layer formed on a part of the gate insulating layer; A semiconductor layer formed on the gate insulating layer, the first blocking layer, and the second blocking layer; and a second insulating layer formed on the semiconductor layer, the semiconductor layer comprising: , A source region, a channel region, a drain region, a first low-concentration implantation region formed in contact with the source region and the channel region, and a drain region and the channel region, respectively. Formed in contact A second low-concentration implantation region, wherein the first blocking layer is provided between the gate insulating layer and the first low-concentration implantation region, and the second blocking layer includes the gate insulating layer and The mobility of mobile ions in the first blocking layer and the mobility of mobile ions in the second blocking layer are provided between the second low-concentration implantation region and the mobility of mobile ions in the gate insulating layer. It is smaller than mobility.

  According to this structure, the penetration | invasion of the movable ion from a gate insulating layer with respect to a 1st low concentration implantation area | region and a 2nd low concentration implantation area | region can be suppressed with a 1st blocking layer and a 2nd blocking layer. Thereby, it is possible to suppress a change in resistance in the first low concentration implantation region and the second low concentration implantation region. This can prevent a decrease in on-current in the first low-concentration implantation region and the second low-concentration implantation region, and can suppress a change in characteristics of the conductor layer.

[Application Example 7]
In the other semiconductor device, the first blocking layer and the second blocking layer are formed of silicon oxynitride, silicon nitride, aluminum oxide, tantalum oxide, tantalum nitride, or tantalum oxynitride. At least one of titanium oxide, titanium nitride, and titanium oxynitride is preferably the main material.

  According to this configuration, by using these materials, the mobility of mobile ions in the first blocking layer and the second blocking layer can be reduced in a gate insulating layer formed using a commonly used material. The mobility of mobile ions in can be smaller.

[Application Example 8]
In the other semiconductor device, it is preferable that the first blocking layer and the second blocking layer have a thickness of 10 nm to 2000 nm.

  According to this configuration, by setting the thickness of the first blocking layer and the second blocking layer within the above range, the first low-concentration implantation region and the second low-concentration region can be obtained without increasing the size of the semiconductor device. High resistance in the concentration implantation region can be suppressed.

[Application Example 9]
In the other semiconductor device, it is preferable that the semiconductor device further includes a third blocking layer formed between the substrate and the first insulating layer.

  According to this configuration, it is possible to reduce the influence of mobile ions on the semiconductor layer by delaying the propagation of mobile ions from the substrate side to the semiconductor layer by the third blocking layer.

[Application Example 10]
In the other semiconductor device, it is preferable that a fourth blocking layer provided on the second insulating layer is further provided.

  According to this configuration, it is possible to reduce the influence of mobile ions on the semiconductor layer by delaying the propagation of mobile ions from the upper side of the fourth blocking layer.

[Application Example 11]
A display device according to the present invention preferably includes the semiconductor device described above.

  According to this configuration, it is possible to configure a display device with excellent reliability by including the semiconductor device in which the characteristic change due to the movable ions hardly occurs.

[Application Example 12]
An electronic apparatus according to the present invention preferably includes the display device described above.

  According to this configuration, it is possible to configure an electronic device having excellent reliability by including the display device described above.

1 is a longitudinal sectional view schematically showing a first embodiment of a semiconductor device of the present invention. It is a longitudinal cross-sectional view which shows 2nd Embodiment of the semiconductor device of this invention typically. It is a longitudinal cross-sectional view which shows 3rd Embodiment of the semiconductor device of this invention typically. It is a longitudinal section showing a 4th embodiment of a semiconductor device of the present invention typically. It is a longitudinal section showing a 5th embodiment of a semiconductor device of the present invention typically. It is a longitudinal cross-sectional view which shows typically 6th Embodiment of the semiconductor device of this invention. It is a longitudinal cross-sectional view which shows typically 7th Embodiment of the semiconductor device of this invention. It is a longitudinal cross-sectional view which shows typically 8th Embodiment of the semiconductor device of this invention. It is sectional drawing which shows typically the electrophoretic display device which is embodiment of the display apparatus of this invention. It is a block diagram which shows the structure of an active matrix apparatus. It is a figure which shows typically the electronic paper which is embodiment of the electronic device of this invention.

  Hereinafter, embodiments of a semiconductor device, a display device, and an electronic device according to the present invention will be described with reference to the drawings. In the description of the embodiment according to the present invention, the upper side in the figure is “upper” and the lower side is “lower”. Further, the drawings used are for convenience of explanation, and for example, the ratio of the sizes of the components may be different from the actual ones.

(First embodiment)
FIG. 1 shows a cross-sectional view of a semiconductor device 1A in the present embodiment. The semiconductor device 1 is a so-called top gate / bottom contact type TFT.

  The semiconductor device 1A includes a substrate 2, a first interlayer insulating layer 4, a semiconductor layer 10 (a source region 5, a drain region 6, a channel region 9, a first low-concentration implantation region 7, and a second low-concentration implantation region 8). A first blocking layer 11, a second blocking layer 12, a gate insulating layer 13, a gate electrode 14, a second interlayer insulating layer 15, a conductive portion 17, and a conductive portion 18.

  Although it does not specifically limit as the board | substrate 2, For example, metal substrates, such as a glass substrate, a quartz substrate, a silicon substrate, molybdenum sulfide, copper, zinc, aluminum, stainless steel, magnesium, iron, nickel, gold, silver, a gallium arsenide group etc. A semiconductor substrate, a plastic substrate, or the like can be used.

  The first interlayer insulating layer 4 is formed on the substrate 2 and serves to suppress electrical connection between the semiconductor layer 10 and the substrate 2.

  The first blocking layer 11 is formed on the first low concentration implantation region 7. The second blocking layer 12 is formed on the second low concentration implantation region 8. The gate insulating layer 13 is for suppressing electrical connection between the gate electrode 14 and the semiconductor layer 10 and is formed on the semiconductor layer 10, the first blocking layer 11, and the second blocking layer 12. .

  Each of the first blocking layer 11 and the second blocking layer 12 is formed such that the mobility of mobile ions is lower than the mobility of mobile ions in the gate insulating layer 13. As a result, even if mobile ions are present in the gate insulating layer 13, it is possible to expect suppression of diffusion of the mobile ions to the first low concentration implantation region 7 and the second low concentration implantation region 8.

  The materials of the first blocking layer 11 and the second blocking layer 12 are silicon oxynitride, silicon nitride, aluminum oxide, tantalum oxide, tantalum nitride, tantalum oxynitride, titanium oxide, titanium nitride. And titan oxynitride, etc., and one or more of these may be used in combination. By using these materials, the mobility of mobile ions in the first blocking layer 11 and the second blocking layer 12 is set so that the mobile ions move in the gate insulating layer 13 when formed of a normal material. Less than a degree.

  A gate electrode 14 and a second interlayer insulating layer 15 are formed on the gate insulating layer 13. The source region 5 is connected to the conductive portion 17. The drain region 6 is connected to the conductive portion 18. The conductive portion 17 and the conductive portion 18 are connected to elements and the like outside the semiconductor device 1 by a predetermined conductive pattern formed on the second interlayer insulating layer 15.

  As described above, in the semiconductor device 1A, the movable ions are transferred from the gate insulating layer 13 to the first low concentration implantation region 7 and the second low concentration implantation region 8 by the first blocking layer 11 and the second blocking layer 12. Diffusion is suppressed. Thereby, it is possible to suppress a change in the characteristics of the semiconductor device 1 </ b> A that changes due to accumulation of movable ions in the first low concentration implantation region 7 and the second low concentration implantation region 8.

(Second Embodiment)
FIG. 2 shows a cross-sectional view of the semiconductor device 1B in the present embodiment. In the following embodiments including this embodiment, differences from the semiconductor device 1 of the first embodiment will be mainly described, and the same or similar reference numerals will be given to the same components, and the description thereof will be omitted. There is a case.

  The semiconductor device 1B includes a substrate 2, a first interlayer insulating layer 4, a semiconductor layer 10 (a source region 5, a drain region 6, a channel region 9, a first low concentration implantation region 7, and a second low concentration implantation region 8). A first blocking layer 11B, a second blocking layer 12B, a gate insulating layer 13, a gate electrode 14, a second interlayer insulating layer 15, a conductive portion 17, and a conductive portion 18.

  The difference between this embodiment and 1st Embodiment exists in the difference in the area | region in which the 1st blocking layer 11B and the 2nd blocking layer 12B are provided. In the present embodiment, the first blocking layer 11B is formed not only on the first low concentration implantation region 7 but also on the source region 5 adjacent to the first low concentration implantation region 7 in a continuous form. Further, the second blocking layer 12B in the present embodiment is formed not only on the second low concentration implantation region 8 but also on the drain region 6 adjacent to the second low concentration implantation region 8 in a continuous form. . In addition, the 1st blocking layer 11B and the 2nd blocking layer 12B are formed with the material similar to the 1st blocking layer 11 and the 2nd blocking layer 12 in 1st Embodiment. Thereby, diffusion of movable ions from the gate insulating layer 13 to the source region 5 and the drain region 6 as well as the first low concentration implantation region 7 and the second low concentration implantation region 8 can be suppressed. Thereby, the change of the characteristic by the influence of the movable ion in the semiconductor device 1B can be suppressed.

(Third embodiment)
FIG. 3 shows a cross-sectional view of the semiconductor device 1C in the present embodiment.

  The semiconductor device 1C includes a substrate 2, a third blocking layer 3, a first interlayer insulating layer 4, a semiconductor layer 10 (a source region 5, a drain region 6, a channel region 9, a first low-concentration implantation region 7, and a first 2 including a low concentration implantation region 8), a first blocking layer 11, a second blocking layer 12, a gate insulating layer 13, a gate electrode 14, a second interlayer insulating layer 15, a fourth blocking layer 16, and a conductive portion. 17 and a conductive portion 18.

  The difference between the present embodiment and the semiconductor device 1A shown in the first embodiment is that the third blocking layer 3 exists between the substrate 2 and the first interlayer insulating layer 4, and the second interlayer The fourth blocking layer 16 exists on the insulating layer 15. The third blocking layer 3 and the fourth blocking layer 16 are formed of the same material as the first blocking layer 11 and the second blocking layer 12 in the first embodiment.

  By providing the third blocking layer 3, the semiconductor device 1 </ b> C can suppress intrusion of mobile ions from the substrate 2 to the first interlayer insulating layer 4. In addition, the semiconductor device 1 </ b> C includes the fourth blocking layer 16, thereby suppressing the invasion of movable ions from the outside of the upper surface of the semiconductor device 1 </ b> C. Therefore, an increase in mobile ions in the first interlayer insulating layer 4 is suppressed. Further, an increase in mobile ions in the second interlayer insulating layer 15 is suppressed, and as a result, an increase in mobile ions in the gate insulating layer 13 can be suppressed. Thereby, coupled with the effects of the first blocking layer 11 and the second blocking layer 12, it is possible to suppress fluctuations in characteristics due to the influence of mobile ions as the semiconductor device 1C.

(Fourth embodiment)
The present embodiment is an example of a semiconductor device 1D in which the third blocking layer 3 and the fourth blocking layer 16 described in the third embodiment are provided in the semiconductor device 1B in the second embodiment. FIG. 4 shows a cross-sectional view of the semiconductor device 1D in the present embodiment.

  The semiconductor device 1D includes a substrate 2, a third blocking layer 3, a first interlayer insulating layer 4, a semiconductor layer 10 (a source region 5, a drain region 6, a channel region 9, a first low-concentration implantation region 7, and a first 2 including the low concentration implantation region 8), the first blocking layer 11B, the second blocking layer 12B, the gate insulating layer 13, the gate electrode 14, the second interlayer insulating layer 15, the fourth blocking layer 16, and the conductive portion. 17 and a conductive portion 18.

  The semiconductor device 1 </ b> D can suppress the invasion of mobile ions from the substrate 2 to the first interlayer insulating layer 4 by including the third blocking layer 3. In addition, the semiconductor device 1D includes the fourth blocking layer 16, so that the entry of movable ions from the outside of the upper surface of the semiconductor device 1C can be suppressed. Therefore, an increase in mobile ions in the first interlayer insulating layer 4 is suppressed. Further, an increase in mobile ions in the second interlayer insulating layer 15 is suppressed, and as a result, an increase in mobile ions in the gate insulating layer 13 can be suppressed. Thereby, coupled with the effects of the first blocking layer 11B and the second blocking layer 12B, it is possible to suppress fluctuations in characteristics due to the influence of mobile ions as the semiconductor device 1C.

(Fifth embodiment)
FIG. 5 shows a cross-sectional view of the semiconductor device 1E in the present embodiment. The semiconductor device 1E is a so-called bottom gate type TFT. The semiconductor device 1E includes a substrate 2, a first interlayer insulating layer 4, a gate electrode 14E, a gate insulating layer 13E, a first blocking layer 11E, a second blocking layer 12E, and a semiconductor layer 10E (a source region 5E and a drain region 6E). , A channel region 9E, a first low concentration implantation region 7E, and a second low concentration implantation region 8E), a second interlayer insulating layer 15E, a conductive portion 17, and a conductive portion 18.

  The materials of the first blocking layer 11E and the second blocking layer 12E may be the same as those of the first blocking layer 11 and the second blocking layer 12 in the semiconductor device 1A described in the first embodiment. Thereby, it is possible to suppress diffusion of mobile ions existing in the gate insulating layer 13E to the first low concentration implantation region 7E and the second low concentration implantation region 8E. As a result, the time until the characteristics of the semiconductor device 1E change can be increased, and the life of the semiconductor device 1E can be extended.

(Sixth embodiment)
The semiconductor device 1F in the present embodiment is a modification of the semiconductor device 1E shown in the fifth embodiment, like the semiconductor device 1B in the second embodiment with respect to the semiconductor device 1A in the first embodiment described above. A cross-sectional view of the semiconductor device 1F is shown in FIG.

  The first blocking layer 11F in the semiconductor device 1F is formed between the first low concentration implantation region 7E and the source region 5F and the gate insulating layer 13E. Similarly, the second blocking layer 12F in the semiconductor device 1F is formed between the second low concentration implantation region 8E and the drain region 6F and the gate insulating layer 13E. The material of the first blocking layer 11F may be the same material as that of the first blocking layer 11E, and the material of the second blocking layer 12F may be the same material as that of the second blocking layer 12E. Thereby, diffusion of movable ions from the gate insulating layer 13E can be suppressed not only in the first low concentration implantation region 7E and the second low concentration implantation region 8E but also in the source region 5F and the drain region 6F. Thereby, the fluctuation | variation of the characteristic by the movable ion in the semiconductor device 1F is suppressed.

(Seventh embodiment)
FIG. 7 shows a cross-sectional view of the semiconductor device 1G in the present embodiment. The semiconductor device 1G includes a third blocking layer 3G between the substrate 2 of the semiconductor device 1E and the first interlayer insulating layer 4 in the fifth embodiment, and a fourth blocking layer on the second interlayer insulating layer 15E. 16G is provided.

  As a result, an effect of suppressing the invasion of mobile ions into the first interlayer insulating layer 4 and the second interlayer insulating layer 15E can be expected, and the change in characteristics due to the mobile ions in the semiconductor device 1G can be suppressed.

(Eighth embodiment)
A sectional view of the semiconductor device 1H in the present embodiment is shown in FIG. The semiconductor device 1H includes a third blocking layer 3G between the substrate 2 and the first interlayer insulating layer 4 of the semiconductor device 1F in the sixth embodiment, and a fourth blocking layer on the second interlayer insulating layer 15F. 16G is provided.

  Thereby, the diffusion of mobile ions to the first interlayer insulating layer 4 and the second interlayer insulating layer 15F can be suppressed, and the change in characteristics due to the mobile ions of the semiconductor device 1H can be suppressed.

(Ninth embodiment)
The semiconductor devices described in the first to eighth embodiments can be used as control elements for various electronic devices. By suppressing changes in characteristics as a semiconductor device, it is possible to maintain the original performance of an electronic device for a long time. As an example, an example in which a semiconductor device according to the present invention is used in an electrophoretic display device will be described.

  A cross-sectional view of the electrophoretic display device 100 is shown in FIG. The electrophoretic display device 100 has a structure in which a common electrode substrate 21, an electrophoretic sheet 400, and a driving substrate 22 are stacked. The drive substrate 22 has a plurality of TFTs formed on a predetermined substrate, and an active matrix circuit 23 shown in FIG. 10 is formed by using the plurality of TFTs.

  The active matrix circuit 23 includes a plurality of data lines 301, a plurality of scanning lines 302 arranged in a direction different from the plurality of data lines 301, and intersections of the plurality of data lines 301 and the plurality of scanning lines 302. And a plurality of TFTs 300 formed in the. Any of the semiconductor devices described in the above embodiments can be used as the TFT 300. One of the plurality of data lines 301 is electrically connected to the conductive portion 17 of each TFT 300, and the pixel electrode portion 32 is electrically connected to the conductive portion 18. The position of the electrophoretic particles 34 a and 34 b in the electrophoretic capsule 40 included in the electrophoretic sheet 400 is controlled by an electric field generated between the pixel electrode unit 32 and the common electrode substrate 21, so that the electrophoretic display device 100. It is possible to display various information and images. The electrophoretic particles 34 a and 34 b are dispersed in the liquid phase dispersion medium 35.

(10th Embodiment)
FIG. 11 illustrates an electronic paper 600 as an example of an electronic apparatus using the electrophoretic display device 100.

  In the case of the electronic paper 600, it may be preferable to use a flexible substrate as the substrate 2 in the configuration shown in the first to eighth embodiments. As the flexible substrate, for example, a plastic substrate can be considered. As the plastic substrate, either a thermoplastic resin or a thermosetting resin may be used. For example, polyolefin such as polyethylene, polypropylene, ethylene-propylene copolymer, ethylene-vinyl acetate copolymer (EVA), cyclic polyolefin, modified polyolefin, polyvinyl chloride, polyvinylidene chloride, polystyrene, polyamide, polyimide (PI), Polyamideimide, polycarbonate, poly- (4-methylbenten-1), ionomer, acrylic resin, polymethyl methacrylate, acrylic-styrene copolymer (AS resin), butadiene-styrene copolymer, polio copolymer (EVOH) ), Polyesters such as polyethylene terephthalate (PET), polybutylene terephthalate, polyethylene naphthalate (PEN), precyclohexane terephthalate (PCT), polyethers, polyether ketones Polyethersulfone (PES), polyetherimide, polyacetal, polyphenylene oxide, modified polyphenylene oxide, polyarylate, aromatic polyester (liquid crystal polymer), polytetrafluoroethylene, polyvinylidene fluoride, other fluororesins, styrene, polyolefin Various types of thermoplastic elastomers such as polyvinyl chloride, polyurethane, fluororubber, chlorinated polyethylene, epoxy resin, phenol resin, urea resin, melamine resin, unsaturated polyester, silicone resin, polyurethane, etc. Copolymers, blends, polymer alloys and the like are mentioned, and a laminate obtained by laminating one or more of these can be used.

  Although the semiconductor device of the present invention, the display device including the device, and the electronic apparatus have been described above, the present invention is not limited to these. The present invention can be widely applied without departing from the gist of the present invention.

  DESCRIPTION OF SYMBOLS 1,1A, 1B, 1C, 1D, 1E ... Semiconductor device, 2 ... Board | substrate, 3 ... 3rd blocking layer, 4 ... 1st interlayer insulation layer, 5, 5D ... Source region, 6, 6D ... Drain region, 7, 7D: first low concentration implantation region, 8, 8D: second low concentration implantation region, 9, 9D: channel region, 11, 11A, 11B, 11C, 11D: first blocking layer, 12, 12A, 12B , 12C, 12D ... second blocking layer, 13, 13D ... gate insulating layer, 14, 14A ... gate electrode, 15, 15D ... second interlayer insulating layer, 16, 16E ... fourth blocking layer, 17 ... conductive , 18 ... conductive part, 21 ... common electrode substrate, 22 ... drive substrate, 23 ... active matrix circuit, 32 ... pixel electrode part, 34a ... electrophoretic particles, 35 ... liquid phase dispersion medium, 40 ... electrophoretic capsule, 100 …Electrical Dynamic display device, 300 ... TFT, 301 ... data line, 302 ... scan line, 400 ... electrophoretic sheet, 600 ... electronic paper

Claims (12)

A substrate,
A first insulating layer formed on the substrate;
A semiconductor layer formed on the first insulating layer;
A gate insulating layer formed on the semiconductor layer;
A gate electrode formed on the gate insulating layer;
A first blocking layer;
A second blocking layer,
The semiconductor layer includes a source region, a channel region, a drain region, a first low-concentration implantation region provided in contact with each other between the source region and the channel region, and the drain region and the channel region. A second low-concentration implantation region provided in contact with each other,
The first blocking layer is provided between the gate insulating layer and the first low concentration implantation region,
The second blocking layer is provided between the gate insulating layer and the second low concentration implantation region,
The mobility of mobile ions in the first blocking layer and the mobility of mobile ions in the second blocking layer are smaller than the mobility of mobile ions in the gate insulating layer.   The first blocking layer and the second blocking layer include silicon oxynitride, silicon nitride, aluminum oxide, tantalum oxide, tantalum nitride, tantalum oxynitride, titanium oxide, titanium nitride, and titanium. The semiconductor device according to claim 1, wherein at least one of the oxynitrides is a main material.   3. The semiconductor device according to claim 1, wherein each of the first blocking layer and the second blocking layer has a thickness of 10 nm to 500 nm.   The semiconductor device according to claim 1, further comprising a third blocking layer formed between the substrate and the first insulating layer. A second insulating layer is provided on the gate insulating layer and the gate electrode;
The semiconductor device according to claim 1, wherein a fourth blocking layer is provided on the second insulating layer. A substrate,
A first insulating layer formed on the substrate;
A gate electrode formed on the first insulating layer;
A gate insulating layer formed on the first insulating layer and on the gate electrode;
A first blocking layer formed in part on the gate insulating layer;
A second blocking layer formed in part on the gate insulating layer;
A semiconductor layer formed on the gate insulating layer, on the first blocking layer, and on the second blocking layer;
A second insulating layer formed on the semiconductor layer;
Including
The semiconductor layer includes a source region, a channel region, a drain region, a first low concentration implantation region formed in contact with the source region and the channel region, and a drain region and a channel region. A second low-concentration implantation region formed in contact with each other in between,
The first blocking layer is provided between the gate insulating layer and the first low concentration implantation region,
The second blocking layer is provided between the gate insulating layer and the second low concentration implantation region,
The semiconductor device characterized in that the mobility of mobile ions in the first blocking layer and the mobility of mobile ions in the second blocking layer are smaller than the mobility of mobile ions in the gate insulating layer.   The first blocking layer and the second blocking layer include silicon oxynitride, silicon nitride, aluminum oxide, tantalum oxide, tantalum nitride, tantalum oxynitride, titanium oxide, titanium nitride, and titanium. 7. The semiconductor device according to claim 6, wherein at least one of the oxynitrides is a main material.   The semiconductor device according to claim 6, wherein the first blocking layer and the second blocking layer have a thickness of 10 nm to 2000 nm.   The semiconductor device according to claim 6, further comprising a third blocking layer formed between the substrate and the first insulating layer.   The semiconductor device according to claim 6, further comprising a fourth blocking layer provided on an upper side of the second insulating layer.   A display device comprising the semiconductor device according to claim 1.   An electronic apparatus comprising the display device according to claim 11.

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