JP2017005156A - Semiconductor light-emitting element and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light-emitting element with improved light extraction efficiency compared with the conventional art.SOLUTION: A semiconductor light-emitting element comprises: a first semiconductor layer; an active layer; a second semiconductor layer; a current interruption layer formed so as to be contacted with a surface at a side close to the substrate, of surfaces of the first semiconductor layer; a first electrode formed so as to be contacted with a surface at the side close to the substrate of surfaces of the first semiconductor layer, and in a region where no current interruption layer is formed; and a second electrode contacted with the second semiconductor layer and formed at a position opposed to the current interruption layer with respect to a direction orthogonal to the surface of the substrate. The current interruption layer is configured by an Ag alloy containing at least one of Pd and Cu. A contact resistance between the current interruption layer and the first semiconductor layer is higher than that between the first electrode and the first semiconductor layer.SELECTED DRAWING: Figure 1A

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.

  In recent years, light-emitting elements using nitride semiconductors have been developed. This light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer formed so as to be sandwiched between the n-type semiconductor layer and the p-type semiconductor layer. By providing a potential difference between the n-type semiconductor layer and the p-type semiconductor layer, a current flows between them, and electrons and holes are recombined in the active layer to emit light. Various researches and developments are in progress to effectively use the light generated in the active layer.

  For example, Patent Document 1 below discloses a light-emitting element having a so-called “vertical structure”. An element having a vertical structure refers to an element in which the active layer emits light when a voltage is applied to the active layer in a direction perpendicular to the substrate.

  FIG. 7 schematically shows a cross-sectional view of the light-emitting element disclosed in Patent Document 1. As shown in FIG. A conventional light emitting device 90 includes a conductive layer 92, a reflective film 93, an insulating layer 94, a reflective electrode 95, a semiconductor layer 99, and an n-side electrode 100 on a substrate 91. The semiconductor layer 99 is configured by sequentially stacking a p-type semiconductor layer 96, an active layer 97, and an n-type semiconductor layer 98 from the substrate 91 side.

  A reflective film 93 made of a metal material is formed below the insulating layer 94. However, the reflective film 93 does not have ohmic properties and does not function as an electrode. On the other hand, the reflective electrode 95 is made of a metal material and functions as an electrode (p-side electrode) by realizing ohmic contact between the p-type semiconductor layers 96.

  The reflective electrode 95 reflects light emitted in the direction toward the substrate 91 (downward in the drawing) out of the light generated in the active layer 97 and extracts the light to the n-side semiconductor layer 98 side (upward in the drawing). It also serves the purpose of increasing the take-out efficiency. The reflective film 93 is also formed for the same purpose, and reflects light that travels downward through a portion where the reflective electrode 95 is not formed, and changes the traveling direction to the n-side semiconductor layer 98 side. The take-out efficiency is increased.

Japanese Patent No. 4207781

  However, when the light emitted downward from the active layer 97 is reflected by the reflective film 93 and extracted upward, this light is reflected twice before being reflected by the reflective film 93 and after being reflected. Will pass through. Although the insulating layer 94 is configured as a transparent film, several percent of light is absorbed by the insulating layer 94 when light passes through the insulating layer 94. More specifically, about 3-4% of light is absorbed from the active layer 97 through the insulating layer 94 to reach the reflective film 93, and the light reflected by the reflective film 93 passes through the insulating layer 94. Thus, 3-4% of light is further absorbed before being extracted to the outside on the n-type semiconductor layer 98 side.

  That is, in the conventional configuration, although the light emitted from the active layer 97 is reflected downward to improve the extraction efficiency, a part of the light is absorbed in the insulating layer 94. Therefore, it cannot be said that the extraction efficiency is sufficiently increased.

  In view of the above problems, an object of the present invention is to provide a semiconductor light emitting device with improved light extraction efficiency as compared with the conventional art.

The present invention relates to an n-type or p-type first semiconductor layer, an active layer formed on the first semiconductor layer, and an active layer formed on the active layer and having a conductivity type different from that of the first semiconductor layer. A semiconductor light emitting device in which a semiconductor layer including two semiconductor layers is formed on a substrate,
A current blocking layer formed in contact with the surface of the first semiconductor layer close to the substrate; and
A first electrode formed on the surface of the first semiconductor layer that is close to the substrate and in contact with a surface in a region where the current blocking layer is not formed;
A second electrode formed in a position in contact with the second semiconductor layer and facing the current blocking layer with respect to a direction orthogonal to the surface of the substrate;
The current blocking layer is made of an Ag alloy containing at least one of Pd or Cu,
The contact resistance between the current blocking layer and the first semiconductor layer is higher than the contact resistance between the first electrode and the first semiconductor layer.

  According to the above configuration, it is difficult for current to flow between the current blocking layer and the second electrode in a direction perpendicular to the surface of the substrate, and an effect of spreading the current flowing in the semiconductor layer in a direction parallel to the surface of the substrate is obtained. It is done. As a result, a light emitting region can be provided in a wide range in the active layer, and the light emission efficiency is improved. Further, unlike the semiconductor light emitting device 90 shown in FIG. 7, there is no need to provide an insulating layer for the purpose of spreading current, so that a situation in which light is absorbed in the insulating layer does not occur. As a result, the light extraction efficiency is increased as compared with the conventional light emitting device 90.

  The current blocking layer is made of a material containing Ag. Since Ag exhibits a high reflectance with respect to light emitted from the active layer, it is possible to reflect light emitted from the active layer toward the substrate side with high efficiency to the second semiconductor layer side.

  Furthermore, in said structure, the electric current interruption layer is comprised with the Ag alloy containing at least one of Pd or Cu. When the current blocking layer is made of the above-described Ag alloy, the operating voltage of the element is realized while realizing the Schottky contact with the first semiconductor layer, as compared with the case where the current interruption layer is made of pure Ag. It has been found that the effect of reducing can be obtained. This point will be described later with reference to the examples in the section “DETAILED DESCRIPTION”.

  Therefore, according to said structure, the semiconductor light-emitting device which shows light extraction efficiency higher than before is implement | achieved in the state which lowered the operating voltage.

  In the above configuration, the first electrode may be made of a material containing Ag.

  According to such a configuration, the reflectance with respect to the light emitted from the active layer can be increased in both the first electrode and the current blocking layer, and the light extraction efficiency can be improved. In addition, you may comprise this 1st electrode with the same material as an electric current interruption layer.

  In addition, in the area | region of the edge part of said 1st semiconductor layer, it is good also as what has an insulating layer formed in contact with the surface near the said board | substrate among the surfaces of said 1st semiconductor layer. This insulating layer can function as an etching stopper when manufacturing the semiconductor light emitting device. That is, it is possible to prevent the semiconductor layer from being etched more than necessary, particularly in the etching process related to element isolation.

The present invention relates to an n-type or p-type first semiconductor layer, an active layer formed on the first semiconductor layer, and an active layer formed on the active layer and having a conductivity type different from that of the first semiconductor layer. A semiconductor light emitting device manufacturing method, wherein a semiconductor layer including two semiconductor layers is formed on a substrate,
Forming the semiconductor layer in the order of the second semiconductor layer, the active layer, and the first semiconductor layer;
Forming a first electrode on the first region of the upper surface of the first semiconductor layer (b);
Forming a current blocking layer made of an Ag alloy containing at least one of Pd or Cu in a second region different from the first region on the top surface of the first semiconductor layer;
Adhering the substrate to the upper layer of the first electrode and the current blocking layer and exposing the second semiconductor layer;
Forming a second electrode at a position facing the current blocking layer in a direction orthogonal to the surface of the substrate, of the exposed upper surface of the second semiconductor layer, and (e)
The step (c) is a step of forming the current blocking layer so that a contact resistance with the first semiconductor layer is higher than that of the first electrode formed in the step (b). It is characterized by.

  According to the above method, it is possible to manufacture a semiconductor light emitting device that exhibits a higher light extraction efficiency than the conventional one with a lower operating voltage.

  In the above method, the step (b) includes a step of performing an annealing process after forming a metal material, and the step (c) is performed at a lower temperature than the step (b) after forming the Ag alloy. It may include a step of performing an annealing process at or without performing an annealing process.

  Further, the metal material formed in the step (b) may contain Ag.

In the above method, before the step (d), a step (f) of forming an insulating layer in an end region of the upper surface of the first semiconductor layer;
A step (g) of etching the semiconductor layer until the insulating layer is exposed after the step (d) may be included.

  The insulating layer manufactured in the step (f) can function as an etching stopper in the element isolation step according to the step (g), and the semiconductor layer can be prevented from being etched more than necessary.

  According to the present invention, a semiconductor light emitting device with higher light extraction efficiency than the conventional one can be realized without increasing the operating voltage.

It is drawing which shows typically the structure of one Embodiment of a semiconductor light-emitting device. It is drawing which shows typically the structure of one Embodiment of a semiconductor light-emitting device. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a part of process sectional drawing which shows the manufacturing method of a semiconductor light-emitting device typically. It is a graph which shows the current-voltage characteristic between a current interruption layer and a p-type semiconductor layer. It is the graph which contrasted the current-voltage characteristic of the light emitting element of an Example and a reference example. It is drawing which shows typically the structure of another embodiment of a semiconductor light-emitting device. It is drawing which shows typically the structure of another embodiment of a semiconductor light-emitting device. 1 is a diagram schematically illustrating a configuration of a conventional light emitting device.

The nitride semiconductor light emitting device of the present invention will be described with reference to the drawings. In each figure, the dimensional ratio in the drawing does not necessarily match the actual dimensional ratio. In the following, the description “AlGaN” is synonymous with the description Al _m Ga _1-m N (0 <m <1), and the description of the composition ratio of Al and Ga is simply omitted. And it is not the meaning limited to the case where the composition ratio of Al and Ga is 1: 1. The same applies to the description “InGaN”.

[Constitution]
1A and 1B are drawings schematically showing a configuration of an embodiment of a semiconductor light emitting device of the present invention. 1B corresponds to a plan view when viewed from the light extraction direction, and FIG. 1A corresponds to a cross-sectional view taken along line XX in FIG. 1B. The semiconductor light emitting device 1 includes a substrate 3, a semiconductor layer 5, a first electrode 13, a current blocking layer 14, and a second electrode 15. Hereinafter, the semiconductor light emitting element 1 is simply abbreviated as “light emitting element 1” as appropriate.

(Substrate 3)
The substrate 3 is composed of a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si.

(Semiconductor layer 5)
In this embodiment, the semiconductor layer 5 is formed by sequentially stacking a p-type semiconductor layer 11, an active layer 9, and an n-type semiconductor layer 7 from the side close to the substrate 3. In the present embodiment, the p-type semiconductor layer 11 corresponds to a “first semiconductor layer”, and the n-type semiconductor layer 7 corresponds to a “second semiconductor layer”.

  The p-type semiconductor layer 11 is composed of a nitride semiconductor layer doped with a p-type impurity such as Mg, Be, Zn, or C, for example. As the nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN, or the like can be used.

  The active layer 9 is formed of a semiconductor layer in which, for example, a light emitting layer made of InGaN and a barrier layer made of n-type AlGaN are periodically repeated. These layers may be undoped or p-type or n-type doped. The active layer 9 only needs to be configured by laminating layers made of at least two kinds of materials having different energy band gaps. The constituent material of the active layer 9 is appropriately selected according to the wavelength of light to be generated.

  The n-type semiconductor layer 7 is composed of a nitride semiconductor layer doped with an n-type impurity such as Si, Ge, S, Se, Sn, or Te. As this nitride semiconductor layer, for example, GaN, AlGaN, AlInGaN or the like can be used. The n-type semiconductor layer 7 may be made of a material having a composition different from that of the p-type semiconductor layer 11.

(First electrode 13)
The first electrode 13 is formed in contact with the p-type semiconductor layer 11, and ohmic contact is formed with the p-type semiconductor layer 11. In the present embodiment, the first electrode 13 constitutes a p-side electrode.

  In the present embodiment, the first electrode 13 is made of a conductive material exhibiting a high reflectance (for example, 80% or more, more preferably 90% or more) with respect to light emitted from the active layer 9. . More specifically, it is made of a material containing, for example, Ag, Al, or Rh.

(Second electrode 15)
The second electrode 15 is formed on the upper surface of the n-type semiconductor layer 7 and is made of, for example, Cr—Au. In the present embodiment, the second electrode 15 constitutes an n-side electrode.

  As shown in FIG. 1B, in the light emitting device 1 of this embodiment, the second electrode 15 surrounds the n-type semiconductor layer 7 when viewed from the side opposite to the substrate 3, that is, from the light extraction direction. Is formed. More specifically, the second electrode 15 is configured to extend in a predetermined direction at three spaced locations. However, the number of the second electrodes 15 to be stretched is not limited to three, and may be four or more. The shape of the second electrode 15 shown in FIG. 1B is merely an example, and may be appropriately changed according to the design.

  In the example shown in FIG. 1B, the second electrode 15 has a wide region 15a as viewed from the light extraction direction in some portions. The region 15a may be configured as a pad electrode by connecting a wire (not shown) made of, for example, Au or Cu. At this time, the other end of the wire may be connected to a power feeding pattern of the substrate 3 or the like. Note that the second electrode 15 does not necessarily have to include the wide region 15a.

  By applying a voltage between the first electrode 13 and the second electrode 15, a current flows in the active layer 9 and the active layer 9 emits light.

  As described above, the first electrode 13 is made of a material that exhibits a high reflectance with respect to the light generated in the active layer 9. The light-emitting element 1 shown in FIG. 1A is assumed to extract light emitted from the active layer 9 to the n-type semiconductor layer 7 side. The first electrode 13 functions to improve the light extraction efficiency by reflecting light emitted from the active layer 9 toward the substrate 3 toward the n-type semiconductor layer 7.

(Conductive layer 20)
The conductive layer 20 is formed on the upper layer of the substrate 3. In the present embodiment, the conductive layer 20 has a multilayer structure of a protective layer 23, a bonding layer 21, a bonding layer 19, and a protective layer 17.

  The bonding layer 19 and the bonding layer 21 are made of, for example, Au—Sn, Au—In, Au—Cu—Sn, Cu—Sn, Pd—Sn, Sn, or the like. As will be described later, the bonding layer 19 and the bonding layer 21 make the bonding layer 21 formed on the substrate 3 and the bonding layer 19 formed on another substrate (a growth substrate 25 described later) face each other. Later, they were formed by bonding them together. The bonding layer 19 and the bonding layer 21 may be integrated as a single layer.

  The protective layer 17 has a multilayer structure of Ni / Ti / Pt, for example. Among these, the Ti / Pt layer is provided for the purpose of suppressing the material constituting the bonding layer (19, 21) from diffusing to the first electrode 13 side and reducing the reflectance of the first electrode 13. Yes. The Ni layer is provided for the purpose of suppressing the material contained in the Ti / Pt layer, particularly Ti, from diffusing to the first electrode 13 side and the reflectance of the first electrode 13 from decreasing. However, the protective layer 17 should just be comprised with the material which has a function which suppresses that the material which comprises a joining layer (19, 21) diffuses at least.

  The protective layer 23 is made of the same material as that of the protective layer 17, for example, and is provided for the purpose of suppressing the material constituting the bonding layers (19, 21) from diffusing to the substrate 3 side. However, the protective layer 23 may not necessarily be provided.

(Current blocking layer 14)
The light emitting element 1 includes a current blocking layer 14. The current blocking layer 14 is in contact with the p-type semiconductor layer 11 and is formed in at least a part of a region where the first electrode 13 is not formed. In the present embodiment, the current blocking layer 14 is made of an Ag alloy containing Pd and Cu, and is a material that exhibits a high reflectance with respect to light emitted from the active layer 9, as with the first electrode 13. It is configured.

  As shown in FIG. 1A, both the first electrode 13 and the current blocking layer 14 are formed in contact with the p-type semiconductor layer 11. As described above, the first electrode 13 is in ohmic contact with the p-type semiconductor layer 11. On the other hand, the current blocking layer 14 is in Schottky contact with the p-type semiconductor layer 11, and has a higher contact resistance with the p-type semiconductor layer 11 than the first electrode 13.

  The current blocking layer 14 is formed at a position facing the second electrode 15 in a direction orthogonal to the surface of the substrate 3 (hereinafter referred to as “vertical direction” as an example). If a layer having a low contact resistance with the p-type semiconductor layer 11 is formed at a position facing the second electrode 15 in the vertical direction, when a voltage is applied to the light emitting element 1, the second in the vertical direction. Most of the current flows in a region facing the electrode 15. As a result, only a specific region of the active layer 9 emits light, and the light emission efficiency decreases. The current blocking layer 14 has a function of increasing the luminous efficiency of the active layer 9 by spreading the current flowing through the active layer 9 in a direction parallel to the surface of the substrate 3.

  Further, as in the present embodiment, the current blocking layer 14 is formed of a material having a high reflectance with respect to the light generated in the active layer 9, so that the light blocking layer 14 can be used for the same reason as the first electrode 13. The extraction efficiency can be improved.

(Insulating layer 24)
In the present embodiment, the light emitting element 1 includes an insulating layer 24 formed in contact with a part of the p-type semiconductor layer 11 in the end region of the semiconductor layer 5. Insulating layer 24 is composed for example _{SiO 2, SiN, Zr 2 O} 3, AlN, etc. Al ₂ O _3. The insulating layer 24 is provided for the purpose of functioning as an etching stopper during element isolation, as will be described later in the section of the manufacturing method.

  Although not shown in FIG. 1A, an insulating layer as a protective film may be formed on the side surface of the semiconductor layer 5.

  According to the light emitting element 1 shown in FIG. 1A, the point that the light extraction efficiency is improved as compared with the conventional case will be described after the method for manufacturing the light emitting element 1 is described.

[Production method]
Next, an example of a method for manufacturing the light-emitting element 1 will be described with reference to process cross-sectional views schematically shown in FIGS. 2A to 2J. In addition, dimensions such as manufacturing conditions and film thickness described below are merely examples.

(Step S1)
As shown in FIG. 2A, a growth substrate 25 is prepared. As an example of the growth substrate 25, a sapphire substrate having a C-plane can be used.

  As a preparation step, the growth substrate 25 is cleaned. As a more specific example of this cleaning, a growth substrate 25 is disposed in a processing furnace of a MOCVD (Metal Organic Chemical Vapor Deposition) apparatus, and hydrogen having a flow rate of, for example, 10 slm is placed in the processing furnace. While flowing the gas, the temperature in the furnace is raised to, for example, 1150 ° C.

(Step S2)
As shown in FIG. 2B, an undoped layer 27, an n-type semiconductor layer 7, an active layer 9, and a p-type semiconductor layer 11 are sequentially formed on the growth substrate 25. This step S2 is performed by the following procedure, for example.

  First, a low-temperature buffer layer made of GaN is formed on the upper surface of the growth substrate 25, and an underlayer made of GaN is formed thereon. These low-temperature buffer layer and underlayer correspond to the undoped layer 27. A specific method for forming the undoped layer 27 is, for example, as follows.

  First, the furnace pressure of the МОCVD apparatus is 100 kPa, and the furnace temperature is 480 ° C. Then, while flowing nitrogen gas and hydrogen gas with a flow rate of 5 slm respectively as carrier gas into the processing furnace, trimethylgallium (TMG) with a flow rate of 50 μmol / min and ammonia with a flow rate of 250,000 μmol / min are used as the raw material gas in the processing furnace. For 68 seconds. Thereby, a low-temperature buffer layer made of GaN having a thickness of 20 nm is formed on the surface of the growth substrate 25.

  Next, the furnace temperature of the MOCVD apparatus is raised to 1150 ° C. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas in the processing furnace, TMG having a flow rate of 100 μmol / min and ammonia having a flow rate of 250,000 μmol / min are introduced into the processing furnace as source gases. Feed for 30 minutes. As a result, a base layer made of GaN having a thickness of 1.7 μm is formed on the surface of the low-temperature buffer layer.

  Next, the n-type semiconductor layer 7 is formed on the undoped layer 27. A specific method for forming the n-type semiconductor layer 7 is, for example, as follows.

First, with the furnace temperature kept at 1150 ° C., the furnace pressure of the MOCVD apparatus is set to 30 kPa. Then, while flowing nitrogen gas having a flow rate of 20 slm and hydrogen gas having a flow rate of 15 slm as a carrier gas into the processing furnace, TMG having a flow rate of 94 μmol / min, trimethylaluminum (TMA) having a flow rate of 6 μmol / min, Ammonia with a flow rate of 250,000 μmol / min and tetraethylsilane with a flow rate of 0.013 μmol / min are supplied into the treatment furnace for 60 minutes. Thereby, for example, an n-type semiconductor layer 7 having a composition of Al _0.06 Ga _0.94 N and a thickness of 2 μm is formed on the undoped layer 27.

  After this, the supply of TMA is stopped, and other source gases are supplied for 6 seconds, thereby having a protective layer made of n-type GaN having a thickness of about 5 nm on the n-type AlGaN layer. An n-type semiconductor layer 7 may be realized.

  In the above description, the case where Si is used as the n-type impurity contained in the n-type semiconductor layer 7 has been described. However, as the n-type impurity, Ge, S, Se, Sn, Te, or the like can be used in addition to Si. .

  Next, an active layer 9 is formed on the n-type semiconductor layer 7. A specific method for forming the active layer 9 is, for example, as follows.

  First, the furnace pressure of the MOCVD apparatus is 100 kPa, and the furnace temperature is 830 ° C. Then, while flowing nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 1 slm as a carrier gas in the processing furnace, TMG having a flow rate of 10 μmol / min, trimethylindium (TMI) having a flow rate of 12 μmol / min, and A step of supplying ammonia at a flow rate of 300,000 μmol / min into the processing furnace for 48 seconds is performed. Thereafter, TMG having a flow rate of 10 μmol / min, TMA having a flow rate of 1.6 μmol / min, tetraethylsilane having a flow rate of 0.002 μmol / min, and ammonia having a flow rate of 300,000 μmol / min are supplied into the processing furnace for 120 seconds. Hereinafter, by repeating these two steps, an active layer 9 in which a light-emitting layer made of InGaN having a thickness of 2 nm and a barrier layer made of n-type AlGaN having a thickness of 7 nm are stacked for 15 periods is formed into an n-type semiconductor layer. 7 is formed on the upper layer.

  Next, the p-type semiconductor layer 11 is formed on the active layer 9. A specific method for forming the p-type semiconductor layer 11 is, for example, as follows.

Specifically, the furnace pressure of the MOCVD apparatus is maintained at 100 kPa, and the furnace temperature is raised to 1025 ° C. while nitrogen gas having a flow rate of 15 slm and hydrogen gas having a flow rate of 25 slm are supplied as carrier gases in the processing furnace. To do. Thereafter, as source gases, TMG with a flow rate of 35 μmol / min, TMA with a flow rate of 20 μmol / min, ammonia with a flow rate of 250,000 μmol / min, and biscyclopentadiene with a flow rate of 0.1 μmol / min for doping p-type impurities. Enilmagnesium (Cp ₂ Mg) is fed into the processing furnace for 60 seconds. Thereby, a hole supply layer having a composition of Al _0.3 Ga _0.7 N having a thickness of 20 nm is formed on the surface of the active layer 33. Thereafter, by changing the flow rate of TMA to 4 μmol / min and supplying the source gas for 360 seconds, a hole supply layer having a composition of Al _0.13 Ga _0.87 N having a thickness of 120 nm is formed. A p-type semiconductor layer 11 is formed by these hole supply layers.

After this step, the supply of TMA is stopped, the flow rate of CP ₂ Mg is changed to 0.2 μmol / min, and the source gas is supplied for 20 seconds, so that the thickness is about 5 nm and the p-type impurity concentration is increased. However, a p-type semiconductor layer 11 having a p-type GaN layer of about 1 × 10 ²⁰ / cm ³ may be realized.

  This step S2 corresponds to the step (a).

(Step S3)
An activation process is performed on the wafer obtained in step S2. As a specific example, an activation process is performed at 650 ° C. for 15 minutes in a nitrogen atmosphere using an RTA (Rapid Thermal Anneal) apparatus.

(Step S4)
An insulating layer 24 is formed at a predetermined location on the upper surface of the p-type semiconductor layer 11 (see FIG. 2C).

More specifically, the insulating layer 24 is formed by forming, for example, Al ₂ O ₃ with a film thickness of about 200 nm on the upper surface of the p-type semiconductor layer 11 in a region serving as a boundary with an adjacent element by a sputtering method. Form. It should be noted that the material to be deposited may be an insulating material, and may be SiN or SiO _{2 in} addition to Al ₂ O ₃ .

  This step S4 corresponds to the step (f).

(Step S5)
The first electrode 13 is formed in a predetermined region on the upper surface of the p-type semiconductor layer 11 (see FIG. 2C). A specific method for forming the first electrode 13 is, for example, as follows.

  A material film made of a conductive material is formed in a predetermined region on the upper surface of the p-type semiconductor layer 11. As an example, Ag having a thickness of about 150 nm and Ni having a thickness of about 3 nm are formed in a predetermined region on the upper surface of the p-type semiconductor layer 11 by sputtering.

  Here, Ag contained in the material film is an example of a material exhibiting a high reflectance (90% or more) with respect to light emitted from the active layer 9 included in the light emitting element 1. A material other than Ag (for example, Al, Rh, etc.) may be included as long as it is a material that exhibits high reflectance with respect to light emitted from the active layer 9. Moreover, you may be comprised with the alloy containing the material which shows these high reflectances.

  In addition, Ni contained in the material film is formed for the purpose of improving the adhesion with other layers. However, if sufficient adhesion is ensured, Ni may not be included in the material film. It doesn't matter. In addition, other materials for ensuring adhesion may be included.

  After the material film is formed, a contact annealing process is performed, for example, at 400 ° C. to 550 ° C. for 60 seconds to 300 seconds in an atmosphere of dry air or inert gas using an RTA apparatus or the like. Thereby, the first electrode 13 in which an ohmic contact is formed with the p-type semiconductor layer 11 is formed.

  Step S5 corresponds to step (b). This step S5 may be performed before step S4.

(Step S6)
Next, the current blocking layer 14 is formed in the region where the p-type semiconductor layer 11 is exposed (see FIG. 2D).

  As a more specific example, an Ag alloy containing Cu and Pd is formed with a film thickness of about 200 nm by a sputtering method as in step S5. As an example, the concentration of Cu contained in the Ag alloy is about 1%, and the concentration of Pd is about 1%. By including Cu in Ag, the oxidation resistance and sulfidation resistance of Ag are improved. By including Pd in Ag, the adhesion to the p-type semiconductor layer 11 is improved. However, when Cu and Pd are excessively contained, the reflectance of the Ag alloy is reduced. Therefore, the concentration of Cu contained in the Ag alloy is preferably 0% or more and 0.5% or less, and the concentration of Pd contained in the Ag alloy is preferably 0% or more and 1% or less. In order to improve the adhesion between the current blocking layer 14 and the p-type semiconductor layer 11, a thin Ni film having a thickness of about 3 nm may be formed together with the Ag alloy.

  Then, annealing is performed at a lower temperature than in step S5, or annealing is not performed. Thereby, the material film formed in this step forms a Schottky contact with the p-type semiconductor layer 11. Thereby, the current interruption layer 14 is formed.

  In step S5, the first electrode 13 may be formed by depositing the same material as the material deposited in step S6.

  This step S6 corresponds to the step (c).

(Step S7)
A protective layer 17 is formed on the entire surface so as to cover the upper surfaces of the first electrode 13 and the current blocking layer 14. Thereafter, the bonding layer 19 is formed on the upper surface of the protective layer 17 (see FIG. 2E). An example of a specific method is as follows.

  First, the protective layer 17 is formed by depositing 100 nm of Ti and 200 nm of Pt for three periods using an electron beam evaporation apparatus (EB apparatus). After that, Ti having a thickness of 10 nm is vapor-deposited on the upper surface (Pt surface) of the protective layer 17, and then a bonding layer 19 is formed by vapor-depositing Au-Sn solder composed of 80% Sn20% with a thickness of 3 μm. To do.

(Step S8)
A protective layer 23 and a bonding layer 21 are formed on the upper surface of the substrate 3 prepared separately from the growth substrate 25 by the same method as in step S7 (see FIG. 2F). As the substrate 3, as described above, a conductive substrate such as CuW, W, or Mo, or a semiconductor substrate such as Si can be used. The protective layer 23 may not be formed.

(Step S9)
As shown in FIG. 2G, the growth substrate 25 and the substrate 3 are bonded together by bonding the bonding layer 19 formed on the upper layer of the growth substrate 25 and the bonding layer 21 formed on the upper layer of the substrate 3. As a specific example, the bonding process is performed at a temperature of 280 ° C. and a pressure of 0.2 MPa.

  By this process, the bonding layer 19 and the bonding layer 21 are melted and bonded to form a structure in which the substrate 3 and the growth substrate 25 are bonded to the front and back surfaces. That is, the bonding layer 19 and the bonding layer 21 may be integrated after this step. And since the protective layer 23 and the protective layer 17 are formed in the stage before execution of this step S9, the spreading | diffusion of the structural material of a joining layer (19, 21) is suppressed.

(Step S10)
Next, the growth substrate 25 is peeled off (see FIG. 2H). More specifically, laser light is irradiated from the growth substrate 25 side with the growth substrate 25 facing upward and the substrate 3 facing downward. Here, the laser beam to be irradiated is light having a wavelength that transmits the constituent material of the growth substrate 25 (sapphire in this embodiment) and is absorbed by the constituent material of the undoped layer 27 (GaN in this embodiment). . As a result, the laser light is absorbed by the undoped layer 27, so that the interface between the growth substrate 25 and the undoped layer 27 is heated to decompose GaN, and the growth substrate 25 is peeled off.

  Thereafter, GaN (undoped layer 27) remaining on the wafer is removed by wet etching using hydrochloric acid or the like, or dry etching using an ICP apparatus, and the n-type semiconductor layer 7 is exposed. In this step S10, the undoped layer 27 is removed, and the semiconductor layer 5 in which the p-type semiconductor layer 11, the active layer 9, and the n-type semiconductor layer 7 are stacked in this order from the substrate 3 side remains (FIG. 2I).

  Steps S9 and S10 correspond to step (d).

(Step S11)
Next, as shown in FIG. 2J, adjacent elements are separated from each other. Specifically, the semiconductor layer 5 is etched using the ICP apparatus until the upper surface of the insulating layer 24 is exposed in the boundary region with the adjacent element. At this time, as described above, the insulating layer 24 functions as an etching stopper.

  In FIG. 2J, the side surface of the semiconductor layer 5 is illustrated as being inclined with respect to the vertical direction. However, this is an example, and the present invention is not limited to such a shape.

  This step S11 corresponds to the step (g).

(Step S12)
Next, a predetermined region on the upper surface of the n-type semiconductor layer 7, more specifically, a part of the upper surface of the n-type semiconductor layer 7 that does not face the first electrode 13 in the vertical direction, that is, current blocking. The second electrode 15 is formed in a part of the region facing the layer 14 in the vertical direction. As an example of a specific method, a film thickness of 100 nm is formed on the upper surface of the n-type semiconductor layer 7 in a state where a region other than the region where the second electrode 15 is to be formed is masked with a resist or the like. Cr and 3 μm thick Au are vapor-deposited. Thereafter, the mask is peeled off, and annealing is performed at 250 ° C. for about 1 minute in a nitrogen atmosphere.

  This step S12 corresponds to the step (e).

(Step S13)
Next, the elements are separated from each other by, for example, a laser dicing apparatus, and the back surface of the substrate 3 is joined to the package by, for example, Ag paste. Thereafter, wire bonding is performed on a partial region of the second electrode 15. Through the above steps, the light emitting device 1 shown in FIG. 1A is manufactured.

[Action]
According to the light emitting element 1 shown in FIG. 1A, as described above, by providing the current blocking layer 14, a current can flow through a wide range in the active layer 9, and the light emission efficiency is improved. Since the current blocking layer 14 can realize the effect of expanding the current, it is not necessary to provide the insulating layer 94 for the purpose of expanding the current unlike the light emitting element 90 shown in FIG.

  As a result, the light emitted from the active layer 9 toward the substrate 3 is insulated by configuring the first electrode 13 and the current blocking layer 14 with a material having a high reflectance with respect to the light emitted from the active layer 9. The light can be reflected toward the light extraction surface (n-type semiconductor layer 7) without passing through the layer. As a result, the light extraction efficiency is improved as compared with the conventional case.

  Further, like the light-emitting element 1, the current blocking layer 14 is made of an Ag alloy containing Pd and Cu, so that the operation of the light-emitting element 1 is achieved while realizing Schottky contact with the p-type semiconductor layer 11. The effect of reducing the voltage can be obtained.

  FIG. 3 is a graph showing the current-voltage characteristics between the current blocking layer 14 and the p-type semiconductor layer 11. In FIG. 3, an Ag alloy containing Pd and Cu is formed on the upper surface of the p-type semiconductor layer 11 made of AlGaN at two locations with a separation, and then the annealing treatment is not performed. It is the graph obtained by applying a voltage between Ag alloys formed in <5>, and measuring current-voltage characteristics. In addition, the film formation method of Ag alloy employ | adopts the method similar to step S6. Here, the distance between the Ag alloys provided at two locations was set to 5 μm.

  In addition, for the purpose of further approximating the situation of Step S6 when actually manufacturing the light emitting element 1, heat treatment at about 450 ° C. was performed in the same manner as Step S5 before the Ag alloy film was formed.

  According to FIG. 3, it can be seen that the current-voltage characteristic exhibits nonlinearity and Schottky contact is realized. Thereby, it can be seen that the Schottky contact can be realized between the current blocking layer 14 and the p-type semiconductor layer 11 also in the light-emitting element 1 manufactured by the above-described manufacturing method. That is, the contact resistance between the current blocking layer 14 and the p-type semiconductor layer 11 can be made higher than the contact resistance between the first electrode 13 and the p-type semiconductor layer 11.

  FIG. 4 is a graph comparing the current-voltage characteristics of the light emitting elements in the example and the reference example. An Example respond | corresponds to the light emitting element 1 manufactured through steps S1-S13 mentioned above. In the example, both the first electrode 13 and the current blocking layer 14 were formed of an Ag alloy containing Pd and Cu.

  The reference example is different in that the current blocking layer 14 made of pure Ag is formed in step S6. In the reference example, the first electrode 13 was also formed of pure Ag.

  According to FIG. 4, it can be seen that the voltage required for flowing the same current in the example can be reduced as compared with the reference example. For example, looking at the voltage required to pass a current of 1 A, the reference example requires the application of a voltage of about 4.3 V, whereas the embodiment can be realized by applying a voltage of about 3.8 V. Yes.

  Although not shown in the graph of FIG. 4, in the example, an element manufactured by configuring the material of the first electrode 13 with pure Ag has substantially the same current-voltage characteristics as in the example. It was confirmed that

  According to the above, it can be seen that the effect of reducing the operating voltage of the light emitting element can be obtained by configuring the current blocking layer 14 with an Ag alloy containing Pd and Cu instead of pure Ag. This is presumably due to the following reasons.

  Pd is a material having higher adhesion than Ag. For this reason, it is speculated that by mixing Pd with Ag, the adhesion with the p-type semiconductor layer 11 is increased and the contact resistance is decreased. Further, since both Pd and Cu are materials having a work function larger than that of Ag, the contact property with the p-type semiconductor layer 11 is improved and the contact resistance is decreased as compared with the case of pure Ag. Conceivable. Even in this case, as described above with reference to FIG. 3, since the Schottky contact is formed between the current blocking layer 14 and the p-type semiconductor layer 11, the current is parallel to the surface of the substrate 3. A function that expands in the direction is realized.

  In addition, when oxidation or sulfidation occurs in Ag, the reflectance decreases. Since Cu has a function of improving oxidation resistance and sulfidation resistance with respect to pure Ag, it also has a function of suppressing a decrease in reflectance by mixing Cu. Therefore, from the viewpoint of further improving the light extraction efficiency, not only the current blocking layer 14 but also the first electrode 13 is preferably composed of an Ag alloy.

[Another embodiment]
Hereinafter, another embodiment will be described.

  <1> In the above embodiment, the current blocking layer 14 has been described as being composed of an Ag alloy containing Pd and Cu, but may be composed of an Ag alloy containing either Pd or Cu. I do not care. Even in the case of containing either Pd or Cu, the effect of lowering the operating voltage can be obtained as compared with the case of comprising pure Ag.

  <2> In the above-described embodiment, the first electrode 13 is thinner than the current blocking layer 14 and the insulating layer 24, and a part of the current blocking layer 14 is buried under the first electrode 13 (FIG. 1A). Reference) was described as an example. However, the relationship among the thicknesses of the first electrode 13, the current blocking layer 14, and the insulating layer 24 may be appropriately set according to the design.

  For example, as in the structure shown in FIG. 5, the first electrode 13 and the current blocking layer 14 are configured to have substantially the same thickness, and the insulating layer 24 is thinner than the current blocking layer 14. The portion may be embedded in the lower layer of the insulating layer 24. Further, as in the structure shown in FIG. 6, the thicknesses of the first electrode 13, the current blocking layer 14, and the insulating layer 24 are substantially equal, and all the layers are adjacent only in the direction parallel to the surface of the substrate 3. Thus, a configuration that is not adjacent to the direction orthogonal to the surface of the substrate 3 may be employed.

  <3> In the light emitting device 1 shown in FIG. 1A, FIG. 5, or FIG. 6, a fine uneven shape may be formed on the upper surface of the n-type semiconductor layer 7 in order to further improve the light extraction efficiency.

  <4> In the above-described embodiment, among the layers constituting the semiconductor layer 5, the side near the substrate 3 is described as the p-type semiconductor layer 11, and the side far from the substrate 3 is described as the n-type semiconductor layer 7. You may invert the mold.

  <5> In the above embodiment, the light-emitting element 1 has been described as including the protective layer 17, but the protective layer 17 does not necessarily have to be provided. However, since it can suppress that the reflectance of the 1st electrode 13 and the electric current interruption layer 14 falls by providing the protective layer 17, in order to implement | achieve high light extraction efficiency continuously, a protective layer 17 is preferably provided.

DESCRIPTION OF SYMBOLS 1: Semiconductor light emitting element 3: Substrate 7: N-type semiconductor layer 9: Active layer 11: P-type semiconductor layer 13: First electrode 14: Current blocking layer 15: Second electrode 15a: Pad electrode 17: Protective layer 19: Junction Layer 20: Conductive layer 21: Bonding layer 23: Protective layer 25: Growth substrate 27: Undoped layer 90: Conventional light emitting device 91: Substrate 92: Conductive layer 93: Reflective film 94: Insulating layer 95: Reflective electrode 96: P-type Semiconductor layer 97: active layer 98: n-type semiconductor layer 99: semiconductor layer 100: n-side electrode

Claims (7)

an n-type or p-type first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer and having a conductivity type different from that of the first semiconductor layer. A semiconductor light-emitting element comprising a semiconductor layer formed on a substrate,
A current blocking layer formed in contact with the surface of the first semiconductor layer close to the substrate; and
A first electrode formed on the surface of the first semiconductor layer that is close to the substrate and in contact with a surface in a region where the current blocking layer is not formed;
A second electrode formed in a position in contact with the second semiconductor layer and facing the current blocking layer with respect to a direction orthogonal to the surface of the substrate;
The current blocking layer is made of an Ag alloy containing at least one of Pd or Cu,
A semiconductor light emitting element, wherein a contact resistance between the current blocking layer and the first semiconductor layer is higher than a contact resistance between the first electrode and the first semiconductor layer.   The semiconductor light emitting element according to claim 1, wherein the first electrode is made of a material containing Ag.   3. The insulating layer formed in contact with the surface of the first semiconductor layer close to the substrate in the region of the end portion of the first semiconductor layer. 4. The semiconductor light-emitting device described in 1. an n-type or p-type first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer and having a conductivity type different from that of the first semiconductor layer. A semiconductor light emitting device manufacturing method in which a semiconductor layer containing is formed on a substrate,
Forming the semiconductor layer in the order of the second semiconductor layer, the active layer, and the first semiconductor layer;
Forming a first electrode on the first region of the upper surface of the first semiconductor layer (b);
Forming a current blocking layer made of an Ag alloy containing at least one of Pd or Cu in a second region different from the first region on the top surface of the first semiconductor layer;
Adhering the substrate to the upper layer of the first electrode and the current blocking layer and exposing the second semiconductor layer;
Forming a second electrode at a position facing the current blocking layer in a direction orthogonal to the surface of the substrate, of the exposed upper surface of the second semiconductor layer, and (e)
The step (c) is a step of forming the current blocking layer so that a contact resistance with the first semiconductor layer is higher than that of the first electrode formed in the step (b). A method for manufacturing a semiconductor light emitting device. The step (b) includes a step of performing an annealing treatment after forming a metal material into a film,
5. The step (c) includes a step of performing an annealing process at a lower temperature than the step (b) after forming the Ag alloy film, or the annealing process is not performed. Manufacturing method of the semiconductor light-emitting device.   6. The method for manufacturing a semiconductor light emitting element according to claim 5, wherein the metal material formed in the step (b) contains Ag. Before the step (d), a step (f) of forming an insulating layer in a region of an end portion of the upper surface of the first semiconductor layer;
A semiconductor light emitting device according to claim 4, further comprising a step (g) of etching the semiconductor layer until the insulating layer is exposed after the step (d). Manufacturing method.

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