JP2016220154A - Image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image display device capable of enhancing visibility gradation for an image quality effect image in frame rate conversion processing.SOLUTION: An image display device 100 includes a frame rate conversion processor 130 and a sub-frame division processor 140, an image data selector 150, and a display 170. The frame rate conversion processor 130 outputs image data of Y bit gradation by N times of the input frame rate M. The sub-frame division processor 140 divides the image data of Y+logN bit gradation into N subframes becoming the image data of Y bit, and outputs in order by N times of the input frame rate M. The selector 150 switches the output of the frame rate conversion processor 130 and the output image data of the sub-frame division processor 140, and outputs to the display 170 by frame rate of M×N.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to an image display apparatus that performs image processing on image data and displays the image data.

  In recent years, image display devices capable of displaying at a high frame rate have been introduced for the purpose of improving moving image performance. These increase the number of frames of the moving image by frame rate conversion processing by frame interpolation using the motion vector between successive frames of the input image signal, thereby generating a smoother moving image with less afterimage. Yes. For example, a technique for converting an input moving image of 60 frames per second (60 Hz) into a moving image of 240 frames (240 Hz) four times through frame rate conversion processing has been put into practical use. Such a technique is disclosed in Patent Document 1 and Patent Document 2, for example.

JP 2009-71842 A JP 2009-21868 A

  In the present disclosure, there is no difference in the images generated by the interpolation by the frame rate conversion process. An image display device capable of improving tonality is provided.

  An image display device according to an embodiment of the present disclosure is an image display device for displaying an image on a display, and an image signal having a high frame rate is obtained by frame interpolation of an input terminal that receives an image signal and an image signal supplied from the input terminal. A frame rate conversion processor that converts and outputs an image signal supplied from an input terminal into a plurality of subframes, and outputs a frame at the same frame rate as the frame rate conversion processor; A selector is provided for selecting either the output of the frame rate conversion processor or the subframe division processor and outputting the selected output to the display.

The image display device according to the present disclosure realizes improvement in moving image performance by frame rate conversion in a portion with a large amount of motion, while a still image, an image with little motion, or a region with little motion corresponds to the number of displayable gradations 2 ^Y. Thus, the number of gradations corresponding to N times can be expressed by a time integration effect, and the gradation is improved.

1 is a block diagram illustrating a configuration of an image display device according to an embodiment The block diagram which shows the structure of the sub-frame division | segmentation processor of the image display apparatus in embodiment The figure which shows the gradation of the input of a sub-frame division | segmentation processor at the time of the 4 time speed drive in an embodiment, and the gradation of an output sub-frame The figure which shows the image of the input image signal of the sub-frame division | segmentation processor in an embodiment, an output image signal, and a visual recognition image The figure which shows the gradation / the number of gradations which can be expressed by the sub-frame division | segmentation processor in embodiment The figure which shows the image selection in the selector part in embodiment The figure for demonstrating the effect of embodiment

  Hereinafter, embodiments will be described in detail with reference to the drawings as appropriate. However, more detailed description than necessary may be omitted. For example, detailed descriptions of already well-known matters and repeated descriptions for substantially the same configuration may be omitted. This is to avoid the following description from becoming unnecessarily redundant and to facilitate understanding by those skilled in the art.

  The accompanying drawings and the following description are provided to enable those skilled in the art to fully understand the present disclosure, and are not intended to limit the subject matter described in the claims.

(Embodiment)
Hereinafter, embodiments will be described with reference to FIGS.

[1-1. Overall configuration / frame rate conversion processor]
FIG. 1 is a block diagram of an image display apparatus according to an embodiment.

  The image display apparatus 100 includes an input terminal 110, an image processor 120, a frame rate conversion processor 130, a subframe division processor 140, a selector unit 150, an input device 160, and a display 170. In the image display device 100, an image signal with a frame rate M is input to the input terminal 110 as image data with X-bit gradation, and an image signal with a frame rate M × N (N-times speed) is processed with image data with Y-bit gradation. The image signal is output and displayed on the display 170 having the ability to display the image signal. In the following description, X = 10 bits, Y = 8 bits, M = 60 Hz, and N = 4 × speed will be described as an example.

  An image signal having a frame rate of 60 Hz with 10-bit gradation image data is input to the image processor 120. The image processor 120 converts the input signal into 8-bit gradation image data and outputs the image data to the frame rate conversion processor 130. Also, the image processor outputs 10-bit gradation image data to the sub-frame division processor 140. The conversion of the number of bits may be performed together with image processing such as gamma correction and resizing processing.

  The frame rate conversion processor 130 detects a motion vector from a plurality of frames of an image signal input at a frame rate of 60 Hz. Frame interpolation processing is performed based on the result of the detected motion vector, and four frames, which are 8-bit gradation image data that can be displayed on the display 170, are generated for one frame of the input signal. The created four frames are output to the selector unit at a frame rate of 240 Hz (4 × speed). Since the output image signal of the frame rate conversion processor 130 is an 8-bit gradation signal that can be displayed on the display 170 with respect to the 10-bit gradation of the input signal to the image display device 100, the gradation is reduced. Yes. However, the input signal frame rate of 60 Hz is converted into a quadruple-speed 240 Hz image signal by frame interpolation, resulting in a smoother signal with improved after-image performance. The frame rate conversion processor 130 outputs a stillness determination result SO for each pixel calculated by motion vector detection. For example, a pixel having no motion vector and outputting the pixel value of the frame input in the interpolation frame as it is as the interpolation data value outputs the stillness determination result as a still pixel. In addition, a synchronization signal Sy having an output frame rate of 240 Hz is output to the subframe division processor 140. There are various methods and algorithms for frame rate conversion, but details thereof are omitted because they are not the essence of the present disclosure.

  The sub-frame dividing processor 140 divides the 10-bit gradation image data into four sub-frame image data to be 8-bit gradation image data that can be displayed on the display 170. The divided four subframes are sequentially output to the selector unit 150 in synchronization with the quadruple speed 240 Hz synchronization signal input from the frame rate conversion unit.

  The selector unit 150 outputs one of the output signals of the frame rate conversion processor 130 and the subframe division processor 140 to the display 170 in accordance with the still determination result from the frame rate conversion processor and the notification from the input device. The display 170 converts an image signal of 240 Hz frame rate into a display device drive signal using the input 8-bit gradation image data and displays it. When this embodiment is applied to a projector, the display is a DMD (digital micromirror device), for example.

[1-1-2. Subframe division processor]
FIG. 2 is a block diagram showing a configuration of the subframe division processor 140.

  The subframe division processor 140 converts the input 10-bit gradation image data into four subframes a, subframe b, subframe c, which are converted into 8-bit gradation image data by the subframe division processing circuit 200. Divide into subframes d. The four sub-frames are divided so as to become approximately input 10-bit gradation image data when the respective values are added. The data of the four subframes divided by the subframe division processing circuit 200 is stored in the memory 210.

  FIG. 3 is a diagram showing an example of input image data gradation to the subframe division processing circuit 200 and gradations of four subframes divided by the subframe division processing circuit 200. The subframe a outputs 1 when the input gradation is 1, and outputs a value obtained by adding 1 every time the input gradation increases by 4 thereafter. The subframe b outputs 1 when the input gradation is 2, and outputs a value obtained by adding 1 every time the input gradation increases by 4 thereafter. The subframe c outputs 1 when the input gradation is 3, and outputs a value obtained by adding 1 each time the input gradation increases by 4 thereafter. The subframe d outputs 1 when the input gradation is 4, and outputs a value obtained by adding 1 every time the input gradation increases by 4 thereafter. The four subframe data stored in the memory are sequentially output in accordance with the 240 Hz synchronization signal input from the frame rate conversion processor 130. Since one subframe is output at 240 Hz, four subframes are output at 60 Hz.

  FIG. 4 is an image diagram of an input image signal, an output image signal, and a visually recognized image of the sub-frame division processor 140. Since an image of one frame is composed of four output subframes, an image with a feeling of afterimage is obtained with respect to an image with a large movement, similar to the frame rate of 60 Hz of the input signal of the image display apparatus 100. However, since one image is composed of four pieces of 8-bit gradation image data that can be displayed on the display 170, an image signal with improved gradation is considered in consideration of the time-integrating effect of human eyes.

  FIG. 5A shows the gradation that is visually recognized in the prior art. When the input image is image data having 10-bit gradation data, the lightness and darkness of the image is expressed by the number of gradations 1024 from 0 to 1023. When the display has the ability to process image data of up to 8 bits, the prior art converts the image data into image data having 8 bits of gradation data and displays it. Is expressed. Therefore, the gradation that is visually recognized with respect to the input image is reduced.

  FIG. 5B shows the gradation that is visually recognized when the output image of the sub-frame division processor 140 is displayed on a display. Since one sub-frame is image data having 8-bit gradation that can be processed by the display, the lightness and darkness of the image is expressed with 256 gradations from 0 to 255. In the case of quadruple speed display, one frame of the input image is divided into four sub-frames with 256 gradations and displayed on the display at quadruple speed. Considering the time-integrating effect of the human eye, light and dark are expressed with a gradation number of 1020 from 0 to 1019 by superimposing four subframes. There is little reduction in the gradation that is visually recognized with respect to the input image, and finer expression of brightness and darkness is possible compared with the prior art, and the gradation is improved.

FIG. 5C shows the relationship between the number of bits Y of the output image of the sub-frame division processor 140, the frame rate (N-times speed), and the number of tones that can be expressed. For example, in the case of Y = 8 bits and N = 4 × speed, as shown in FIG. 5C, 1020 gradations, which is about four times the 256 gradation number, can be expressed.
When outputting to a display 170 capable of processing a video signal having a frame rate of M × N (N times speed) with Y-bit gradation image data, Y + log ₂ N-bit gradation image data is converted into Y-bit gradation image data. Are divided into N sub-frames and displayed at a frame rate of M × N (N-times speed). Therefore, 2 ^{(Y + log} 2 ^N) −N, which is approximately N times the number of gradations, can be expressed with respect to the number of gradations 2 ^Y that can be expressed when Y-bit gradations are displayed at the input frame rate M. Become.
[1-1-3. Selector part]
The selector unit 150 outputs one of the input signals of the frame rate conversion processor 130 and the subframe division processor 140 to the display 170 according to the switching signal from the input device 160 and the stillness determination result So from the frame rate conversion processor 130. . As shown in FIG. 6, the selector unit 150 includes a first selector 151 and a second selector 152, and FIG. 6 schematically shows how image data is selected.

  The second selector 152 selects and outputs one of the image signals of the frame rate conversion processor 130 and the subframe division processor 140 in accordance with the stillness determination result So from the frame rate conversion processor 130 for each pixel data. For example, for a pixel determined as a still pixel as a result of stillness determination, data from the sub-frame division processor 140 that is a high gradation image signal is selected and output. As a result of the stillness determination result, data of the frame rate conversion processor 130, which is an image signal with a smooth motion at a high frame rate, is selected and output for a pixel determined as a moving pixel. FIG. 6 shows a state where the second selector 152 selects the output of the frame rate conversion processor 130.

  The first selector 151 switches and outputs the output of the second selector 152, the output of the frame rate conversion processor 130, and the output image signal of the subframe division processor 140 according to a user operation. For example, a user who is supposed to display a moving image with a lot of motion on the entire screen can always select data of the frame rate conversion processor 130 with a high frame rate and a smooth motion, and display an image signal. And Users who are supposed to display still images on the entire screen can always select the data of the sub-frame division processor 140, which is a high gradation image signal, and display an image signal with high gradation characteristics. And A user who is assumed to display a moving image having a motion on a part of the screen or an image in which a still image and a moving image are switched. It is possible to select and display an image of the second selector 152 that is an image signal obtained by switching data of the sub-frame division processor 140 with high gradation.

[1-2. Effect]
FIG. 7 is an image diagram comparing the image quality effects in the prior art (a) and the present embodiment (b). For an area with motion in the screen, both the conventional technique (a) and the present embodiment (b) result in a smooth motion image at a high frame rate. On the other hand, for the still region, the high gradation image is about four times as high as that of the prior art (a) in the present embodiment (b).
As described above, in this embodiment, a portion with a large amount of motion is improved in moving image performance by frame rate conversion, and a still image, an image with a small amount of motion, or a portion with a small amount of motion is 4 for the number of displayable gradations 255. The number of gradations 1020 equivalent to double can be expressed by a time integration effect, and the gradation is improved. In the above description, Y = 8 bits and N = 4 × speed have been described as an example. However, in the case where the Y bit gradation number is output to the display at N × speed, the number of gradations with respect to the gradation number 2 ^Y that can be represented by the display. 2 ^{(Y + log} ₂ ^N) −N and the number of gradations corresponding to about N times can be expressed by a time-integrating effect, and the gradation is improved.

  The above-described embodiments are for illustrating the technique in the present disclosure, and various modifications, replacements, additions, omissions, and the like can be made within the scope of the claims and their equivalents.

  The present disclosure is applicable to an image display device. Specifically, the present disclosure is applicable to projectors, liquid crystal monitors, and the like.

DESCRIPTION OF SYMBOLS 100 Image display apparatus 110 Input terminal 120 Image processor 130 Frame rate conversion processor 140 Sub-frame division | segmentation processor 150 Selector part 151 1st selector 152 2nd selector 160 Input device 170 Display 200 Sub-frame division | segmentation processing circuit 210 Memory

Claims (4)

An image display device for displaying an image on a display,
An input terminal for receiving an image signal;
A frame rate conversion processor that converts the image signal supplied from the input terminal into a high frame rate image signal by frame interpolation and outputs the image signal;
The image signal supplied from the input terminal is divided into gradations into a plurality of subframes, and the subframe division processor outputs the same frame rate as the frame rate conversion processor;
A selector that selects and outputs one of the outputs of the frame rate conversion processor and the subframe division processor to the display;
An image display device comprising:   The image display apparatus according to claim 1, further comprising an input device for inputting a user operation, wherein the output of the selector is switched according to the user operation input to the input device.   The image display device according to claim 1, wherein the output of the selector is switched according to a stillness determination result for each pixel of the image signal from the input terminal determined by the frame rate conversion processor. An input device for inputting a user's operation;
A first selector whose output is switched by a user's operation input to the input device;
A second selector whose output is switched in accordance with a stillness determination result for each pixel of the image signal from the input terminal determined by the frame rate conversion processor,
2. The image display device according to claim 1, wherein the first selector and the second selector select and output one of outputs of a frame rate conversion processor and a subframe division processor, respectively.