JP2016201693A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a saturation current to restrain an amount of heat generation in short circuit duration and achieve a significant increase in a short circuit duration length while minimally suppressing an increase in on-resistance.SOLUTION: A semiconductor device comprises: a normally-on first switching element (Q1) having a source (S1), a drain (D1) and a gate (G1); a normally-off second switching element (Q2) which has a source (S2), a drain (D2) and a gate (G2), and in which the drain (D2) is electrically connected to the source (S1) of the first switching element (Q1), and which composes a cascode circuit together with the first switching element (Q1); and an overcurrent detection circuit (22) parallely connected to the second switching element (Q2), for detecting an overcurrent passing through the cascode circuit. The overcurrent detection circuit (22) limits a current passing through the cascode circuit when a value of a current passing through the cascode circuit becomes equal to or greater than a preset predetermined overcurrent value.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device provided with a cascode circuit, and more particularly to a nitride semiconductor device.

  In recent years, power semiconductors are important in the fields of IT equipment such as servers and personal computers, white goods such as air conditioners, power conditioners used in solar power generation systems, electric vehicles such as hybrid cars, trains and power transmission systems. Plays an important role.

  In particular, devices using GaN (gallium nitride) are expected to have a significantly higher breakdown voltage, lower resistance, and higher frequency than the Si material of the current material because of the superior material properties of GaN.

  One of the characteristics of GaN transistors is high frequency. One reason that the switching frequency can be improved is that the mobility of electrons as carriers is high. Generally, a GaN transistor employs a “HEMT (High Electron Mobility Transistor) structure” in which an AlGaN layer and a GaN layer are joined, and “two-dimensional electron gas” is generated near the interface between the two layers. Since electrons can move at high speed in the “two-dimensional electron gas”, the switching speed can be increased.

  For this reason, the use of the GaN transistor as a switching power supply device is rapidly expanding. However, since the GaN transistor is mainly a normally-on type switching element, a gate driving circuit for driving a normally-off type switching element generally used in a switching power supply device or the like (a gate drive for normally-off operation). Circuit) cannot be applied.

  Therefore, when the normally-on switching element is normally off, the drain of the normally-off switching element is connected to the source of the normally-on switching element to form a cascode circuit. Can be considered. When such a cascode circuit is configured, a normally-on type switching element is turned off in the same manner as a normally-off type switching element when turned off by a gate drive circuit for normally-off operation. The gate drive circuit for normally-off operation can be applied as it is.

  By the way, when the power semiconductor is used in an inverter circuit or the like, depending on the use environment, the transistor element may be short-circuited due to abnormal fluctuations in the load or power supply. In view of this, the power semiconductor is required to have a transistor that does not break even when the power circuit is in a short-circuited state.

  However, at the time of the short circuit, since a large current flows in a state where a high voltage is applied to the transistor, energy of voltage × current is applied, the transistor element generates heat at a stretch, and the transistor element deteriorates or There is a problem of causing destruction.

  In particular, as described above, the GaN transistor can have a significantly higher breakdown voltage / lower resistance than the Si device because of its superior material properties, and the short circuit time increases as the chip area decreases. Has become a major issue. Therefore, suppression of heat generation during a short circuit has become important.

  As a circuit capable of suppressing heat generation at the time of the short circuit, a saturation current limiting circuit for a power transistor disclosed in US 2014/0055192 (Patent Document 1) and US Pat. No. 8,624,662 (Patent Document 2). The semiconductor electronic configuration and circuit disclosed in FIG.

  FIG. 5 is a circuit diagram showing a circuit configuration disclosed in Patent Document 1. The circuit exemplifies a part of a specific circuit of the power transistor 1 that limits the saturation current.

  The power transistor 1 includes a normally-on GaN transistor M1 having a first drain D1, a first source S1, and a first gate G1. The power transistor 1 includes a normally-off type MOS transistor M2 having a second drain D2, a second source S2, and a second gate G2. The first source S1 of the normally on transistor M1 and the second drain D2 of the normally off transistor M2 are connected, and the normally on transistor M1 and the normally off transistor M2 are connected in series.

A current limiting circuit 2 is connected between the first terminal T1 connected to the first gate G1 and the second terminal T2 connected to the second source S2. The current limiting circuit 2 is composed of at least one passive circuit element such as a resistor and / or at least one active circuit element having a maximum steady state voltage V _GS (gate-source voltage) lower than 0V, An example is a diode 3. Thus, the normally-on transistor M1 and the normally-off transistor M2 are cascode-connected.

  FIG. 6 is a circuit diagram showing a circuit configuration disclosed in Patent Document 2. The circuit has a circuit configuration for driving the load 5, and similarly to the circuit configuration shown in Patent Document 1, a high-voltage depletion mode GaN transistor (normally on transistor) 7 connected in series with each other, and And a low voltage enhancement mode MOS transistor (normally off transistor) 8. The gate of the depletion mode transistor 7 and the source of the enhancement mode transistor 8 are connected via a negative bias power source 9. In this way, the normally-on transistor 7 and the normally-off transistor 8 are cascode-connected, and the negative bias power supply 9 is connected between the gate of the normally-on transistor 7 and the source of the normally-off transistor 8. Thus, the saturation current is limited.

  In general, as shown in FIG. 7, the cascode circuit 11 has, for example, an external drain terminal Dc, an external source terminal Sc, and an external gate terminal Gc as external terminals. In the cascode circuit 11, a normally-on type first transistor Q11 and a normally-off type second transistor Q12 are cascode-connected, and the gate G12 of the second transistor Q12 and the external gate terminal Gc are gated. They are connected via a resistor Rg. Further, the gate G11 of the first transistor Q11 and the external source terminal Sc are connected through a resistor R11.

Here, a power source and a load are connected to the external drain terminal Dc, and the external source terminal Sc is fixed to the GND potential. When an ON input signal is input to the external gate terminal Gc, if the current flowing through the transistors Q11 and Q12 is ID, the gate-source voltage of the GaN transistor Q11 is Vgs, the threshold voltage is Vth, When the transconductance in the saturation region is gm, the current ID can be experimentally expressed by the following equation.
ID ≒ gm x (Vgs-Vth)

  First, the gate-source voltage is considered with respect to Vgs. The potential of the gate G11 of the GaN transistor Q11 is 0V, and when the on-resistance of the MOS transistor Q12 is sufficiently low, the potential of the source S11 of the GaN transistor Q11 is approximately 0V and Vgs≈0V.

Therefore, the current ID is
ID ≒ gm x (-Vth)
When the threshold voltage of the normally-on GaN transistor Q11 is -6V, for example, the current ID is
ID ≒ 6 x gm
Is calculated by

On the other hand, for example, in the circuit configuration disclosed in Patent Document 1 shown in FIG. 5, the current limiting circuit 2 causes the gate-source voltage V _{GS of the} normally-on transistor M1 to be negatively biased. Similarly, in the circuit configuration disclosed in Patent Document 2 shown in FIG. 6, the gate-source voltage V _{GS of the} normally-on transistor 7 is negatively biased by the power supply 9.

Here, the gate-source voltage Vgs in the circuit configurations disclosed in Patent Document 1 and Patent Document 2 is set to −2 V, for example. Then, the saturation current flowing in the normally-on transistor M1 and the normally-off transistor M2 in Patent Document 1 and the saturation current Idsat flowing in the normally-on transistor 7 and the normally-off transistor 8 in Patent Document 2 are
Idsat ≒ gm x (Vgs-Vth) = gm x (-2 + 6) = 4 x gm
Is calculated by

  That is, it can be seen that the saturation current can be reduced by about 30% in the circuit configurations disclosed in Patent Document 1 and Patent Document 2 as compared with the general cascode circuit shown in FIG.

  Therefore, in the cascode circuits having the circuit configurations in Patent Document 1 and Patent Document 2, the saturation current can be reduced by applying a negative bias as the gate-source voltage Vgs in the normally-on GaN transistor. .

US Patent Application Publication No. 2014/0055192 US Pat. No. 8,624,662

  However, the conventional circuit configurations disclosed in Patent Document 1 and Patent Document 2 have the following problems.

  That is, in the cascode circuits disclosed in Patent Document 1 and Patent Document 2, a negative bias is always applied as the gate-source voltage Vgs in the normally-on GaN transistor during the switching operation. Therefore, there is a problem that the on-resistance of the GaN transistor always increases.

Generally, when a normally-on type GaN transistor and a normally-off type MOS transistor are cascode-connected, the on-resistance of the GaN transistor is Ron (GaN), and the on-resistance of the MOS transistor is Ron (MOS).
Ron (GaN) >> Ron (MOS)
(For example, Ron (GaN) is about 3 to 10 times that of Ron (MOS)).

  Therefore, when a cascode circuit is formed, the proportion of the entire cascode connection between the GaN transistor and the MOS transistor in the on-resistance is mostly a GaN transistor, and the proportion of the MOS transistor is small. The reason is as follows.

That is, since the GaN transistor is applied with a high voltage, it is necessary to increase the breakdown voltage by designing a long drift length. However, for a GaN transistor which is a lateral device, an increase in drift length is directly reflected in an increase in on-resistance and an increase in chip. On the other hand, the MOS transistor can be designed to have a short drift length because a high voltage is not applied, and the chip area can be reduced by adopting a vertical structure. as a result,
Ron (GaN) >> Ron (MOS)
It becomes.

  In the circuit configurations of Patent Document 1 and Patent Document 2, it is possible to reduce the saturation current. However, as described above, the on-resistance of the GaN transistor, which accounts for a large percentage of the on-resistance of the entire cascode connection, always increases during the switching operation. As a result, the on-resistance of the entire cascode connection increases during the switching operation. There is a problem that it always grows.

  Accordingly, an object of the present invention is to provide a semiconductor device capable of reducing the saturation current and suppressing the amount of heat generated during the short circuit time while minimizing the increase in the on-resistance, thereby significantly increasing the short circuit time length. It is to provide.

In order to solve the above problems, a semiconductor device of the present invention is
A normally-on first switching element having a source, a drain, and a gate;
A normally-off type second switching having a source, a drain, and a gate, wherein the drain is electrically connected to the source of the first switching element, and forms a cascode circuit together with the first switching element. Elements,
An overcurrent detection circuit that is connected in parallel to the second switching element and detects an overcurrent flowing through the cascode circuit;
The overcurrent detection circuit is configured to limit a current flowing through the cascode circuit when a value of a current flowing through the cascode circuit becomes equal to or higher than a predetermined predetermined overcurrent value. To do.

In the semiconductor device of one embodiment,
The overcurrent detection circuit is
A normally-off third switching element connected in parallel to the second switching element and having a source, a drain, and a gate;
An overcurrent detection resistor connected between the source of the third switching element and the source of the second switching element;
A normally-off type fourth switching element having a source, a drain, and a gate;
The drain of the fourth switching element is connected in common with the gate of the third switching element and the gate of the second switching element;
The gate of the fourth switching element is connected in common with the source of the third switching element and one end of the overcurrent detection resistor;
The source of the fourth switching element is connected in common with the other end of the overcurrent detection resistor and the source of the second switching element;
The gate width W3 of the third switching element is set to be 1 / n (n> 1) times the gate width W2 of the second switching element.

In the semiconductor device of one embodiment,
An external gate terminal commonly connected to the gate of the third switching element, the gate of the second switching element, and the drain of the fourth switching element;
The overcurrent detection circuit is
A gate resistor connected between the external gate terminal and the drain of the fourth switching element;

In the semiconductor device of one embodiment,
The second switching element, the third switching element, and the fourth switching element are formed on the same chip.

In the semiconductor device of one embodiment,
The first switching element, the second switching element, the third switching element, and the fourth switching element are built in the same package.

  As is clear from the above, when the overcurrent detection circuit detects that the current value flowing through the cascode circuit is equal to or higher than a predetermined overcurrent value, the semiconductor device of the present invention is The on-resistance of the cascode circuit is increased and the flowing current is limited. Therefore, the amount of heat generated during the short circuit time can be significantly suppressed.

  In this case, the overcurrent detection circuit limits the current flowing by increasing the on-resistance of the cascode circuit only when the current value flowing through the cascode circuit becomes equal to or greater than the overcurrent value. Therefore, the on-resistance of the cascode circuit does not increase during normal operation.

  That is, according to the semiconductor device of the present invention, while suppressing an increase in on-resistance to a minimum, it is possible to reduce the saturation current and suppress the amount of heat generated during the short-circuit time, thereby significantly increasing the short-circuit time length. .

FIG. 1 is a circuit diagram of a nitride semiconductor device as a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram of a nitride semiconductor device as a semiconductor device according to the second embodiment of the present invention. FIG. 3 is a circuit diagram of a nitride semiconductor device as a semiconductor device according to the third embodiment of the present invention. FIG. 4 is a diagram showing a change over time in the current flowing through the nitride semiconductor device of FIGS. FIG. 5 is a circuit diagram of a saturation current limiting circuit section of a conventional power transistor. FIG. 6 is a circuit diagram of a conventional semiconductor electronic circuit. FIG. 7 is a circuit diagram of a general cascode circuit.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

[First Embodiment]
FIG. 1 is a circuit diagram of a nitride semiconductor device 21 as the semiconductor device of the first embodiment.

  The nitride semiconductor device 21 has, for example, an external drain terminal Dc, an external source terminal Sc, and an external gate terminal Gc as external terminals.

  The nitride semiconductor device 21 is generally composed of a normally-on type first transistor Q 1, a normally-off type second transistor Q 2, and an overcurrent detection circuit 22. The normally-on type first transistor Q1 is, for example, a GaN transistor. The normally-off type second transistor Q2 is, for example, a MOS transistor. The first transistor Q1 and the second transistor Q2 are examples of the first switching element and the second switching element.

  An external drain terminal Dc is connected to the drain D1 of the first transistor Q1. The source D1 of the first transistor Q1 is connected to the drain D2 of the second transistor Q2, and the external source terminal Sc is connected to the source S2 of the second transistor Q2. A resistor R1 is connected between the gate G1 of the first transistor Q1 and the source S2 of the second transistor Q2. Thus, the first transistor Q1 and the second transistor Q2 connected in series form a cascode circuit. The overcurrent detection circuit 22 is connected in parallel with the second transistor Q2.

  Further, the gate G2 of the second transistor Q2 is connected to the external gate terminal Gc via the overcurrent detection circuit 22.

  Hereinafter, an example of an operation in which the flowing current is limited when an overcurrent flows through the nitride semiconductor device 21 having the above configuration will be described. Here, it is assumed that a power source (not shown) and a load (not shown) are connected to the external drain terminal Dc, and the external source terminal Sc is fixed to the GND potential. Further, when an ON input signal is input to the external gate terminal Gc, the current flowing through the cascode circuit formed by the first and second transistors Q1 and Q2 is defined as ID.

  The overcurrent detection circuit 22 is connected to the drain D2 and the source S2 of the second transistor Q2, and can detect the current ID flowing through the second transistor Q2. Then, the overcurrent detection circuit 22 reduces the potential of the on signal from the external gate terminal Gc when the current value of the detected current ID becomes equal to or greater than a preset overcurrent value, and the second transistor Q2. To the gate G2.

  Thus, when the current value of the current ID flowing through the cascode circuit becomes equal to or higher than a predetermined overcurrent value set by the overcurrent detection circuit 22, the potential of the gate G2 of the second transistor Q2 is lowered. Controlled. As a result, the on-resistance of the second transistor Q2 increases, and the potential of the source S1 of the first transistor Q1 increases. In this case, since the potential of the gate G1 of the first transistor Q1 is 0 V, an increase in the potential of the source S1 means that the gate overdrive voltage of the normally-on type first transistor Q1 is decreased. For this reason, the saturation current value of the first transistor Q1 decreases.

  On the other hand, the overcurrent detection circuit 22 does not perform the control operation in a normal operation in which the current value of the current ID flowing through the cascode circuit is smaller than a predetermined overcurrent value. The on-resistance of the second transistor Q2 does not increase. For this reason, the on-resistance of the entire cascode connection does not increase.

  As described above, in the first embodiment, in the nitride semiconductor device 21 having the cascode circuit in which the normally-on GaN first transistor Q1 and the normally-off MOS second transistor Q2 are connected in series. The overcurrent detection circuit 22 for detecting the current ID flowing through the second transistor Q2 is connected in parallel with the second transistor Q2.

  Then, when the current value of the current ID flowing through the nitride semiconductor device 21 becomes equal to or higher than a preset overcurrent value by the overcurrent detection circuit 22, the potential of the gate G2 of the second transistor Q2 is lowered. Is controlling. Therefore, the on-resistance of the second transistor Q2 increases, the potential of the source S1 of the first transistor Q1 increases, and the gate overdrive voltage of the normally-on type first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 can be reduced.

  Therefore, according to the nitride semiconductor device 21 of the first embodiment, the amount of heat generated during the short circuit time can be greatly improved.

  In this case, the saturation current is limited only when the predetermined overcurrent is detected by the overcurrent detection circuit 22. Therefore, the on-resistance of the entire cascode connection does not increase during normal operation.

  That is, according to the nitride semiconductor device 21 of the first embodiment, while suppressing an increase in on-resistance to a minimum, the saturation current is reduced to suppress the amount of heat generated during the short-circuit time, and the short-circuit time length is significantly increased. It can be increased.

[Second Embodiment]
FIG. 2 is a circuit configuration diagram of a nitride semiconductor device 31 as a semiconductor device according to the second embodiment of the present invention.

  The nitride semiconductor device 31 of the second embodiment relates to a specific configuration of the overcurrent detection circuit 22 in the first embodiment. Therefore, the same members as those shown in FIG. 1 in the first embodiment are denoted by the same reference numerals as those in the first embodiment, and detailed description thereof is omitted.

  The overcurrent detection circuit 32 in the nitride semiconductor device 31 includes a normally-off third transistor Q3 and a fourth transistor Q4. The third and fourth transistors Q3 and Q4 are, for example, MOS transistors. Here, the third transistor Q3 and the fourth transistor Q4 are examples of the third switching element and the fourth switching element.

  The third transistor Q3 is connected in parallel with the second transistor Q2 via the overcurrent detection resistor Rgs4, and the drain D3 of the third transistor Q3 is connected in common with the drain D2 of the second transistor Q2. . Further, the gate G3 of the third transistor Q3 and the gate G2 of the second transistor Q2 are commonly connected to the external gate terminal Gc. Here, the gate width W3 of the third transistor Q3 is 1 / n (n >> 1) of the gate width W2 of the second transistor Q2.

  The drain D4 of the fourth transistor Q4 is commonly connected to the gate G3 of the third transistor Q3 and the gate G2 of the second transistor Q2. The drain D4 of the fourth transistor Q4, the gate G3 of the third transistor Q3, and the gate G2 of the second transistor Q2 are connected to the external gate terminal Gc. Further, the source S3 of the third transistor Q3 and the gate G4 of the fourth transistor Q4 are connected.

  One end of the overcurrent detection resistor Rgs4 is connected to the source S3 of the third transistor Q3 and the gate G4 of the fourth transistor Q4, while the other end of the overcurrent detection resistor Rgs4 is connected to the source S4 of the fourth transistor Q4. And connected to the source S2 of the second transistor Q2. Thus, the other end of the overcurrent detection resistor Rgs4, the source S4 of the fourth transistor Q4, and the source S2 of the second transistor Q2 are connected to the external source terminal Sc.

  Hereinafter, an operation of limiting the current when an overcurrent flows through the nitride semiconductor device 31 having the above configuration will be described. Here, it is assumed that a power source (not shown) and a load (not shown) are connected to the external drain terminal Dc, and the external source terminal Sc is fixed to the GND potential. When an ON input signal is input to the external gate terminal Gc, the current flowing through the cascode circuit formed by the first and second transistors Q1 and Q2 is ID, and the current flowing through the third transistor Q3 is ID3. The current flowing through the fourth transistor Q4 is ID4.

For example, when the magnification n of the gate width W2 of the second transistor Q2 with respect to the gate width W3 of the third transistor Q3 is n = 1000, the gate width W3 of the third transistor Q3 is equal to the gate width W2 of the second transistor Q2. 1/1000 of that. Therefore, the current ID3 flowing through the third transistor Q3 is
ID3 ≒ ID / n = ID / 1000
It becomes.

In that case, the potential of the source S3 of the third transistor Q3 is lifted by the overcurrent detection resistor Rgs4,
ID3 x Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 x Rgs4
When this voltage reaches the threshold voltage of the fourth transistor Q4, the fourth transistor Q4 is turned on. At that time, the voltage Vg of the drain D4 of the fourth transistor Q4 is limited by the product of the on-resistance Ron4 of the fourth transistor Q4 and the current ID4, and the gate potential of the second transistor Q2 is
Ron4 x ID4
Will be limited.

  As a result, the on-resistance of the second transistor Q2 increases, and the potential of the source S1 of the first transistor Q1 increases. In this case, since the potential of the gate G1 of the first transistor Q1 is 0 V, an increase in the potential of the source S1 means that the gate overdrive voltage of the normally-on type first transistor Q1 is decreased. As a result, the saturation current value of the first transistor Q1 decreases.

  That is, as shown in FIG. 4, when there is the overcurrent detection circuit 32 shown in this embodiment, the current value of the current ID flowing through the cascode circuit is a preset overcurrent value at the time of a short circuit or the like. When ID (max) or more is reached, the gate voltage of the second transistor Q2 is limited, and the current ID of the nitride semiconductor device 31 is limited.

The value of the overcurrent detection resistor Rgs4 is the threshold voltage of the fourth transistor Q4 when the ratio of the gate width W3 of the third transistor Q3 to the gate width W2 of the second transistor Q2 is (1 / n). Vth4 is
Vth4 = (ID (max) / n) x Rgs4
What is necessary is just to design so that.

  On the other hand, in the case of normal operation where the current value of the current ID flowing through the cascode circuit is smaller than a predetermined overcurrent value set in advance, the overcurrent detection circuit 32 does not perform the control operation. The on-resistance of the two-transistor Q2 does not increase. For this reason, the on-resistance of the entire cascode connection does not increase.

  As described above, in the second embodiment, the overcurrent detection circuit 32 in the first embodiment is a normally-off type first connected in parallel via the second transistor Q2 and the overcurrent detection resistor Rgs4. The third transistor Q3 includes a fourth transistor Q4 connected between the gate G3 of the third transistor Q3 and the source S2 of the second transistor Q2.

  The gate G4 of the fourth transistor Q4 is connected to the source S3 of the third transistor Q3. Further, the drain D4 of the fourth transistor Q4, the gate G3 of the third transistor Q3, and the gate G2 of the second transistor Q2 are connected to the external gate terminal Gc. The gate width W3 of the third transistor Q3 is set to 1 / n (n >> 1) of the gate width W2 of the second transistor Q2.

Then, the current ID3 flowing through the third transistor Q3 is
ID3 ≒ ID / n
And the potential of the source S3 is
ID3 x Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 x Rgs4
When this voltage reaches the threshold voltage Vth4 of the fourth transistor Q4, the fourth transistor Q4 is turned on. That means
ID3 x Rgs4 = (ID / n) x Rgs4 ≥ Vth4
So, organize this formula,
ID ≧ (Vth4 × n) / Rgs4
Then, the fourth transistor Q4 is turned on.

Therefore, when the current ID flowing through the cascode circuit is equal to or greater than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second transistor Q2 is
Ron4 x ID4
Limited to

  As a result, the potential of the gate G2 of the second transistor Q2 decreases and the on-resistance Ron2 increases. Then, the potential of the source S1 of the first transistor Q1 increases, and the gate overdrive voltage of the normally-on first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 can be reduced.

  Therefore, according to the nitride semiconductor device 31 of the second embodiment, the amount of heat generated during the short circuit time can be significantly improved.

  In that case, the overcurrent detection circuit 32 limits the saturation current only when the current ID becomes equal to or greater than the overcurrent value ID (max). Therefore, the on-resistance of the entire cascode connection does not increase during normal operation.

  That is, while suppressing an increase in on-resistance to a minimum, the saturation current can be reduced to suppress the amount of heat generated during the short-circuit time, and the short-circuit time length can be significantly increased.

[Third Embodiment]
FIG. 3 is a circuit configuration diagram of a nitride semiconductor device 41 as a semiconductor device according to the third embodiment of the present invention.

  The nitride semiconductor device 41 of the third embodiment relates to a specific configuration different from the overcurrent detection circuit 32 of the second embodiment. Therefore, the same members as those shown in FIG. 2 of the second embodiment are denoted by the same reference numerals as those of the second embodiment, and detailed description thereof is omitted.

  As in the case of the second embodiment, the overcurrent detection circuit 42 in the nitride semiconductor device 41 includes a normally-off third transistor Q3 and a fourth transistor Q4. The third and fourth transistors Q3 and Q4 are, for example, MOS transistors. An overcurrent detection resistor Rgs4 is connected between the source S3 of the third transistor Q3 and the source S2 of the second transistor Q2.

  The overcurrent detection circuit 42 in the nitride semiconductor device 41 of the third embodiment has a gate resistance Rg between the external gate terminal Gc and the drain D3 of the fourth transistor Q4. Different from the current detection circuit 32.

  Hereinafter, an operation of limiting the current when an overcurrent flows through the nitride semiconductor device 41 having the above configuration will be described. Here, it is assumed that a power source (not shown) and a load (not shown) are connected to the external drain terminal Dc, and the external source terminal Sc is fixed to the GND potential. When an ON input signal is input to the external gate terminal Gc, the current flowing through the cascode circuit formed by the first and second transistors Q1 and Q2 is defined as ID, and the current flowing through the third transistor Q3 is defined as ID3. And the current flowing through the fourth transistor Q4 is ID4.

For example, when the magnification n of the gate width W2 of the second transistor Q2 with respect to the gate width W3 of the third transistor Q3 is n = 1000, the gate width W3 of the third transistor Q3 is equal to the gate width W2 of the second transistor Q2. 1/1000 of that. Therefore, the current ID3 flowing through the third transistor Q3 is
ID3 ≒ ID / n = ID / 1000
It becomes.

In that case, the potential of the source S3 of the third transistor Q3 is lifted by the overcurrent detection resistor Rgs4,
ID3 x Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 x Rgs4
When this voltage reaches the threshold voltage of the fourth transistor Q4, the fourth transistor Q4 is turned on. At this time, the voltage Vg of the drain D4 of the fourth transistor Q4 is divided by the gate resistance Rg and the on-resistance Ron4 of the fourth transistor Q4 when the voltage of the external gate terminal Gc is VG. It is represented by (1).
Vg = {Ron4 / (Rg + Ron4)} × VG (1)

Therefore, the voltage Vg of the drain D4 of the fourth transistor Q4 is limited by the above equation (1), and the gate potential of the second transistor Q2 is
{Ron4 / (Rg + Ron4)} × VG
Will be limited.

  As a result, the on-resistance of the second transistor Q2 increases, and the potential of the source S1 of the first transistor Q1 increases. In this case, since the potential of the gate G1 of the first transistor Q1 is 0 V, an increase in the potential of the source S1 means that the gate overdrive voltage of the normally-on type first transistor Q1 is decreased. For this reason, the saturation current value of the first transistor Q1 decreases.

  That is, as shown in FIG. 4, when there is the overcurrent detection circuit 42 shown in this embodiment, the current value of the current ID flowing through the cascode circuit is a preset overcurrent value at the time of a short circuit or the like. When ID (max) or higher, the gate voltage of the second transistor Q2 is limited, and the current ID of the nitride semiconductor device 41 is limited.

The value of the overcurrent detection resistor Rgs4 is the threshold voltage of the fourth transistor Q4 when the ratio of the gate width W3 of the third transistor Q3 to the gate width W2 of the second transistor Q2 is (1 / n). Vth4 is
Vth4 = (ID (max) / n) x Rgs4
What is necessary is just to design so that. Further, the gate resistance Rg may be adjusted to a voltage Vg that provides an appropriate current ID according to the above equation (1).

  On the other hand, in the case of normal operation in which the current value of the current ID flowing through the cascode circuit is smaller than a predetermined overcurrent value set in advance, the overcurrent detection circuit 42 does not perform the above control operation. The on-resistance of the two-transistor Q2 does not increase. For this reason, the on-resistance of the entire cascode connection does not increase.

  As described above, in the third embodiment, the overcurrent detection circuit 42 is connected in parallel via the second transistor Q2 and the overcurrent detection resistor Rgs4, like the overcurrent detection circuit 32 in the second embodiment. And a normally-off third transistor Q3 connected to the second transistor Q3, and a fourth transistor Q4 interposed between the gate G3 of the third transistor Q3 and the source S2 of the second transistor Q2. .

  The gate G4 of the fourth transistor Q4 is connected to the source S3 of the third transistor Q3. Further, the drain D4 of the fourth transistor Q4, the gate G3 of the third transistor Q3, and the gate G2 of the second transistor Q2 are connected to the external gate terminal Gc. The gate width W3 of the third transistor Q3 is set to 1 / n (n >> 1) of the gate width W2 of the second transistor Q2.

  Further, a gate resistor Rg is interposed between the external gate terminal Gc and the drain D3 of the fourth transistor Q4.

Then, the current ID3 flowing through the third transistor Q3 is
ID3 ≒ ID / n
And the potential of the source S3 is
ID3 x Rgs4
It becomes. Therefore, the gate-source voltage of the fourth transistor Q4 is
ID3 x Rgs4
When this voltage reaches the threshold voltage Vth4 of the fourth transistor Q4, the fourth transistor Q4 is turned on. That means
ID3 x Rgs4 = (ID / n) x Rgs4 ≥ Vth4
So, organize this formula,
ID ≧ (Vth4 × n) / Rgs4
Then, the fourth transistor Q4 is turned on.

Therefore, when the current ID flowing through the cascode circuit is overcurrent value ID (max) = (Vth4 × n) / Rgs4 or more, the potential of the gate G2 of the second transistor Q2 is
{Ron4 / (Rg + Ron4)} × VG
Limited to

  As a result, the potential of the gate G2 of the second transistor Q2 decreases and the on-resistance Ron2 increases. Then, the potential of the source S1 of the first transistor Q1 increases, and the gate overdrive voltage of the normally-on first transistor Q1 decreases. Therefore, the saturation current value of the first transistor Q1 can be reduced.

  Therefore, according to the nitride semiconductor device 41 of the third embodiment, the amount of heat generated during the short circuit time can be greatly improved.

  In that case, the overcurrent detection circuit 42 limits the saturation current only when the current ID is equal to or greater than the overcurrent value ID (max). Therefore, the on-resistance of the entire cascode connection does not increase during normal operation.

  That is, while suppressing an increase in on-resistance to a minimum, the saturation current can be reduced to suppress the amount of heat generated during the short-circuit time, and the short-circuit time length can be significantly increased.

As described above, the potential of the gate G2 of the second transistor Q2 when the current ID is equal to or greater than the overcurrent value ID (max) is
{Ron4 / (Rg + Ron4)} × VG
Restricted to Therefore, the potential of the gate G2 of the second transistor Q2 can be lowered by an amount corresponding to the divided voltage to the gate resistance Rg as compared with the second embodiment without the gate resistance Rg (Rg = 0). Therefore, the saturation current value of the first transistor Q1 can be further reduced as compared with the case of the second embodiment.

  Here, the second, third, and fourth transistors Q2, Q3, and Q4 in the first to third embodiments are preferably formed on the same chip. By doing so, the normally-off type second, third, and fourth transistors Q2, Q3, and Q4 can be easily formed by MOS transistors in the same process.

  Further, it is desirable that the first transistor Q1 to the fourth transistor Q4 are built in the same package. By doing so, it is possible to obtain a small semiconductor device in which the first transistor Q1 to the fourth transistor Q4 are built in the same package, and the amount of heat generated during the short circuit time is significantly reduced.

  In the first to third embodiments, as a countermeasure against drain current oscillation caused by repeated ON / OFF in the second transistor Q2, stable operation may be performed by applying phase compensation by a phase compensation circuit.

  In the first to third embodiments, the first transistor Q1 is a GaN transistor. However, the first transistor Q1 is not limited to a nitride semiconductor device such as a GaN transistor. However, in the case of a GaN transistor, a great effect can be obtained by reducing the on-resistance.

  Although specific embodiments of the present invention have been described, the present invention is not limited to the first to third embodiments, and various modifications can be made within the scope of the present invention. For example, what combined suitably the content described in the said 1st-3rd embodiment is good also as one Embodiment of this invention.

In summary, the semiconductor devices 21, 31, 41 of the present invention are
A normally-on type first switching element Q1 having a source S1, a drain D1, and a gate G1,
A normally including a source S2, a drain D2, and a gate G2, and the drain D2 is electrically connected to the source S1 of the first switching element Q1 to form a cascode circuit together with the first switching element. An off-type second switching element Q2,
An overcurrent detection circuit 22, 32, 42 that is connected in parallel with the second switching element Q2 and detects an overcurrent flowing through the cascode circuit;
The overcurrent detection circuits 22, 32, 42 limit the current flowing through the cascode circuit when the value of the current flowing through the cascode circuit becomes equal to or higher than a predetermined overcurrent value set in advance. It is characterized by being.

  According to the above configuration, when it is detected by the overcurrent detection circuits 22, 32, and 42 that the current flowing through the cascode circuit is equal to or higher than a predetermined overcurrent value set in advance, the second current is detected. The on-resistance of the switching element Q2 is increased and the flowing current is limited. Therefore, the amount of heat generated during the short circuit time can be significantly suppressed.

  In that case, the overcurrent detection circuits 22, 32, 42 increase the on-resistance of the second switching element Q2 only when the current value flowing through the cascode circuit becomes equal to or greater than the overcurrent value, I try to limit it. Therefore, the on-resistance of the cascode circuit does not increase during normal operation.

  That is, while suppressing an increase in the on-resistance to a minimum, the saturation current can be reduced to suppress the amount of heat generated during the short-circuit time, and the short-circuit time length can be significantly increased.

In the semiconductor device 31 of the embodiment,
The overcurrent detection circuit 32 includes:
A normally-off type third switching element Q3 connected in parallel with the second switching element Q2 and having a source S3, a drain D3, and a gate G3;
An overcurrent detection resistor Rgs4 connected between the source S3 of the third switching element Q3 and the source S2 of the second switching element Q2,
A normally-off fourth switching element Q4 having a source S4, a drain D4, and a gate G4;
The drain D4 of the fourth switching element Q4 is connected in common with the gate G3 of the third switching element Q3 and the gate G2 of the second switching element Q2,
The gate G4 of the fourth switching element Q4 is connected in common with the source S3 of the third switching element Q3 and one end of the overcurrent detection resistor Rgs4.
The source S4 of the fourth switching element Q4 is connected in common with the other end of the overcurrent detection resistor Rgs4 and the source S2 of the second switching element Q2.
The gate width W3 of the third switching element Q3 is set to be 1 / n (n> 1) times the gate width W2 of the second switching element Q2.

According to this embodiment, when the current flowing through the cascode circuit is ID and the overcurrent detection resistor is Rgs4, the current ID3 flowing through the third switching element Q3 is:
ID3 ≒ ID / n
And the potential of the source S3 of the third switching element Q3 is based on the potential of the source S2 of the second switching element Q2.
ID3 x Rgs4
It becomes. Therefore, the gate-source voltage of the fourth switching element Q4 is
ID3 x Rgs4
When this voltage reaches the threshold voltage Vth4 of the fourth switching element Q4, the fourth switching element Q4 is turned on. That is, when ID ≧ (Vth4 × n) / Rgs4, the fourth switching element Q4 is turned on.

Therefore, when the current ID flowing through the cascode circuit is equal to or greater than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second switching element Q2 is
Ron4 x ID4
Limited to

  As a result, the potential of the gate G2 of the second switching element Q2 decreases, and the on-resistance Ron2 increases. Then, the potential of the source S1 of the first switching element Q1 increases, and the gate overdrive voltage of the normally-on type first switching element Q1 decreases. Therefore, it is possible to limit the current flowing through the cascode circuit by reducing the value of the current flowing through the first switching element Q1.

In the semiconductor device 41 according to the embodiment,
An external gate terminal Gc connected in common to the gate G3 of the third switching element Q3, the gate G2 of the second switching element Q2 and the drain D4 of the fourth switching element Q4;
The overcurrent detection circuit 42 includes:
A gate resistor Rg is connected between the external gate terminal Gc and the drain D4 of the fourth switching element Q4.

  According to this embodiment, with reference to the potential of the source S2 of the second switching element Q2, the current flowing through the cascode circuit is ID, the overcurrent detection resistor is Rgs4, and the voltage of the external gate terminal Gc Is VG, and the on-resistance of the fourth switching element Q4 is Ron4, the fourth switching element Q4 is turned on when ID ≧ (Vth4 × n) / Rgs4, as in the above-described embodiment. .

At that time, the voltage Vg of the drain D4 of the fourth switching element Q4 is divided by the gate resistance Rg and the on-resistance Ron4 of the fourth switching element Q4.
{Ron4 / (Rg + Ron4)} × VG
It becomes.

Therefore, when the current ID flowing through the cascode circuit is equal to or greater than the overcurrent value ID (max) = (Vth4 × n) / Rgs4, the potential of the gate G2 of the second switching element Q2 is
{Ron4 / (Rg + Ron4)} × VG
Limited to

  As a result, as in the case of the above-described embodiment, the current ID flowing through the first switching element Q1 can be reduced to limit the current ID flowing through the cascode circuit.

Further, as described above, the potential of the gate G2 of the second switching element Q2 when the current ID is equal to or greater than the overcurrent value ID (max) is
{Ron4 / (Rg + Ron4)} × VG
Restricted to Therefore, as compared with the above-described embodiment without the gate resistance Rg (Rg = 0), the voltage can be lowered by the partial pressure to the gate resistance Rg. That is, the current flowing through the cascode circuit can be further limited as compared with the above-described embodiment.

Moreover, in the semiconductor devices 21, 31, 41 of the embodiment,
The second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are formed on the same chip.

  According to this embodiment, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are formed on the same chip. Therefore, the normally-off type second switching element Q2 to fourth switching element Q4 can be easily formed by MOS transistors in the same process.

Moreover, in the semiconductor devices 21, 31, 41 of the embodiment,
The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are built in the same package.

  According to this embodiment, it is possible to obtain a small semiconductor device in which the first switching element Q1 to the fourth switching element Q4 are built in the same package, and the amount of heat generated during the short circuit time is significantly reduced.

21, 31, 41 ... Nitride semiconductor devices 22, 32, 42 ... Overcurrent detection circuit Dc ... External drain terminal (external terminal)
Sc: External source terminal (external terminal)
Gc: External gate terminal (external terminal)
Q1 ... normally-on type first transistor S1 ... first transistor source D1 ... first transistor drain G1 ... first transistor gate Q2 ... normally-off type second transistor S2 ... second transistor source D2 ... Second transistor drain G2 ... Second transistor gate Q3 ... Normally-off type third transistor S3 ... Third transistor source D3 ... Third transistor drain G3 ... Third transistor gate Q4 ... Normally-off type Fourth transistor S4 ... Fourth transistor source D4 ... Fourth transistor drain G4 ... Fourth transistor gate R1 ... Resistance Rgs4 ... Overcurrent detection resistor Rg ... Gate resistance

Claims (5)

A normally-on first switching element having a source, a drain, and a gate;
A normally-off type second switching element having a source, a drain, and a gate, the drain being electrically connected to the source of the first switching element, and forming a cascode circuit together with the first switching element When,
An overcurrent detection circuit that is connected in parallel to the second switching element and detects an overcurrent flowing through the cascode circuit;
The overcurrent detection circuit is configured to limit a current flowing through the cascode circuit when a value of a current flowing through the cascode circuit becomes equal to or higher than a predetermined predetermined overcurrent value. Semiconductor device. The semiconductor device according to claim 1,
The overcurrent detection circuit is
A normally-off third switching element connected in parallel to the second switching element and having a source, a drain, and a gate;
An overcurrent detection resistor connected between the source of the third switching element and the source of the second switching element;
A normally-off type fourth switching element having a source, a drain, and a gate;
The drain of the fourth switching element is connected in common with the gate of the third switching element and the gate of the second switching element;
The gate of the fourth switching element is connected in common with the source of the third switching element and one end of the overcurrent detection resistor;
The source of the fourth switching element is connected in common with the other end of the overcurrent detection resistor and the source of the second switching element;
A semiconductor device characterized in that the gate width W3 of the third switching element is set to be 1 / n (n> 1) times the gate width W2 of the second switching element. The semiconductor device according to claim 2,
An external gate terminal commonly connected to the gate of the third switching element, the gate of the second switching element, and the drain of the fourth switching element;
The overcurrent detection circuit is
A semiconductor device comprising: a gate resistor connected between the external gate terminal and the drain of the fourth switching element. The semiconductor device according to claim 2 or claim 3,
The semiconductor device, wherein the second switching element, the third switching element, and the fourth switching element are formed on the same chip. In the semiconductor device according to any one of claims 2 to 4,
The semiconductor device, wherein the first switching element, the second switching element, the third switching element, and the fourth switching element are built in the same package.

Images