JP2016195238A - Wiring board and semiconductor package - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board which does not require positioning of an embedded substrate with respect to a core substrate.SOLUTION: The present wiring board which comprises a core substrate including a resin substrate and a through hole piercing the resin substrate in a thickness direction, a plate-like body and a plurality of linear conductors piercing the plate-like body in a thickness direction includes: an embedded substrate arranged in the through hole; a first insulation layer which covers a first surface of the resin substrate; a first pad pattern formed on a first surface of the embedded substrate; and a third wiring pattern which is formed on the first surface of the resin substrate and covered with the first insulation layer. A clearance between the neighboring linear conductors of the plurality of linear conductors is smaller than a diameter of each linear conductor and a thickness of the third wiring pattern is thicker than a thickness of the first pad pattern.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a wiring board and a semiconductor package.

  Conventionally, a wiring board is known in which a through hole is provided in a core substrate and a ceramic substrate is embedded in the through hole. In this wiring board, a build-up layer in which wiring layers and insulating layers are alternately stacked can be formed on the upper and lower surfaces of a core substrate and a ceramic substrate, and a semiconductor chip can be mounted on the uppermost wiring layer. A plurality of through wirings are formed in the ceramic substrate, and the upper wiring layer and the lower wiring layer are connected via the through wiring.

JP 2012-74536 A

  However, it is difficult to reduce the pitch of the through wiring formed in the ceramic substrate. Further, if the pitch can be reduced, it is necessary to adjust the position with high accuracy when the ceramic substrate is disposed in the through hole of the core substrate.

  The present invention has been made in view of the above points, and an object of the present invention is to provide a wiring board that does not require position adjustment of the embedded board with respect to the core board.

  The wiring board includes a core substrate including a resin substrate and a through-hole penetrating the resin substrate in the thickness direction, a plate-like body, and a plurality of linear conductors penetrating the plate-like body in the thickness direction. The embedded substrate disposed in the through hole, a first insulating layer covering the first surface of the resin substrate, a first pad pattern formed on the first surface of the embedded substrate, A third wiring pattern formed on the first surface of the resin substrate and covered with the first insulating layer, wherein the plurality of linear conductors are adjacent to each other in diameter than the diameter of each linear conductor. It is a requirement that the distance between the conductors is small, and the thickness of the third wiring pattern is thicker than the thickness of the first pad pattern.

  According to the disclosed technology, it is possible to provide a wiring board that does not require position adjustment of the embedded board with respect to the core board.

It is sectional drawing which illustrates the wiring board which concerns on 1st Embodiment. FIG. 3 is a diagram (part 1) illustrating a manufacturing process of the wiring board according to the first embodiment; FIG. 6 is a diagram (part 2) illustrating the manufacturing process of the wiring board according to the first embodiment; It is a figure explaining a coaxial pad pattern. It is FIG. (1) explaining the back surface feed plating alignment mark formation process. It is FIG. (2) explaining the back surface feed plating alignment mark formation process. It is FIG. (3) explaining the back surface feed plating alignment mark formation process. It is FIG. (4) explaining the back surface feed plating alignment mark formation process. It is FIG. (5) explaining the back surface feed plating alignment mark formation process. It is FIG. (6) explaining the back surface feed plating alignment mark formation process. FIG. 10 is a diagram (part 1) illustrating another manufacturing process of the wiring board according to the first embodiment; FIG. 10 is a diagram (part 2) illustrating another manufacturing process of the wiring board according to the first embodiment; It is sectional drawing which illustrates the wiring board which concerns on 3rd Embodiment. It is a figure which illustrates the manufacturing process of the wiring board which concerns on 3rd Embodiment. It is sectional drawing which illustrates the wiring board which concerns on 4th Embodiment. It is a figure which illustrates the manufacturing process of the wiring board which concerns on 4th Embodiment. It is sectional drawing which illustrates the wiring board which concerns on 5th Embodiment. It is a figure which illustrates the manufacturing process of the wiring board which concerns on 5th Embodiment. It is sectional drawing which illustrates the wiring board which concerns on 6th Embodiment. It is FIG. (The 1) which illustrates the manufacturing process of the wiring board which concerns on 6th Embodiment. It is FIG. (The 2) which illustrates the manufacturing process of the wiring board which concerns on 6th Embodiment. It is FIG. (The 1) which illustrates the core board | substrate which concerns on 7th Embodiment. It is FIG. (The 2) which illustrates the core board | substrate which concerns on 7th Embodiment. This is an example in which the core substrate shown in FIG. 22 is applied to the first embodiment. It is sectional drawing which illustrates the wiring board which concerns on 8th Embodiment. It is a figure which illustrates the manufacturing process of the wiring board which concerns on 8th Embodiment. 10 is a cross-sectional view illustrating a wiring board according to Modification 1. FIG. 10 is a cross-sectional view illustrating a wiring board according to Modification 2. FIG. 10 is a diagram illustrating a manufacturing process of a wiring board according to Modification 2. FIG. 10 is a cross-sectional view illustrating a wiring board according to application example 1. FIG. It is a figure explaining the wiring method of the upper layer of the wiring board concerning the example 1 of application. 12 is a cross-sectional view illustrating a semiconductor package according to Application Example 2. FIG.

  Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to the same component and the overlapping description may be abbreviate | omitted.

<First Embodiment>
[Structure of Wiring Board According to First Embodiment]
First, the structure of the wiring board according to the first embodiment will be described. FIG. 1 is a cross-sectional view illustrating a wiring board according to the first embodiment, and FIG. 1B is an enlarged view of the embedded substrate 100 of FIG.

  Referring to FIG. 1, a wiring board 1 includes a core substrate 10, insulating layers 21 and 22, via wirings 31 and 32, wiring patterns 41 and 42, insulating layers 51 and 52, wiring layers 61 and 62, an insulating layer 71 and 72, wiring layers 81 and 82, and an embedded substrate 100.

  In the present embodiment, for convenience, the wiring layer 81 side of the wiring substrate 1 is referred to as the upper side or the first surface side, and the wiring layer 82 side is referred to as the lower side or the second surface side. Further, the surface on the wiring layer 81 side of each part is the upper surface or the first surface, and the surface on the wiring layer 82 side is the lower surface or the second surface. However, the wiring board 1 can be used upside down, or can be arranged at an arbitrary angle. Further, the planar view indicates that the object is viewed from the normal direction of the upper surface of the core substrate 10, and the planar shape indicates the shape of the object viewed from the normal direction of the upper surface of the core substrate 10. .

  The core substrate 10 includes a resin substrate 11, a wiring pattern 12, a wiring pattern 13, and a through wiring 14. In the core substrate 10, for example, the resin substrate 11 has a rectangular planar shape, and a through hole 11 x that penetrates in the thickness direction is formed. The through hole 11x is a portion where the embedded substrate 100 is disposed. A wiring pattern 12 is formed on the upper surface of the resin substrate 11 and a wiring pattern 13 is formed on the lower surface. The wiring pattern 12 and the wiring pattern 13 are electrically connected through a through wiring 14 that fills a through hole 11 y that penetrates the resin substrate 11. The wiring pattern 12 is a typical example of the third wiring pattern according to the present invention, and the wiring pattern 13 is a typical example of the fourth wiring pattern according to the present invention.

  Note that an arbitrary number of multilayer wiring layers including the wiring patterns 12 and 13 may be formed on the upper and lower surfaces of the resin substrate 11. The number of wiring layers on the upper surface side of the core substrate 10 and the number of wiring layers on the lower surface side may not be the same. However, the number of wiring layers on the upper surface side of the core substrate 10 is reduced due to warpage suppression and manufacturing ease. The number of wiring layers on the lower surface side is preferably the same. The number of wiring layers of the core substrate 10 is arbitrary as long as the relationship of the thickness of the core substrate 10 + the thickness of the insulating layer necessary on the core substrate 10 × 2 (both sides) = the thickness of the embedded substrate 100 is satisfied. Can be selected.

  As the resin substrate 11, for example, a so-called glass epoxy substrate in which a reinforcing member such as glass fiber is impregnated with a thermosetting epoxy resin or the like can be used. The thickness of the resin substrate 11 can be, for example, about 40 to 180 μm. However, the resin substrate 11 may not have a reinforcing member. For example, copper (Cu) can be used as the material of the wiring patterns 12 and 13 and the through wiring 14. The thickness of the wiring patterns 12 and 13 can be about 10 to 20 μm, for example.

  The embedded substrate 100 is disposed in the through hole 11 x of the resin substrate 11. The embedded substrate 100 includes a plate-like body 110 made of aluminum oxide and a plurality of linear conductors 120 penetrating the plate-like body 110 in the thickness direction. The linear conductor 120 is a portion formed by filling a large number of through holes 110x penetrating in the thickness direction over the entire plate-like body 110 with a metal material. The thickness of the embedded substrate 100 can be, for example, about 50 to 200 μm.

  The plate-like body 110 may be formed from other than aluminum oxide. The plate-like body 110 can be formed from, for example, silicon oxide, mullite, aluminum nitride, glass ceramics (a composite material of glass and ceramics), barium strontium titanate, barium titanate, strontium titanate, titanium zircon and the like.

The linear conductors 120 are preferably formed so densely that the distance between the adjacent linear conductors 120 is smaller than the diameter of each linear conductor 120. The linear conductor 120 can be formed with a density of 4 × 10 ⁶ pieces / mm ² or more and 1 × 10 ¹⁰ pieces / mm ² or less, for example. However, the arrangement form of the linear conductor 120 is not particularly limited, and may be arranged, for example, in a hexagonal form or in a grid form. For example, copper (Cu), silver (Ag), nickel (Ni), or the like can be used as the metal material forming the linear conductor 120.

  The linear conductor 120 has an upper end surface exposed from the upper surface of the plate-like body 110 and a lower end surface exposed from the lower surface of the plate-like body 110. The respective linear conductors 120 are formed over substantially the entire surface of the plate-like body 110 at substantially constant intervals substantially parallel to each other. The linear conductor 120 is formed, for example, in a circular shape in plan view, and the diameter thereof can be set to, for example, about 50 nm to 2 μm. However, the circular shape in plan view here includes not only a strictly circular shape but also a substantially circular shape.

  The upper surface of the plate-like body 110 and the upper end surface of the linear conductor 120 can be flush with each other, for example. Moreover, the lower surface of the plate-like body 110 and the lower end surface of the linear conductor 120 can be flush, for example.

  The insulating layer 21 is formed on the upper surface of the resin substrate 11 and covers the wiring pattern 12. The insulating layer 21 covers the periphery of the protruding portion of the embedded substrate 100. The insulating layer 21 does not cover the upper surface of the embedded substrate 100, and the upper surface of the embedded substrate 100 is exposed from the upper surface of the insulating layer 21. The insulating layer 21 has a via hole 21x, and the upper surface of the wiring pattern 12 is exposed in the via hole 21x.

  The insulating layer 22 is formed on the lower surface of the resin substrate 11 and covers the wiring pattern 13. The insulating layer 22 covers the periphery of the protruding portion of the embedded substrate 100. The insulating layer 22 does not cover the lower surface of the embedded substrate 100, and the lower surface of the embedded substrate 100 is exposed from the lower surface of the insulating layer 22. The insulating layer 22 has a via hole 22x, and the lower surface of the wiring pattern 13 is exposed in the via hole 22x. The insulating layer 21 is a typical example of the first insulating layer according to the present invention, and the insulating layer 22 is a typical example of the second insulating layer according to the present invention.

  The insulating layer 21 is filled in a gap (space) formed by the side surface (side wall) of the embedded substrate 100 and the inner wall surface of the through hole 11x. However, the insulating layer 22 may be filled in all or part of the gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x.

As a material of the insulating layers 21 and 22, for example, a thermosetting insulating resin whose main component is an epoxy resin, a phenol resin, a polyimide resin, an acrylic resin, a vinyl ester resin, or the like can be used. The insulating layers 21 and 22 may contain a filler such as silica (SiO ₂ ). The thermosetting insulating resin used for the insulating layers 21 and 22 may be a non-photosensitive insulating resin or a photosensitive insulating resin. Further, each of the insulating layers 21 and 22 may be laminated by laminating a plurality of insulating resins having different elastic moduli for stress relaxation. The thicknesses of the insulating layers 21 and 22 can be appropriately determined according to the thickness of the wiring patterns 12 and 13 formed on the upper and lower surfaces of the resin substrate 11 or the multilayer wiring layer.

  The via wiring 31 fills the via hole 21x and is electrically connected to the wiring pattern 12 exposed in the via hole 21x. For example, the upper surface of the via wiring 31, the upper surface of the insulating layer 21, and the upper surface of the embedded substrate 100 can be polished to be flush with each other (same plane). The via wiring 32 fills the via hole 22x and is electrically connected to the wiring pattern 13 exposed in the via hole 22x. The lower surface of the via wiring 32, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100 can be polished to be flush with each other, for example. As a material of the via wirings 31 and 32, for example, copper (Cu) can be used. The height of the via wirings 31 and 32 can be set to about 10 to 20 μm, for example.

  As described above, by planarizing the upper surface of the via wiring 31, the upper surface of the insulating layer 21, and the upper surface of the embedded substrate 100 by polishing, a fine pattern can be easily formed on the planarized surface. Further, by flattening the lower surface of the via wiring 32, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100 by polishing, a fine pattern can be easily formed on the flattened surface.

  The wiring pattern 41 is formed on a flat surface formed by the upper surface of the via wiring 31, the upper surface of the insulating layer 21, and the upper surface of the embedded substrate 100. A part of the wiring pattern 41 is electrically connected to the wiring pattern 12 via the via wiring 31. The wiring pattern 42 is formed on a flat surface formed by the lower surface of the via wiring 32, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100. A part of the wiring pattern 42 is electrically connected to the wiring pattern 13 via the via wiring 32. As a material of the wiring patterns 41 and 42, for example, copper (Cu) or the like can be used. The thickness of the wiring patterns 41 and 42 can be about 1 to 10 μm, for example. The wiring pattern 41 is a typical example of the first wiring pattern according to the present invention, and the wiring pattern 42 is a typical example of the second wiring pattern according to the present invention.

  The wiring pattern 41 formed on the upper surface of the embedded substrate 100 and the wiring pattern 42 formed on the lower surface of the embedded substrate 100 are arranged at positions facing each other with the embedded substrate 100 interposed therebetween. The wiring pattern 41 formed on the upper surface of the embedded substrate 100 is a pad pattern (first pad pattern), and is directly connected to the upper ends of the plurality of linear conductors 120. The wiring pattern 42 formed on the lower surface of the embedded substrate 100 is a pad pattern (second pad pattern), and is directly connected to the lower end surfaces of the plurality of linear conductors 120. One pad constituting the wiring pattern 41 and one pad constituting the wiring pattern 42 arranged so as to be opposed thereto are electrically connected through a plurality of linear conductors 120. The via wiring 31 and the wiring pattern 41 including the pad pattern (first pad pattern) may be collectively referred to as a first wiring layer. The via wiring 32 and the wiring pattern 42 including the pad pattern (second pad pattern) may be collectively referred to as a second wiring layer.

  As described above, by forming the pad pattern at the opposite positions on both surfaces of the embedded substrate 100, the vertical transmission path can be formed on the embedded substrate 100. When the pad pattern on the embedded substrate 100 is a coaxial pad pattern, the vertical transmission path can be made coaxial to suppress crosstalk. In this case, the coaxial pad pattern may be formed on only one surface of the embedded substrate 100. Details of the coaxial pad pattern will be described later.

  The insulating layer 51 is formed on the upper surface of the insulating layer 21 and the upper surface of the embedded substrate 100 and covers the wiring pattern 41. The insulating layer 51 has a via hole 51x, and the upper surface of the wiring pattern 41 is exposed in the via hole 51x. The insulating layer 52 is formed on the lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100 and covers the wiring pattern 42. The insulating layer 52 has a via hole 52x, and the lower surface of the wiring pattern 42 is exposed in the via hole 52x. The thickness of the insulating layers 51 and 52 can be set to about 3 to 30 μm, for example. The material of the insulating layers 51 and 52 can be the same as that of the insulating layers 21 and 22, for example. However, when a photosensitive insulating resin is used as the material of the insulating layers 51 and 52, the via holes 51x and 71x can be formed by a photolithography method, which is suitable for forming fine wiring.

  The wiring layer 61 is formed on the upper side of the insulating layer 51. The wiring layer 61 includes a via wiring filled in the via hole 51 x and a wiring pattern formed on the upper surface of the insulating layer 51. The wiring layer 61 is electrically connected to the wiring pattern 41 through the via hole 51x. The wiring layer 62 is formed below the insulating layer 52. The wiring layer 62 includes a via wiring filled in the via hole 52 x and a wiring pattern formed on the lower surface of the insulating layer 52. The wiring layer 62 is electrically connected to the wiring pattern 42 through the via hole 52x. The material of the wiring layers 61 and 62 and the thickness of the wiring pattern constituting the wiring layers 61 and 62 can be the same as those of the wiring patterns 41 and 42, for example.

  The insulating layer 71 is formed on the upper surface of the insulating layer 51 and covers the wiring layer 61. The insulating layer 71 has a via hole 71x, and the upper surface of the wiring layer 61 is exposed in the via hole 71x. The insulating layer 72 is formed on the lower surface of the insulating layer 52 and covers the wiring layer 62. The insulating layer 72 has a via hole 72x, and the lower surface of the wiring layer 62 is exposed in the via hole 72x. The material and thickness of the insulating layers 71 and 72 can be the same as that of the insulating layers 51 and 52, for example.

  The wiring layer 81 is the outermost wiring layer formed on the upper side of the insulating layer 71. The wiring layer 81 includes a via wiring filled in the via hole 71 x and a wiring pattern formed on the upper surface of the insulating layer 71. The wiring layer 81 is electrically connected to the wiring layer 61 through the via hole 71x. The wiring layer 82 is the outermost wiring layer formed below the insulating layer 72. The wiring layer 82 includes a via wiring filled in the via hole 72 x and a wiring pattern formed on the lower surface of the insulating layer 72. The wiring layer 82 is electrically connected to the wiring layer 62 through the via hole 72x. The material of the wiring layers 81 and 82 and the thickness of the wiring patterns constituting the wiring layers 81 and 82 can be the same as those of the wiring patterns 41 and 42, for example.

  The wiring layers 81 and 82 function as pads that are electrically connected to a semiconductor chip, another wiring board, or the like. If necessary, a metal layer may be formed on the upper surface of the wiring layer 81 or the lower surface of the wiring layer 82. Moreover, you may perform antioxidant process, such as OSP (Organic Solderability Preservative) process. The surface treatment layer formed by the OSP treatment is an organic film made of an azole compound or an imidazole compound.

  Examples of metal layers include an Au layer, a Ni / Au layer (a metal layer in which an Ni layer and an Au layer are stacked in this order), and a Ni / Pd / Au layer (a Ni layer, a Pd layer, and an Au layer in this order). And a laminated metal layer). Further, external connection terminals such as solder balls may be formed on the upper surface of the wiring layer 81 and the lower surface of the wiring layer 82.

  As described above, the wiring substrate 1 has a structure in which the embedded substrate 100 including the narrow-pitch linear conductor 120 is embedded in the resin substrate 11. Therefore, it is possible to provide a wiring board having a narrow pitch and high density vertical transmission path, which is difficult to realize with only a resin board, at low cost.

  Further, as will be described later, since alignment and position adjustment are not required when the embedded substrate 100 is embedded in the resin substrate 11, it can be embedded by a simple process, and the cost of the wiring substrate 1 can be reduced.

  Further, even if the pad arrangement of the semiconductor chip mounted on the wiring substrate 1 is changed, the size and position of the vertical transmission path and the like can be freely changed at the stage of forming the wiring on the embedded substrate 100. That is, since the substrate structure in which the embedded substrate 100 is embedded in the resin substrate 11 can be shared, a wide variety of wiring substrates can be manufactured at low cost.

  Although the embedded substrate 100 including the plurality of linear conductors 120 is fragile, most of the wiring substrate 1 is formed of the resin substrate 11 and the embedded substrate 100 is a small piece and is difficult to break. Further, since the embedded substrate 100 is surrounded and protected by the resin substrate 11, the wiring substrate 1 as a whole can obtain high strength. As a result, handling in the manufacturing process is facilitated and the conventional manufacturing process of the organic resin substrate can be diverted, so that the cost can be reduced.

  Further, although the embedded substrate 100 is relatively expensive, since the wiring substrate 1 is only partially used, the cost of the entire wiring substrate 1 can be suppressed.

  In addition, since the embedded substrate 100 is embedded in the resin substrate 11 and the insulating layers 21 and 22 on the resin substrate 11 and the embedded substrate 100 are polished to make the surface flat (same plane), the flat surface A fine wiring layer can be formed, and the density of planar wiring can be increased.

  Further, by forming the wiring pattern 12 and the wiring pattern 13 on the resin substrate 11 or a multilayer wiring layer including them, rewiring can be performed with a small number of layers after the embedded substrate 100 is embedded. This reduces the risk of damage to the embedded substrate 100 during the manufacturing process. Further, the connection interface on the vertical transmission path of the embedded substrate 100 can be reduced, and the transmission path length is also shortened.

  In addition, the power supply and the ground line are preferably low resistance in order to improve stability, and the wiring thickness is preferably thick. On the other hand, a thinner wiring thickness is advantageous for miniaturization of the wiring. A fine pattern for connecting to the pad of the semiconductor chip is necessary on the embedded substrate 100, and it is difficult to form a thick wiring layer in accordance with the power supply system. However, if the wiring pattern 12 or the wiring pattern 13 or a multilayer wiring layer including them is formed on the resin substrate 11 and the specification is suitable for the power supply system, the wiring specifications of the power supply system and the signal system are set. Both can be achieved.

  That is, the optimum values of the wiring thickness and the insulating layer thickness are different between the power supply system wiring and the signal wiring. In the wiring board 1, wirings of different specifications are mixed in the same substrate, such as wiring suitable for the power supply system (thick wiring pattern + thick insulating layer) on the core substrate 10 and fine wiring on the embedded substrate 100. be able to. However, a signal wiring may be formed on a part of the core substrate 10, or a power supply system wiring may be formed on a part of the embedded substrate 100. This will be described in more detail below.

  In order to ensure a stable power supply and ground, it is necessary to form a thick and wide pattern. Therefore, for example, the wiring pattern 12 formed on the core substrate 10 is a thick wiring (for example, 10 to 20 μm) suitable for the power supply system (power supply pattern or ground pattern), and the insulating layer 21 covering the wiring pattern 12 is thickly insulated. It is set as a layer (for example, 20-60 micrometers).

  In this case, when the insulating layer 21 is thinned, a parasitic capacitance is generated between the thick and wide wiring pattern 12 and the wiring pattern 41 arranged via the insulating layer 21, which may act as a capacitor. By making the insulating layer 21 thick, parasitic capacitance can be reduced. The same applies to the wiring patterns 13 and 42 and the insulating layer 22. In order to stably supply power, it is preferable to increase the diameter of the through wiring 14 that connects the wiring pattern 12 and the wiring pattern 13.

  On the other hand, since the embedded substrate 100 includes the narrow-pitch linear conductors 120 on the entire surface, the embedded substrate 100 is suitable for forming fine wirings serving as signal wirings on the embedded substrate 100. In this case, the thinner wiring thickness is suitable for miniaturization of the wiring, and the thickness of the wiring pattern constituting the wiring pattern 41 and the wiring layers 61 and 81 is preferably 1 to 10 μm. In order to connect the fine wiring layers, the sizes of the via holes 51x and 71x provided in the insulating layers 51 and 71 must be reduced. In order to form a small diameter via hole, a thinner insulating layer is suitable, and it is preferably 3 to 30 μm. Furthermore, by using a photosensitive insulating resin as the material of the insulating layer, the via holes 51x and 71x can be formed by photolithography, and a small diameter via hole can be easily formed. The same applies to the wiring pattern 42, the wiring layers 62 and 82, and the insulating layers 52 and 72.

[Method for Manufacturing Wiring Board According to First Embodiment]
Next, a method for manufacturing a wiring board according to the first embodiment will be described. 2 and 3 are diagrams illustrating the manufacturing process of the wiring board according to the first embodiment.

  First, in the step shown in FIG. 2A, the core substrate 10 is manufactured. In order to produce the core substrate 10, for example, a resin substrate 11 such as a so-called glass epoxy substrate in which a reinforcing member such as a glass fiber is impregnated with a thermosetting epoxy resin or the like is prepared, and the resin substrate 11 is machined. The through hole 11x and the through hole 11y are formed by laser processing or the like. The through hole 14 is formed by filling the through hole 11y with a conductor such as copper (Cu) by a plating method or the like. Thereafter, wiring patterns 12 and 13 made of copper (Cu) or the like are formed on the upper and lower surfaces of the resin substrate 11 by a subtractive method, a semi-additive method, or the like. The wiring pattern 12 and the wiring pattern 13 are electrically connected through the through wiring 14. However, the resin substrate 11 may not have a reinforcing member. Alternatively, the through hole 11y, the through wiring 14, and the wiring patterns 12 and 13 may be formed in the resin substrate 11, and then the through hole 11x may be formed.

  Next, in the step shown in FIG. 2B, the embedded substrate 100 is manufactured and placed in the through hole 11 x of the core substrate 10. The embedded substrate 100 is formed thicker than the total thickness of the core substrate 10 including the thickness of the resin substrate 11 and the wiring patterns 12 and 13, and the upper and lower surfaces protrude from the upper and lower surfaces of the wiring patterns 12 and 13 of the core substrate 10. Are arranged as follows. Thereafter, a film-like insulating resin to be the insulating layers 21 and 22 is laminated on both surfaces of the core substrate 10 so as to cover the upper and lower surfaces of the embedded substrate 100.

  When the embedded substrate 100 is disposed in the through hole 11 x of the core substrate 10, it is not necessary to adjust the position of the embedded substrate 100 with respect to the core substrate 10. This is because the embedded substrate 100 is formed with a narrow-pitch linear conductor 120 penetrating in the thickness direction on the entire surface. Therefore, even if the embedded substrate 100 is displaced in the through hole 11x, when the wiring patterns 41 and 42 (pad pattern) are formed in the process of FIG. This is because it is electrically connected to the linear conductor 120.

  The embedded substrate 100 can be manufactured as follows, for example. First, a flat plate made of aluminum (Al) is prepared, and a plate-like body 110 made of aluminum oxide having a large number of through-holes 110x is formed from the prepared flat plate by an anodic oxidation method.

  The through-hole 110x can be, for example, circular in plan view, and the diameter in that case can be, for example, about 50 nm to 2 μm. Further, it is preferable that the through holes 110x are formed so dense that the interval between the adjacent through holes 110x is smaller than the diameter of the through holes 110x. However, the arrangement form of the through holes 110x is not particularly limited, and may be arranged in a hexagonal form or a grid form, for example.

  In the anodic oxidation method, a flat plate made of aluminum (Al) is immersed as an anode in an electrolyte (preferably an aqueous sulfuric acid solution), and an electrode such as platinum (Pt) disposed opposite thereto is energized as a cathode (pulse voltage is applied). Application). Thus, a plate-like body 110 (aluminum anodic oxide film) made of aluminum oxide in which a large number of through holes 110x are formed can be formed.

  Thereafter, the linear conductor 120 is formed by filling the through hole 110x formed in the plate-like body 110 with a metal material. Thereby, the embedded substrate 100 including the plate-like body 110 made of aluminum oxide and the plurality of linear conductors 120 penetrating the plate-like body 110 in the thickness direction is manufactured. The linear conductor 120 can be formed by filling the through-hole 110x with a conductive paste such as copper (Cu) or silver (Ag), for example, using a plating method, a screen printing method, an inkjet method, or the like.

  Further, if necessary, both surfaces of the linear conductor 120 can be polished and flattened by mechanical polishing, chemical mechanical polishing (CMP), or the like, and both end surfaces of the linear conductor 120 can be exposed on both surfaces of the plate-like body 110. In this manner, the embedded substrate 100 in which the fine conductors 120 having a small diameter penetrating the plate body 110 in the thickness direction are provided on the plate body 110 at a high density can be manufactured. The embedded substrate 100 may be manufactured in parallel with the step of FIG. 2A or before the step of FIG.

  Next, in the step shown in FIG. 2C, the insulating resin to be the insulating layers 21 and 22 is pressed toward the core substrate 10 while being heated. As a result, the insulating resin flows into the periphery of the embedded substrate 100 in the through hole 11x and is then cured to form the insulating layers 21 and 22. At this time, the upper surface of the embedded substrate 100 is covered with the insulating layer 21, and the lower surface is covered with the insulating layer 22. Note that the interface between the insulating layer 21 and the insulating layer 22 around the embedded substrate 100 may be at any position.

  Here, an example of the thickness of each part of the structure shown in FIG. 2C is as follows. For example, the thickness of the resin substrate 11 is 40 μm, the thickness of the wiring patterns 12 and 13 is 10 μm, the thickness of the insulating layers 21 and 22 on the wiring patterns 12 and 13 is 15 μm, and the thickness of the embedded substrate 100 is 80 μm. It can be. Insulating layers 21 and 22 are formed on the upper and lower surfaces of the embedded substrate 100 by a thickness of 5 μm. In this case, the total thickness of the structure shown in FIG. 2C (thickness from the lower surface of the insulating layer 22 to the upper surface of the insulating layer 21) is 90 μm.

Next, in the step shown in FIG. 2D, via holes 21 x that penetrate the insulating layer 21 and expose the upper surface of the wiring pattern 12 are formed in the insulating layer 21. In addition, a via hole 22 x that penetrates the insulating layer 22 and exposes the lower surface of the wiring pattern 13 is formed in the insulating layer 22. The via holes 21x and 22x can be formed by, for example, a laser processing method using a CO ₂ laser or the like. After forming the via holes 21x and 22x, it is preferable to perform a desmear process to remove the resin residue attached to the surfaces of the wiring patterns 12 and 13 exposed at the bottoms of the via holes 21x and 22x. When the insulating layers 21 and 22 are formed from a photosensitive insulating resin, the via holes 21x and 22x may be formed by photolithography.

  Next, in the process shown in FIG. 3A, via wirings 31 and 32 are formed by filling the via holes 21x and 22x with copper (Cu) or the like by plating or the like. The via wirings 31 and 32 are electrically connected to the wiring patterns 12 and 13.

  Next, in the step shown in FIG. 3B, both surfaces of the structure shown in FIG. 3A are polished by mechanical polishing, chemical mechanical polishing (CMP), etc., and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. The lower surface of the embedded substrate 100 is exposed from the lower surface of the insulating layer 22. For example, the upper surface of the embedded substrate 100, the upper surface of the insulating layer 21, and the upper surface of the via wiring 31 can be flush with each other. Further, the lower surface of the embedded substrate 100, the lower surface of the insulating layer 22, and the lower surface of the via wiring 32 can be flush, for example.

  The polishing amount of each surface of the structure shown in FIG. 3A can be set to 5 μm, for example. For example, when the total thickness of the structure shown in FIG. 3A (the thickness from the lower surface of the insulating layer 22 to the upper surface of the insulating layer 21) is 90 μm, the upper surface and the lower surface are polished by 5 μm at a time. The total thickness (same as above) of the structure shown in (b) is 80 μm. The polished surface has very high flatness and facilitates the formation of fine wiring described later.

  Next, in the step shown in FIG. 3C, the wiring pattern 41 is formed on the upper surface of the insulating layer 21 and the upper surface of the embedded substrate 100. Further, the wiring pattern 42 is formed on the lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100. The wiring patterns 41 and 42 can be formed using various wiring forming methods such as a semi-additive method and a subtractive method.

  As described above, a vertical transmission path can be formed on the embedded substrate 100 by forming pad patterns on opposite sides of the embedded substrate 100. When the pad pattern on the embedded substrate 100 is a coaxial pad pattern, the vertical transmission path can be made coaxial to suppress crosstalk.

  In this step, a back surface feeding plating alignment mark forming process can also be used. In this case, the positional deviation of the upper and lower wiring patterns can be reduced to half that when the same process is not used. Details of the coaxial pad pattern and the back surface feeding plating alignment mark forming process will be described later.

  Next, in the step shown in FIG. 3D, the insulating layer 51, the wiring layer 61, the insulating layer 71, and the wiring layer 81 are sequentially stacked on the upper side of the structure shown in FIG. In addition, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked below the structure shown in FIG. The insulating layers 51, 71, 52 and 72 can be formed by the same method as the insulating layers 21 and 22. The wiring layers 61, 81, 62, and 82 have a thinner wiring thickness and a smaller wiring pitch than the wiring patterns 12 and 13.

  The wiring layers 61, 81, 62, and 82 can be formed using various wiring forming methods such as a semi-additive method and a subtractive method. A photosensitive insulating resin is used as the insulating layers 51, 71, 52, and 72, the via holes 51x, 71x, 52x, and 72x are formed by a photolithography method, and the wiring layers 61, 81, 62, and 82 are formed by a semi-additive method. By forming, each wiring layer can be miniaturized. Through the above steps, the wiring substrate 1 shown in FIG. 1 is completed.

  Here, the coaxial pad pattern and the back surface feeding plating alignment mark forming process will be described.

(Coaxial pad pattern)
When the upper surface of the embedded substrate 100 is exposed from the insulating layer 21, the wiring pattern 41 formed on the upper surface of the embedded substrate 100 has a structure having a pad pattern 411 and a ground pattern 412 as shown in FIG. Can do. In FIG. 4, the pad pattern 411 is a pattern in which circular pads that are electrically independent from each other are arranged vertically and horizontally. The pad pattern 411 is surrounded by the ground pattern 412 with a predetermined interval in plan view. Each pad constituting the pad pattern 411 is electrically connected to the plurality of linear conductors 120.

  In other words, the plurality of linear conductors 120 connected to the respective pads constituting the pad pattern 411 form a vertical transmission path extending below the respective pads. The pads constituting the pad pattern 411 and the periphery of the vertical transmission path extending below each pad are surrounded by a ground pattern 412 and a plurality of linear conductors 120 connected to the ground pattern 412. As a result, a coaxial structure can be realized, and crosstalk between adjacent vertical transmission paths can be suppressed even when vertical transmission paths are formed with a narrow pitch. Although the same coaxial pad pattern may be formed on the lower surface of the embedded substrate 100, the above effect can be obtained if the coaxial pad pattern is formed on either the upper or lower surface of the embedded substrate 100.

(Back feed plating alignment mark formation process)
When both surfaces of the embedded substrate 100 are exposed from the insulating layers 21 and 22, as shown in FIGS. 5 to 10, when the wiring patterns 41 and 42 are formed on both surfaces of the embedded substrate 100, the back surface feeding plating method is used. An alignment mark formation process can be applied. When this process is used, the positional deviation of the wiring patterns formed on the upper and lower surfaces can be reduced to half that when this process is not used. Further, even when the embedded substrate 100 is embedded, even if the linear conductor 120 of the embedded substrate 100 is tilted with respect to the core substrate 10, a deviation due to the tilt can be corrected. This will be described in more detail below.

  First, as shown in FIG. 5A, seed layers 415 and 416 are formed on the upper and lower surfaces of the embedded substrate 100 after the step of FIG. 3B.

  Next, as shown in FIG. 5B, a resist 311 having an opening 311 x is formed on the seed layer 415 with reference to an alignment mark (not shown) provided in advance on the core substrate 10, and the seed layer 416. A resist 312 having no opening is formed thereon. Then, an electrolytic plating layer 417 made of copper (Cu) or the like is formed on the seed layer 415 exposed in the opening 311x by an electrolytic plating method using the seed layer 415 as a power feeding layer.

  Next, as shown in FIG. 5C, the resist 311 shown in FIG. 5B is removed. 417a is an alignment mark on the upper surface of the embedded substrate 100. Then, in the resist 312, an opening 312x having a larger planar shape than the alignment mark 417a is formed at a position overlapping the alignment mark 417a in plan view, and the seed layer 416 is exposed in the opening 312x.

  Next, as shown in FIG. 6, the seed layer 415 not covered with the electrolytic plating layer 417 and the seed layer 416 not covered with the resist 312 (the seed layer 416 exposed in the opening 312x) are removed by etching. To do. Here, FIG. 6 (b) is a partial plan view of FIG. 6 (a), FIG. 6 (c) is a partial bottom view of FIG. 6 (a), and FIGS. 6 (b) and 6 (c). Is drawn smaller than FIG. 6A (the same applies to FIGS. 7 to 9).

  In this step, the wiring pattern 41 in which the electrolytic plating layer 417 is laminated on the seed layer 415 is formed. The wiring pattern 41 includes a pad pattern 411 in which an electrolytic plating layer 417 is stacked on a seed layer 415 and a ground pattern 412 in which an electrolytic plating layer 417 is stacked on the seed layer 415. The ground pattern 412 surrounds the pad pattern 411 in plan view.

  In this example, four alignment marks 417 a are formed outside the region where the pad pattern 411 is formed on the upper surface of the embedded substrate 100. Four openings 312x having a planar shape larger than that of the alignment mark 417a are formed on the lower surface of the embedded substrate 100 at positions overlapping the alignment mark 417a in plan view. However, the numbers of alignment marks 417a and openings 312x are not limited to this.

  Next, as shown in FIG. 7, power is supplied from the upper surface side of the embedded substrate 100 via the wiring pattern 41 and the linear conductor 120 to perform electrolytic plating on the lower surface of the embedded substrate 100, and copper (Cu ) And the like are deposited to form alignment marks 419. Since the alignment mark 419 is formed only on a portion where the wiring pattern 41 exists on the upper surface of the embedded substrate 100 (a portion overlapping the wiring pattern 41 in plan view), the alignment mark 417a is accurately transferred. Next, as shown in FIG. 8, the resist 312 is removed.

  Next, as shown in FIG. 9, a wiring pattern 42 is formed on the lower surface of the embedded substrate 100 with the transferred alignment mark 419 as a reference. Specifically, a resist having an opening is formed on the seed layer 416 with the alignment mark 419 as a reference. Then, an electrolytic plating layer 418 made of copper (Cu) or the like is formed on the seed layer 416 exposed in the opening by an electrolytic plating method using the seed layer 416 as a power feeding layer. Next, the resist is removed, and the seed layer 416 not covered with the electrolytic plating layer 418 is removed by etching.

  Thereby, the wiring pattern 42 in which the electrolytic plating layer 418 is laminated on the seed layer 416 is formed. The wiring pattern 42 includes a pad pattern 421 in which an electrolytic plating layer 418 is stacked on a seed layer 416 and a ground pattern 422 in which an electrolytic plating layer 418 is stacked on the seed layer 416. The ground pattern 422 surrounds the pad pattern 421 in plan view.

  If the adhesion between the alignment mark 419 and the embedded substrate 100 is low, a plating film may not be formed on the seed layer 416 and may be removed together in order to prevent peeling in a later process. . In that case, the alignment mark 419 is removed, and the opening 418a remains.

  Generally, in the formation of a wiring pattern, the position of the actually exposed pattern is shifted from the design value due to the overlay position accuracy of the exposure apparatus used at the time of resist patterning. For example, in the case of an exposure apparatus with an overlay position accuracy of ± 5 μm, even if the same alignment mark is used as a reference, the position of the actually exposed pattern is exposed to a different position every time within a range of 5 μm or less.

  When wiring patterns are formed on the upper and lower surfaces of the embedded substrate 100, two exposures are necessary. Therefore, when the same alignment mark provided in advance on the core substrate 10 is used as a reference, the wiring pattern is displaced between the upper surface and the lower surface by 5 μm with respect to the design value by one exposure on each of the upper surface and the lower surface of the embedded substrate 100. May occur up to 10 μm.

  On the other hand, also in the case of the back surface feeding plating alignment mark formation process described with reference to FIGS. 6 to 9, when the exposure is performed on the basis of the alignment mark provided in advance on the core substrate 10 during the exposure on the upper surface side of the embedded substrate 100. The position of the wiring pattern 41 is shifted by a maximum of 5 μm. However, the alignment mark 417 a in the same pattern is also shifted together with the wiring pattern 41. That is, the positional deviation between the wiring pattern 41 on the upper surface side of the embedded substrate 100 and the alignment mark 417a is zero.

  Subsequently, the alignment mark 417 a is transferred to the lower surface side of the embedded substrate 100 to form an alignment mark 419. Then, exposure of the lower surface side of the embedded substrate 100 is performed using the alignment mark 419 as a new reference. There is a possibility that a maximum positional deviation of 5 μm may occur in the exposure on the lower surface side of the embedded substrate 100, but since the positional deviation on the upper surface side is zero, the positional deviation between the upper wiring pattern 41 and the lower wiring pattern 42 is The maximum is 5 μm. That is, by using the back surface feeding plating alignment mark forming process, the positional deviation of the wiring patterns on the upper and lower surfaces can be reduced by half compared to the case where the same process is not used.

  Next, it is assumed that when the embedded substrate 100 is embedded in the core substrate 10, the upper surface of the embedded substrate 100 is inclined without being parallel to the upper surface of the core substrate 10. In this case, the cross-sectional structure after the embedded substrate 100 is exposed in the step of FIG. 3B is as shown in FIG. 10A, and the linear conductor 120 is not perpendicular to the core substrate 10 but inclined. It becomes a state. In this state, even if the pad patterns 411 and 421 are formed at completely opposite positions with the embedded substrate 100 in between, the linear conductor 120 is inclined, so that the pad pattern 411 and the pad pattern 421 are sufficiently connected. Not.

  On the other hand, when the back surface feed plating alignment mark formation process is used, the position where the alignment mark 419 is transferred moves in the direction of the arrow according to the inclination of the linear conductor 120 as shown in FIG. Therefore, by forming the pad pattern 421 using the transferred alignment mark 419 as a reference, as shown in FIG. 10C, the position of the pad pattern 421 is also the same distance as the arrow in FIG. 10B. Moving. Thereby, the inclination of the linear conductor 120 can be corrected, and the upper surface pad pattern 411 and the lower surface pad pattern 421 can be reliably connected.

<Second Embodiment>
In the second embodiment, another example of the method for manufacturing the wiring board 1 according to the first embodiment will be described. In the second embodiment, description of the same components as those of the already described embodiments may be omitted.

  First, after performing the same process as FIG. 2A, in the process shown in FIG. 11A, an opening corresponding to the through hole 11x is provided on the lower surface side of the structure shown in FIG. The insulating resin 22 is formed by laminating and curing the insulating resin. Then, a temporary fixing film 313 serving as a support is laminated on the lower surface side of the insulating layer 22. Next, the embedded substrate 100 is manufactured by the same method as in the first embodiment, and is placed on the upper surface of the temporary fixing film 313 exposed in the through hole 11x of the core substrate 10 and temporarily fixed. At this time, the embedded substrate 100 is disposed such that the upper surface protrudes from the upper surface of the core substrate 10. Next, a film-like insulating resin that becomes the insulating layer 21 is laminated on the upper surface of the core substrate 10 so as to cover the upper surface of the embedded substrate 100. It is to be noted that an arbitrary number of multilayer wiring layers including the wiring patterns 12 and 13 may be formed on the upper and lower surfaces of the resin substrate 11 in the same manner as in the first embodiment.

  Next, in the step shown in FIG. 11B, the insulating resin to be the insulating layer 21 is pressed toward the temporary fixing film 313 while heating. Thereby, a part of the insulating resin that becomes the insulating layer 21 flows into the periphery of the embedded substrate 100 in the through hole 11x. At this time, the upper surface of the embedded substrate 100 is covered with the insulating layer 21. After the insulating layer 21 is cured, the temporary fixing film 313 is peeled off to expose the lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100. For example, the lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100 can be flush with each other.

  Next, in the step shown in FIG. 11C, via holes 21x and 22x are formed in the same manner as in the step shown in FIG. 2D, and vias 21x are formed in the via holes 21x in the same manner as in the step shown in FIG. A wiring 31 is formed. At this time, only the seed layer 32a is formed on the via hole 22x side. The seed layer 32a is formed so as to continuously cover the lower surface of the insulating layer 22, the lower surface of the embedded substrate 100, and the inner wall surface and the bottom surface of the via hole 22x.

  Next, in the step shown in FIG. 11D, similarly to the step shown in FIG. 3B, the upper surface of the structure shown in FIG. 11C is polished, and the upper surface of the embedded substrate 100 is replaced with the insulating layer 21. It is exposed from the top surface of. For example, the upper surface of the embedded substrate 100, the upper surface of the insulating layer 21, and the upper surface of the via wiring 31 can be flush with each other.

  Thereafter, in the same manner as the steps shown in FIG. 3C and FIG. 3D, the wiring pattern 41, the insulating layer 51, the wiring layer 61, the insulating layer 71, and the upper side of the structure shown in FIG. Wiring layers 81 are sequentially stacked. Further, the via wiring 32 and the wiring pattern 42 are formed on the lower side of the structure shown in FIG. At this time, the via wiring 32 and the wiring pattern 42 can be integrally formed by an electrolytic plating method using the seed layer 32a as a power feeding layer. Thereafter, the insulating layer 52, the wiring layer 62, the insulating layer 72, and the wiring layer 82 are sequentially stacked on the wiring pattern 42. Through the above steps, the wiring substrate 1 shown in FIG. 1 is completed.

  In addition, it is good also as a process of Fig.12 (a) and FIG.12 (b) instead of the process of Fig.11 (a) and FIG.11 (b). 12A and 12B, an insulating layer 23 having characteristics different from those of the insulating layers 21 and 22 is formed so as to fill a gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x. This is an example.

  First, in the step shown in FIG. 12A, the embedded substrate 100 is disposed and temporarily fixed on the upper surface of the temporary fixing film 313 exposed in the through hole 11 x of the core substrate 10. Then, before laminating the film-like insulating resin to be the insulating layer 21 on the upper surface of the core substrate 10, the insulating layer 23 and the insulating layer 23 are filled so as to fill a gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x. Filled with a liquid insulating resin to be cured. Next, a film-like insulating resin that becomes the insulating layer 21 is laminated on the upper surface of the core substrate 10 so as to cover the upper surface of the embedded substrate 100.

  Here, as the liquid insulating resin to be the insulating layer 23, a resin having a low elastic modulus is selected with respect to the insulating resin to be the insulating layer 21, thereby forming a stress relaxation layer around the embedded substrate 100 by the insulating layer 23. can do. In addition, in the wiring pattern 12, if the pattern 12a surrounding the periphery of the through hole 11x in a plan view is prepared, the pattern 12a functions as a dam when filled with a liquid insulating resin, and the liquid insulating resin is not intended. This is preferable because it can be prevented from flowing out.

  Next, in the step shown in FIG. 12B, the insulating resin to be the insulating layer 21 is pressed to the temporary fixing film 313 side while heating each insulating resin to be the insulating layers 21 and 23, and then cured. At this time, the upper surface of the embedded substrate 100 is covered with the insulating layer 21. Next, the temporary fixing film 313 is peeled off to expose the lower surface of the insulating layer 22, the lower surface of the insulating layer 23, and the lower surface of the embedded substrate 100. For example, the lower surface of the insulating layer 22, the lower surface of the insulating layer 23, and the lower surface of the embedded substrate 100 can be flush with each other. The subsequent steps are the same as those shown in FIGS. 11 (c) and 11 (d).

  As described above, in the second embodiment, the number of times of polishing is only one time of polishing the upper surface of the structure shown in FIG. 11C in the step shown in FIG. On the other hand, in the first embodiment, since both surfaces of the structure shown in FIG. 3A are polished in the step shown in FIG. 3B, the number of times of polishing is two. Since the polishing process is expensive, the manufacturing process according to the second embodiment can reduce the manufacturing cost of the wiring board as compared with the manufacturing process according to the first embodiment.

<Third Embodiment>
In the third embodiment, an example of a wiring board using a board structure that can be used for general purposes will be described. Note that in the third embodiment, description of the same components as those of the already described embodiments may be omitted.

[Structure of Wiring Board According to Third Embodiment]
First, the structure of the wiring board according to the third embodiment will be described. FIG. 13 is a cross-sectional view illustrating a wiring board according to the third embodiment.

  Referring to FIG. 13, the wiring board 2 is mainly different from the wiring board 1 (see FIG. 1) in that a wiring pattern is not formed on the upper and lower surfaces of the resin substrate 11.

  In the wiring substrate 2, the insulating layer 21 is formed on the upper surface of the resin substrate 11. The insulating layer 21 does not cover the embedded substrate 100, and the upper surface of the embedded substrate 100 is exposed from the upper surface of the insulating layer 21. The insulating layer 22 is formed on the lower surface of the resin substrate 11. The insulating layer 22 does not cover the embedded substrate 100, and the lower surface of the embedded substrate 100 is exposed from the lower surface of the insulating layer 22. A through wiring 14 is provided that fills the through hole 11 y that continuously penetrates the insulating layer 21, the resin substrate 11, and the insulating layer 22.

  An insulating layer 21 is filled in a gap formed between the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x. However, all or part of the gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x may be filled with the insulating layer 22.

  For example, the upper surface of the through wiring 14, the upper surface of the insulating layer 21, and the upper surface of the embedded substrate 100 can be polished to be flush with each other. Further, the lower surface of the through wiring 14, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100 can be polished to be flush with each other, for example. As described above, by flattening the upper surface of the through wiring 14, the upper surface of the insulating layer 21, and the upper surface of the embedded substrate 100 by polishing, a fine pattern can be easily formed on the flattened surface. Further, by flattening the lower surface of the through wiring 14, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100 by polishing, a fine pattern can be easily formed on the flattened surface.

  The wiring pattern 41 is formed on a flat surface formed by the upper surface of the through wiring 14, the upper surface of the insulating layer 21, and the upper surface of the embedded substrate 100. The wiring pattern 42 is formed on a flat surface formed by the lower surface of the through wiring 14, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100. A part of the wiring pattern 42 is electrically connected to the wiring pattern 41 through the through wiring 14.

  The wiring pattern 41 formed on the upper surface of the embedded substrate 100 and the wiring pattern 42 formed on the lower surface of the embedded substrate 100 are the same as those in the first embodiment. In other words, the vertical transmission path can be formed on the embedded substrate 100 by forming the pad pattern with the wiring patterns 41 and 42 arranged at opposite positions on both surfaces of the embedded substrate 100. At this time, it is preferable that at least one of the pad patterns on the embedded substrate 100 be a coaxial pad pattern to make the vertical transmission line coaxial, in that crosstalk can be suppressed.

[Method for Manufacturing Wiring Board According to Third Embodiment]
Next, a method for manufacturing a wiring board according to the third embodiment will be described. FIG. 14 is a diagram illustrating a manufacturing process of the wiring board according to the third embodiment.

  First, in the step shown in FIG. 14A, a resin substrate 11 is prepared as a core substrate, and through holes 11x are formed in the resin substrate 11 by a machining method, a laser processing method, or the like. The resin substrate 11 may or may not have a reinforcing member. In the present embodiment, the core substrate consists only of the resin substrate 11, and no wiring pattern is formed.

  Next, the embedded substrate 100 is produced by the same method as in the first embodiment, and is placed in the through hole 11 x of the resin substrate 11. The embedded substrate 100 is disposed so that the upper and lower surfaces protrude from both surfaces of the core substrate 10. Then, a film-like insulating resin to be the insulating layers 21 and 22 is laminated on both surfaces of the resin substrate 11 so as to cover the upper and lower surfaces of the embedded substrate 100.

  Then, the insulating resin to be the insulating layers 21 and 22 is pressed toward the resin substrate 11 while being heated. As a result, the insulating resin flows into the periphery of the embedded substrate 100 in the through hole 11x and is then cured to form the insulating layers 21 and 22. At this time, the upper surface of the embedded substrate 100 is covered with the insulating layer 21, and the lower surface is covered with the insulating layer 22. Note that the interface between the insulating layer 21 and the insulating layer 22 around the embedded substrate 100 may be at any position.

  The insulating resin constituting the resin substrate 11, the insulating layer 21, and the insulating layer 22 may all be the same resin, or only two of them may be the same resin, or different resins. It may be.

  Next, in the step shown in FIG. 14B, both surfaces of the structure shown in FIG. 14A are polished by mechanical polishing, chemical mechanical polishing (CMP), or the like, and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. The lower surface of the embedded substrate 100 is exposed from the lower surface of the insulating layer 22. For example, the upper surface of the embedded substrate 100 and the upper surface of the insulating layer 21 can be flush with each other. Further, the lower surface of the embedded substrate 100 and the lower surface of the insulating layer 22 can be flush with each other, for example.

  Thereafter, a solid metal layer 41 a that continuously covers the upper surface of the embedded substrate 100 and the upper surface of the insulating layer 21 is formed. In addition, a solid metal layer 42 a that continuously covers the lower surface of the embedded substrate 100 and the lower surface of the insulating layer 22 is formed. The metal layers 41a and 42a can be formed by, for example, an electroless plating method or a sputtering method.

  As a material of the metal layers 41a and 42a, for example, titanium (Ti), titanium nitride (TiN), or the like can be used. The thickness of the metal layers 41a and 42a can be, for example, about 1 μm or less.

  The metal layers 41a and 42a may have a multilayer structure in which a second layer made of copper (Cu) or the like is laminated on a first layer made of titanium (Ti), titanium nitride (TiN), or the like. The thickness of the first layer can be, for example, about 1 μm or less. Further, the thickness of the second layer can be set to about several μm, for example. In this case, the first layer functions as a barrier layer that prevents mutual diffusion between the second layer and the linear conductor 120, and an adhesion layer that improves connection reliability between the second layer and the linear conductor 120. The second layer functions as a seed layer (feeding layer) when forming a wiring pattern by electrolytic plating.

  Note that the substrate structure shown in FIG. 14B is highly versatile and can be shared for various uses. Therefore, the substrate structure shown in FIG. 14B may be distributed to the market as one product.

  Next, in the step shown in FIG. 14C, a through hole 11y that continuously penetrates the insulating layer 21, the resin substrate 11, and the insulating layer 22 is formed. The through hole 14 is formed by filling the through hole 11y with a conductor such as copper (Cu) by a plating method or the like. Thereafter, wiring patterns 41 and 42 made of copper (Cu) or the like are formed on both surfaces of the resin substrate 11. The wiring pattern 41 and the wiring pattern 42 are electrically connected via the through wiring 14.

  The wiring patterns 41 and 42 can be formed by, for example, a semi-additive method. For example, a resist layer having an opening corresponding to the wiring pattern 41 is formed on the metal layer 41a. Then, an electrolytic plating layer made of copper (Cu) or the like is formed on the metal layer 41a exposed in the opening of the resist layer by an electrolytic plating method using the metal layer 41a as a power feeding layer. Similarly, a resist layer having an opening corresponding to the wiring pattern 42 is formed on the metal layer 42a. Then, an electrolytic plating layer made of copper (Cu) or the like is formed on the metal layer 42a exposed in the opening of the resist layer by an electrolytic plating method using the metal layer 42a as a power feeding layer.

  Next, after the resist layer on the upper surface side of the resin substrate 11 is removed, the metal layer 41a not covered with the electrolytic plating layer is removed by etching or the like, whereby the electrolytic plating layer is laminated on the metal layer 41a. A pattern 41 is formed. Similarly, after the resist layer on the lower surface side of the resin substrate 11 is removed, the metal layer 42a not covered with the electrolytic plating layer is removed by etching or the like, whereby the electrolytic plating layer is laminated on the metal layer 42a. A pattern 42 is formed. When the wiring patterns 41 and 42 are formed, it is preferable to adopt a coaxial pad pattern or a back surface feeding plating alignment mark formation process as in the first embodiment. In FIG. 14C, the metal layers 41a and 42a are not shown.

  Thereafter, similarly to the step shown in FIG. 3D, the insulating layer 51, the wiring layer 61, the insulating layer 71, and the wiring layer 81 are sequentially stacked on the upper side of the structure shown in FIG. Further, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked below the structure shown in FIG. The wiring board 2 shown in FIG. 13 is completed through the above steps.

<Fourth embodiment>
In the fourth embodiment, an example of a wiring board that can be manufactured without performing a polishing process is shown. Note that in the fourth embodiment, descriptions of the same components as those of the above-described embodiments may be omitted.

[Structure of Wiring Board According to Fourth Embodiment]
First, the structure of the wiring board according to the fourth embodiment will be described. FIG. 15 is a cross-sectional view illustrating a wiring board according to the fourth embodiment.

  Referring to FIG. 15, the wiring board 3 is such that the upper surface of the embedded substrate 100 and the upper surface of the wiring pattern 12 are substantially flush, and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. 1 (see FIG. 1).

  In the wiring substrate 3, the insulating layer 21 continuously covers the upper surface of the resin substrate 11 and the upper surface of the embedded substrate 100. A via hole 21y is provided in the insulating layer 21 formed on the upper surface of the embedded substrate 100, and upper end surfaces of the plurality of linear conductors 120 are exposed in the via hole 21y.

  The wiring layer 45 is formed on the upper side of the insulating layer 21. The wiring layer 45 includes a via wiring filled in the via hole 21 x, a via wiring filled in the via hole 21 y, and a wiring pattern formed on the upper surface of the insulating layer 21. The wiring layer 45 is electrically connected to the wiring pattern 12 via via wiring (first via wiring) filled in the via hole 21x. The wiring layer 45 is electrically connected to the upper end surfaces of the plurality of linear conductors 120 via via wiring (second via wiring) filled in the via hole 21y.

  The wiring layer 46 is formed on a flat surface formed by the lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100. The wiring layer 46 is configured to include a via wiring filled in the via hole 22 x, a wiring pattern formed on the lower surface of the insulating layer 22, and a pad pattern formed on the lower surface of the embedded substrate 100. The wiring layer 46 is electrically connected to the wiring pattern 13 via via wiring filled in the via hole 22x. Each pad constituting the pad pattern of the wiring layer 46 is directly electrically connected to the lower end surfaces of the plurality of linear conductors 120. The wiring layer 45 is a typical example of the first wiring layer according to the present invention, and the wiring layer 46 is a typical example of the second wiring layer according to the present invention.

  An end of the via wiring of the wiring layer 45 formed on the upper surface of the embedded substrate 100 on the upper surface side of the embedded substrate 100 becomes a pad pattern (first pad pattern). Further, the pad pattern (second pad pattern) of the wiring layer 46 formed on the lower surface of the embedded substrate 100 can be formed at a position facing the first pad pattern with the embedded substrate 100 interposed therebetween. Thereby, a vertical transmission line can be formed in the embedded substrate 100. At this time, it is preferable that the vertical transmission path is made coaxial by using the second pad pattern on the lower surface of the embedded substrate 100 as a coaxial pad pattern in that crosstalk can be suppressed.

  Alternatively, instead of changing the second pad pattern to a coaxial pad pattern, a photosensitive resin is used as the insulating layer 21 and a floating ring (annular) insulating layer is formed around the via wiring of the wiring layer 45 so that the coaxial pattern is formed. A structure may be realized. In that case, since a coaxial pattern can be formed on the upper surface of the embedded substrate 100 when forming the via wiring in the via hole, it is possible to have a crosstalk suppressing effect between the vertical transmission lines.

  Similar to the first embodiment, wiring with different specifications such as wiring suitable for the power supply system (thick wiring + thick insulating layer) is provided on the core substrate 10 and fine wiring is provided on the embedded substrate 100. They can be mixed in the same substrate.

[Method for Manufacturing Wiring Board According to Fourth Embodiment]
Next, a method for manufacturing a wiring board according to the fourth embodiment will be described. FIG. 16 is a diagram illustrating a manufacturing process of the wiring board according to the fourth embodiment.

  First, in the process shown in FIG. 16A, the core substrate 10 is manufactured by the same process as that in FIG. 2A, and the embedded substrate 100 is manufactured by the same process as in the first embodiment. And the process similar to the process shown to Fig.11 (a) is performed. However, unlike the process shown in FIG. 11A, the embedded substrate 100 is arranged so that the upper surface of the embedded substrate 100 and the upper surface of the wiring pattern 12 are substantially flush with each other when placed on the temporary fixing film 313. The thickness is adjusted. When a multilayer wiring layer including the wiring pattern 12 is formed on the upper surface of the resin substrate 11, the embedding is performed so that the upper surface of the embedded substrate 100 is substantially flush with the upper surface of the uppermost wiring pattern. The thickness of the substrate 100 is adjusted.

  Next, a film-like insulating resin that becomes the insulating layer 21 is laminated on the upper surface of the core substrate 10 so as to cover the upper surface of the embedded substrate 100. Then, the insulating layer 21 is formed by pressing and curing the temporary fixing film 313 while heating the insulating resin. The gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x is filled with the insulating layer 21, and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. Instead of laminating the film-like insulating resin that becomes the insulating layer 21, a liquid insulating resin that becomes the insulating layer 21 is applied by a spin coating method or the like, and the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x are formed. The gap to be formed may be filled.

  Next, in the step shown in FIG. 16B, the temporary fixing film 313 shown in FIG. 16A is peeled off, the lower surface of the insulating layer 21 filling the periphery of the embedded substrate 100, the lower surface of the insulating layer 22, and the embedding. The lower surface of the substrate 100 is exposed. For example, the lower surface of the insulating layer 21, the lower surface of the insulating layer 22, and the lower surface of the embedded substrate 100 can be flush with each other.

  Next, in the step shown in FIG. 16C, as in the step shown in FIG. 2D, the via hole 21x that penetrates the insulating layer 21 and exposes the upper surface of the wiring pattern 12 and the insulating layer 21 are insulated. A via hole 21 y that penetrates the layer 21 and exposes the upper end surfaces of the plurality of linear conductors 120 is formed. In addition, a via hole 22 x that penetrates the insulating layer 22 and exposes the lower surface of the wiring pattern 13 is formed in the insulating layer 22.

  Next, in the step shown in FIG. 16D, wiring layers 45 and 46 are formed on the insulating layers 21 and 22 by a semi-additive method or the like. The wiring layer 45 is formed on the upper surface of the insulating layer 21 and the via wiring filled in the via hole 21 x and connected to the wiring pattern 12, the via wiring filled in the via hole 21 y and connected to the plurality of linear conductors 120. It is configured including a wiring pattern. The wiring layer 46 includes a via wiring filled in the via hole 22x and connected to the wiring pattern 13, a wiring pattern formed on the lower surface of the insulating layer 22, and a pad pattern formed on the lower surface of the embedded substrate 100. Composed. The via wiring filling the via hole 21 y and the pad pattern of the wiring layer 46 are arranged at positions facing each other with the embedded substrate 100 interposed therebetween. Thereby, a vertical transmission path is formed in the embedded substrate 100. It is to be noted that, when the wiring layer 46 is formed, it is preferable to adopt a coaxial pad pattern as in the first embodiment.

  Thereafter, similarly to the step shown in FIG. 3D, the insulating layer 51, the wiring layer 61, the insulating layer 71, and the wiring layer 81 are sequentially stacked on one side of the structure shown in FIG. In addition, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked on the other side of the structure shown in FIG. The wiring substrate 3 shown in FIG. 15 is completed through the above steps.

  In place of the steps of FIGS. 16A and 16B, the insulating layer 21 is formed around the embedded substrate 100 in the same manner as in the steps of FIGS. 12A and 12B. The insulating layer 23 serving as a stress relaxation layer may be formed of an insulating resin having a low elastic modulus with respect to the resin.

  Thus, in the fourth embodiment, there is no polishing step. On the other hand, as described above, in the first embodiment, the number of times of polishing is two, and in the second embodiment, the number of times of polishing is one. Since the polishing process is expensive, the manufacturing process according to the fourth embodiment can reduce the manufacturing cost of the wiring board as compared with the manufacturing processes according to the first and second embodiments. It becomes.

<Fifth embodiment>
In the fifth embodiment, another example of a wiring board that can be manufactured without performing a polishing step will be described. Note that in the fifth embodiment, description of the same components as those of the above-described embodiments may be omitted.

[Structure of Wiring Board According to Fifth Embodiment]
First, the structure of the wiring board according to the fifth embodiment will be described. FIG. 17 is a cross-sectional view illustrating a wiring board according to the fifth embodiment.

  Referring to FIG. 17, the wiring board 4 is such that the upper surface of the embedded substrate 100 and the upper surface of the wiring pattern 12 are substantially flush, and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. Mainly different from (see FIG. 1). Also, the difference between the lower surface of the embedded substrate 100 and the lower surface of the wiring pattern 13 is substantially the same, and the lower surface of the embedded substrate 100 is covered with the insulating layer 22 mainly from the wiring substrate 1 (see FIG. 1). To do.

  In the wiring substrate 4, the insulating layer 21 continuously covers the upper surface of the resin substrate 11 and the upper surface of the embedded substrate 100. A via hole 21y is provided in the insulating layer 21 formed on the upper surface of the embedded substrate 100, and upper end surfaces of the plurality of linear conductors 120 are exposed in the via hole 21y. Similarly, the insulating layer 22 continuously covers the lower surface of the resin substrate 11 and the lower surface of the embedded substrate 100. A via hole 22y is provided in the insulating layer 22 formed on the lower surface of the embedded substrate 100, and lower end surfaces of the plurality of linear conductors 120 are exposed in the via hole 22y.

  The wiring layer 45 is the same as that in the fourth embodiment. The wiring layer 46 is formed below the insulating layer 22. The wiring layer 46 includes a via wiring filled in the via hole 22x, a via wiring filled in the via hole 22y, and a wiring pattern formed on the lower surface of the insulating layer 22. The wiring layer 46 is electrically connected to the wiring pattern 13 via via wiring (third via wiring) filled in the via hole 22x. The wiring layer 46 is electrically connected to the lower end surfaces of the plurality of linear conductors 120 via via wiring (fourth via wiring) filled in the via hole 22y.

  An end of the via wiring of the wiring layer 45 formed on the upper surface of the embedded substrate 100 on the upper surface side of the embedded substrate 100 becomes a pad pattern (first pad pattern). In addition, an end of the via wiring of the wiring layer 46 formed on the lower surface of the embedded substrate 100 on the lower surface side of the embedded substrate 100 becomes a pad pattern (second pad pattern). By arranging the first pad pattern and the second pad pattern at positions facing each other through the embedded substrate 100, a vertical transmission path can be formed in the embedded substrate 100.

  A coaxial structure can be realized by using a photosensitive resin as the insulating layers 21 and 22 and forming an insulating layer in a floating ring shape (annular) around the via wirings of the wiring layers 45 and 46. In that case, when via wiring is formed in the via hole, a coaxial pattern can be formed on both surfaces of the embedded substrate 100, so that the crosstalk suppression effect between the vertical transmission paths can be provided.

  Similar to the first embodiment, wiring with different specifications such as wiring suitable for the power supply system (thick wiring + thick insulating layer) is provided on the core substrate 10 and fine wiring is provided on the embedded substrate 100. They can be mixed in the same substrate.

[Manufacturing Method of Wiring Board According to Fifth Embodiment]
Next, a method for manufacturing a wiring board according to the fifth embodiment will be described. FIG. 18 is a diagram illustrating a manufacturing process of the wiring board according to the fifth embodiment.

  First, in the process shown in FIG. 18A, the core substrate 10 is manufactured by the same process as that in FIG. 2A, and the embedded substrate 100 is manufactured by the same process as in the first embodiment. Then, the temporary fixing film 313 is laminated on the lower surface side of the core substrate 10, and the embedded substrate 100 is disposed and temporarily fixed on the upper surface of the temporary fixing film 313 exposed in the through holes 11 x of the core substrate 10. At this time, the thickness of the embedded substrate 100 is adjusted so that the upper surface of the embedded substrate 100 and the upper surface of the wiring pattern 12 are substantially flush with each other in a state of being disposed on the upper surface of the temporary fixing film 313.

  When a multilayer wiring layer including the wiring pattern 12 is formed on the upper surface of the resin substrate 11, the embedding is performed so that the upper surface of the embedded substrate 100 is substantially flush with the upper surface of the uppermost wiring pattern. The thickness of the substrate 100 is adjusted.

  Next, a film-like insulating resin that becomes the insulating layer 21 is laminated on the upper surface of the core substrate 10 so as to cover the upper surface of the embedded substrate 100. Then, the insulating layer 21 is formed by pressing and curing the temporary fixing film 313 while heating the insulating resin. The gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x is filled with the insulating layer 21, and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. Instead of laminating the film-like insulating resin that becomes the insulating layer 21, a liquid insulating resin that becomes the insulating layer 21 is applied by a spin coating method or the like, and the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x are formed. The gap to be formed may be filled.

  In the step shown in FIG. 18A, a photosensitive insulating resin film having adhesiveness or a non-photosensitive insulating resin film to be the insulating layer 22 may be used instead of the temporary fixing film 313. In this case, the temporary fixing of the embedded substrate 100 and the formation of the insulating layer 22 can be performed simultaneously, which is preferable. In this case, the step shown in FIG.

  Next, in the step shown in FIG. 18B, the temporary fixing film 313 shown in FIG. 18A is peeled, and the lower surface of the core substrate 10 and the lower surface of the embedded substrate 100 are exposed. For example, the lower surface of the core substrate 10 (the lower surface of the wiring pattern 13) and the lower surface of the embedded substrate 100 can be flush with each other. Then, a film-like insulating resin that becomes the insulating layer 22 is laminated on the lower surface of the core substrate 10 so as to cover the lower surface of the embedded substrate 100. Then, while heating the insulating resin, it is pressed toward the core substrate 10 and cured to form the insulating layer 22. The lower surface of the embedded substrate 100 is covered with the insulating layer 22. Note that a liquid insulating resin to be the insulating layer 22 may be applied by a spin coating method or the like instead of the laminate of the film-like insulating resin to be the insulating layer 22.

  Next, in the step shown in FIG. 18C, as in the step shown in FIG. 2D, the via hole 21x that penetrates the insulating layer 21 and exposes the upper surface of the wiring pattern 12 and the insulating layer 21 are formed. A via hole 21 y that penetrates the layer 21 and exposes the upper end surfaces of the plurality of linear conductors 120 is formed. In addition, a via hole 22x that penetrates the insulating layer 22 and exposes the lower surface of the wiring pattern 13 and a via hole 22y that penetrates the insulating layer 22 and exposes the lower end surfaces of the plurality of linear conductors 120 are formed in the insulating layer 22. The via hole 21y and the via hole 22y are arranged at positions facing each other with the embedded substrate 100 interposed therebetween. Thereby, a vertical transmission path can be formed in the embedded substrate 100.

  Next, in the step shown in FIG. 18D, wiring layers 45 and 46 are formed on the insulating layers 21 and 22 by a semi-additive method or the like. The wiring layer 45 is formed on the upper surface of the insulating layer 21 and the via wiring filled in the via hole 21 x and connected to the wiring pattern 12, the via wiring filled in the via hole 21 y and connected to the plurality of linear conductors 120. It is configured including a wiring pattern. The wiring layer 46 is formed on the lower surface of the insulating layer 22 and the via wiring filled in the via hole 22 x and connected to the wiring pattern 13, the via wiring filled in the via hole 22 y and connected to the plurality of linear conductors 120. The wiring pattern is configured.

  3D, an insulating layer 51, a wiring layer 61, an insulating layer 71, and a wiring layer 81 are sequentially stacked on one side of the structure shown in FIG. Further, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked on the other side of the structure shown in FIG. The wiring substrate 4 shown in FIG. 17 is completed through the above steps.

  In place of the steps of FIGS. 18A and 18B, the insulating layer 21 is formed around the embedded substrate 100 in the same manner as in the steps of FIGS. 12A and 12B. The insulating layer 23 serving as a stress relaxation layer may be formed of an insulating resin having a low elastic modulus with respect to the resin.

  Thus, in the fifth embodiment, there is no polishing step. On the other hand, as described above, in the first embodiment, the number of times of polishing is two, and in the second embodiment, the number of times of polishing is one. Since the polishing process is expensive, the manufacturing process according to the fifth embodiment can reduce the manufacturing cost of the wiring board compared to the manufacturing processes according to the first and second embodiments. It becomes.

<Sixth embodiment>
In the sixth embodiment, still another example of the wiring board that can be manufactured without performing the polishing step will be described. Note that in the sixth embodiment, descriptions of the same components as in the already described embodiments may be omitted.

[Structure of Wiring Board According to Sixth Embodiment]
First, the structure of the wiring board according to the sixth embodiment will be described. FIG. 19 is a cross-sectional view illustrating a wiring board according to the sixth embodiment.

  Referring to FIG. 19, the wiring board 5 is that the wiring pattern 41 is formed only on the upper surface of the embedded substrate 100 and is exposed in the opening 21 z formed in the insulating layer 21. 1)). Further, the wiring pattern 42 is mainly formed on the lower surface of the embedded substrate 100 and is exposed in the opening 22z formed in the insulating layer 22, which is mainly different from the wiring substrate 1 (see FIG. 1).

  In the wiring substrate 5, the insulating layer 21 continuously covers the outer periphery of the upper surface of the resin substrate 11 and the upper surface of the embedded substrate 100. The insulating layer 21 is provided with an opening 21z that penetrates the insulating layer 21 and exposes a region excluding the outer peripheral portion of the upper surface of the embedded substrate 100. The opening 21z is formed only on the upper surface of the embedded substrate 100. The wiring pattern 41 (first pad pattern) is exposed.

  An insulating layer 25 that covers the wiring pattern 41 and extends on the insulating layer 21 is formed on the insulating layer 21. That is, the insulating layer formed on the upper surface of the core substrate 10 has a two-layer structure in which the insulating layer 25 is stacked on the insulating layer 21. The two-layer structure of the insulating layer 21 (first layer) and the insulating layer 25 (second layer) is a typical example of the first insulating layer according to the present invention. The insulating layer 25 is provided with a via hole 25x that penetrates the insulating layer 25 and exposes the upper surface of the wiring pattern 12, and a via hole 25y that penetrates the insulating layer 25 and exposes the upper surface of the wiring pattern 41. The via hole 25x is provided in the via hole 21x.

  The insulating layer 22 continuously covers the outer periphery of the lower surface of the resin substrate 11 and the lower surface of the embedded substrate 100. The insulating layer 22 is provided with an opening 22z that penetrates the insulating layer 22 and exposes a region excluding the outer peripheral portion of the lower surface of the embedded substrate 100, and is formed only on the lower surface of the embedded substrate 100 in the opening 22z. The wiring pattern 42 (second pad pattern) is exposed.

  An insulating layer 26 that covers the wiring pattern 42 and extends on the insulating layer 22 is formed below the insulating layer 22. That is, the insulating layer formed on the lower surface of the core substrate 10 has a two-layer structure in which the insulating layer 26 is laminated on the insulating layer 22. The two-layer structure of the insulating layer 22 (third layer) and the insulating layer 26 (fourth layer) is a typical example of the second insulating layer according to the present invention. The insulating layer 26 is provided with a via hole 26 x that penetrates the insulating layer 26 and exposes the lower surface of the wiring pattern 13, and a via hole 26 y that penetrates the insulating layer 26 and exposes the lower surface of the wiring pattern 42. The via hole 26x is provided in the via hole 22x.

  The wiring layer 45 is formed on the upper side of the insulating layer 25. The wiring layer 45 includes a via wiring filled in the via hole 25x, a via wiring filled in the via hole 25y, and a wiring pattern (fifth wiring pattern) formed on the upper surface of the insulating layer 25. . The wiring pattern of the wiring layer 45 is electrically connected to the wiring pattern 12 via via wiring filled in the via hole 25x (that is, via the insulating layers 21 and 25). The wiring layer 45 is electrically connected to the wiring pattern 41 via via wiring filled in the via hole 25y (that is, via the insulating layer 25).

  The wiring layer 46 is formed below the insulating layer 26. The wiring layer 46 includes a via wiring filled in the via hole 26x, a via wiring filled in the via hole 26y, and a wiring pattern (sixth wiring pattern) formed on the lower surface of the insulating layer 26. . The wiring pattern of the wiring layer 46 is electrically connected to the wiring pattern 13 via via wiring filled in the via hole 26x (that is, via the insulating layers 22 and 26). The wiring layer 46 is electrically connected to the wiring pattern 42 via via wiring filled in the via hole 26y (that is, via the insulating layer 26).

  Similar to the first embodiment, the wiring pattern 41 formed on the upper surface of the embedded substrate 100 is directly connected to the upper ends of the plurality of linear conductors 120. In addition, the wiring pattern 42 formed on the lower surface of the embedded substrate 100 is directly connected to the lower end surfaces of the plurality of linear conductors 120. A vertical transmission path can be formed on the embedded substrate 100 by forming a pad pattern with the wiring patterns 41 and 42 arranged at opposite positions on both surfaces of the embedded substrate 100. At this time, it is preferable that at least one of the pad patterns on the embedded substrate 100 be a coaxial pad pattern to make the vertical transmission line coaxial, in that crosstalk can be suppressed.

  Similar to the first embodiment, wiring with different specifications such as wiring suitable for the power supply system (thick wiring + thick insulating layer) is provided on the core substrate 10 and fine wiring is provided on the embedded substrate 100. They can be mixed in the same substrate.

  In the wiring substrate 5, the upper surface of the embedded substrate 100 and the upper surface of the wiring pattern 12 may be substantially flush with each other. Further, the lower surface of the embedded substrate 100 and the lower surface of the wiring pattern 13 may be substantially flush.

[Manufacturing Method of Wiring Board According to Sixth Embodiment]
Next, a method for manufacturing a wiring board according to the sixth embodiment will be described. 20 and 21 are diagrams illustrating the manufacturing process of the wiring board according to the sixth embodiment.

  First, in the step shown in FIG. 20A, the insulating layer 21 is formed on the upper surface of the core substrate 10 and the insulating layer 22 is formed on the lower surface by the same steps as in FIGS. 18A and 18B. . The gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x is filled with the insulating layer 21, and the upper surface of the embedded substrate 100 is covered with the insulating layer 21. Further, the lower surface of the embedded substrate 100 is covered with the insulating layer 22.

  Next, in the step shown in FIG. 20B, as in the step shown in FIG. 2D, the via hole 21x that penetrates the insulating layer 21 and exposes the upper surface of the wiring pattern 12 and the insulating layer 21 are insulated. An opening 21z that penetrates the layer 21 and exposes a region excluding the outer peripheral portion of the upper surface of the embedded substrate 100 is formed. The upper end surfaces of the plurality of linear conductors 120 are exposed in the opening 21z. Also, a via hole 22x that penetrates the insulating layer 22 and exposes the lower surface of the wiring pattern 13 and an opening 22z that penetrates the insulating layer 22 and exposes a region other than the outer peripheral portion of the lower surface of the embedded substrate 100 are formed in the insulating layer 22. To do. The lower end surfaces of the plurality of linear conductors 120 are exposed in the opening 22z. The opening 21z that exposes the entire area of the upper surface of the embedded substrate 100 and the opening 22z that exposes the entire area of the lower surface of the embedded substrate 100 may be formed.

  Next, in the step shown in FIG. 20C, the wiring pattern 41 is formed on the upper surface of the embedded substrate 100 exposed in the opening 21z. Further, the wiring pattern 42 is formed on the lower surface of the embedded substrate 100 exposed in the opening 22z. The wiring patterns 41 and 42 can be formed using, for example, a semi-additive method. It is to be noted that when the wiring patterns 41 and 42 are formed, it is the same as in the first embodiment that a coaxial pad pattern or a back surface feeding plating alignment mark formation process is preferably employed.

  Next, in the process shown in FIG. 21A, a film-like insulating resin is laminated so as to cover the inside of the via hole 21x, the opening 21z, and the upper surface of the insulating layer 21, and is heated and cured to be insulated. Layer 25 is formed. Further, an insulating layer 26 is formed by laminating a film-like insulating resin so as to cover the inside of the via hole 22x, the opening 22z, and the lower surface of the insulating layer 22, and curing by heating. However, regarding the formation of the insulating layers 25 and 26, a liquid insulating resin may be spin-coated instead of the film-like insulating resin laminate.

  Next, in the step shown in FIG. 21B, as in the step shown in FIG. 2D, via holes 25x that penetrate through the insulating layer 25 and expose the upper surface of the wiring pattern 12 are formed in the insulating layer 25, and the insulating layer 25 is insulated. A via hole 25y that penetrates the layer 25 and exposes the upper surface of the wiring pattern 41 is formed. In addition, a via hole 26x that penetrates the insulating layer 26 and exposes the lower surface of the wiring pattern 13 and a via hole 26y that penetrates the insulating layer 26 and exposes the lower surface of the wiring pattern 42 are formed in the insulating layer 26.

  In FIG. 21B, as an example, the via hole 25x is formed in the via hole 21x, and the via hole 26x is formed in the via hole 22x. As another example, the via hole 25x may be formed to be slightly larger than the via hole 21x so as to include the via hole 21x, and the via hole 26x may be formed to be slightly larger than the via hole 22x so as to include the via hole 22x. When the via holes 25x and 26x are formed by a laser, the insulating layers 21 and 25 are formed in the step shown in FIG. 21B without forming the via holes 21x and 22x in the step shown in FIG. A via hole 25x that penetrates and a via hole 26x that penetrates the insulating layers 22 and 26 may be formed.

  Next, in the step shown in FIG. 21C, wiring layers 45 and 46 are formed on the insulating layers 25 and 26 by a semi-additive method or the like. The wiring layer 45 is formed on the upper surface of the insulating layer 25 and the via wiring filled in the via hole 25x and connected to the wiring pattern 12, the via wiring filled in the via hole 25y and connected to the wiring pattern 41 (pad pattern). Including a wiring pattern. The wiring layer 46 is filled in the via hole 26x and connected to the wiring pattern 13, the via wiring filled in the via hole 26y and connected to the wiring pattern 42 (pad pattern), and the lower surface of the insulating layer 26. It is configured including the formed wiring pattern.

  Thereafter, similarly to the step shown in FIG. 3D, the insulating layer 51, the wiring layer 61, the insulating layer 71, and the wiring layer 81 are sequentially stacked on one side of the structure shown in FIG. In addition, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked on the other side of the structure shown in FIG. Through the above steps, the wiring board 5 shown in FIG. 19 is completed.

  In place of the process of FIG. 20A, low elasticity with respect to the insulating resin constituting the insulating layer 21 around the embedded substrate 100, as in the processes of FIG. 12A and FIG. The insulating layer 23 serving as a stress relaxation layer may be formed of an insulating resin having a ratio.

  Thus, in the sixth embodiment, there is no polishing step. On the other hand, as described above, in the first embodiment, the number of times of polishing is two, and in the second embodiment, the number of times of polishing is one. Since the polishing process is expensive, the manufacturing process according to the sixth embodiment can reduce the manufacturing cost of the wiring board as compared with the manufacturing processes according to the first and second embodiments. It becomes.

  Similarly to the first embodiment, when forming the wiring patterns 41 and 42, it is preferable in that a coaxial pad pattern or a back surface feeding plating alignment mark forming process can be employed.

  In order to expose the upper and lower surfaces of the embedded substrate 100, relatively large openings 21z and 22z may be formed in the insulating layers 21 and 22, and it is necessary to form fine via holes in the insulating layers 21 and 22. Absent. Therefore, as the insulating layers 21 and 22, it is possible to use a resin that places emphasis on embedding without placing importance on resolution and via processability. In addition, since the insulating layers 21 and 22 can be made thicker, filling failure or the like at the time of embedding can be suppressed.

  Further, even if the insulating layer 21 (insulating layer 22) is uneven according to the wiring pattern or the like provided on the core substrate 10 and the embedded substrate 100, the insulating layer 25 (insulating layer 26) formed thereon has the unevenness. Can be relaxed and the flatness can be improved. Thereby, the formability at the time of forming a wiring pattern on the insulating layer 25 (insulating layer 26) can be improved.

  Alternatively, the insulating layer 21 (insulating layer 22) may be formed of a photosensitive resin, and the insulating layer 25 (insulating layer 26) may be formed of a thermosetting resin (non-photosensitive resin). In this case, even if a photosensitive resin having a high thermal expansion coefficient is used, by further covering with a thermosetting resin having a low thermal expansion coefficient, the warpage of the core substrate 10 can be adjusted while suppressing the generation of stress. Note that it is difficult to adjust the thermal expansion coefficient of the photosensitive resin. On the other hand, the thermal expansion coefficient of a thermosetting resin can be adjusted with the kind and quantity of the filler contained in a thermosetting resin, for example (a thermal expansion coefficient can be restrained low).

  Further, by using a photosensitive resin as the insulating layer 21 (insulating layer 22), the opening 21z (opening 22z) that exposes a portion including the upper surface of the embedded substrate 100 can be formed by a photolithography process. This is preferable in that the possibility of damaging the embedded substrate 100 having relatively low strength can be reduced unlike the laser opening method.

<Seventh embodiment>
In the seventh embodiment, an example of a suitable wiring pattern of the core substrate is shown. Note that in the seventh embodiment, description of the same components as those of the above-described embodiment may be omitted.

[Structure of Core Substrate According to Seventh Embodiment]
First, the structure of the core substrate according to the seventh embodiment will be described. FIG. 22 is a diagram (part 1) illustrating a core substrate according to a seventh embodiment, in which FIG. 22 (a) is a plan view, and FIG. 22 (b) is an AA line in FIG. 22 (a). FIG.

  Referring to FIG. 22, in the core substrate 10 </ b> A, a plurality of wiring patterns 12 having a rectangular planar shape are periodically arranged on the upper surface of the resin substrate 11. A plurality of wiring patterns 13 having a rectangular planar shape are periodically arranged on the lower surface of the resin substrate 11. The position of each wiring pattern 12 and the position of each wiring pattern 13 substantially overlap in plan view. The planar shape of the wiring patterns 12 and 13 may be a polygon other than a rectangle, a circle, or the like.

  The wiring pattern 12 and the wiring pattern 13 that are disposed at substantially overlapping positions in plan view are electrically connected via a through wiring 14 that fills the through hole 11y. Each through hole 11y is formed at substantially equal pitch. The diameter of the through holes 11y can be, for example, 100 μm or more, and the pitch of the through holes 11y can be, for example, 300 μm or more.

  In addition, a periodic pattern 18 divided by a length equal to or less than the pitch of the through holes 11 y is disposed on the upper surface of the resin substrate 11. Further, a periodic pattern 19 divided by a length equal to or less than the pitch of the through holes 11y is arranged on the lower surface of the resin substrate 11. The position of each pattern 18 and the position of each pattern 19 substantially overlap in plan view. The patterns 18 and 19 are floating patterns that are electrically floating without being connected to any wiring pattern including the wiring patterns 12 and 13. The floating pattern is an expansion pattern, and can have the same function (power supply line, ground line, signal line, etc.) by connecting with a pattern in which a through hole exists. The planar shape of the patterns 18 and 19 can be, for example, a cross shape.

  FIG. 23 shows another example. FIG. 23 is a diagram (part 2) illustrating the core substrate according to the seventh embodiment, in which FIG. 23 (a) is a plan view, and FIG. 23 (b) is a BB line in FIG. 23 (a). FIG.

  Referring to FIG. 23, in the core substrate 10B, a plurality of wiring patterns 12 having a rectangular planar shape are periodically (checkered) arranged on the upper surface of the resin substrate 11. In addition, a plurality of wiring patterns 13 having a rectangular planar shape are periodically (checkered) arranged on the lower surface of the resin substrate 11. The position of each wiring pattern 12 and the position of each wiring pattern 13 substantially overlap in plan view. The planar shape of the wiring patterns 12 and 13 may be a polygon other than a rectangle, a circle, or the like.

  The wiring pattern 12 and the wiring pattern 13 that are disposed at substantially overlapping positions in plan view are electrically connected via a through wiring 14 that fills the through hole 11y. Each through hole 11y is formed at substantially equal pitch. The diameter of the through holes 11y can be, for example, 100 μm or more, and the pitch of the through holes 11y can be, for example, 300 μm or more.

  Further, on the upper surface of the resin substrate 11, a rectangular pattern 18 (substantially the same shape as the wiring pattern 12) partitioned by a length equal to or less than the pitch of the through holes 11 y is disposed between the adjacent wiring patterns 12. . On the lower surface of the resin substrate 11, a rectangular pattern 19 (substantially the same shape as the wiring pattern 13) divided by a length equal to or less than the pitch of the through holes 11 y is disposed between the adjacent wiring patterns 13. . The position of each pattern 18 and the position of each pattern 19 substantially overlap in plan view. The patterns 18 and 19 are floating patterns that are electrically floating without being connected to any wiring pattern including the wiring patterns 12 and 13.

  FIG. 24 shows an example in which the core substrate 10A shown in FIG. 22 is applied to the first embodiment. First, in the process shown in FIG. 24A, the core substrate 10A is manufactured by the same process as that shown in FIG. 2A, and the embedded substrate 100 is manufactured by the same process as that shown in FIG. Then, as in the step shown in FIG. 2C, the insulating resin to be the insulating layers 21 and 22 is pressed toward the core substrate 10A side while being heated. As a result, the insulating resin flows into the periphery of the embedded substrate 100 in the through hole 11x and is then cured to form the insulating layers 21 and 22. At this time, the upper surface of the embedded substrate 100 is covered with the insulating layer 21, and the lower surface is covered with the insulating layer 22. Note that the interface between the insulating layer 21 and the insulating layer 22 around the embedded substrate 100 may be at any position.

  Next, in the step shown in FIG. 24B, the wiring pattern 41 is formed on the upper surface of the insulating layer 21 and the upper surface of the embedded substrate 100 in the same manner as the steps shown in FIGS. 2D to 3C. . Further, the wiring pattern 42 is formed on the lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100.

  Next, in the step shown in FIG. 24C, in the same manner as the step shown in FIG. 3D, the insulating layer 51, the wiring layer 61, and the insulating layer are formed on one side of the structure shown in FIG. 71 and the wiring layer 81 are sequentially laminated. In addition, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked on the other side of the structure shown in FIG. Through the above steps, the wiring substrate 1 shown in FIG. 1 is completed.

  Thus, the versatility of a core board | substrate can be improved by making the through hole and wiring pattern which are formed in a core board | substrate into the unified regular shape and arrangement | positioning. That is, according to the design of the wiring board, it is possible to select and connect the through hole at the optimum position and the wiring pattern connected thereto among the through holes formed at equal intervals on the entire surface of the core substrate. The wiring patterns of the core substrate are all independent, but a wide power supply line and ground line can be formed by electrical connection through a wiring layer formed thereon.

  The embedded substrate 100 is a substrate having a high degree of design freedom capable of forming a narrow pitch vertical transmission line at an arbitrary position. However, since it is not easy to change the wiring pattern of the core substrate around the embedded substrate 100, the characteristics of the embedded substrate 100 cannot be fully exploited. That is, the structure that can be formed is limited by the wiring pattern of the core substrate on the outer periphery of the embedded substrate 100.

  However, by adopting the core substrate structure as shown in FIG. 22 or FIG. 23, the core substrate portion can also be handled like the embedded substrate 100 having a very large vertical transmission path pitch. The parts that require fine vertical transmission lines and precise layout adjustment are embedded boards 100, and the parts that do not have problems with large vertical transmission lines and rough layout adjustments are core boards 10A or 10B. Design freedom can be obtained. That is, the structure of the core substrate as shown in FIG. 22 or FIG. 23 can be used as the core substrate of the wiring substrate having various uses and designs, so that the core substrate can be shared.

  Further, in the core substrate structure as shown in FIG. 22 or FIG. 23, the through holes and the wiring patterns are uniformly distributed with good symmetry in the upper and lower surfaces and in the surface, so that the warpage can be suppressed. Further, since the through hole 11y (through wiring 14) is formed on the entire surface, they also act as a heat conduction path, and the heat dissipation of the core substrate can be enhanced.

  In general, the through-holes and the thick wiring pattern portions on the upper and lower surfaces also have a large extension during heating. Therefore, when the pattern shape and distribution change for each product, the substrate shrinkage also changes greatly. However, in the case of the core substrate structure as shown in FIG. 22 or FIG. 23, the shape and distribution of the through holes and the wiring patterns are all the same, so that the change in the shrinkage can be reduced even if the product changes. Therefore, it can be suitably used as a general-purpose core substrate when combined with the embedded substrate 100.

  In the case of the core substrate structure as shown in FIG. 22 or FIG. 23, the entire surface of the core substrate has the same periodic pattern. Therefore, no matter where the embedded substrate 100 is embedded, the pattern shape and arrangement around the embedded substrate 100 are always constant, and the embedded position is not restricted.

<Eighth embodiment>
In the eighth embodiment, an example in which the core substrate is a flexible substrate will be described. Note that in the eighth embodiment, description of the same components as those of the above-described embodiments may be omitted.

[Structure of Wiring Board According to Eighth Embodiment]
First, the structure of the wiring board according to the eighth embodiment will be described. FIG. 25 is a cross-sectional view illustrating a wiring board according to the eighth embodiment.

  Referring to FIG. 25, the wiring substrate 6 uses a flexible resin such as a polyimide resin as a material of the resin substrate 11, and a rigid frame member 90 is provided around the embedded substrate 100. This is mainly different from the wiring board 1 (see FIG. 1). As the frame member 90, for example, a resin (an epoxy resin or the like) having higher rigidity than the resin constituting the resin substrate 11 can be used. As the frame member 90, a frame-like wiring board provided with through electrodes may be used.

[Method of Manufacturing Wiring Board According to Eighth Embodiment]
Next, a method for manufacturing a wiring board according to the eighth embodiment will be described. FIG. 26 is a diagram illustrating a manufacturing process of the wiring board according to the eighth embodiment.

  First, in the step shown in FIG. 26A, the flexible core substrate 10 is manufactured by the same process as in FIG. 2A using a flexible resin such as a polyimide resin as the resin substrate 11. In addition, the embedded substrate 100 is manufactured by the same process as in the first embodiment. Then, the embedded substrate 100 and a frame member 90 surrounding the periphery thereof are disposed in the through hole 11x of the core substrate 10. Thereafter, a film-like insulating resin (flexible resin such as polyimide resin) to be the insulating layers 21 and 22 is laminated on both surfaces of the core substrate 10 so as to cover the upper and lower surfaces of the embedded substrate 100.

  Then, the insulating resin to be the insulating layers 21 and 22 is pressed toward the core substrate 10 while being heated. Thereby, the insulating resin flows into the periphery of the embedded substrate 100 and the periphery of the frame member 90 in the through hole 11x, and is then cured to form the insulating layers 21 and 22. At this time, the upper surface of the embedded substrate 100 is covered with the insulating layer 21, and the lower surface is covered with the insulating layer 22. Note that the interface between the insulating layer 21 and the insulating layer 22 around the embedded substrate 100 may be at any position.

  Next, in the step shown in FIG. 26B, the same steps as in FIGS. 2D to 3B are executed. As a result, the upper surface of the embedded substrate 100 and the upper surface of the frame member 90 are exposed from the upper surface of the insulating layer 21, and the lower surface of the embedded substrate 100 and the lower surface of the frame member 90 are exposed from the lower surface of the insulating layer 22. For example, the upper surface of the embedded substrate 100, the upper surface of the frame member 90, the upper surface of the insulating layer 21, and the upper surface of the via wiring 31 can be flush with each other. Further, the lower surface of the embedded substrate 100, the lower surface of the frame member 90, the lower surface of the insulating layer 22, and the lower surface of the via wiring 32 can be flush with each other, for example.

  Thereafter, the wiring substrate 6 shown in FIG. 25 is completed by a process similar to the process shown in FIGS. 3C and 3D.

  As described above, in the eighth embodiment, since a flexible resin such as a polyimide resin is used as the material of the resin substrate 11, a flexible wiring substrate 6 suitable for a wearable terminal or the like can be realized. Further, since the wiring board 6 includes the embedded substrate 100 including the high-density linear conductors 120, it is possible to provide a high-density connection comparable to a silicon interposer.

  Furthermore, by disposing the highly rigid frame member 90 around the embedded substrate 100, when the wiring substrate 6 is bent, the stress applied to the embedded substrate 100 is relaxed, and the possibility that the embedded substrate 100 is damaged can be reduced.

  If the thickness of the embedded substrate 100 is thin enough to bend flexibly, or if the size of the embedded substrate 100 is smaller than the curvature of curvature assumed when the wiring substrate 6 is used, the frame member 90 is used. It is also possible to exclude.

<Modification 1>
Modification 1 shows an example of a wiring board in which the lower surface of the embedded substrate and the lower surface of the wiring pattern of the core substrate are not on the same plane, and the lower surface of the embedded substrate is covered with an insulating layer. In the first modification, the description of the same components as those of the already described embodiments may be omitted.

  FIG. 27 is a cross-sectional view illustrating a wiring board according to the first modification. Referring to FIG. 27, in the wiring substrate 7, the lower surface of the embedded substrate 100 and the upper surface of the wiring pattern of the wiring layer 46 are not on the same surface, and the lower surface of the embedded substrate 100 is covered with the insulating layer 22. This is mainly different from the wiring board 1 (see FIG. 1).

  Similar to the first embodiment, wiring with different specifications such as wiring suitable for the power supply system (thick wiring + thick insulating layer) is provided on the core substrate 10 and fine wiring is provided on the embedded substrate 100. They can be mixed in the same substrate.

<Modification 2>
Modification 2 shows an example of a wiring board in which the wiring pattern of the embedded board and the wiring pattern of the core board are directly connected. In the second modification, the description of the same components as those of the already described embodiments may be omitted.

[Structure of Wiring Board According to Modification 2]
First, the structure of the wiring board according to Modification 2 will be described. FIG. 28 is a cross-sectional view illustrating a wiring board according to the second modification.

  Referring to FIG. 28, in the wiring substrate 8, the upper surface of the wiring pattern 42 formed on the lower surface of the embedded substrate 100 and the lower surface of the wiring pattern 13 formed on the lower surface of the resin substrate 11 are connected via via wiring or the like. It is mainly different from the wiring board 1 (see FIG. 1) in that it is directly connected without being connected. In addition, the insulating layer 22 is not provided, and a step is generated between the wiring pattern 13 formed on the lower surface of the resin substrate 11 and the wiring pattern 42 formed on the lower surface of the embedded substrate 100.

  Similar to the first embodiment, wiring with different specifications such as wiring suitable for the power supply system (thick wiring + thick insulating layer) is provided on the core substrate 10 and fine wiring is provided on the embedded substrate 100. They can be mixed in the same substrate.

[Manufacturing Method of Wiring Board According to Modification 2]
Next, a method for manufacturing a wiring board according to Modification 2 will be described. FIG. 29 is a diagram illustrating a manufacturing process of the wiring board according to the second modification.

  First, in the process shown in FIG. 29A, after performing the same process as in FIG. 18A, a via hole 21x that penetrates the insulating layer 21 and exposes the upper surface of the wiring pattern 12 is formed in the insulating layer 21. Then, in the same manner as in the step shown in FIG. 3A, the via wiring 31 is formed by filling the via hole 21x with copper (Cu) or the like by plating or the like. The via wiring 31 is electrically connected to the wiring pattern 12.

  Next, in the step shown in FIG. 29B, similarly to the step shown in FIG. 3B, the upper surface of the structure shown in FIG. 29A is polished, and the upper surface of the embedded substrate 100 is insulated from the insulating layer 21. It is exposed from the top surface of. For example, the upper surface of the embedded substrate 100, the upper surface of the insulating layer 21, and the upper surface of the via wiring 31 can be flush with each other.

  Next, in the step shown in FIG. 29C, after the temporary fixing film 313 is removed, the wiring patterns 41 and 42 are formed. The wiring patterns 41 and 42 can be formed by, for example, a semi-additive method. The wiring pattern 42 is directly formed on the lower surface of the wiring pattern 13 and the lower surface of the embedded substrate 100 without via via wiring. It is to be noted that when the wiring patterns 41 and 42 are formed, it is the same as in the first embodiment that a coaxial pad pattern or a back surface feeding plating alignment mark formation process is preferably employed.

  Thereafter, in the same manner as the step shown in FIG. 3D, the insulating layer 51, the wiring layer 61, the insulating layer 71, and the wiring layer 81 are sequentially stacked on one side of the structure shown in FIG. In addition, an insulating layer 52, a wiring layer 62, an insulating layer 72, and a wiring layer 82 are sequentially stacked on the other side of the structure shown in FIG. The wiring substrate 8 shown in FIG. 28 is completed through the above steps.

  As described above, in Modification 2, the number of times of polishing is only once for polishing the upper surface of the structure shown in FIG. 29A in the step shown in FIG. On the other hand, in the first embodiment, since both surfaces of the structure shown in FIG. 3A are polished in the step shown in FIG. 3B, the number of times of polishing is two. Since the polishing process is expensive, the manufacturing process according to the second modification can reduce the manufacturing cost of the wiring board as compared with the manufacturing process according to the first embodiment.

  In addition, although there is a step between the wiring pattern 13 on the lower surface of the resin substrate 11 and the wiring pattern 42 on the lower surface of the embedded substrate 100, the wiring pattern 42 can be directly superimposed on the wiring pattern 13. Thereby, the wiring pattern 13 of the core substrate 10 and the wiring pattern 42 of the embedded substrate 100 can be continuously connected. In this structure, since it is not necessary to cover one surface of the core substrate 10 with an insulating layer, the production of the wiring substrate 8 is simplified.

<Application example 1>
The application example 1 shows another example of a suitable wiring pattern of the core substrate. In the application example 1, the description of the same components as those of the embodiment described above may be omitted.

[Structure of Wiring Board According to Application Example 1]
First, the structure of the wiring board according to Application Example 1 will be described. 30 is a cross-sectional view illustrating a wiring board according to Application Example 1. FIG. 30A is a plan view, and FIG. 30B is a cross-sectional view taken along the line CC in FIG. . In addition, illustration of the insulating layer 21 is abbreviate | omitted in Fig.30 (a).

  Referring to FIG. 30, through-holes 11y are formed on the entire surface of core substrate 10C of the wiring substrate according to Application Example 1 at a constant pitch, and through-holes 14 are filled in each through-hole 11y. The diameter of the through holes 11y can be, for example, 100 μm or more, and the pitch of the through holes 11y can be, for example, 300 μm or more.

  In the core substrate 10C, on the upper surface of the resin substrate 11, a plurality of wiring patterns 12 having a rectangular planar shape divided smaller than the pitch of the through holes 11y are periodically arranged. Further, on the lower surface of the resin substrate 11, a plurality of wiring patterns 13 having a rectangular planar shape divided smaller than the pitch of the through holes 11y are periodically arranged.

  The position of each wiring pattern 12 and the position of each wiring pattern 13 substantially overlap in plan view. The planar shape of the wiring patterns 12 and 13 may be a polygon other than a rectangle, a circle, or the like. The wiring pattern 12 and the wiring pattern 13 that are disposed at substantially overlapping positions in plan view are electrically connected via a through wiring 14 that fills the through hole 11y.

  The insulating layer 21 is formed on the upper surface of the resin substrate 11 and covers the wiring pattern 12. The insulating layer 21 does not cover the embedded substrate 100, and the upper surface of the embedded substrate 100 is exposed from the upper surface of the insulating layer 21. For example, the upper surface of the insulating layer 21 and the upper surface of the embedded substrate 100 can be polished to be flush with each other. The insulating layer 22 is formed on the lower surface of the resin substrate 11 and covers the wiring pattern 13. The insulating layer 22 does not cover the embedded substrate 100, and the lower surface of the embedded substrate 100 is exposed from the lower surface of the insulating layer 22. The lower surface of the insulating layer 22 and the lower surface of the embedded substrate 100 can be polished to be flush with each other, for example.

  An insulating layer 21 is filled in a gap formed between the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x. However, all or part of the gap formed by the side surface of the embedded substrate 100 and the inner wall surface of the through hole 11x may be filled with the insulating layer 22. The core substrate 10C is a highly versatile substrate and can be used, for example, as shown in FIG.

  FIGS. 31A and 31B are diagrams for explaining a wiring method of an upper layer of the wiring board according to the application example 1. FIG. 31A is a plan view, and FIG. 31B is along the line CC in FIG. It is sectional drawing. In FIG. 31A, illustration of the insulating layers 21 and 51 is omitted.

  Referring to FIG. 31, in the wiring layers 45 and 46 which are the upper layers of the insulating layers 21 and 22, the wiring patterns 12 and 13 are appropriately selected and connected to each other, so that a wide power supply / ground line, I / O line, etc. Can be formed arbitrarily.

  Thus, by using the core substrate 10C, via holes and upper wiring layers are formed in the insulating layers 21 and 22, and the wiring patterns 12 and 13 can be freely connected to realize various wiring shapes. . At this time, since a laser processing machine and an LDI (Laser Direct Imaging) exposure apparatus can be used, the degree of freedom during processing can be increased.

  Further, since the core substrate 10C can be formed with a through hole anywhere and has the embedded substrate 100 having a high degree of freedom in design, it becomes a more versatile substrate and can easily cope with a small variety of products.

  In the core substrate 10C, the through hole 11y (through wiring 14) formed on the entire surface also acts as a heat conduction path, so that the heat dissipation of the wiring substrate can be enhanced.

  In the conventional substrate, the through-hole position, the shape of the thick wiring pattern for the power source, and the like differ depending on the product, so that the deformation (shrinkage) of the substrate also differs depending on the product. On the other hand, in the core substrate 10C, the shape of the through hole 11y (through wiring 14) and the wiring patterns 12 and 13 are common to all types, and the structure is highly versatile with the same skeleton. Can be made almost constant. As a result, even when the product type is changed, it is possible to manufacture a wiring board with the same shrinkage and design rules, and it can be used as a base for various wiring boards. As a result, it is possible to minimize the effort of design correction and manufacturing condition adjustment required every time the product type is changed, so that the cost of the manufacturing process can be reduced.

<Application example 2>
The application example 2 shows an example of a semiconductor package in which a semiconductor chip is mounted on the wiring board according to the first embodiment. In the application example 2, the description of the same components as those of the embodiment described above may be omitted.

  FIG. 32 is a cross-sectional view illustrating a semiconductor package according to Application Example 2. Referring to FIG. 32, the semiconductor package 9 includes a wiring board 1, semiconductor chips 500 and 600, bumps 510 and 610, underfill resins 520 and 620, and external connection terminals 650.

  The semiconductor chip 500 is mounted on one side of the wiring board 1, and the electrode pads 501 of the semiconductor chip 500 are electrically connected to the wiring layer 81 of the wiring board 1 through bumps 510. An underfill resin 520 is filled between the semiconductor chip 500 and the insulating layer 71 of the wiring board 1.

  The semiconductor chip 600 is mounted on the other side of the wiring substrate 1, and the electrode pads 601 of the semiconductor chip 600 are electrically connected to the wiring layer 82 disposed on the center side of the wiring substrate 1 via the bumps 610. It is connected. An underfill resin 620 is filled between the semiconductor chip 600 and the insulating layer 72 of the wiring board 1. External connection terminals 650 are formed on the wiring layer 82 disposed on the outer peripheral side of the wiring board 1.

  For example, solder balls can be used as the bumps 510 and 610 and the external connection terminal 650. As a material of the solder ball, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Sb, an alloy of Sn and Ag, an alloy of Sn, Ag, and Cu can be used.

  Thus, the semiconductor package 9 can be realized by mounting the semiconductor chips 500 and 600 on the wiring substrate 1. Here, the embedded substrate 100 may be smaller than the planar shape of the semiconductor chips 500 and 600 because only the necessary portions of the semiconductor chip 500 and the semiconductor chip 600 need to be connected. However, the planar shape of the embedded substrate 100 may be larger than the planar shape of one or both of the semiconductor chip 500 and the semiconductor chip 600. In this case, it is possible to improve the degree of freedom of arrangement of semiconductor chips having a planar shape smaller than that of the embedded substrate 100. Further, the embedded substrate 100 is not necessarily arranged at the center of the core substrate 10 and may be arranged at a position suitable for connection. A plurality of embedded substrates 100 may be embedded in the core substrate 10.

  The semiconductor chips 500 and 600 may have the same shape or different shapes. Further, the semiconductor chips 500 and 600 may have the same function or different functions. A plurality of semiconductor chips may be mounted on one side, the other side, or both sides of the wiring board 1. Further, a semiconductor chip may be mounted only on one side of the wiring board 1. Further, instead of the wiring board 1, wiring boards 2 to 8 may be used.

  The preferred embodiments and the like have been described in detail above, but the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope described in the claims. Variations and substitutions can be added.

1, 2, 3, 4, 5, 6, 7, 8 Wiring substrate 9 Semiconductor package 10, 10A, 10B, 10C Core substrate 11 Resin substrate 11x Through hole 11y Through hole 12, 13, 41, 42 Wiring pattern 12a, 18 , 19 Pattern 14 Through wiring 21, 22, 23, 25, 26, 51, 52, 71, 72 Insulating layer 21x, 21y, 22x, 22y, 25x, 25y, 26x, 26y, 51x, 52x, 71x, 72x Via hole 21z , 22z, 311x, 312x, 418a Opening 31, 32 Via wiring 41a, 42a Metal layer 45, 46, 61, 62, 81, 82 Wiring layer 90 Frame material 100 Embedded substrate 110 Plate body 110x Through hole 120 Linear conductor 311, 312 resist 313 temporary fixing film 411, 421 pad pattern 41 2, 422 Ground pattern 415, 416 Seed layer 417, 418 Electroplating layer 417a, 419 Alignment mark 500, 600 Semiconductor chip 501, 601 Electrode pad 510, 610 Bump 520, 620 Underfill resin 650 External connection terminal

Claims (14)

A core substrate comprising a resin substrate and a through-hole penetrating the resin substrate in the thickness direction;
A plate-like body, and a plurality of linear conductors penetrating the plate-like body in the thickness direction, and an embedded substrate disposed in the through hole;
A first insulating layer covering the first surface of the resin substrate;
A first pad pattern formed on the first surface of the embedded substrate;
A third wiring pattern formed on the first surface of the resin substrate and covered with the first insulating layer;
The plurality of linear conductors have smaller intervals between adjacent linear conductors than the diameter of each linear conductor,
The wiring board, wherein the third wiring pattern is thicker than the first pad pattern. A first wiring layer including the first pad pattern and a first wiring pattern formed on a first surface of the first insulating layer;
The wiring board according to claim 1, wherein a thickness of the third wiring pattern is thicker than a thickness of the first wiring pattern. The first insulating layer includes a first layer that covers the first surface of the resin substrate and exposes the first pad pattern, and a second layer that covers the first pad pattern and extends on the first layer. And including
The wiring substrate according to claim 1, wherein a fifth wiring pattern connected to the first pad pattern and connected to the third wiring pattern is formed on the second layer.   The wiring board according to claim 3, wherein the first layer is also disposed in a space between an inner wall surface of the through hole and a side wall of the embedded substrate. The third wiring pattern is exposed in the opening provided in the first layer,
The second layer is formed to fill the opening,
A via hole penetrating the second layer filling the opening is provided;
The wiring board according to claim 3 or 4, wherein a via for connecting the third wiring pattern and the fifth wiring pattern is provided in a via hole penetrating the second layer. A via hole penetrating the first layer and the second layer is provided;
The third wiring pattern is exposed in a via hole penetrating the first layer and the second layer;
The wiring board according to claim 3 or 4, wherein a via for connecting the third wiring pattern and the fifth wiring pattern is provided in a via hole penetrating the first layer and the second layer.   The wiring board according to claim 3, wherein the first layer is made of a photosensitive resin. A second insulating layer covering the second surface of the resin substrate;
A second pad pattern formed on the second surface of the embedded substrate;
A fourth wiring pattern formed on the second surface of the resin substrate and covered with the second insulating layer;
The said 1st pad pattern and the said 2nd pad pattern are mutually arrange | positioned through the said embedded substrate, and are connected through the said some linear conductor. Wiring board.   The wiring board according to claim 8, further comprising a second wiring layer including a second wiring pattern formed on the second surface of the second insulating layer. The second insulating layer includes a third layer that covers the second surface of the resin substrate and exposes the second pad pattern, and a fourth layer that covers the second pad pattern and extends on the third layer. And including
On the fourth layer, a sixth wiring connected to the second pad pattern through the fourth layer and connected to the fourth wiring pattern through the third layer and the fourth layer. The wiring board according to claim 8, wherein a pattern is formed. A core substrate comprising a resin substrate and a through-hole penetrating the resin substrate in the thickness direction;
A plate-like body, and a plurality of linear conductors penetrating the plate-like body in the thickness direction, and an embedded substrate disposed in the through hole;
A first insulating layer covering the first surface of the resin substrate and the first surface of the embedded substrate;
A first wiring pattern formed on the first surface of the first insulating layer;
A third wiring pattern formed on the first surface of the resin substrate and covered with the first insulating layer;
A via that penetrates through the first insulating layer and connects the first wiring pattern and the third wiring pattern;
A via penetrating the first insulating layer and in direct contact with the first surface of the embedded substrate;
The plurality of linear conductors have smaller intervals between adjacent linear conductors than the diameter of each linear conductor,
The wiring board is formed such that the third wiring pattern is thicker than the first wiring pattern. A second insulating layer covering the second surface of the resin substrate;
A second wiring pattern formed on the second surface of the second insulating layer;
A fourth wiring pattern formed on the second surface of the resin substrate and covered with the second insulating layer;
A via passing through the second insulating layer and connecting the second wiring pattern and the fourth wiring pattern;
The wiring board according to claim 11, further comprising a via that penetrates the second insulating layer and directly contacts the second surface of the embedded substrate.   The wiring board according to claim 11, wherein the first insulating layer is made of a photosensitive resin.   14. A semiconductor package, wherein a semiconductor chip that is electrically connected to an outermost wiring layer is provided on the wiring board according to any one of claims 1 to 13.