JP2016178259A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem in which, when an alignment mark is formed of a wire having a large thickness, the size and shape of the alignment mark and fluctuation of the surface state thereof become large, and thus the alignment performance is degraded in the facilities of an assembling step.SOLUTION: A semiconductor device includes: a semiconductor substrate; a wiring and an alignment mark on the semiconductor substrate; a passivation film which covers the wiring and the alignment mark on the semiconductor substrate; and a rewiring on the passivation film. The film thickness of the rewiring is larger than the thickness of the wiring, and the alignment mark is formed of the same material as the wiring, and located inside a first opening surrounded by the rewiring in plan view.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a thick film rewiring is formed on a passivation film.

  Conventionally, a semiconductor device in which a thick film rewiring is formed on a passivation film has been developed for the purpose of increasing the density of the package. In such a semiconductor device, an alignment mark for alignment of the thick film redistribution layer is usually formed of the same material as that of the thick film redistribution on the passivation film in the package assembly process (for example, Patent Documents). 1).

  FIG. 12A is a plan view of a semiconductor device (semiconductor chip) 1 in which a typical representative alignment mark is formed on a passivation film. Bumps 2 and alignment marks 3 are formed on the semiconductor device 1.

  12B is a cross-sectional view taken along the line II of the semiconductor device 1 shown in FIG. In FIG. 12B, a wiring layer 5, a passivation film 6, and a rewiring layer 7 are formed on the semiconductor substrate 4. On the rewiring layer 7, the alignment mark 3 and the electrode pad 8 are formed by thick film rewiring made of the same material, and the bump 2 is formed on the electrode pad 8.

  In this structure, the alignment mark 3 is formed of the same material in the same layer as the electrode pad 8, and the alignment mark 3 and the electrode pad 8 can be formed in the same process. For this reason, an additional process is not required to form the alignment mark 3, and the cost can be suppressed. Further, the positional relationship between the alignment mark 3 and the electrode pad 8 can be arranged with high accuracy.

  Here, the semiconductor device in which bumps and rewirings are formed has been described as an example, but this structure also provides the same effect in a semiconductor device connected to the outside by wire bonding.

JP 2001-144197 A

  However, in the above-described conventional structure, since the alignment mark 3 is formed by thick film rewiring, patterning of the alignment mark 3 takes time, and there is a problem that variations in the size, shape, and surface state of the alignment mark 3 increase. is there.

  In particular, when a thick film rewiring is formed on the semiconductor chip plane as a high-voltage or low-resistance wiring such as a power semiconductor in recent years, the size and shape of the thick-film rewiring in the same layer around the alignment mark Variations in surface conditions have a significant effect on alignment.

  If the variation in the size, shape, and surface state of the alignment mark becomes large, the alignment property deteriorates in an assembly process facility such as a wire bonder. As described above, if the equipment cannot be aligned, manual alignment is required, and even if an alignment failure occurs with a small number of chips, the productivity is significantly reduced.

  Furthermore, if the thick film rewiring in the same layer is not formed in the vicinity of the alignment mark in consideration of the alignment property, the useless area that cannot be used in the semiconductor chip plane increases, the chip size increases, and the chip cost increases. To do.

  Therefore, in view of the above problems, the present invention provides a semiconductor device in which a thick film rewiring is formed on a passivation film, and improves the alignment of the thick film rewiring layer while suppressing an increase in chip size. It is an object of the present invention to provide a semiconductor device that can be used.

  In order to solve the above problems, a semiconductor device of the present invention includes a semiconductor substrate, a wiring and an alignment mark on the semiconductor substrate, a passivation film that covers the wiring and the alignment mark on the semiconductor substrate, Rewiring on the passivation film, and the rewiring is thicker than the wiring, and the alignment mark is made of the same material as the wiring. It is located within the enclosed first opening.

  In the semiconductor device of the present invention, it is preferable that the alignment mark is located in the first opening surrounded by the rewiring in four directions in a plan view.

  In the semiconductor device of the present invention, it is preferable that a second opening surrounded by the passivation film is formed on the alignment mark.

  The semiconductor device according to the present invention preferably further includes a protective film that covers the rewiring.

  In the semiconductor device of the present invention, it is preferable that the protective film covers the alignment mark.

  In the semiconductor device of the present invention, a third opening surrounded by the protective film is formed on the alignment mark, and a side surface of the first opening surrounded by the rewiring is formed on the protective film. Preferably it is covered.

  In the semiconductor device of the present invention, the rewiring is formed of a laminated film in which a plurality of rewirings are stacked, and at least the uppermost rewiring is less likely to be oxidized than the rewiring below the uppermost rewiring. It is preferable to consist of materials.

  In the semiconductor device of the present invention, it is preferable that the uppermost layer rewiring is mainly made of gold, and the rewiring below the uppermost layer rewiring is mainly made of copper.

  Further, in the semiconductor device of the present invention, a third opening surrounded by the protective film on the alignment mark is formed, and the third opening surrounded by the protective film is in the plan view, It is preferable that the first opening is surrounded by the rewiring.

In the semiconductor device of the present invention, the rewiring includes a first rewiring and a second rewiring,
The first rewiring and the second rewiring are separated by an isolation region, and the third opening surrounded by the protective film is surrounded by the second rewiring in a plan view. Preferably, the protective film includes one opening and is formed so as to continuously cover the first rewiring and the isolation region.

  In the semiconductor device of the present invention, it is preferable that the second rewiring and the isolation region are surrounded on all sides by the first rewiring in a plan view.

  In the semiconductor device of the present invention, it is preferable that the first rewiring constitutes a current path, and the second rewiring is a dummy rewiring not constituting a current path.

In the semiconductor device of the present invention,
The alignment mark preferably has a thickness of 0.2 to 2 μm, and the rewiring preferably has a thickness of 5 to 30 μm.

  In the semiconductor device of the present invention, it is preferable that the alignment mark has an L shape, a cross shape, a rectangle including a square, or a circular shape in plan view.

  In the semiconductor device of the present invention, it is preferable that the rewiring is composed of any one of a single-layer wiring mainly containing copper or a copper alloy and a multilayer wiring mainly containing copper.

  In the semiconductor device of the present invention, it is preferable that the alignment mark is an alignment mark used in a package assembly process of the semiconductor substrate.

  According to the semiconductor device of the present invention, by forming the alignment mark with the thin film wiring of the rewiring layer disposed below the thick film rewiring, surrounded by the thick film rewiring, the size and shape of the alignment mark, Variations in the surface state can be suppressed. Further, the contrast between the thick film rewiring around the alignment mark and the alignment mark can be increased. Therefore, the alignment property is improved. Furthermore, since the periphery of the alignment mark can be used as a thick film rewiring, the expansion of the semiconductor chip can be suppressed.

FIG. 1 is a plan view showing an example of a planar shape of a redistribution layer of the semiconductor device according to the first embodiment of the present invention. 2A and 2B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark portion of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a process cross-sectional view illustrating an example of a method for manufacturing an alignment mark portion of the semiconductor device according to the first embodiment of the present invention. 4A and 4B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark portion of the semiconductor device according to the modification of the first embodiment of the present invention. FIG. 5 is a sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the second embodiment of the present invention. 6A and 6B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the first modification of the second embodiment of the present invention. 7A and 7B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the second modification of the second embodiment of the present invention. 8A and 8B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark portion of the semiconductor device according to the third modification of the second embodiment of the present invention. FIG. 9 is a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the third embodiment of the present invention. FIG. 10 is a plan view showing an example of a planar shape of an alignment mark portion of a semiconductor device according to a modification common to the first to third embodiments of the present invention. FIG. 11 is a plan view showing an example of a planar shape of an alignment mark portion of a semiconductor device according to a modification common to the first to third embodiments of the present invention. 12A and 12B are a plan view and a cross-sectional view illustrating an example of the shape of the rewiring layer of the semiconductor device according to the related art.

  In the following description of the present embodiment, for the sake of simplification, the case where the wiring layer has one layer and the passivation film has one layer on the semiconductor substrate is taken as an example. Needless to say, the case where the wiring layer and the passivation film are multi-layered is also included in the present invention.

  In the description of this embodiment, the wiring layer or the rewiring layer is defined to mean an interlayer insulating film in which wiring or rewiring is formed inside or on the surface and a layer including the wiring or rewiring.

  Although omitted in the description of the present embodiment, the wiring layer and the rewiring layer include, in addition to the wiring or the rewiring, wirings of different layers or vias for connecting the rewirings.

  In addition, the material used in the description of the present embodiment is an example, and other materials can be used in the same manner as long as they are materials used in this technical field.

  In addition, the manufacturing method disclosed in the description of the present embodiment is an example, and the same manufacturing method can be used by using another manufacturing method used in this technical field.

(First embodiment)
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a plan view showing an example of a planar shape of a rewiring layer of the semiconductor device according to the first embodiment of the present invention. The semiconductor device 1 includes an electrode pad 81 and a rewiring 82 formed by thick film rewiring on the passivation film 6, and a passivation film directly below an opening 83 (first opening) provided in the rewiring 82. An alignment mark 31 formed in the same layer as the wiring 5a is disposed below.

  For example, the electrode pad 81 is formed in a substantially square shape or a substantially rectangular shape having a side length of 50 μm to 300 μm. For example, the alignment mark 31 is formed in a size that fits within a square or rectangle having a side length of 50 μm to 100 μm. The opening 83 surrounded by the rewiring 82 is formed with a size larger than the alignment mark 31 by 5 μm to 30 μm per side, for example.

  2A and 2B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the first embodiment of the present invention. 2A is an enlarged view around the alignment mark 31 in FIG. 1, and FIG. 2B is a cross-sectional view taken along the line II-II in FIG.

  In FIG. 2B, a wiring layer 5 is formed on the semiconductor substrate 4, a wiring 5a (not shown), and an alignment mark 31 formed in the same layer as the wiring 5a are formed on the wiring layer 5. A passivation film 6 covering the wiring 5a and the alignment mark 31 is formed in this order. A rewiring 82 is formed on the passivation film 6. An opening 83 is formed in the rewiring 82 immediately above the alignment mark 31.

Here, the semiconductor substrate 4 is made of, for example, silicon (Si) and has a thickness of 50 μm to 800 μm. The main component of the wiring layer 5 is an interlayer insulating film made of, for example, a silicon oxide (SiO ₂ ) film. Although not shown, a wiring 5 a made of, for example, aluminum (Al) is formed inside or on the surface of the wiring layer 5. . An alignment mark 31 made of, for example, aluminum (Al), copper (Cu), aluminum alloy, copper alloy, or the like is formed in a predetermined region on the wiring layer 5.

  Here, the thickness of the wiring layer 5 is 0.3 μm to 4 μm, and the thickness of the wiring 5 a and the alignment mark 31 is 0.2 μm to 2 μm. The passivation film 6 is formed of, for example, a silicon nitride (SiN) film and has a thickness of 0.5 μm to 2 μm. Further, the rewiring is made of, for example, copper (Cu), a copper alloy, etc., and the thickness thereof is 5 μm to 30 μm. As one embodiment of the semiconductor device of the present invention, the thickness of the rewiring is preferably larger than the thickness of the wiring.

  Next, an example of a method for manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. 3A and 3B are process cross-sectional views illustrating an example of a method for manufacturing an alignment mark portion of the semiconductor device according to the first embodiment of the present invention.

  Here, as an example, a case will be described in which the alignment mark 31 is formed of aluminum (Al), the passivation film 6 is formed of a silicon nitride (SiN) film, and the rewiring 82 is formed of copper (Cu).

  First, as shown in FIG. 3A, the wiring layer 5 is formed on the semiconductor substrate 4. The interlayer insulating film of the wiring layer 5 is formed by using, for example, a chemical vapor deposition (CVD) method. Although not shown, the wiring included in the wiring layer 5 may be formed by sputtering for aluminum (Al) or damascene for copper (Cu).

  Next, a barrier metal film made of titanium (Ti) and titanium nitride (TiN) and an aluminum (Al) film are deposited by sputtering, for example. Thereafter, alignment marks 31 are formed by patterning the deposited barrier metal film and aluminum film in a region immediately below the opening surrounded by the rewiring 82 by using a lithography method and an etching method.

  Although not shown, when the alignment mark 31 is formed by patterning, an upper layer wiring may be formed in a predetermined region on the wiring layer 5 at the same time.

  Next, a passivation film 6 made of silicon nitride (SiN) is formed on the wiring layer 5 including the alignment mark 31 by, eg, CVD.

  Next, as shown in FIG. 3B, a titanium nitride (TiN) film and a copper (Cu) seed film (not shown) are deposited on the passivation film 6 by, eg, sputtering, and a resist is applied thereon. . Next, a predetermined region of the resist is opened by lithography to expose the underlying copper (Cu) seed film. Next, an opening 83 is formed in a region on the alignment mark 31 in the electrode pad 81, the rewiring 82, and the rewiring 82 by a semi-additive method of forming copper (Cu) by electrolytic plating. Thereafter, the titanium nitride (TiN) film remaining in the opening is removed as necessary.

  As described above, a structure for visualizing the lower alignment mark 31 through the passivation film 6 can be formed in the opening 83 surrounded on all sides by the rewiring 82.

  As one mode of the semiconductor device of the present invention, the opening may be surrounded by the rewiring instead of four sides, or two sides may face each other. Note that the method for manufacturing the semiconductor device according to the present embodiment is merely an example, and the present invention is not limited to the materials and dimensions of each part described above, and the manufacturing method described above.

  According to the semiconductor device of the present embodiment, since the alignment mark in the assembly process is formed not by the thick film rewiring of the rewiring layer but by the thin film wiring located in the lower layer, the shape, size, and surface state of the alignment mark Variation is small and alignment is improved.

  Further, since the thick film rewiring can be formed so as to approach the vicinity of the alignment mark, the surrounding thick film rewiring also enters the detection field of the alignment mark during alignment. As a result, the contrast between the alignment mark and the vicinity thereof increases, and the alignment performance is further improved.

  Furthermore, since the thick film rewiring can be formed so as to approach the vicinity of the alignment mark, the peripheral area of the alignment mark can be effectively used.

(Modification of the first embodiment)
A modification of the first embodiment according to the present embodiment will be described with reference to FIG. 4A and 4B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark portion of the semiconductor device according to the modification of the first embodiment of the present invention. Here, only differences from the first embodiment will be described.

  4A is an enlarged view around the alignment mark 31 in FIG. 1 corresponding to FIG. 2A of the first embodiment, and FIG. 4B is a cross-sectional view taken along III-III in FIG. 4A. FIG.

  The difference between FIG. 4 and FIG. 2 is that, in FIG. 4, an opening 61 (second opening) is formed in the passivation film 6 on the alignment mark 31 and the center of the alignment mark 31 is exposed. It is.

  According to the semiconductor device of this modification, since the passivation film 6 does not exist on the center portion of the alignment mark 31, the alignment property is improved as compared with the first embodiment.

(Second Embodiment)
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the second embodiment of the present invention. Here, only differences from the first embodiment will be described.

  FIG. 5 is a cross-sectional view around the alignment mark 31 corresponding to FIG. 2B of the first embodiment.

  The difference between FIG. 5 and FIG. 2 is that in FIG. 5, a protective film 71 is formed on the rewiring 82 formed by thick film rewiring, and the alignment mark 31 is covered with the protective film 71. It is. However, although not shown, an opening is provided in the protective film 71 on the electrode pad 81 formed in the same layer as the rewiring 82 for electrical connection with the outside.

  Here, the protective film 71 is formed of, for example, a polyimide film and has a thickness of 3 μm to 30 μm. When the protective film 71 is a polyimide film, a polyimide resin is applied by spin coating, opened using a lithography method and an etching method, and cured by baking to obtain a polyimide film.

  According to the semiconductor device of the present embodiment, the rewiring 82 is covered with the protective film 71, and the rewiring 82 is protected from corrosion, so that the reliability of the rewiring 82 can be improved.

  The protective film 71 may not be a polyimide film as long as it has a property of transmitting light.

(First Modification of Second Embodiment)
A first modification of the second embodiment according to the present embodiment will be described with reference to FIG. 6A and 6B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the first modification of the second embodiment of the present invention. Here, only differences from the second embodiment will be described.

  6A is an enlarged view around the alignment mark 31 corresponding to FIG. 2A of the first embodiment, and FIG. 6B is a cross-sectional view taken along IV-IV in FIG. 6A. It is.

  The difference between FIG. 6 and FIG. 5 is that, in FIG. 6, an opening 72 (third opening) is formed in the protective film 71 on the alignment mark 31 and the side surface of the rewiring 82 around the opening 72 is protected. It is covered with the film 71 and the alignment mark 31 is visualized through the passivation film 6.

  According to the semiconductor device of this modification, since the protective film 71 does not exist on the alignment mark 31, the alignment property is improved as compared with the second embodiment. Further, since the protective film 71 covers the rewiring 82 and protects the rewiring 82 from corrosion or the like, the reliability of the rewiring 82 can be improved.

(Second Modification of Second Embodiment)
A second modification of the second embodiment according to the present embodiment will be described with reference to FIG. 7A and 7B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the second modification of the second embodiment of the present invention. Here, only differences from the first modification of the second embodiment will be described.

  FIG. 7A is an enlarged view around the alignment mark 31 corresponding to FIG. 6A of the first modification of the second embodiment, and FIG. It is sectional drawing between V.

  The difference between FIG. 7 and FIG. 6 is that in FIG. 7, the rewiring 82 has a laminated film structure of an upper film 84 and a lower film 85. Although not shown, the electrode pad 81 formed in the same layer as the rewiring 82 has a similar laminated film structure.

  Here, the side surface of the rewiring 82 around the opening 72 is covered with the protective film 71 as in the first modification of the second embodiment. As a result, the region exposed in the rewiring 82 is only the upper film 84 due to the opening formed in the upper part of the electrode pad 81.

  For this reason, as the lower layer film 85 where the rewiring 82 is not exposed, for example, copper (Cu) which is easy to oxidize is used as the main material, but inexpensive copper (Cu) is used. However, expensive gold (Au) can be used.

  As a manufacturing method of the rewiring 82, it can be formed by a semi-additive method as in the case of a single layer. For example, after forming a lower layer film 85 made of copper (Cu) by an electrolytic plating method, An upper film 84 made of gold (Au) is formed by electrolytic plating or sputtering.

  According to the semiconductor device of the present modification example, gold (Au) that is expensive but difficult to oxidize and has stable physical properties is used only for the upper layer film 84 exposed in the rewiring 82, so that the rewiring 82 as a whole can be manufactured at low cost. In addition, the reliability of the semiconductor device 1 can be improved.

(Third Modification of Second Embodiment)
A third modification of the second embodiment according to the present embodiment will be described with reference to FIG. 8A and 8B are a plan view and a cross-sectional view showing an example of the shape of the alignment mark portion of the semiconductor device according to the third modification of the second embodiment of the present invention. Here, only differences from the first modification of the second embodiment will be described.

  FIG. 8A is an enlarged view around the alignment mark 31 corresponding to FIG. 6A of the first modification of the second embodiment, and FIG. It is sectional drawing between VI.

  The difference between FIG. 8 and FIG. 6 is that in FIG. 8, the opening 73 surrounded by the protective film 71 on the alignment mark 31 is opened so that the entire opening 83 surrounded by the rewiring 82 is exposed. The opening is larger than the portion 83. That is, in the semiconductor device of the present invention, the opening surrounded by the protective film may include an opening formed in the rewiring in a plan view.

  As shown in FIG. 6, when the opening 72 surrounded by the protective film 71 is smaller than the opening 83 surrounded by the rewiring 82, the protective film 71 is also formed on the side surface of the rewiring 82. At this time, since the rewiring 82 is a thick film, patterning takes time, and the shape of the side surface of the opening 83 surrounded by the rewiring 82 may not be stable. Therefore, the protection formed on the side surface of the rewiring 82 The film 71 also tends to vary in film thickness and shape and is not stable. As a result, the alignment property is degraded.

  On the other hand, if the opening 73 surrounded by the protective film 71 on the alignment mark 31 is larger than the opening 83 surrounded by the rewiring 82 as shown in FIG. Since the protective film 71 does not exist on the side surface of the enclosed opening 83, the alignment property is improved.

(Third embodiment)
A semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 9 is a plan view and a cross-sectional view showing an example of the shape of the alignment mark part of the semiconductor device according to the third embodiment of the present invention. Here, only differences from the third modification of the second embodiment will be described.

  FIG. 9A is an enlarged view around the alignment mark 31 corresponding to FIG. 8A of the third modified example of the second embodiment, and FIG. 9B is the outermost surface of FIG. 9A. FIG. 9C is a cross-sectional view taken along the line VII-VII in FIG. 8A.

  The difference between FIG. 9 and FIG. 8 is that the first rewiring 82a in which the opening 83 surrounded by the rewiring 82 of FIG. 8 is formed larger than FIG. A second rewiring (dummy wiring) 86 that is not connected to the first rewiring 82a and does not function electrically is formed inside the opening 83a surrounded on all sides by the first rewiring 82a. . Further, the alignment mark 31 is arranged inside the opening 87 provided in the second rewiring 86 and is visualized through the passivation film 6. Here, the opening 72 surrounded on all sides by the protective film 71 is larger than the opening 87 surrounded on all sides by the second rewiring 86 in a plan view, and the side surface 74 of the opening 72 surrounded by the protective film 71. Is located on the second rewiring 86. That is, in the semiconductor device of the present invention, the first opening surrounded by the rewiring is surrounded by the second rewiring, and the third opening surrounded by the protective film is the planar view in the plan view. Including the first opening surrounded by the second rewiring, the protective film may be formed so as to continuously cover the first rewiring and the isolation region. Note that the opening 83a and the opening 87 are not four sides, but three sides may be surrounded by the first rewiring and the second rewiring, or two sides may face each other.

  Therefore, the opening 73 surrounded by the protective film 71 is opened larger than the opening 87 surrounded by the second rewiring 86, and on the side surface of the opening 73 surrounded by the second rewiring 86. Since the protective film 71 does not exist, the alignment property is improved for the same reason as described in the third modification of the second embodiment.

  Further, the inner side surface of the second rewiring 86 is exposed from the protective film 71, but the second rewiring 86 is a dummy wiring and does not affect the operation of the semiconductor device. Therefore, even if corrosion or the like occurs, the operation of the semiconductor device is not affected. However, even when the second rewiring 86 functions electrically, if the potential is fixed, the current path as in the first rewiring is not formed, and the operation of the semiconductor device is not substantially affected.

  Further, the first rewiring 82a is covered with the protective film 71 on the inner side surface thereof, and the first rewiring 82a is protected from corrosion or the like, so that the reliability of the first rewiring 82a can be improved.

  FIG. 10 is a plan view showing an example of a planar shape of an alignment mark portion of a semiconductor device according to a modification common to the first to third embodiments of the present invention. In the description of the first to third embodiments of the present invention, the case where the shape of the alignment mark 31 in plan view is L-shaped and the shape of the opening 83 of the rewiring 82 is square has been described. In addition, for example, the effects of the present invention can be obtained even when other shapes such as a cross shape, a circular shape, and a rectangle including a square as shown in FIGS. 10 (a), (b), and (c) are used. And is included in the present invention.

  FIG. 11 is a plan view showing an example of a planar shape of an alignment mark portion of a semiconductor device according to a modification common to the first to third embodiments of the present invention. For example, by arranging a plurality of fine wiring patterns 32 as shown in FIG. 11A in a predetermined shape, the effect of the present invention can be achieved even when the alignment mark 33 surrounded by the plurality of wiring patterns 32 is formed. And is included in the present invention.

  Furthermore, the effect of the present invention can be obtained even when the opening 83 as shown in FIG. 11B is changed to another shape such as an L-shape matching the shape of the alignment mark 31, and is included in the present invention. It is.

  The semiconductor device of the present invention is capable of improving the alignment property of the thick film redistribution layer while suppressing the increase in the chip size, and particularly requires the thick film rewiring with high withstand voltage and low resistance. This is useful in a semiconductor device in which a thick film rewiring is formed on a passivation film, such as a power semiconductor.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Bump 3, 31, 33 Alignment mark 4 Semiconductor substrate 5 Wiring layer 5a Wiring 6 Passivation film 7 Rewiring layer 8 Electrode pad 32 Wiring pattern 61, 72, 73, 83, 83a, 87 Opening 71 Protective film 81 Electrode pad 82 Rewiring 82a First rewiring 84 Upper layer film 85 Lower layer film 86 Second rewiring (dummy rewiring)

Claims (16)

A semiconductor substrate;
Wiring and alignment marks on the semiconductor substrate;
A passivation film covering the wiring and the alignment mark on the semiconductor substrate;
Rewiring on the passivation film,
The film thickness of the rewiring is thicker than the film thickness of the wiring,
The alignment mark is formed of the same material as the wiring, and is located in a first opening surrounded by the rewiring in plan view. The semiconductor device according to claim 1,
The said alignment mark is a semiconductor device located in the said 1st opening part enclosed by the said rewiring in four directions in planar view. The semiconductor device according to claim 1 or 2,
A semiconductor device in which a second opening surrounded by the passivation film is formed on the alignment mark. The semiconductor device according to any one of claims 1 to 3,
A semiconductor device further comprising a protective film covering the rewiring. The semiconductor device according to claim 4,
The semiconductor device, wherein the protective film covers the alignment mark. The semiconductor device according to claim 4,
A third opening surrounded by the protective film is formed on the alignment mark,
A semiconductor device in which a side surface of the first opening surrounded by the rewiring is covered with the protective film. The semiconductor device according to claim 6.
The rewiring comprises a laminated film in which a plurality of rewirings are laminated,
At least the uppermost layer rewiring is a semiconductor device made of a material that is less susceptible to oxidation than the uppermost layer rewiring. The semiconductor device according to claim 7,
The uppermost layer rewiring is mainly made of gold, and the rewiring below the uppermost layer rewiring is mainly made of copper. The semiconductor device according to claim 4,
A third opening surrounded by the protective film on the alignment mark is formed;
The semiconductor device is formed such that the third opening surrounded by the protective film includes the first opening surrounded by the rewiring in a plan view. The semiconductor device according to claim 4,
The rewiring has a first rewiring and a second rewiring,
The first rewiring and the second rewiring are separated by a separation region,
The third opening surrounded by the protective film includes the first opening surrounded by the second rewiring in a plan view, and the protective film includes the first rewiring and the isolation region. A semiconductor device formed so as to cover continuously. The semiconductor device according to claim 10.
The semiconductor device in which the second rewiring and the isolation region are surrounded on all sides by the first rewiring in a plan view. The semiconductor device according to any one of claims 10 and 11,
The semiconductor device, wherein the first rewiring constitutes a current path, and the second rewiring is a dummy rewiring not constituting a current path. The semiconductor device according to any one of claims 1 to 12,
The alignment mark has a thickness of 0.2 μm to 2 μm,
A semiconductor device having a film thickness of the rewiring of 5 μm to 30 μm. The semiconductor device according to any one of claims 1 to 13,
A shape of the alignment mark is a semiconductor device having an L shape, a cross shape, a rectangle including a square, or a circular shape in plan view. The semiconductor device according to any one of claims 1 to 14,
The rewiring is a semiconductor device composed of either a single-layer wiring mainly containing copper or a copper alloy or a multilayer wiring mainly containing copper. The semiconductor device according to any one of claims 1 to 15,
The semiconductor device, wherein the alignment mark is an alignment mark used in a package assembly process of the semiconductor substrate.

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