JP2016158086A - Switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switch circuit capable of suppressing current counter flow.SOLUTION: According to an embodiment, a switch circuit comprises a first MOS transistor, and a counter flow prevention part. The first MOS transistor has a first electrode connected with an input node, a second electrode connected with an output node, and a third electrode supplied with a control voltage, and is turned on and off depending on a voltage level of the control voltage. The counter flow prevention part electrically disconnects a back gate and the second electrode of the first MOS transistor from each other when the first MOS transistor is in an off state, and makes the back gate and the second electrode of the first MOS transistor electrically conductive to each other when the first MOS transistor is in an on state.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to a switch circuit.

  In general, a power switch circuit includes a MOS transistor connected between an input terminal to which a power source or the like is connected and an output terminal to which a load is connected.

  In this type of power switch circuit, when the MOS transistor is off and the output voltage at the output terminal is higher than the input voltage at the input terminal, current flows backward from the output terminal to the input terminal via the parasitic diode of the MOS transistor. . Therefore, when various devices and circuit elements are connected to the input terminal, they may be damaged.

JP-A-10-136562

  Embodiments of the present invention provide a switch circuit that can suppress reverse current flow.

  According to the embodiment, the switch circuit includes a first MOS transistor and a backflow prevention unit. The first MOS transistor has a first electrode connected to the input node, a second electrode connected to the output node, and a third electrode to which a control voltage is supplied, and the voltage of the control voltage Turns on or off depending on the level. The backflow prevention unit electrically cuts off the back gate and the second electrode of the first MOS transistor when the first MOS transistor is off, and turns on when the first MOS transistor is on. The back gate of the first MOS transistor and the second electrode are electrically connected.

1 is a circuit diagram of a power switch circuit according to a first embodiment. FIG. FIG. 5 is a circuit diagram of a power switch circuit according to a second embodiment. It is a circuit diagram of the power switch circuit concerning a 3rd embodiment. It is a circuit diagram of the power switch circuit of the 1st comparative example. It is a circuit diagram of the power switch circuit of the 2nd comparative example.

  Embodiments of the present invention will be described below with reference to the drawings. These embodiments do not limit the present invention.

(First embodiment)
FIG. 1 is a circuit diagram of a power switch circuit (switch circuit) 10 according to the first embodiment. As shown in FIG. 1, the power switch circuit 10 includes a first MOS transistor NM1, a backflow prevention unit 11, and a control voltage generation unit 12.

  The first MOS transistor NM1 has a drain (first electrode) connected to an input terminal (input node) T1, a source (second electrode) connected to an output terminal (output node) T2, and a control voltage VG. And a gate to be supplied (third electrode). The first MOS transistor NM1 is turned on or off depending on the voltage level of the control voltage VG. The first MOS transistor NM1 is an N-type MOS transistor.

  The backflow prevention unit 11 electrically disconnects the back gate and the source of the first MOS transistor NM1 when the first MOS transistor NM1 is off, and the first MOS transistor NM1 is on when the first MOS transistor NM1 is on. The back gate and the source of the MOS transistor NM1 are electrically connected.

  In the present embodiment, the backflow prevention unit 11 includes a second MOS transistor NM2 having the same conductivity type as that of the first MOS transistor NM1. That is, the second MOS transistor NM2 is an N-type MOS transistor. The second MOS transistor NM2 is supplied with a drain (fourth electrode) connected to the back gate of the first MOS transistor NM1, a source (fifth electrode) connected to the output terminal T2, and a control voltage VG. A gate (sixth electrode) and a back gate connected to the reference voltage terminal T3.

  The control voltage generator 12 is configured to turn on the first and second MOS transistors NM1 and NM2 according to a control signal S supplied from the outside of the power switch circuit 10, or the first and second control voltages VG A control voltage VG having a voltage level for turning off the second MOS transistors NM1 and NM2 is generated. The control voltage VG may be supplied from the outside of the power switch circuit 10.

  The parasitic diodes D1 and D2 are parasitic elements of the first MOS transistor NM1. That is, the anodes of the parasitic diodes D1 and D2 are connected to the back gate of the first MOS transistor NM1. The cathode of the parasitic diode D1 is connected to the drain of the first MOS transistor NM1. The cathode of the parasitic diode D2 is connected to the source of the first MOS transistor NM1.

  The parasitic diodes D3 and D4 are parasitic elements of the second MOS transistor NM2. That is, the anodes of the parasitic diodes D3 and D4 are connected to the back gate of the second MOS transistor NM2. The cathode of the parasitic diode D3 is connected to the drain of the second MOS transistor NM2. The cathode of the parasitic diode D4 is connected to the source of the second MOS transistor NM2.

  A positive power supply voltage VIN is supplied to the input terminal T1, and various devices and circuit elements (not shown) are connected to the input terminal T1. A load capacitor CL and a load RL are connected to the output terminal T2. The reference voltage terminal T3 is set to a reference voltage (for example, ground voltage).

  Note that a node in this specification is a concept including not only physical signal connection points such as ports and terminals but also signal wirings of the same potential or arbitrary points on a pattern.

  Next, the operation of the power switch circuit 10 will be described.

  First, a positive power supply voltage VIN is applied to the input terminal T1, an appropriate control voltage VG higher than the power supply voltage VIN is applied to the gates of the first and second MOS transistors NM1 and NM2, and the first and second MOS transistors are applied. When the transistors NM1 and NM2 are on, the current path between the input terminal T1 and the output terminal T2 is conducted. In this case, the second MOS transistor NM2 conducts the source and back gate of the first MOS transistor NM1. As a result, the potentials of the source and back gate of the first MOS transistor NM1 become equal, so that an increase in the threshold voltage of the first MOS transistor NM1 is suppressed and the on-resistance of the first MOS transistor NM1 is minimized. can do. Therefore, the power loss between the input terminal T1 and the output terminal T2 can be minimized. The current flows from the input terminal T1 to the output terminal T2.

  At this time, since no current flows through the second MOS transistor NM2, the on-resistance of the second MOS transistor NM2 may be higher than the on-resistance of the first MOS transistor NM1. Thereby, since the size of the second MOS transistor NM2 can be made smaller than the size of the first MOS transistor NM1, the power switch circuit 10 can be configured to be small and inexpensive. Further, as described above, the back gate of the second MOS transistor NM2 can be connected to the reference voltage terminal T3.

  On the other hand, when an appropriate control voltage VG such as a reference voltage is applied to the gates of the first and second MOS transistors NM1 and NM2, and the first and second MOS transistors NM1 and NM2 are off, the input terminal The current path between T1 and the output terminal T2 is interrupted. In this case, the second MOS transistor NM2 electrically cuts off the source and back gate of the first MOS transistor NM1. Further, the back gate of the second MOS transistor NM2 is not connected to the output terminal T2. Therefore, even when the power supply voltage VIN is zero and the voltage at the output terminal T2 is positive due to the load capacitance CL or the like, no current flows backward from the output terminal T2 to the input terminal T1.

  Here, the power switch circuits 10X and 10Y of the comparative example will be described.

  FIG. 4 is a circuit diagram of the power switch circuit 10X of the first comparative example. The power switch circuit 10X does not include the second MOS transistor NM2 of FIG. In order to reduce the on-resistance of the first MOS transistor NM1, the back gate and the source of the first MOS transistor NM1 are connected.

  When the first MOS transistor NM1 is turned off, the power supply voltage VIN is zero, and the voltage at the output terminal T2 is positive, unlike the first embodiment, the drain of the first MOS transistor NM1 A current flows backward from the output terminal T2 to the input terminal T1 via the parasitic diode D1 existing between the back gate.

  FIG. 5 is a circuit diagram of the power switch circuit 10Y of the second comparative example. The power switch circuit 10Y includes an N-type second MOS transistor NM10 connected in series to the first MOS transistor NM1 in addition to the configuration of the power switch circuit 10X of FIG. The size of the second MOS transistor NM10 is the same as the size of the first MOS transistor NM1.

  The second MOS transistor NM10 has a source connected to the source of the first MOS transistor NM1, a drain connected to the output terminal T2, and a gate to which the control voltage VG is supplied. The back gate and the source of the second MOS transistor NM10 are connected. The anodes of the parasitic diodes D11 and D12 are connected to the back gate of the second MOS transistor NM10. The cathode of the parasitic diode D11 is connected to the drain of the second MOS transistor NM10. The cathode of the parasitic diode D12 is connected to the source of the second MOS transistor NM10.

  When the first and second MOS transistors NM1 and NM10 are off, current does not flow backward from the output terminal T2 to the input terminal T1 due to the presence of the parasitic diode D11.

  However, in the power switch circuit 10Y, when the first and second MOS transistors NM1 and NM10 are on, the on-resistance of the second MOS transistor NM10 is the resistance between the input terminal T1 and the output terminal T2. Join. Therefore, there is a problem that the power loss between the input terminal T1 and the output terminal T2 increases as compared with the first comparative example. Further, when the power switch circuit 10Y is configured as an integrated circuit (IC), there is a problem that the chip area is increased and the manufacturing cost is increased.

  On the other hand, in the first embodiment, since the resistance between the input terminal T1 and the output terminal T2 is equivalent to that of the first comparative example, the power loss is also equivalent to that of the first comparative example. In addition, as described above, in the first embodiment, the size of the second MOS transistor NM2 can be made smaller than the size of the first MOS transistor NM1, so that the chip area and the manufacturing can be reduced as compared with the second comparative example. There is little increase in cost.

  As described above, according to the present embodiment, the backflow prevention unit 11 (second MOS transistor NM2) includes the back gate and the source of the first MOS transistor NM1 when the first MOS transistor NM1 is off. And is electrically cut off. Thereby, even if the parasitic diode D1 exists, a current path from the output terminal T2 to the input terminal T1 is not formed. Therefore, even when the voltage at the output terminal T2 is higher than the power supply voltage VIN, it is possible to prevent the backflow of current from the output terminal T2 to the input terminal T1.

(Second Embodiment)
The second embodiment is different from the first embodiment in that the back gate of the first MOS transistor NM1 is connected to the reference voltage terminal T3 via a resistor (impedance element) R1.

  FIG. 2 is a circuit diagram of a power switch circuit 10A according to the second embodiment. In FIG. 2, the same reference numerals are given to the components common to FIG. 1, and the differences will be mainly described below.

  The power switch circuit 10A includes a resistor R1 in addition to the configuration of the power switch circuit 10 of FIG. The resistor R1 is connected between the back gate of the first MOS transistor NM1 and the back gate of the second MOS transistor NM2.

  The resistance value of the resistor R1 is preferably sufficiently larger than the on-resistance of the second MOS transistor NM2. The reason is that when the first and second MOS transistors NM1 and NM2 are on, a current flows from the output terminal T2 to the reference voltage terminal T3 via the second MOS transistor NM2 and the resistor R1. This is because the voltage drop due to the ON resistance of the first MOS transistor NM2 can be reduced, and the decrease in the voltage of the back gate of the first MOS transistor M1 can be reduced. Thereby, the on-resistance of the first MOS transistor NM1 can be minimized as in the first embodiment. Also, power loss can be reduced.

  With this configuration, according to the present embodiment, when the first MOS transistor NM1 is off, the voltage of the back gate of the first MOS transistor NM1 can be set to the reference voltage via the resistor R1. That is, the indefinite state of the back gate voltage of the first MOS transistor NM1 when the first MOS transistor NM1 is off can be eliminated. Therefore, malfunction of the first MOS transistor NM1 can be prevented.

(Third embodiment)
The third embodiment is different from the second embodiment in that a P-type MOS transistor is used instead of the N-type MOS transistor.

  FIG. 3 is a circuit diagram of a power switch circuit 10B according to the third embodiment. In FIG. 3, the same reference numerals are given to the components common to FIG. 2, and the differences will be mainly described below.

  As shown in FIG. 3, the power switch circuit 10B includes a first MOS transistor PM1, a backflow prevention unit 11B, and a control voltage generation unit 12B.

  The first MOS transistor PM1 includes a drain (first electrode) connected to the input terminal T1, a source (second electrode) connected to the output terminal T2, and a gate (third electrode) supplied with the control voltage VG. And). The first MOS transistor PM1 is turned on or off depending on the voltage level of the control voltage VG. The first MOS transistor PM1 is a P-type MOS transistor.

  The backflow prevention unit 11B electrically disconnects the back gate and the source of the first MOS transistor PM1 when the first MOS transistor PM1 is off, and the first current prevention unit 11B when the first MOS transistor PM1 is on. The back gate and the source of the MOS transistor PM1 are electrically connected.

  The backflow prevention unit 11B includes a second MOS transistor PM2 that is a P-type MOS transistor. The second MOS transistor PM2 is supplied with a drain (fourth electrode) connected to the back gate of the first MOS transistor PM1, a source (fifth electrode) connected to the output terminal T2, and a control voltage VG. A gate (sixth electrode) and a back gate connected to the reference voltage terminal T3.

  In response to the control signal S, the control voltage generator 12B controls the negative voltage level control voltage VG for turning on the first and second MOS transistors PM1 and PM2, or the first and second MOS transistors PM1 and PM2. A control voltage VG having a negative voltage level is generated to turn off.

  The cathodes of the parasitic diodes D1 and D2 are connected to the back gate of the first MOS transistor PM1. The anode of the parasitic diode D1 is connected to the drain of the first MOS transistor PM1. The anode of the parasitic diode D2 is connected to the source of the first MOS transistor PM1.

  The cathodes of the parasitic diodes D3 and D4 are connected to the back gate of the second MOS transistor PM2. The anode of the parasitic diode D3 is connected to the drain of the second MOS transistor PM2. The anode of the parasitic diode D4 is connected to the source of the second MOS transistor PM2.

  A negative power supply voltage VIN is supplied to the input terminal T1, and various devices and circuit elements (not shown) are connected to the input terminal T1. The reference voltage terminal T3 is set to a reference voltage (for example, ground voltage). Thus, the power switch circuit 10B functions as a negative power switch circuit.

  When the appropriate control voltage VG is applied and the first and second MOS transistors PM1 and PM2 are turned on, the current path between the input terminal T1 and the output terminal T2 becomes conductive. In this case, the second MOS transistor PM2 makes the source of the first MOS transistor PM1 and the back gate conductive. Thereby, the on-resistance of the first MOS transistor PM1 can be minimized, and the power loss between the input terminal T1 and the output terminal T2 can be minimized. The current flows from the output terminal T2 to the input terminal T1.

  On the other hand, when the first and second MOS transistors PM1 and PM2 are turned off by the appropriate control voltage VG, the current path between the input terminal T1 and the output terminal T2 is interrupted. In this case, the second MOS transistor PM2 electrically cuts off the source and back gate of the first MOS transistor PM1. Therefore, even when the power supply voltage VIN is zero and the voltage at the output terminal T2 is negative due to the load capacitance CL or the like, no current flows backward from the input terminal T1 to the output terminal T2.

  Further, when the first MOS transistor PM1 is off, the voltage of the back gate of the first MOS transistor PM1 can be set to the reference voltage via the resistor R1.

  Therefore, the effects of the second embodiment can be obtained also by the third embodiment.

  Note that the resistor R1 may not be provided in the third embodiment.

  In the power switch circuits 10, 10A, 10B according to the first to third embodiments, the entire circuit may be formed on the same semiconductor substrate, or a part of the circuit may be formed on another semiconductor substrate. Also good. The power switch circuits 10, 10A, and 10B may be mounted on a printed circuit board or the like using discrete components.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

10, 10A, 10B Power switch circuit (switch circuit)
11, 11B Backflow prevention unit 12, 12B Control voltage generation unit NM1, PM1 First MOS transistor NM2, PM2 Second MOS transistor D1-D4 Parasitic diode R1 Resistance (impedance element)
T1 input terminal (input node)
T2 output terminal (output node)
T3 reference voltage terminal

Claims (5)

A first electrode connected to the input node; a second electrode connected to the output node; and a third electrode to which a control voltage is supplied; a first electrode that is turned on or off according to a voltage level of the control voltage MOS transistors of
When the first MOS transistor is off, the back gate of the first MOS transistor and the second electrode are electrically disconnected, and when the first MOS transistor is on, the first MOS transistor A backflow prevention unit that electrically connects the back gate and the second electrode;
A switch circuit comprising:   The backflow prevention unit includes a fourth electrode connected to the back gate of the first MOS transistor, a fifth electrode connected to the output node, a sixth electrode supplied with the control voltage, and a predetermined electrode 2. The switch circuit according to claim 1, further comprising a second MOS transistor having the same conductivity type as that of the first MOS transistor.   The switch circuit according to claim 2, further comprising an impedance element connected between the back gate of the first MOS transistor and the back gate of the second MOS transistor.   4. The switch circuit according to claim 3, wherein an impedance of the impedance element is larger than an on-resistance of the second MOS transistor.   5. The switch circuit according to claim 2, wherein an on-resistance of the second MOS transistor is larger than an on-resistance of the first MOS transistor.

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