JP2016155706A - Method for manufacturing free-standing substrate, substrate and free-standing substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce dislocation density on the surface of a joint body in a method capable of obtaining a joint body of group III nitride semiconductor crystals by growing a group III nitride semiconductor crystal on a base substrate having pieces of group III nitride semiconductor crystal adjacently arranged each other to join the group III nitride semiconductor crystals grown from each piece of the crystals.SOLUTION: A method for manufacturing a free-standing substrate comprises: a mask formation step S10 of covering a boundary part between adjacent crystal pieces on a first surface of a base substrate formed by arranging two or more pieces of group III nitride semiconductor crystal to expose a portion without having the boundary part and forming a mask including an insulation layer; and a growth step S20 of growing a group III nitride semiconductor from the exposed portion of the base substrate to form a group III nitride semiconductor layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a self-supporting substrate manufacturing method, a substrate, and a self-supporting substrate.

  Patent Document 1 discloses a technique for manufacturing a group III nitride semiconductor substrate. In the technique described in Patent Document 1, a plurality of IIIs having a principal surface of {hk− (h + k) 0} (h and k are integers) are generated from a group III nitride semiconductor mother crystal having a {0001} plane as a principal surface. The first step of cutting the group nitride semiconductor crystal piece and the group III nitride semiconductor by bonding the crystal pieces to each other at least at a part of their main surfaces so that the [0001] direction of the crystal piece is the same. A second step of obtaining a crystal bonded body, and forming a main surface of {hk− (h + k) l} (h, k, and l are integers) arbitrarily specified other than {0001} on the bonded body; A third step of obtaining a group nitride semiconductor crystal junction substrate (see FIG. 1 of Patent Document 1).

JP 2010-13298 A

  The inventors have grown group III nitride semiconductor crystals on a base substrate in which group III nitride semiconductor crystal pieces are arranged close to each other, and group III nitride semiconductor crystals grown from each of the crystal pieces. The following problems have been found in a method of joining to obtain a joined body of a group III nitride semiconductor crystal.

  In the base substrate, the crystal is discontinuous at the boundary between the crystal pieces. In such a group III nitride semiconductor crystal bonded body formed on the base substrate, defects are likely to occur near the boundary. This defect propagates in the thickness direction of the bonded body as the group III nitride semiconductor crystal grows, and can reach the surface of the bonded body.

  In this way, a group III nitride semiconductor crystal is grown on a base substrate in which group III nitride semiconductor crystal pieces are arranged close to each other, and the group III nitride semiconductor crystals grown from each of the crystal pieces are joined together. Thus, the method for obtaining a group III nitride semiconductor crystal bonded body has a problem of increasing the dislocation density on the surface of the bonded body. This invention makes it a subject to reduce the dislocation density of the conjugate | zygote surface in the said method.

According to the present invention,
A portion where a boundary portion between adjacent crystal pieces on the first surface is covered on a first surface of a base substrate formed by arranging a plurality of group III nitride semiconductor crystal pieces and the boundary portion does not exist And forming a mask including an insulating layer, and exposing a mask,
After the mask formation step, grow a group III nitride semiconductor from the exposed portion of the base substrate, and a growth step of forming a group III nitride semiconductor layer,
A method for manufacturing a self-supporting substrate having the above is realized.

Moreover, according to the present invention,
A base substrate configured by arranging a plurality of group III nitride semiconductor crystal pieces;
A mask located on the first surface of the base substrate, covering a boundary portion between adjacent crystal pieces on the first surface, exposing a portion where the boundary portion does not exist, and including an insulating layer When,
Is realized.

Moreover, according to the present invention,
The substrate;
A group III nitride semiconductor layer located on the substrate;
A self-supporting substrate having is realized.

  According to the present invention, a group III nitride semiconductor crystal is grown on a base substrate in which group III nitride semiconductor crystal pieces are arranged close to each other, and group III nitride semiconductor crystals grown from each of the crystal pieces are separated. In the method of bonding and obtaining a group III nitride semiconductor crystal bonded body, the dislocation density on the surface of the bonded body can be reduced.

It is a flowchart which shows an example of the flow of a process of the manufacturing method of the self-supporting substrate of this embodiment. It is a plane schematic diagram which shows an example of the base substrate of this embodiment. It is a side surface schematic diagram which shows an example of the base substrate of this embodiment. It is a plane schematic diagram which shows an example of the base substrate of this embodiment. It is a plane schematic diagram which shows an example of the base substrate of this embodiment. It is a side surface schematic diagram which shows an example of a mode that the mask was formed on the base substrate of this embodiment. It is a side surface schematic diagram which shows an example of a mode that the mask was formed on the base substrate of this embodiment. It is a schematic diagram of an HVPE apparatus. It is a side surface schematic diagram which shows an example of a mode that the group III nitride semiconductor layer was formed over the mask on the base substrate of this embodiment. It is a side surface schematic diagram which shows an example of a mode that the group III nitride semiconductor layer was formed over the mask on the base substrate of this embodiment. It is a flowchart which shows an example of the flow of a process of the manufacturing method of the self-supporting substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment. It is a manufacturing process figure which shows an example of the flow of a process of the manufacturing method of the self-supporting board | substrate of this embodiment.

  Hereinafter, an embodiment of a method for manufacturing a self-supporting substrate of the present invention will be described with reference to the drawings. The drawings are only schematic diagrams for explaining the configuration of the invention, and the size, shape, number, and ratio of different member sizes are not limited to those shown in the drawings.

<First Embodiment>
First, an outline of the present embodiment will be described. In the self-supporting substrate manufacturing method of the present embodiment, a plurality of group III nitride semiconductor crystal pieces are arranged close to each other to form a base substrate, and then an insulating layer is formed on the growth surface (first surface) of the base substrate. Forming a mask containing The mask is formed in a pattern that covers a boundary portion between adjacent crystal pieces on the growth surface and exposes a portion where the boundary portion does not exist. Thereafter, a group III nitride semiconductor is epitaxially grown from the exposed portion of the base substrate. Then, the group III nitride semiconductor crystals grown from the exposed portions are joined together to form a group III nitride semiconductor layer.

  Next, the manufacturing method of the self-supporting substrate of this embodiment will be described in detail. FIG. 1 is a flowchart showing an example of a processing flow of the method for manufacturing a self-supporting substrate according to the present embodiment. As shown in the figure, the method for manufacturing a self-supporting substrate according to the present embodiment includes a mask formation step S10 and a growth step S20.

  In the mask formation step S10, a boundary surface between adjacent crystal pieces on the growth surface is covered on the growth surface (first surface) of the base substrate formed by arranging a plurality of group III nitride semiconductor crystal pieces, A portion including no boundary portion is exposed, and a mask including an insulating layer is formed.

  First, the base substrate will be described. FIG. 2 shows an example of a schematic plan view of the base substrate 10. The base substrate 10 shown in the figure is configured by arranging six crystal pieces 11 having a rectangular planar shape in contact with each other so that their longitudinal directions are parallel to each other (a gap may exist in part). . The illustrated surface is a growth surface of the base substrate 10.

  FIG. 3 shows an example of a schematic side view of the base substrate 10 of FIG. FIG. 3 shows a state where the base substrate 10 of FIG. 2 is observed from the bottom to the top in the drawing.

  FIG. 4 shows another example of a schematic plan view of the base substrate 10. The base substrate 10 shown in the figure is configured by arranging six crystal pieces 11 having a rectangular planar shape with a gap therebetween so that their longitudinal directions are parallel to each other. In the illustrated example, the gap is a space where air or the like exists, but the gap may be formed by an adhesive or the like that joins adjacent crystal pieces 11 together. The illustrated surface is a growth surface of the base substrate 10.

  FIG. 5 shows another example of a schematic plan view of the base substrate 10. The illustrated base substrate 10 is configured by arranging a plurality of crystal pieces 11 whose plane shape is a parallelogram in contact with each other (a gap may exist in part). The illustrated surface is a growth surface of the base substrate 10.

  The crystal piece 11 may be a fragment of a group III nitride semiconductor substrate, a fragment of a group III nitride semiconductor that has not grown to a desired size, or a group III nitride semiconductor having a predetermined shape. It may be one cut out from the substrate using a wire saw or the like, or may be one obtained by processing (polishing or the like) the small piece thus obtained to expose a desired surface. The plurality of crystal pieces 11 constituting one base substrate 10 are preferably made of the same group III nitride semiconductor.

  The plurality of crystal pieces 11 have exposed surfaces having substantially the same plane orientation (a slight deviation may exist). Then, the exposed surface is directed in substantially the same direction (there may be some deviation) to form a growth surface of the base substrate 10 (the surface shown in FIGS. 2, 4 and 5). Yes. The plurality of crystal pieces 11 are preferably arranged so that the directions of the crystals are aligned (so that the directions of arbitrary crystal axes are the same), but there may be some deviation.

  The crystal pieces 11 may be bonded to each other or may not be bonded. As the joining means, for example, (1) a method in which an adhesive such as a ceramic adhesive or a carbon adhesive is interposed between the joining surfaces of the crystal pieces 11, and (2) a metal (Au / Ti or the like) on the joining surface of the crystal pieces 11. ) In contact with another crystal piece 11 in a deposited state, and then heated and fused. (3) Activate the bonding surface of the crystal piece 11 by irradiating atoms and ions in a vacuum. And a method of bonding the activated bonding surfaces by bringing them into contact with each other, and (4) a method of forming a bonding layer straddling the plurality of crystal pieces 11 on a surface side different from the growth surface of the base substrate 10. However, it is not limited to these. In the case where the plurality of crystal pieces 11 are not joined together, the base substrate 10 is prepared by arranging the plurality of crystal pieces 11 side by side on a predetermined mounting table and fixing them with predetermined means as necessary.

  The planar shape, size, thickness, number, etc. of the plurality of crystal pieces 11 are not limited to those illustrated. The planar shapes of the plurality of crystal pieces 11 may be the same or may vary. Further, the thickness of the plurality of crystal pieces 11 may be the same or may vary. The thickness of the crystal piece 11 (thickness of the base substrate 10) is, for example, not less than 200 μm and not more than 2000 μm.

  The boundary portion 12 appears on the growth surface of the base substrate 10. A boundary line or a gap existing between the crystal pieces 11 becomes the boundary portion 12. In the base substrate 10 configured by arranging a plurality of crystal pieces 11, crystals are discontinuous at such a boundary portion 12.

Returning to FIG. 1, in the mask formation step S <b> 10, at least a part (for example, all) of the boundary portion 12 on the growth surface is covered on the growth surface of the base substrate 10 described above, and at least a portion where the boundary portion 12 does not exist. A mask for exposing a part is formed. For example, the mask includes a dielectric such as SiO ₂ or SiN. For example, the mask is made of a dielectric. When a part of the GaN surface is covered with such a dielectric mask, nucleation is not performed on the mask, but growth occurs only from the exposed GaN surface, and so-called ELO (Epitaxial Lateral Overgrowth) growth is performed.

  As means for forming a mask having such a pattern, in addition to a technique using photolithography, a technique described in the following embodiments can be used.

  FIG. 6 and FIG. 7 show an example of a schematic side view in which the mask 20 is formed on the base substrate 10. FIG. 6 corresponds to a state in which the mask 20 is formed on the base substrate 10 shown in FIGS. FIG. 7 corresponds to a state in which the mask 20 is formed on the base substrate 10 shown in FIG. In FIG. 7, the mask 20 does not exist in the gap between the crystal pieces 11, but a part of the mask 20 may enter the gap.

  The thickness of the mask 20 is, for example, 50 nm to 1000 nm, preferably 80 nm to 200 nm. The width L of the mask 20 is, for example, 1 μm or more and 500 μm or less, preferably 10 μm or more and 100 μm or less.

  When the mask 20 is configured in this way, the state in the vicinity of the boundary portion 12 of the base substrate 10 is not easily inherited by the group III nitride semiconductor grown from the exposed portion of the base substrate 10 in the following growth step S20. As a result, in the group III nitride semiconductor layer made of the group III nitride semiconductor, the occurrence of dislocations in the vicinity of the boundary portion 12 can be reduced. Further, the group III nitride semiconductor grown from the exposed portion of the base substrate 10 advances in the width direction of the mask 20 and collides with the group III nitride semiconductor grown from the opposite direction, and is bonded to each other. Propagation can be stopped. As a result, the number of dislocations on the exposed surface of the group III nitride semiconductor layer generated in the following growth step S20 can be reduced.

  The width H of the exposed portion of the base substrate 10 is, for example, 10 μm or more and 3000 μm or less, preferably 300 μm or more and 600 μm or less.

  Returning to FIG. 1, in the growth step S <b> 20 performed after the mask formation step S <b> 10, the group III nitride semiconductor is epitaxially grown from the exposed portion of the base substrate 10. The group III nitride semiconductor grown from the exposed portion proceeds on the mask 20 in the lateral direction and continues to grow, and joins with the group III nitride semiconductor grown from the other direction. In this way, a continuous group III nitride semiconductor layer is formed on the base substrate 10. The group III nitride semiconductor grown in this process is GaN.

  Specific examples of the epitaxial growth are not particularly limited, and MOVPE (Metal Organic Vapor Phase Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), MBE (Molecular Beam Epitaxy), LPE (Liquid Phase Epitaxy) and the like can be used.

  Here, an example of epitaxially growing GaN with the hydride vapor phase epitaxy (HVPE) apparatus 100 will be described with reference to FIG.

  The illustrated HVPE apparatus 100 includes a reaction tube 121 and a substrate holder 123 provided in the reaction tube 121. The substrate holder 123 holds the base substrate 141 (the base substrate 10 described above). The HVPE apparatus 100 includes a group III source gas supply unit 139 that supplies a group III source gas into the reaction tube 121 and a nitrogen source gas supply unit 137 that supplies a nitrogen source gas into the reaction tube 121. Further, the HVPE apparatus 100 includes a gas exhaust pipe 135 and heaters 129 and 130.

  The substrate holder 123 is rotatably provided on the downstream side of the reaction tube 121 by a rotation shaft 132. The gas discharge pipe 135 is provided on the downstream side of the substrate holder 123 in the reaction pipe 121.

  The group III source gas supply unit 139 includes a gas supply pipe 126, a source boat 128, a group III (Ga) source 127, and a layer below the shielding plate 136 among the reaction tubes 121.

  The nitrogen source gas supply unit 137 includes a gas supply pipe 124 and a layer on the shielding plate 136 in the reaction pipe 121.

  The group III source gas supply unit 139 generates a halide of group III atoms (for example, GaCl) and supplies it to the surface of the base substrate 141 held by the substrate holder 123.

  The supply port of the gas supply pipe 126 is arranged on the upstream side in the group III source gas supply unit 139. For this reason, the supplied hydrogen halide gas (for example, HCl gas) comes into contact with the group III source material 127 in the source boat 128 in the group III source gas supply unit 139.

  Thereby, the halogen-containing gas supplied from the gas supply pipe 126 comes into contact with the surface of the group III raw material 127 in the source boat 128 or the volatilized group III molecule, and the group III molecule is halogenated to form a group III halide. A Group III source gas is produced. A heater 129 is disposed around the group III source gas supply unit 139, and the inside of the group III source gas supply unit 139 is maintained at a temperature of about 800 to 900 ° C., for example.

  The upstream side of the reaction tube 121 is divided into two layers by a shielding plate 136. Ammonia supplied from the gas supply pipe 124 passes through the nitrogen source gas supply unit 137 located on the upper side of the shielding plate 136 in the drawing, and decomposition is accelerated by heat. A heater 129 is disposed around the nitrogen source gas supply unit 137, and the nitrogen source gas supply unit 137 is maintained at a temperature of about 800 to 900 ° C., for example.

  In the growth region 122 located on the right side in the figure, the base substrate 141 held by the substrate holder 123 is disposed, and a group III nitride semiconductor such as GaN is grown in the growth region 122. A heater 130 is disposed around the growth region 122, and the inside of the growth region 122 is maintained at a temperature of about 1000 ° C. to 1050 ° C., for example.

  Hereinafter, an example of the growth conditions is shown.

Temperature of the growth region 122: 1040 ° C.
Temperature of group III source gas supply unit 139: 850 ° C.
HCL gas flow rate of group III source gas supply unit 139: 50 cc / min until crystal association on mask, 200 cc / min after association
Ammonia gas flow rate of the nitrogen source gas supply unit 137: 2000 cc / min
Carrier gas: H ₂
Total gas flow: 10L / min

  Here, FIG. 9 and FIG. 10 show an example of a schematic side view of a state in which the group III nitride semiconductor layer 30 is generated over the mask 20 on the base substrate 10. In the present embodiment, as shown in FIGS. 9 and 10, the stacked body in which the group III nitride semiconductor layer 30 is generated on the base substrate 10 through the mask 20 can be used as a self-supporting substrate. In addition, the group III nitride semiconductor layer 30 obtained by removing the base substrate 10 and the mask 20 from the stacked body by polishing or the like can be used as a free-standing substrate. Moreover, a part can be cut out from the group III nitride semiconductor layer 30 included in the stacked body to form a self-supporting substrate.

  In the present embodiment described above, a group III nitride semiconductor crystal is grown from each crystal piece by growing a group III nitride semiconductor crystal on a base substrate in which group III nitride semiconductor crystal pieces are arranged close to each other. The method for obtaining a joined group of group III nitride semiconductor crystals by joining together has a feature that a group III nitride semiconductor crystal is grown on a base substrate in a state where the boundary between crystal pieces is covered with a mask.

  Since the crystal becomes discontinuous at the boundary portion of the base substrate, defects are likely to occur in the group III nitride semiconductor crystal epitaxially grown thereon. According to the present embodiment in which a group III nitride semiconductor crystal is epitaxially grown on a base substrate with the boundary between crystal pieces covered with a mask, the state near the boundary of the base substrate is epitaxially grown on the base substrate. It becomes difficult for the group III nitride semiconductor crystal to inherit. As a result, generation of dislocations in the group III nitride semiconductor crystal can be suppressed. As a result, the number of dislocations on the surface of the layer made of the group III nitride semiconductor crystal can be suppressed.

  In addition, the group III nitride semiconductor grown from the exposed portion of the base substrate advances in the width direction of the mask and collides with the group III nitride semiconductor grown from the opposite direction, and joins each other. Can be stopped. As a result, the number of dislocations on the exposed surface of the group III nitride semiconductor layer generated on the base substrate can be reduced.

<Second Embodiment>
This embodiment is different from the first embodiment in that the mask 20 is formed without using photolithography. Details will be described below.

  FIG. 11 is a flowchart showing an example of a processing flow of the method for manufacturing a self-supporting substrate of the present embodiment. As shown in the figure, the method for manufacturing a self-supporting substrate of this embodiment includes a preparation step S1, a mask formation step S10, and a growth step S20. The mask forming step S10 includes a first step S1 and a second step S12.

  In the preparation step S1, the base substrate 10 is prepared. The base substrate 10 is configured by arranging a plurality of group III nitride semiconductor crystal pieces 11. The base substrate 10 prepared in this step has a recess and a protrusion on the growth surface (first surface), and the boundary portion 12 between adjacent crystal pieces 11 on the growth surface is located at the bottom of the recess. To do. Hereinafter, an example of the preparation step S1 will be described.

  First, as shown in FIGS. 12 and 13, a plurality of crystal pieces 11 are cut out from a group III nitride semiconductor crystal having a {0001} plane as an exposed surface. The cutting method is not particularly limited, and the crystal piece 11 may be cut using a band saw, an inner peripheral blade, an outer peripheral blade, or the like, or may be cut by cleaving on a cleavage plane.

  The group III nitride semiconductor crystal from which the crystal piece 11 is cut has, for example, a substantially circular planar shape and a thickness D1. The exposed surface of the group III nitride semiconductor crystal may be a surface other than the {0001} plane. The planar shape of the group III nitride semiconductor crystal may be other shapes.

  A plurality of crystal pieces 11 extending in the m-axis direction are cut out in stripes from such a group III nitride semiconductor crystal. The cut surface is parallel to the [0001] direction (c-axis direction) and the m-axis direction. The angle α1 formed by the cut surface and the {0001} plane is 90 °. Α1 may be an angle different from 90 °. By appropriately adjusting α1, a desired surface can be exposed to the cut surface.

  Next, the plurality of crystal pieces 11 obtained in this way are joined side by side with at least a part of predetermined surfaces in contact with each other as shown in FIG. For joining the crystal pieces 11, for example, the + c plane and the −c plane may be brought into contact with each other, or the cut surfaces when the crystal pieces 11 are cut out may be brought into contact with each other.

  As the means for joining the crystal pieces 11, (1) a method of interposing an adhesive such as a ceramic adhesive or a carbon adhesive at the interface between the crystal pieces 11, and (2) a metal (Au / Au) on the joint surface of the crystal pieces 11 A method in which the crystal pieces 11 are brought into contact with each other in a state in which Ti or the like is vapor-deposited, and then heated and fused. (3) The bonding surface of the crystal pieces 11 is activated by irradiation with atoms and ions in a vacuum. (4) A method in which a plurality of crystal pieces 11 are overlapped so that at least a part of each of the bonding surfaces face each other, and then the side surfaces are joined. A method of fixing the plurality of crystal pieces 11 by adhering them to each other by applying an adhesive or the like to the surface is conceivable, but is not limited thereto.

  As shown in FIG. 14, the plurality of crystal pieces 11 are joined to each other in a state in which the joining surfaces in contact with each other are inclined by a predetermined angle β. For example, as shown in the figure, the joining is realized by using a table 40. The base 40 is installed in a state where the bottom surface 41 is in contact with a predetermined horizontal installation surface 50. The base 40 has a slope 42 whose angle formed with the bottom surface 41 is β. As shown in the drawing, the above-described joining is realized by joining a plurality of crystal pieces 11 to each other while leaning against the inclined surface 42 of the table 40. In the present embodiment, the bonded body in the state shown in FIG. In addition, the side surface and the back surface (surface opposite to the growth surface) of the base substrate 10 may be polished to perform planarization, shape adjustment, or the like.

  By appropriately adjusting the angles α1 and β when cutting the crystal piece 11 from the group III nitride semiconductor crystal, the desired axial direction of each of the plurality of crystal pieces 11 is changed to the thickness direction of the base substrate 10 ( (Normal direction). The desired axial direction is, for example, the [hk− (h + k) l] direction (h, k, and l are integers), or the [hk− (h + k) l] direction at a predetermined angle (eg, within ± 10 °). The direction is tilted.

  In addition, as shown in FIG. 14, the base substrate 10 obtained in this way has a recessed part and a convex part in a growth surface (upper surface in the figure), and the boundary part 12 is located in the bottom of a concave part. It will be.

Returning to FIG. 11, in the first step S <b> 11, an insulating layer that covers the growth surface (first surface) is formed on the base substrate 10. FIG. 15 is a schematic side view of a part of the base substrate 10 extracted. In this step, an insulating layer 21 is formed on the growth surface of the base substrate 10 as shown in FIG. Insulating layer 21 is, for example, SiO _2.

  Returning to FIG. 11, in the second step S12, by removing a part from the exposed surface side of the insulating layer 21 by polishing or etching, the insulating layer 21 remains at the bottom of the recess, and the bottom of the recess is removed. A state in which the base substrate 10 is exposed at a portion is formed.

  Polishing can employ means such as grinding, lapping, and CMP. Etching can be wet etching or dry etching.

  When a part is removed from the exposed surface side of the insulating layer 21 by polishing, a part is also removed from the top side of the convex portion of the base substrate 10 by the polishing, and a flat surface is exposed at the top portion of the convex portion. On the other hand, when a part is removed from the exposed surface side of the insulating layer 21 by etching, after the insulating layer 21 remains at the bottom of the concave portion and the convex portion is exposed, a polishing process is performed. By this polishing, a part is removed from the top side of the convex portion of the base substrate 10, and a flat surface is exposed at the top portion of the convex portion.

  As described above, by appropriately adjusting the angles α1 and β when cutting the crystal piece 11 from the group III nitride semiconductor crystal, a desired axial direction of each of the plurality of crystal pieces 11 (eg, [hk− (H + k) l] direction) is parallel to the thickness direction (normal direction) of the base substrate 10. By removing a part from the top side of the convex portion of the base substrate 10 with such a polishing surface substantially perpendicular to the thickness direction of the base substrate 10, the flat surface exposed at the top portion of the convex portion is changed to a desired surface. can do. The desired plane is, for example, a {hk- (h + k) l} plane or a plane tilted from the {hk- (h + k) l} plane by a predetermined angle (eg, within ± 10 °).

  FIG. 17 shows the state of the base substrate 10 after the second step S12. In the case of this embodiment, the insulating layer 21 remaining on the bottom of the recess after the second step S <b> 12 becomes the mask 20. The mask 20 is located on the growth surface (first surface) of the base substrate 10 formed by arranging a plurality of group III nitride semiconductor crystal pieces 11, and a boundary portion 12 between adjacent crystal pieces 11 on the growth surface. The portion where the boundary portion 12 does not exist is exposed.

  The width L of the mask 20 (the width in the direction perpendicular to the drawing direction of the crystal piece 11 (the direction perpendicular to the paper surface in the drawing)) is, for example, 1 μm or more and 500 μm or less, preferably 10 μm or more and 100 μm or less. A width H in the same direction between the masks 20 is, for example, 10 μm or more and 3000 μm or less, preferably 300 μm or more and 600 μm or less. The depth of the mask 20 (distance from the deepest part to the exposed surface) is, for example, not less than 50 nm and not more than 1000 nm. When the mask 20 is configured in this way, the same effects as those of the first embodiment are realized.

  Returning to FIG. 11, a growth step S20 is performed thereafter. In the growth step S20, a group III nitride semiconductor is grown from the flat surface exposed at the top of the convex portion. Details of the growth step S20 are the same as those in the first embodiment, and a description thereof will be omitted here. FIG. 18 shows the state of the base substrate 10 after the growth step S20.

  According to the present embodiment described above, the same operational effects as those of the first embodiment can be realized. Further, according to the present embodiment, it is possible to form a mask that covers a desired position of the base substrate without using photolithography. According to the present embodiment as described above, the cost can be reduced to the extent that photolithography can be omitted. In addition, effects such as simplification of the manufacturing process and improvement of manufacturing efficiency are realized.

  According to the first and second embodiments described above, the following substrates (the base substrate 10 on which the mask 20 is formed and the free-standing substrate on which the group III nitride semiconductor layer 30 is formed on the base substrate 10) Explanation is made.

A base substrate configured by arranging a plurality of group III nitride semiconductor crystal pieces;
A mask positioned on the first surface of the base substrate, covering a boundary portion between the adjacent crystal pieces on the first surface, exposing a portion where the boundary portion does not exist, and including an insulating layer When,
Having a substrate.

In the above substrate,
The first surface has a concave portion and a convex portion,
The boundary is located at the bottom of the recess;
The mask is a substrate that exists at the bottom of the recess and does not exist at a portion other than the bottom of the recess.

In the above substrate,
The top of the convex part is a flat surface,
The flat surface is a {hk- (h + k) l} surface (h, k and l are integers) or a surface obtained by inclining the {hk- (h + k) l} surface by a predetermined angle (within ± 10 °). substrate.

The above substrate;
A group III nitride semiconductor layer located on the substrate;
Having a free-standing substrate.

Hereinafter, examples of the reference form will be added.
1. A portion where a boundary portion between adjacent crystal pieces on the first surface is covered on a first surface of a base substrate formed by arranging a plurality of group III nitride semiconductor crystal pieces and the boundary portion does not exist And forming a mask including an insulating layer, and exposing a mask,
After the mask formation step, grow a group III nitride semiconductor from the exposed portion of the base substrate, and a growth step of forming a group III nitride semiconductor layer,
A method for manufacturing a self-supporting substrate.
2. In the manufacturing method of the self-supporting substrate according to 1,
Before the mask formation step, the first surface further includes a preparation step of preparing the base substrate having a concave portion and a convex portion, and the boundary portion positioned at the bottom of the concave portion,
The mask forming step includes
A first step of forming an insulating layer covering the first surface on the base substrate;
After the first step, by removing a part from the exposed surface side of the insulating layer by polishing or etching, the insulating layer remains at the bottom of the recess, and the portion excluding the bottom of the recess A second step of forming a state in which the base substrate is exposed;
A method for manufacturing a self-supporting substrate.
3. In the manufacturing method of the self-supporting substrate according to 2,
In the second step, a part of the insulating layer is removed from the exposed surface side by polishing, and a part is removed from the top side of the convex portion by the polishing to expose a flat surface.
4). In the manufacturing method of the self-supporting substrate according to 2,
In the second step, the exposed surface of the insulating layer is etched to form a state where the insulating layer remains at the bottom of the concave portion and the convex portion is exposed, and then the convex portion is polished by polishing. A method for manufacturing a self-supporting substrate in which a flat surface is exposed by removing a part from the top side.
5. In the method for manufacturing a self-supporting substrate according to 3 or 4,
The plurality of crystal pieces of the base substrate have a [hk− (h + k) l] direction (h, k, and l are integers) or a direction in which the [hk− (h + k) l] direction is inclined by a predetermined angle. Arranged so as to be parallel to the thickness direction of the base substrate,
When a part is removed from the top side of the convex part in the second step, the {hk− (h + k) l} surface or the {hk− (h + k) l} surface is inclined by a predetermined angle as the flat surface. A method for manufacturing a self-supporting substrate with exposed surfaces.
6). In the method for manufacturing a self-supporting substrate according to any one of 3 to 5,
In the growth step, a method for manufacturing a free-standing substrate in which a group III nitride semiconductor is grown from the flat surface.
7). A base substrate configured by arranging a plurality of group III nitride semiconductor crystal pieces;
A mask located on the first surface of the base substrate, covering a boundary portion between adjacent crystal pieces on the first surface, exposing a portion where the boundary portion does not exist, and including an insulating layer When,
Having a substrate.
8). In the substrate according to 7,
The first surface has a concave portion and a convex portion,
The boundary is located at the bottom of the recess;
The mask is a substrate that exists at the bottom of the recess and does not exist at a portion other than the bottom of the recess.
9. 8. The substrate according to 8,
The convex part has a flat top at the top,
The flat surface is a {hk- (h + k) l} plane (h, k, and l are integers), or a substrate obtained by tilting the {hk- (h + k) l} plane by a predetermined angle.
10. A substrate according to any one of 7 to 9,
A group III nitride semiconductor layer located on the substrate;
Having a free-standing substrate.

DESCRIPTION OF SYMBOLS 10 Base substrate 11 Crystal piece 12 Boundary part 20 Mask 30 Group III nitride semiconductor layer 40 Stand 41 Bottom 42 Slope 50 Installation surface 100 HVPE apparatus 121 Reaction tube 122 Growth region 123 Substrate holder 124 Gas supply pipe 125 Pipe 126 Gas supply pipe 127 Group III raw material 128 Source boat 129 Heater 130 Heater 132 Rotating shaft 135 Gas exhaust pipe 136 Shielding plate 137 Nitrogen raw material gas supply part 139 Group III raw material gas supply part 141 Base substrate

Claims (10)

A portion where a boundary portion between adjacent crystal pieces on the first surface is covered on a first surface of a base substrate formed by arranging a plurality of group III nitride semiconductor crystal pieces and the boundary portion does not exist And forming a mask including an insulating layer, and exposing a mask,
After the mask formation step, grow a group III nitride semiconductor from the exposed portion of the base substrate, and a growth step of forming a group III nitride semiconductor layer,
A method for manufacturing a self-supporting substrate. In the manufacturing method of the self-supporting substrate according to claim 1,
Before the mask formation step, the first surface further includes a preparation step of preparing the base substrate having a concave portion and a convex portion, and the boundary portion positioned at the bottom of the concave portion,
The mask forming step includes
A first step of forming an insulating layer covering the first surface on the base substrate;
After the first step, by removing a part from the exposed surface side of the insulating layer by polishing or etching, the insulating layer remains at the bottom of the recess, and the portion excluding the bottom of the recess A second step of forming a state in which the base substrate is exposed;
A method for manufacturing a self-supporting substrate. In the manufacturing method of the self-supporting substrate according to claim 2,
In the second step, a part of the insulating layer is removed from the exposed surface side by polishing, and a part is removed from the top side of the convex portion by the polishing to expose a flat surface. In the manufacturing method of the self-supporting substrate according to claim 2,
In the second step, the exposed surface of the insulating layer is etched to form a state where the insulating layer remains at the bottom of the concave portion and the convex portion is exposed, and then the convex portion is polished by polishing. A method for manufacturing a self-supporting substrate in which a flat surface is exposed by removing a part from the top side. In the manufacturing method of the self-supporting substrate according to claim 3 or 4,
The plurality of crystal pieces of the base substrate have a [hk− (h + k) l] direction (h, k, and l are integers) or a direction in which the [hk− (h + k) l] direction is inclined by a predetermined angle. Arranged so as to be parallel to the thickness direction of the base substrate,
When a part is removed from the top side of the convex part in the second step, the {hk− (h + k) l} surface or the {hk− (h + k) l} surface is inclined by a predetermined angle as the flat surface. A method for manufacturing a self-supporting substrate with exposed surfaces. In the manufacturing method of the self-supporting substrate according to any one of claims 3 to 5,
In the growth step, a method for manufacturing a free-standing substrate in which a group III nitride semiconductor is grown from the flat surface. A base substrate configured by arranging a plurality of group III nitride semiconductor crystal pieces;
A mask located on the first surface of the base substrate, covering a boundary portion between adjacent crystal pieces on the first surface, exposing a portion where the boundary portion does not exist, and including an insulating layer When,
Having a substrate. The substrate according to claim 7, wherein
The first surface has a concave portion and a convex portion,
The boundary is located at the bottom of the recess;
The mask is a substrate that exists at the bottom of the recess and does not exist at a portion other than the bottom of the recess. The substrate according to claim 8, wherein
The convex part has a flat top at the top,
The flat surface is a {hk- (h + k) l} plane (h, k, and l are integers), or a substrate obtained by tilting the {hk- (h + k) l} plane by a predetermined angle. A substrate according to any one of claims 7 to 9,
A group III nitride semiconductor layer located on the substrate;
Having a free-standing substrate.

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