JP2016154174A - Silicon carbide semiconductor device and silicon carbide semiconductor device manufacturing method - Google Patents

Abstract

The present invention relates to a silicon carbide semiconductor device including an ohmic electrode having a stable low resistance for a p-type silicon carbide semiconductor layer, and a method for manufacturing the same. A silicon carbide semiconductor device includes a p-type silicon carbide epitaxial layer included in a p-type silicon carbide semiconductor layer, and an ohmic electrode. Ohmic electrode 200 is formed in ohmic contact on the surface of p-type silicon carbide epitaxial layer 11. In addition, ohmic electrode 200 is formed in contact with p-type silicon carbide epitaxial layer 11, formed in contact with silicon alloy layer 200 c containing aluminum and silicon, silicon alloy layer 200 c, and aluminum. A titanium alloy layer 200d containing titanium. [Selection] Figure 3

Description

  The present technology relates to a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device.

  A silicon carbide semiconductor device has an excellent material property of silicon carbide (hereinafter may be referred to as SiC), and the resistance value during operation of the semiconductor device is determined when silicon (hereinafter may be referred to as Si) semiconductor device. Since it can be made lower than the resistance value, it has attracted attention. At present, in the field of silicon carbide semiconductor devices, development of semiconductor devices for high voltage applications using silicon carbide is underway.

  As a configuration of a semiconductor device for high withstand voltage, there is, for example, an insulated gate bipolar transistor (ie, IGBT). The basic structure of the n-type channel IGBT has a field-effect transistor (metal-effect transistor, or MOSFET) structure on the first main surface of the semiconductor substrate, and is on the opposite side of the first main surface. The second main surface, which is a surface, has a p-type collector.

  When an n-type channel IGBT is manufactured using a silicon carbide semiconductor substrate, a MOSFET structure is formed on the first main surface of the n-type silicon carbide epitaxial layer manufactured by epitaxial growth, and on the second main surface of the n-type silicon carbide epitaxial layer. A p-type silicon carbide layer is formed, and an ohmic electrode is formed on the surface of the p-type silicon carbide layer opposite to the surface in contact with the n-type silicon carbide epitaxial layer. In order to produce a low-resistance n-type channel IGBT, it is necessary to form a low-resistance ohmic electrode on the p-type silicon carbide layer.

  A method for forming an ohmic electrode having a low resistance with respect to a p-type silicon carbide semiconductor substrate is disclosed in Non-Patent Document 1, for example. Further, a method for forming an ohmic electrode using laser annealing is disclosed in Patent Document 1, for example.

  According to the disclosure of Non-Patent Document 1, an alloy layer of aluminum (hereinafter sometimes referred to as Al) and titanium (hereinafter sometimes referred to as Ti) is formed on a p-type silicon carbide semiconductor substrate. Thereafter, lamp annealing is performed to obtain a low-resistance ohmic electrode.

  According to the disclosure of Patent Document 1, a metal film is formed in the order of titanium and aluminum on a p-type silicon carbide semiconductor substrate, and then the metal film is irradiated with laser light to heat the metal film. . Thereby, these alloy layers are formed at the interface between the metal film and the silicon carbide semiconductor substrate. Since the alloy layer is superior in ohmic property compared to the silicon carbide semiconductor substrate, the alloy layer is shown to be an ohmic electrode.

JP 2014-063948 A

J. et al. Crafton, S.M. E. Mohney, J.M. R. Williams, T.W. Isaacs-Smith, “Finding the optimal Al-Ti alloy composition for use as an ohmic contact to p-type SiC,” 18 May 2001, Solid-State Electros. 46 (2002) pp 109-113

  In order to form an ohmic electrode having a low resistance with respect to the p-type silicon carbide semiconductor layer, it is effective to use a metal layer made of aluminum and titanium, as can be seen from the disclosure of Non-Patent Document 1. Therefore, after forming a laminated film of titanium and aluminum in this order on the p-type silicon carbide semiconductor layer, laser annealing was performed to try to form an ohmic electrode. However, as a result, a low-resistance ohmic electrode could not be stably obtained.

  The present technology is intended to solve the above-described problem, and a silicon carbide semiconductor device including an ohmic electrode having a stable low resistance with respect to a p-type silicon carbide semiconductor layer and a method for manufacturing the silicon carbide semiconductor device It is about.

  A silicon carbide semiconductor device according to an aspect of the present technology includes a p-type silicon carbide semiconductor layer and an ohmic electrode formed in ohmic contact with the surface of the silicon carbide semiconductor layer, and the ohmic electrode includes the carbonized semiconductor device. A silicon alloy layer formed in contact with the silicon semiconductor layer and including aluminum and silicon, and a titanium alloy layer formed in contact with the silicon alloy layer and including aluminum and titanium.

  A method for manufacturing a silicon carbide semiconductor device according to an aspect of the present technology includes forming a p-type silicon carbide semiconductor layer, forming an aluminum layer on a surface of the silicon carbide semiconductor layer, and forming a titanium layer on the surface of the aluminum layer. And a silicon alloy layer containing aluminum and silicon, and a titanium alloy layer containing aluminum and titanium, in contact with the silicon carbide semiconductor layer, and in contact with the silicon carbide semiconductor layer. Form.

  A silicon carbide semiconductor device according to an aspect of the present technology includes a p-type silicon carbide semiconductor layer and an ohmic electrode formed in ohmic contact with the surface of the silicon carbide semiconductor layer, and the ohmic electrode includes the carbonized semiconductor device. A silicon alloy layer formed in contact with the silicon semiconductor layer and including aluminum and silicon, and a titanium alloy layer formed in contact with the silicon alloy layer and including aluminum and titanium.

  According to such a configuration, since the ohmic electrode includes the silicon alloy layer containing aluminum and silicon and the titanium alloy layer containing aluminum and titanium, the resistance of the ohmic electrode can be reduced.

  A method for manufacturing a silicon carbide semiconductor device according to an aspect of the present technology includes forming a p-type silicon carbide semiconductor layer, forming an aluminum layer on a surface of the silicon carbide semiconductor layer, and forming a titanium layer on the surface of the aluminum layer. And a silicon alloy layer containing aluminum and silicon, and a titanium alloy layer containing aluminum and titanium, in contact with the silicon carbide semiconductor layer, and in contact with the silicon carbide semiconductor layer. Form.

  According to such a configuration, when the silicon alloy layer and the titanium alloy layer are formed by annealing, the layer located on the side opposite to the side in contact with the p-type silicon carbide semiconductor layer has a high melting point. Therefore, the ablation accompanying the temperature rise can be suppressed, and the composition of the ohmic electrode to be formed does not vary greatly. Therefore, an ohmic electrode having a low resistance can be stably formed on the p-type silicon carbide semiconductor layer.

  Objects, features, aspects, and advantages of the present technology will become more apparent from the following detailed description and the accompanying drawings.

It is a schematic diagram when the silicon carbide semiconductor device according to the embodiment is viewed from above. It is a schematic diagram when the silicon carbide semiconductor device according to the embodiment is viewed from above. It is a figure which shows the A-A 'cross-section structure and B-B' cross-section structure of FIG. 1 and FIG. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming a silicon carbide base | substrate especially. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a process of forming a JTE region. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming a base region. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming a source region. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming a field oxide film and a gate insulating film. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming a gate electrode. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming an interlayer insulating film. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming an opening in an interlayer insulating film and a step of forming a source electrode. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a process of forming a wiring electrode and an insulating film on the wiring electrode. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of removing a silicon carbide semiconductor substrate and exposing a p-type silicon carbide epitaxial layer. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of depositing an aluminum electrode layer and a titanium electrode layer. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming an ohmic electrode especially by irradiating a laser beam. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming a back surface electrode especially. It is a figure which shows the cross-section transmission electron microscope image (cross-section TEM image) of the ohmic electrode produced using the Al / Ti metal film. It is a figure which shows the atomic concentration calculated from energy dispersive x-ray spectroscopy (EDS) acquired in each position in FIG. It is a figure which shows the cross-sectional TEM image in the area | region different from the area | region shown by FIG. 17 of the ohmic electrode formed by laser annealing. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming a silicon carbide base | substrate especially. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming a silicon carbide base | substrate especially. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a process of forming a mesa structure. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming a termination region. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a step of forming an oxide film. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming an ohmic electrode especially. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. It is a figure which shows the process of forming a back surface ohmic electrode especially. It is a figure which shows typically the cross section of an active region and the cross section of a termination | terminus area | region in each manufacturing process of the silicon carbide semiconductor device regarding embodiment. In particular, it is a diagram showing a process of forming a wiring electrode, an insulating film and a back electrode.

  Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that the drawings are schematically shown, and the mutual relationship between the sizes and positions of the images shown in different drawings is not necessarily described accurately, and can be changed as appropriate. Moreover, in the following description, the same code | symbol is attached | subjected and shown in the same component, and those names and functions are also the same. Therefore, the detailed description about them may be omitted.

  In the following description, terms that mean a specific position and direction such as “top”, “bottom”, “side”, “bottom”, “front” or “back” may be used. Is used for convenience in order to facilitate understanding of the contents of the embodiment, and is not related to the direction in which it is actually implemented.

<First Embodiment>
<Configuration>
Hereinafter, the configuration of the silicon carbide semiconductor device and the method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described.

  After forming a laminated film of titanium and aluminum in this order on the p-type silicon carbide semiconductor layer, laser annealing was performed, and when an ohmic electrode was formed, a low-resistance ohmic electrode could not be stably obtained. .

  When the composition of the formed ohmic electrode was analyzed in order to investigate this cause, the composition ratio of aluminum in the ohmic electrode was not stable, and this was the reason why the low resistance ohmic electrode was not obtained with good reproducibility It turns out that.

  The cause of the above phenomenon is that the temperature rises to about several thousand degrees Celsius in a short time on the order of nanoseconds because high energy is locally applied in the region irradiated with laser light. Can be considered. Since the boiling point of aluminum existing on the outermost surface of the metal layer irradiated with laser light is 2519 degrees, ablation occurs in the aluminum by the laser light, and it is considered that the aluminum composition ratio in the ohmic electrode has changed.

  1 and 2 are schematic views of the silicon carbide semiconductor device according to the present embodiment as viewed from above. FIG. 3 is a diagram showing the A-A ′ cross-sectional structure and the B-B ′ cross-sectional structure of FIGS. 1 and 2.

  The structure of the silicon carbide semiconductor device shown in FIG. 1, FIG. 2 and FIG. 3 is common to the following embodiments, but the ion implantation region, the structure of the field oxide film, the structure of the interlayer insulating film, etc. It is not restricted to what was shown by the figure, A different structure may be sufficient. In each of the following embodiments, a planar gate structure is described. However, the present invention is not limited to this, and a trench gate structure may be used.

  In the upper structure of the silicon carbide semiconductor device shown in FIGS. 1 and 2, wiring electrode 300a is formed at the center. A plurality of unit cells, which are MOSFET unit structures, are arranged below the wiring electrode 300a, and the wiring electrode 300a is electrically connected to a source electrode (not shown here) of each unit cell. .

  As shown in FIG. 2, an interlayer insulating film 80 is formed on the outer periphery of the wiring electrode 300 a, and further, a wiring electrode 300 b is formed on the outer periphery of the interlayer insulating film 80. The wiring electrode 300b is connected to the gate electrode (not shown here) of each unit cell, and the gate voltage is supplied through the wiring electrode 300b. An interlayer insulating film 80 is formed on the outer periphery of the wiring electrode 300b with a certain distance from the dicing line 1000.

  As shown in FIG. 1, an insulating film 400 for improving the breakdown voltage is formed on the upper portion of the structure shown in FIG. 2 except for the wiring electrode 300a and a part of the wiring electrode 300b. The insulating film 400 is a film made of polyimide, for example.

  Next, a silicon carbide substrate and the like in the A-A ′ sectional structure and the B-B ′ sectional structure of FIGS. 1 and 2 shown in FIG. 3 will be described.

  In FIG. 3, surface 11a as a main surface has a 4 ° or 8 ° off-angle from the (0001) plane and is the surface of p-type silicon carbide epitaxial layer 11 having a 4H polytype. An n-type silicon carbide epitaxial layer 12 having an off angle of 4 ° or 8 ° from the (0001) plane and having a 4H polytype is formed on the surface 11a. In some cases, p-type silicon carbide epitaxial layer 11 and n-type silicon carbide epitaxial layer 12 are collectively referred to as silicon carbide epitaxial substrate 13.

The thickness of n-type silicon carbide epitaxial layer 12 and the concentration of n-type silicon carbide epitaxial layer 12 depend on the breakdown voltage required for the semiconductor device. For example, the thickness of n-type silicon carbide epitaxial layer 12 is about 10 μm or more and 200 μm. The concentration of the n-type silicon carbide epitaxial layer 12 is in the range of about 1 × 10 ¹⁴ cm ^{−3 to} about 1 × 10 ¹⁷ cm ⁻³ . If the required pressure resistance is changed, it may deviate from the above range.

The thickness of the p-type silicon carbide epitaxial layer 11 is, for example, in the range of about 10 μm to about 100 μm, and the concentration of the p-type silicon carbide epitaxial layer 11 is, for example, about 5 × 10 ¹⁷ cm ⁻³ to 1 × 10 ^21. The range is about cm ⁻³ or less.

  The thickness of the silicon carbide epitaxial substrate 13 composed of the n-type silicon carbide epitaxial layer and the p-type silicon carbide epitaxial layer depends on the breakdown voltage required for the semiconductor device, but is, for example, about 200 μm or less. The epitaxial substrate 13 is thinned.

  Next, the MOSFET structure of the silicon carbide semiconductor device taken along the line B-B ′ in FIGS. 1 and 2 will be described with reference to FIG. 3.

  In the surface layer of n-type silicon carbide epitaxial layer 12, a plurality of base regions 30 containing aluminum as a p-type impurity are formed apart from each other by a certain width. A plurality of source regions 40 containing nitrogen (hereinafter sometimes referred to as N) as n-type impurities are formed on the surface layer of each base region 30 so as to be separated by a certain width. The source region 40 is formed in a region shallower than the base region 30.

A gate electrode 70 is formed on base region 30 sandwiched between source region 40 and n-type silicon carbide epitaxial layer 12 with gate insulating film 60 interposed therebetween. Gate insulating film 60 and gate electrode 70 are formed over the surface of n-type silicon carbide epitaxial layer 12. The gate insulating film 60 is made of, for example, silicon dioxide (SiO ₂ ).

  An interlayer insulating film 80 is formed to cover the gate electrode 70. A source electrode 100 that is in ohmic contact with the surface is formed on the surface of the base region 30 where the gate insulating film 60 is not formed and on the surface of the source region 40. Further, a wiring electrode 300 a is formed so as to cover the source electrode 100 and the interlayer insulating film 80.

  Next, the termination structure of the silicon carbide semiconductor device taken along the line A-A ′ in FIGS. 1 and 2 will be described with reference to FIG. 3.

  The surface layer of n-type silicon carbide epitaxial layer 12 is provided with a base region 30 containing aluminum as a p-type impurity and an ion implantation region containing aluminum as a p-type impurity in order to maintain a breakdown voltage. Hereinafter, this ion implantation region will be described as a junction termination extension (JTE) region 20. The JTE region 20 is formed in a region different from the base region 30.

  Field oxide film 50 is formed on the surface of n-type silicon carbide epitaxial layer 12 including the surface of base region 30 and the surface of JTE region 20. On the field oxide film 50, a gate electrode 70 is partially formed. An interlayer insulating film 80 is deposited so as to cover the field oxide film 50 and the gate electrode 70. However, in a part on the gate electrode 70, the interlayer insulating film 80 is not formed but an opening is formed. Further, a wiring electrode 300b is formed so as to cover the interlayer insulating film 80 and the gate electrode 70 in the opening. The wiring electrode 300b is electrically connected to the gate electrode 70. Further, an insulating film 400 is formed to cover the wiring electrode 300b and to maintain the withstand voltage.

  Finally, the structure of ohmic electrode 200 on the opposite surface, ie, the back surface, which is the surface opposite to the surface of silicon carbide epitaxial substrate 13 will be described with reference to FIG.

  In the ohmic electrode 200, a silicon alloy layer 200c containing aluminum is deposited on the back surface of the p-type silicon carbide epitaxial layer 11, and a titanium alloy layer 200d containing aluminum is further deposited on the silicon alloy layer 200c. It is formed. However, a part of the ohmic electrode 200 may not be formed with only the silicon alloy layer 200c on the p-type silicon carbide epitaxial layer 11 and the titanium alloy layer 200d. A back electrode 500 is formed on the back surface of the ohmic electrode 200.

<Manufacturing method>
Then, the manufacturing method of the silicon carbide semiconductor device shown by FIGS. 1-3 is demonstrated in order, referring FIGS. 4-16.

  4 to 16 are diagrams schematically showing a cross section of the active region and a cross section of the termination region in each manufacturing process of the silicon carbide semiconductor device according to the present embodiment.

As shown in FIG. 4, the surface orientation of the surface is off by 4 ° or 8 ° from the (0001) plane, and the surface 10a of the n-type low resistance silicon carbide semiconductor substrate 10 having a 4H polytype is The p-type impurity concentration is about 5 × 10 ¹⁷ cm ⁻³ or more and about 1 × 10 ²¹ cm ⁻³ or less and has a thickness of about 10 μm or more and about 100 μm or less by a chemical vapor deposition (ie, CVD) method. A p-type silicon carbide epitaxial layer 11 is grown. Further, an n-type impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ or more and about 1 × 10 ¹⁷ cm ⁻³ or less is formed on the surface 11a of the p-type silicon carbide epitaxial layer 11 by CVD, and is about 10 μm or more and 200 μm. An n-type silicon carbide epitaxial layer 12 having a thickness of about or less is grown. A structure in which n-type silicon carbide epitaxial layer 12 is formed on p-type silicon carbide epitaxial layer 11 can be referred to as silicon carbide epitaxial substrate 13.

  Thus, silicon carbide substrate 14 in which silicon carbide epitaxial substrate 13 is formed on n-type silicon carbide semiconductor substrate 10 is prepared.

Next, as shown in FIG. 5, in the termination region, an implantation mask is formed on the surface of n-type silicon carbide epitaxial layer 12, and p-type impurity aluminum is ionized on the surface layer of n-type silicon carbide epitaxial layer 12. inject. At this time, the ion implantation depth of aluminum is about 0.1 μm or more and about 3 μm or less. The impurity concentration of the ion-implanted aluminum is in the range of about 1 × 10 ¹⁷ cm ^{−3 to} about 1 × 10 ¹⁹ cm ⁻³ and higher than the n-type impurity concentration of the n-type silicon carbide epitaxial layer 12. Shall. Here, the formed ion implantation region is for maintaining the breakdown voltage, and is the JTE region 20 described above.

Next, after removing the implantation mask used in FIG. 5, an implantation mask is formed on the surface of n-type silicon carbide epitaxial layer 12 in the active region and the termination region as shown in FIG. Aluminum, which is a p-type impurity, is ion-implanted into the surface layer of the layer 12. At this time, the ion implantation depth of aluminum is about 0.1 μm or more and about 3 μm or less. The impurity concentration of the ion-implanted aluminum is in the range of about 1 × 10 ¹⁷ cm ^{−3 to} about 1 × 10 ¹⁹ cm ⁻³ and higher than the n-type impurity concentration of the n-type silicon carbide epitaxial layer 12. Shall. Here, the formed ion-implanted regions are a plurality of base regions 30 formed in a region different from the JTE region 20 and formed apart from each other.

Next, after removing the implantation mask used in FIG. 6, as shown in FIG. 7, an implantation mask is formed on the surface of n-type silicon carbide epitaxial layer 12 including the surface of base region 30 in the active region, Nitrogen (N), which is an n-type impurity, is ion-implanted into the surface layer of the base region 30 where the implantation mask is formed. The ion implantation depth of nitrogen (N) is assumed to be shallower than the depth of the bottom surface of the base region 30. The impurity concentration of nitrogen (N) ion-implanted is in the range of about 1 × 10 ¹⁸ cm ^{−3 to} about 1 × 10 ²¹ cm ⁻³ and higher than the p-type impurity concentration of the base region 30. And Of the regions into which nitrogen (N) is implanted in the base region 30, the region showing n-type is the source region 40.

  Next, after removing the implantation mask used in FIG. 7, annealing is performed in an inert gas atmosphere such as argon (Ar) gas by a heat treatment apparatus (not shown here). When the annealing treatment is performed, the temperature of the atmosphere is set to about 1300 ° C. to about 1900 ° C., and the time is set to about 30 seconds to about 1 hour. By this annealing treatment, the previously implanted nitrogen (N) and aluminum are activated.

Next, as shown in FIG. 8, a field oxide film 50 made of silicon dioxide (SiO ₂ ) or the like is formed in the termination region by a CVD method or the like. Next, in the active region, the surface of n-type silicon carbide epitaxial layer 12 including base region 30 and source region 40 is thermally oxidized to form gate insulating film 60 having a desired thickness.

  Next, as shown in FIG. 9, a polycrystalline silicon film having conductivity is formed on the field oxide film 50 and the gate insulating film 60 by a low pressure CVD method. The gate electrode 70 is formed by patterning the polycrystalline silicon film. At this time, the gate electrode 70 in the active region is formed on the base region 30 sandwiched between the source region 40 and the n-type silicon carbide epitaxial layer 12 via the gate insulating film 60. Gate electrode 70 in the active region is formed over the surface of n-type silicon carbide epitaxial layer 12.

Next, as shown in FIG. 10, an interlayer insulating film 80 made of silicon dioxide (SiO ₂ ) or the like is formed by CVD or the like in the active region and the termination region. Interlayer insulating film 80 is formed to cover gate insulating film 60 and gate electrode 70 in the active region. Interlayer insulating film 80 is formed to cover gate electrode 70 and field oxide film 50 in the termination region.

Next, as shown in FIG. 11, in the active region, the interlayer insulating film 80 and the gate insulating film 60 in the region excluding the region where the gate electrode 70 is formed are removed to form a contact hole to the silicon carbide layer. To do. Specifically, a contact hole to the silicon carbide layer is opened by dry etching such as reactive ion etching (RIE) using a gas containing C ₃ H ₈ or the like. Then, a nickel (Ni) metal film as the source electrode 100 is formed on the surface of the active region from which the interlayer insulating film 80 and the gate insulating film 60 have been removed by heat treatment and chemical treatment. Here, Ni has been described as an example of the material of the source electrode 100. However, any metal or laminated film may be used as long as the metal film can form the low-resistance source electrode 100.

  In the termination region, the interlayer insulating film 80 is partially removed, and a contact hole to the gate electrode 70 is formed. Specifically, the contact hole to the gate electrode 70 is opened by dry etching, wet etching using hydrogen fluoride, or a combination of dry etching and wet etching.

  Next, as shown in FIG. 12, a wiring electrode that covers the source electrode 100 and the gate electrode 70 in the active region and covers the interlayer insulating film 80 and the gate electrode 70 in the termination region is formed by patterning. The wiring electrode in the active region is the wiring electrode 300a, and the wiring electrode in the termination region is the wiring electrode 300b. Examples of the material for the wiring electrode include aluminum. Further, in order to maintain the breakdown voltage, an insulating film 400 made of polyimide or the like is deposited so as to cover the wiring electrode 300b in the termination region.

  Next, as shown in FIG. 13, silicon carbide semiconductor substrate 10 is ground to expose back surface 11 b of p-type silicon carbide epitaxial layer 11. The total thickness of the p-type silicon carbide epitaxial layer 11 and the n-type silicon carbide epitaxial layer 12 at this time varies depending on the required breakdown voltage, but is, for example, about 200 μm or less. During grinding, it is desirable to protect the non-ground surface by applying a protective tape or applying a wax or the like and attaching a support substrate. As a grindstone used for grinding, for example, diamond abrasive grains bonded with a binder such as vitrified can be considered. Here, grinding is given as an example of a method for removing n-type silicon carbide semiconductor substrate 10, but even when n-type silicon carbide semiconductor substrate 10 is removed by other processing methods. I do not care.

  Next, as shown in FIG. 14, the back surface 11b of the p-type silicon carbide epitaxial layer 11 exposed after the removal of the n-type silicon carbide semiconductor substrate 10 is cleaned by an appropriate method, and an ohmic surface is formed on the entire back surface 11b. An electrode is formed.

  On the exposed back surface 11b of the p-type silicon carbide epitaxial layer 11, an aluminum electrode layer 200a and a titanium electrode layer 200b are sequentially deposited. At the time of deposition, aluminum having a low melting point among the two types of metals is first deposited on the back surface 11b of the p-type silicon carbide epitaxial layer 11, and then titanium having a high melting point among the two types of metals is deposited. Deposited on the aluminum electrode layer 200a. The thickness of each metal film is, for example, about 50 nm for the aluminum electrode layer 200a and about 30 nm for the titanium electrode layer 200b. Regarding the thickness, any thickness other than those described here may be used as long as the formed ohmic electrode has a low resistance. Note that the thickness of aluminum is desirably thicker than that of titanium.

Next, as shown in FIG. 15, the back surface side of the p-type silicon carbide epitaxial layer 11 on which the metal film is deposited is irradiated with a laser beam 201 to form an ohmic electrode. Type of laser light used for the irradiation is, for example, a YVO ₄ laser. However, a YAG laser, an excimer laser, a YLF laser, or the like can be used other than the YVO ₄ laser. For example, when a YVO ₄ laser is used, the wavelength of the laser light to be irradiated can be 355 nm as the third harmonic or 532 nm as the second harmonic. Annealing is performed while blowing an inert gas such as nitrogen on the laser light irradiation surface during laser light irradiation. Here, laser light having a wavelength of 355 nm is used.

Laser irradiation conditions for forming an ohmic electrode with an Al / Ti metal film for p-type silicon carbide epitaxial layer 11 are, for example, as follows. That is, depending on the thickness of the deposited metal film, for the energy density of the laser beam may be a 1.6 J / cm ² less than approximately 2.5 J / cm ² about the range, aluminum is 50 nm, titanium is at 30nm In some cases, the energy density of the laser beam is set to 1.8 J / cm ² . The shape of the laser beam may be any shape such as a dot shape or a line shape. In laser annealing, laser light is irradiated by superimposing beam light by manipulating the shape of the laser light. Here, a line beam is used, and the size of the line beam is 180 μm × 70 μm in a region where the intensity is halved with respect to the maximum intensity of the laser beam. The overlapping of the beam diameters may be 50% or more with respect to the major axis direction and the minor axis direction of the beam, and in this embodiment, irradiation is performed by overlapping 80% of the beam width in the direction where the beam width is 70 μm. Then, the ohmic electrode 200 is formed.

  FIG. 17 is a diagram showing a cross-section transmission electron microscope image (cross-section TEM image) of an ohmic electrode fabricated using an Al / Ti metal film. Moreover, FIG. 18 is a figure which shows the atomic concentration calculated from energy dispersive x-ray spectroscopy (EDS) acquired in each position in FIG.

In the cross-sectional TEM image of FIG. 17, p-type silicon carbide semiconductor substrate 1 having a concentration of 2 × 10 ¹⁸ cm ⁻³ , manufactured ohmic electrode 4, and aluminum electrode layer 5 are shown in order from the bottom. .

  In FIG. 18, atomic concentrations in p-type silicon carbide semiconductor substrate 1, black contrast portion 2 of ohmic electrode 4 and white contrast portion 3 of ohmic electrode 4 are shown.

  Comparing the atomic concentration in p-type silicon carbide semiconductor substrate 1 as a reference, the composition of atomic concentration in black contrast portion 2 is not significantly different from the composition of atomic concentration in p-type silicon carbide semiconductor substrate 1, but the black contrast It can be seen that the composition of atomic concentration in part 2 contains a slight amount of aluminum. Moreover, in FIG. 17, when the p-type silicon carbide semiconductor substrate 1 and the black contrast part 2 are compared, it turns out that the black contrast part 2 is a silicon alloy layer which lost crystallinity.

  On the other hand, when compared with the atomic concentration in p-type silicon carbide semiconductor substrate 1 as a reference, the composition of atomic concentration in white contrast portion 3 is carbonized in which the composition ratio of silicon and carbon (hereinafter sometimes referred to as C) is p-type. Compared with the composition of the atomic concentration in the silicon semiconductor substrate 1, it can be seen that it is a titanium alloy layer containing aluminum.

  The reason why the ohmic electrode 4 having the above composition is formed is that the outermost layer of the metal film irradiated with the pulsed laser light contains titanium having a high melting point, so that ablation by the laser light can be suppressed. Then, aluminum in contact with p-type silicon carbide semiconductor substrate 1 reacts with silicon carbide to form silicon alloy layer 200c containing aluminum, and one of silicon and carbon constituting silicon carbide semiconductor substrate 1 It is considered that the titanium alloy layer 200d containing aluminum was formed by the portion and aluminum and titanium remaining without reacting.

  Thus, it is considered that the ohmic electrode 4 having a low resistance with respect to the p-type silicon carbide semiconductor substrate 1 is formed. When the relationship between the resistance value of the ohmic electrode 4 and the thickness of the silicon alloy layer 200c containing aluminum and the thickness of the titanium alloy layer 200d containing aluminum was evaluated, the thickness of the silicon alloy layer 200c containing aluminum is a titanium alloy containing aluminum. It has been found that the resistance value of the ohmic electrode 4 is lower when the thickness is larger than the thickness of the layer 200d.

  Therefore, it is desirable that the thickness of the silicon alloy layer 200c containing aluminum is larger than the thickness of the titanium alloy layer 200d containing aluminum. For example, the thickness of the silicon alloy layer 200c containing aluminum is 200d. It is desirable that the thickness is about 1.5 times or more.

  FIG. 19 is a diagram showing a cross-sectional TEM image of an ohmic electrode formed by laser annealing in a region different from the region shown in FIG. In forming the ohmic electrode 6 in FIG. 19, the metal film to be deposited is the same as in the case of FIG. 17, but in the superposition of the laser light, the beam width is overlapped by 80% in the direction of 70 μm. After forming a line-shaped ohmic electrode, two line-shaped ohmic electrodes are formed by overlapping and irradiating 50% of the beam width in the direction in which the beam diameter is 180 μm.

  The ohmic electrode 6 shown in FIG. 19 has a region where only the black contrast portion 2 exists. The atomic concentration in the black contrast portion 2 is the same as that shown in FIG. 18, and it can be seen that the black contrast portion 2 is a silicon alloy layer containing aluminum.

  This is because the laser light is further superimposed on the ohmic electrode 4 formed of two layers of a silicon alloy layer containing aluminum and a titanium alloy layer containing aluminum, which is formed by irradiating the laser light in a superimposed manner. Since it was irradiated, it is considered that the titanium alloy layer 200d containing aluminum was dissolved and only the silicon alloy layer 200c containing aluminum was formed. Even in this case, since the laser light is irradiated only to the titanium alloy layer 200d containing aluminum, the composition ratio of aluminum is not greatly changed, and the low-resistance ohmic electrode 6 is formed.

  Next, as shown in FIG. 16, the back electrode 500 is formed on the entire surface of the ohmic electrode 200 composed of the silicon alloy layer 200c and the titanium alloy layer 200d. Here, the back electrode 500 is formed by depositing a metal film in the order of nickel (Ni) and gold (Au). The thicknesses of nickel (Ni) and gold (Au) are, for example, about 700 nm and about 200 nm, respectively, but other thicknesses may be used.

  Thus, the silicon carbide semiconductor device according to this embodiment is completed.

Second Embodiment
In the following, the same components as those described in the above embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

  In the present embodiment, a method for manufacturing a silicon carbide semiconductor device, which is different from the method in the above embodiment, will be described.

  In the first embodiment, a silicon carbide substrate 14 having a p-type silicon carbide epitaxial layer 11 formed on an n-type silicon carbide semiconductor substrate 10 and an n-type silicon carbide epitaxial layer 12 formed thereon is prepared, and carbonized. A method of manufacturing a silicon semiconductor device is described. In manufacturing the silicon carbide semiconductor device, a method other than the method may be used. For example, an n-type silicon carbide epitaxial layer is formed on a p-type silicon carbide semiconductor substrate as described in the present embodiment. A method of manufacturing a silicon carbide semiconductor device by preparing a formed silicon carbide substrate may be used.

FIG. 20 is a diagram schematically showing a cross section of the active region and a cross section of the termination region in each manufacturing process of the silicon carbide semiconductor device according to the present embodiment. In this embodiment, as shown in FIG. 20, a silicon carbide substrate 15 is prepared. Silicon carbide substrate 15 has a surface orientation of 4 ° or 8 ° off from the (0001) plane, and is formed on surface 110a of p-type low-resistance silicon carbide semiconductor substrate 110 having a 4H polytype by CVD. An n-type silicon carbide epitaxial layer 12 having an n-type impurity concentration of about 1 × 10 ¹⁴ cm ^{−3 to} about 1 × 10 ¹⁷ cm ⁻³ and a thickness of about 10 μm to about 200 μm is formed. Structure.

  In manufacturing a silicon carbide semiconductor device using silicon carbide substrate 15, the structure formed on n-type silicon carbide epitaxial layer 12 is the same as that described in the first embodiment. Further, FIGS. A process similar to that shown in FIG. 6 is performed to form a MOSFET structure.

  Next, in the silicon carbide substrate 15 on which the MOSFET structure is formed, an ohmic electrode is formed on the back surface that is the surface opposite to the surface having the MOSFET structure. When the ohmic electrode is formed, the ohmic electrode may be formed directly on the p-type silicon carbide semiconductor substrate 110. Alternatively, the ohmic electrode may be formed after part of p-type silicon carbide semiconductor substrate 110 is removed by grinding or the like.

  The formation method of the ohmic electrode is the same as that shown in the first embodiment. After aluminum and titanium are sequentially deposited, the laser light is irradiated. The thickness of each metal film, the irradiation condition of the laser beam, and the like are the same as those shown in the first embodiment.

  Finally, the back electrode 500 is formed on the entire surface of the ohmic electrode formed by laser annealing. The material and thickness of the back electrode are the same as those shown in the first embodiment.

  Thus, the silicon carbide semiconductor device according to this embodiment is completed.

<Third Embodiment>
In the following, the same components as those described in the above embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

  In the first embodiment and the second embodiment, the IGBT included in the silicon carbide semiconductor device has been described. In this embodiment, the ohmic electrode is formed on the p-type silicon carbide layer in the manufacturing process of the PiN diode. A case where the above-described method is applied will be described with reference to FIGS.

  FIG. 21 to FIG. 27 are diagrams schematically showing a cross-sectional structure in each manufacturing process of the silicon carbide semiconductor device according to the present embodiment.

As shown in FIG. 21, CVD is performed on the surface 10a of the n-type low-resistance silicon carbide semiconductor substrate 10 having a surface orientation of 4 ° or 8 ° off from the (0001) plane and having a 4H polytype. The n-type silicon carbide epitaxial layer 212 having an n-type impurity concentration of about 1 × 10 ¹³ cm ^{−3 to} about 1 × 10 ¹⁶ cm ⁻³ and a thickness of about 5 μm to about 300 μm is grown by the method. Let Further, a p-type impurity concentration of about 5 × 10 ¹⁷ cm ⁻³ or more and about 1 × 10 ²¹ cm ⁻³ or less is formed on the surface 212a of the n-type silicon carbide epitaxial layer 212 by a CVD method, and is about 1 μm or more and 50 μm or more. A p-type silicon carbide epitaxial layer 211 having a thickness less than or equal to the thickness is grown. A structure in which p-type silicon carbide epitaxial layer 211 is formed on n-type silicon carbide epitaxial layer 212 can be referred to as silicon carbide epitaxial substrate 16.

  Thus, silicon carbide substrate 17 in which silicon carbide epitaxial substrate 16 is formed on n-type silicon carbide semiconductor substrate 10 is prepared.

  Next, formation of the mesa structure will be described. As shown in FIG. 22, an etching mask (not shown here) is formed on surface 211b of p-type silicon carbide epitaxial layer 211, and p-type silicon carbide epitaxial layer 211 and n-type silicon carbide epitaxial layer 212 are etched. To do. The depth to be etched is beyond the p-type silicon carbide epitaxial layer 211 until the n-type silicon carbide epitaxial layer 212 is exposed. Examples of the etching method include dry etching.

Next, formation of the termination region will be described. As shown in FIG. 23, an implantation mask (not shown here) is formed on the surfaces of p-type silicon carbide epitaxial layer 211 and n-type silicon carbide epitaxial layer 212 having a mesa structure to form p-type impurities. An aluminum ion is implanted. The region into which aluminum is implanted is a region extending from the exposed surface layer of n-type silicon carbide epitaxial layer 212 and the surface layer of part of p-type silicon carbide epitaxial layer 211. The ion implantation depth of aluminum is about 0.1 μm or more and about 3 μm or less. The impurity concentration of the ion-implanted aluminum is in the range of about 1 × 10 ¹⁶ cm ^{−3 to} about 1 × 10 ¹⁸ cm ⁻³ . The ion-implanted region formed in this way is for maintaining a withstand voltage, and is defined as a termination region 220.

  After removing the implantation mask, an annealing process is performed by using a heat treatment apparatus in an inert gas atmosphere such as argon (Ar) gas for about 1300 ° C. to about 1900 ° C. for about 30 seconds to about 1 hour. The ion-implanted aluminum is activated by the annealing treatment.

Next, the oxide film formed in the termination region 220 will be described. As shown in FIG. 24, an oxide film 250 made of silicon dioxide (SiO ₂ ) or the like is formed by a CVD method or the like. Thereafter, an etching mask (not shown here) is formed, and a part of p-type silicon carbide epitaxial layer 211 is exposed by dry etching or wet etching using hydrofluoric acid (HF). A region where oxide film 250 is formed covers the entire mesa structure on termination region 220 of the silicon carbide semiconductor device, and a region partially covers surface 211b of p-type silicon carbide epitaxial layer 211.

  Next, the formation of ohmic electrodes on the p-type silicon carbide epitaxial layer 211 will be described. As shown in FIG. 25, aluminum and titanium are sequentially deposited on the entire surface 211 b of p-type silicon carbide epitaxial layer 211. The electrode configuration to be deposited is the same as that shown in the first embodiment. For example, the aluminum electrode layer 200a (not shown here) is about 50 nm, and the titanium electrode layer 200b (not shown here) is about 30 nm. To do. The aluminum electrode layer and the titanium electrode layer on the oxide film 250 can be removed with hydrofluoric acid or an aluminum etchant after forming an etching mask (not shown here).

  Thereafter, ohmic electrode 1200 is formed on p-type silicon carbide epitaxial layer 211 by laser light irradiation. The laser light irradiation conditions are the same as those shown in the first embodiment.

  Next, the process of forming a back surface ohmic electrode on back surface 10b of n-type silicon carbide semiconductor substrate 10 will be described. As shown in FIG. 26, part of n-type silicon carbide semiconductor substrate 10 may be removed by grinding from back surface 10b side of n-type silicon carbide semiconductor substrate 10. The grinding method is the same as the method shown in the first embodiment.

  After grinding, a metal film is deposited on the entire back surface 10b of n-type silicon carbide semiconductor substrate 10. Any material can be used as long as it forms an n-type silicon carbide layer and a low-resistance ohmic electrode. For example, a nickel (Ni) film is deposited to a thickness of about 100 nm.

  Then, the low resistance ohmic electrode 2200 is formed by irradiating the nickel (Ni) film with laser light. Laser light irradiation conditions are the same as, for example, the conditions when the ohmic electrode 1200 is formed.

  Although laser annealing has been described here as a method for forming an ohmic electrode on an n-type silicon carbide layer, rapid thermal annealing (RTA) may be used.

  Next, the final process of the PiN diode will be described. As shown in FIG. 27, wiring electrode 300 is further formed on ohmic electrode 1200 formed on p-type silicon carbide epitaxial layer 211. Examples of the material of the wiring electrode 300 include aluminum. An etching mask (not shown here) may be formed, and the wiring electrode on the oxide film 250 may be removed with an aluminum etchant or the like. Furthermore, an insulating film 400 made of polyimide or the like may be deposited in the vicinity of the termination region in order to maintain the breakdown voltage.

  Finally, back electrode 500 is formed on ohmic electrode 2200 formed on back surface 10 b of n-type silicon carbide semiconductor substrate 10. Here, the back electrode 500 is formed by depositing nickel (Ni) and gold (Au) in this order. The thicknesses of nickel (Ni) and gold (Au) are, for example, about 700 nm and about 200 nm, respectively, but other thicknesses may be used.

  Thus, the silicon carbide semiconductor device according to this embodiment is completed.

<Effect>
Below, the effect by said embodiment is illustrated.

  According to the above embodiment, the silicon carbide semiconductor device includes the p-type silicon carbide epitaxial layer 11 included in the p-type silicon carbide semiconductor layer and the ohmic electrode 200.

  Ohmic electrode 200 is formed in ohmic contact on the surface of p-type silicon carbide epitaxial layer 11. In addition, ohmic electrode 200 is formed in contact with p-type silicon carbide epitaxial layer 11, formed in contact with silicon alloy layer 200 c containing aluminum and silicon, silicon alloy layer 200 c, and aluminum. A titanium alloy layer 200d containing titanium.

  According to the above embodiment, the silicon carbide semiconductor device includes p-type silicon carbide epitaxial layer 211 included in the p-type silicon carbide semiconductor layer, and ohmic electrode 1200.

  Ohmic electrode 1200 is formed in ohmic contact on the surface of p-type silicon carbide epitaxial layer 211. Ohmic electrode 1200 is formed in contact with p-type silicon carbide epitaxial layer 211, is formed in contact with silicon alloy layer 200c containing aluminum and silicon, silicon alloy layer 200c, and is formed of aluminum. A titanium alloy layer 200d containing titanium.

  According to such a configuration, the ohmic electrode 200 and the ohmic electrode 1200 include the silicon alloy layer 200c containing aluminum and silicon and the titanium alloy layer 200d containing aluminum and titanium. Can be resistance.

  Note that configurations other than these configurations can be omitted as appropriate, but the above-described effects can be produced even when at least one other configuration shown in this specification is added as appropriate.

  Moreover, according to said embodiment, the ohmic electrode 200 is formed by the annealing process which irradiates a laser beam to the layer used as the titanium alloy layer 200d.

  According to such a configuration, since the annealing process for irradiating laser light to the titanium electrode layer 200b having a relatively high melting point is performed, ablation caused by irradiating the laser light can be suppressed.

  Moreover, according to said embodiment, the thickness of the silicon alloy layer 200c is thicker than the thickness of the titanium alloy layer 200d.

  According to such a configuration, the resistance value of the formed ohmic electrode can be lowered.

  Moreover, according to said embodiment, the thickness of the silicon alloy layer 200c is 1.5 times or more of the thickness of the titanium alloy layer 200d.

  According to such a configuration, the resistance value of the formed ohmic electrode can be lowered.

  According to the above embodiment, the silicon carbide semiconductor device includes an n-type silicon carbide epitaxial layer 12 included in the n-type silicon carbide epitaxial layer, a plurality of p-type base regions 30, and an n-type source region. 40, a gate electrode 70, and a source electrode 100.

  N-type silicon carbide epitaxial layer 12 is formed on the opposite surface which is the surface opposite to the surface of p-type silicon carbide epitaxial layer 11 included in the silicon carbide semiconductor layer.

  Base region 30 is formed on the surface layer of n-type silicon carbide epitaxial layer 12 opposite to the side in contact with p-type silicon carbide epitaxial layer 11 so as to be separated from each other. The source region 40 is formed on the surface layer of each base region 30.

  Gate electrode 70 is formed on the surface of each base region 30 sandwiched between each source region 40 and n-type silicon carbide epitaxial layer 12 via gate insulating film 60. The source electrode 100 is formed across the surface of each base region 30 and the surface of each source region 40.

  According to such a configuration, an IGBT including a low-resistance ohmic electrode can be obtained.

  According to the above embodiment, the silicon carbide semiconductor device is included in the n-type silicon carbide epitaxial layer 212 included in the n-type silicon carbide epitaxial layer, the n-type silicon carbide semiconductor substrate 10, and the electrode layer. And an ohmic electrode 2200.

  N-type n-type silicon carbide epitaxial layer 212 is formed on the surface opposite to the surface of p-type silicon carbide epitaxial layer 211.

  N-type silicon carbide semiconductor substrate 10 is formed on the opposite surface of n-type silicon carbide epitaxial layer 212 that is the surface opposite to the side in contact with p-type silicon carbide epitaxial layer 211.

  Ohmic electrode 2200 is formed in ohmic contact on the opposite surface of silicon carbide semiconductor substrate 10 that is opposite to the side in contact with n-type silicon carbide epitaxial layer 212.

  According to such a configuration, a PiN diode including a low-resistance ohmic electrode can be obtained.

  Moreover, according to said embodiment, the p-type silicon carbide epitaxial layer 11 is formed in the manufacturing method of a silicon carbide semiconductor device. Then, an aluminum electrode layer 200 a included in the aluminum layer is formed on the surface of p-type silicon carbide epitaxial layer 11. Then, a titanium electrode layer 200b included in the titanium layer is formed on the surface of the aluminum electrode layer 200a.

  Then, by annealing, the silicon alloy layer 200c containing aluminum and silicon is in contact with the p-type silicon carbide epitaxial layer 11, and the titanium alloy layer containing aluminum and titanium is in contact with the silicon alloy layer 200c. 200d.

  Moreover, according to said embodiment, the p-type silicon carbide epitaxial layer 211 is formed in the manufacturing method of a silicon carbide semiconductor device. Then, aluminum electrode layer 200a is formed on the surface of p-type silicon carbide epitaxial layer 211. Then, a titanium electrode layer 200b is formed on the surface of the aluminum electrode layer 200a.

  Then, by annealing, the p-type silicon carbide epitaxial layer 211 is in contact with the silicon alloy layer 200c containing aluminum and silicon, and the silicon alloy layer 200c is in contact with the aluminum alloy layer 200c and the titanium alloy layer containing aluminum and titanium. 200d.

  According to such a configuration, when the silicon alloy layer 200c and the titanium alloy layer 200d are formed by annealing, the layer located on the side opposite to the side in contact with the p-type silicon carbide epitaxial layer 211 has a melting point. Since it is a layer containing high titanium, ablation accompanying temperature rise can be suppressed, and the composition of the ohmic electrode formed does not fluctuate significantly. Therefore, an ohmic electrode having a low resistance can be stably formed on the p-type silicon carbide semiconductor layer.

  Further, according to the above embodiment, the annealing process is a process of irradiating the titanium electrode layer 200b with laser light to form the silicon alloy layer 200c and the titanium alloy layer 200d.

  According to such a configuration, since the annealing process for irradiating laser light to the titanium electrode layer 200b having a relatively high melting point is performed, ablation caused by irradiating the laser light can be suppressed.

Moreover, according to said embodiment, the energy of the laser beam irradiated to the titanium electrode layer 200b is larger than 1.6 J / cm < ² >.

  According to such a configuration, an ohmic electrode can be appropriately formed.

  Further, according to the above embodiment, n-type n-type silicon carbide epitaxial layer 12 is formed on the surface opposite to the surface of p-type silicon carbide epitaxial layer 11. Then, a plurality of p-type base regions 30 that are separated from each other are formed on the surface layer of n-type silicon carbide epitaxial layer 12 opposite to the side in contact with p-type silicon carbide epitaxial layer 11. Then, an n-type source region 40 is formed on the surface layer of each base region 30. Then, a gate electrode 70 is formed on the surface of each base region 30 sandwiched between each source region 40 and n-type silicon carbide epitaxial layer 12 via a gate insulating film 60. Then, the source electrode 100 is formed across the surface of each base region 30 and the surface of each source region 40.

  According to such a configuration, an IGBT including a low-resistance ohmic electrode can be obtained.

  According to the above embodiment, p-type silicon carbide epitaxial layer 11 is a layer formed by epitaxial growth from n-type silicon carbide semiconductor substrate 10, and silicon carbide semiconductor substrate 10 is p-type silicon carbide epitaxial. It is removed before forming the aluminum electrode layer 200a on the surface of the layer 11.

  According to such a configuration, an IGBT including a low-resistance ohmic electrode can be obtained.

  According to the above embodiment, n-type silicon carbide epitaxial layer 12 is a layer formed by epitaxial growth from silicon carbide semiconductor substrate 110 included in the silicon carbide semiconductor layer, and the surface of silicon carbide semiconductor substrate 110 is The aluminum electrode layer 200a is at least partially removed before the surface is formed.

  According to such a configuration, an IGBT including a low-resistance ohmic electrode can be obtained.

  According to the above embodiment, p type silicon carbide epitaxial layer 211 is formed on the surface of n type n type silicon carbide epitaxial layer 212. Then, n type silicon carbide epitaxial layer 212 is formed on the surface of n type silicon carbide semiconductor substrate 10. Then, ohmic electrode 2200 that is in ohmic contact is formed on the opposite surface of silicon carbide semiconductor substrate 10 that is opposite to the side in contact with n-type silicon carbide epitaxial layer 212.

  According to such a configuration, a PiN diode including a low-resistance ohmic electrode can be obtained.

  Moreover, according to said embodiment, the opposite surface of the silicon carbide semiconductor substrate 10 is at least partially removed before forming the ohmic electrode 2200 on the opposite surface.

  According to such a configuration, a PiN diode including a low-resistance ohmic electrode can be obtained.

<Modification>
In the above-described embodiment, the material, material, size, shape, relative arrangement relationship, implementation condition, and the like of each component may be described. It is not limited to what is described in the book. Therefore, innumerable modifications not illustrated are assumed within the scope of the present technology. For example, the case where at least one component is modified, added or omitted, and further, the case where at least one component in at least one embodiment is extracted and combined with the components of other embodiments are included. It is.

  In addition, as long as no contradiction arises, “one or more” components described as being provided with “one” in the above-described embodiment may be provided. Furthermore, each component is a conceptual unit. When one component is composed of a plurality of structures and when one component corresponds to a part of the structure, a plurality of components are further included. Is included in one structure. Each component includes a structure having another structure or shape as long as the same function is exhibited.

  Also, the descriptions in this specification are referred to for all purposes of the present technology and are not admitted to be prior art.

  In the above embodiment, the planar type MOSFET has been described. However, the present invention can also be applied to a trench type MOSFET in which a trench is formed on the surface of the drift layer. In the case of a trench type MOSFET, a groove (trench) is formed on the surface of the drift layer, and a gate electrode is embedded via a gate insulating film on the upper surface of the drift layer in the groove, that is, on the bottom surface of the trench.

  Further, in the above embodiment, when a material name or the like is described without being particularly specified, the material includes other additives, for example, an alloy or the like unless a contradiction arises. .

  1, 10, 110 Silicon carbide semiconductor substrate, 2, 3 contrast portion, 5,200a aluminum electrode layer, 4, 6, 200, 1200, 2200 ohmic electrode, 10a, 11a, 110a, 211b, 212a surface, 10b, 11b back surface 11, 211 p-type silicon carbide epitaxial layer, 12,212 n-type silicon carbide epitaxial layer, 13,16 silicon carbide epitaxial substrate, 14,15,17 silicon carbide substrate, 20 JTE region, 30 base region, 40 source region, 50 field oxide film, 60 gate insulating film, 70 gate electrode, 80 interlayer insulating film, 100 source electrode, 200b titanium electrode layer, 200c silicon alloy layer, 200d titanium alloy layer, 201 laser beam, 220 termination region, 250 oxide film, 300,300 , 300b wiring electrode, 400 an insulating film, 500 back electrode, 1000 a dicing line.

Claims (14)

a p-type silicon carbide semiconductor layer;
An ohmic electrode formed in ohmic contact on the surface of the silicon carbide semiconductor layer,
The ohmic electrode is
A silicon alloy layer formed in contact with the silicon carbide semiconductor layer and containing aluminum and silicon;
A titanium alloy layer formed in contact with the silicon alloy layer and including aluminum and titanium;
Silicon carbide semiconductor device. The ohmic electrode is formed by an annealing process in which a layer to be the titanium alloy layer is irradiated with laser light.
The silicon carbide semiconductor device according to claim 1. The thickness of the silicon alloy layer is thicker than the thickness of the titanium alloy layer,
The silicon carbide semiconductor device according to claim 1 or 2. The thickness of the silicon alloy layer is 1.5 times or more the thickness of the titanium alloy layer,
The silicon carbide semiconductor device according to claim 3. An n-type silicon carbide epitaxial layer formed on an opposite surface which is a surface opposite to the surface of the silicon carbide semiconductor layer;
A plurality of p-type base regions formed on the surface layer on the opposite side of the silicon carbide epitaxial layer from the side in contact with the silicon carbide semiconductor layer;
An n-type source region formed on the surface layer of each base region;
A gate electrode formed on the surface of each base region sandwiched between each source region and the silicon carbide epitaxial layer via a gate insulating film;
A source electrode formed on the surface of each base region and on the surface of each source region;
The silicon carbide semiconductor device according to any one of claims 1 to 4. An n-type silicon carbide epitaxial layer formed on an opposite surface which is a surface opposite to the surface of the silicon carbide semiconductor layer;
An n-type silicon carbide semiconductor substrate formed on an opposite surface of the silicon carbide epitaxial layer opposite to a side in contact with the silicon carbide semiconductor layer;
An electrode layer formed in ohmic contact with the opposite surface of the silicon carbide semiconductor substrate on the opposite surface to the side in contact with the silicon carbide epitaxial layer;
The silicon carbide semiconductor device according to any one of claims 1 to 4. forming a p-type silicon carbide semiconductor layer;
Forming an aluminum layer on the surface of the silicon carbide semiconductor layer;
Forming a titanium layer on the surface of the aluminum layer;
By annealing, a silicon alloy layer that contacts the silicon carbide semiconductor layer and includes aluminum and silicon, and a titanium alloy layer that contacts the silicon alloy layer and includes aluminum and titanium are formed.
A method for manufacturing a silicon carbide semiconductor device. The annealing treatment
The titanium layer is irradiated with laser light to form the silicon alloy layer and the titanium alloy layer.
A method for manufacturing a silicon carbide semiconductor device according to claim 7. The energy of the laser light applied to the titanium layer is greater than 1.6 J / cm ² ;
A method for manufacturing a silicon carbide semiconductor device according to claim 8. Forming an n-type silicon carbide epitaxial layer on the surface opposite to the surface of the silicon carbide semiconductor layer;
Forming a plurality of p-type base regions spaced apart from each other on the surface layer of the silicon carbide epitaxial layer opposite to the side in contact with the silicon carbide semiconductor layer;
Forming an n-type source region on the surface of each base region;
On the surface of each base region sandwiched between each of the source region and the silicon carbide epitaxial layer, a gate electrode is formed via a gate insulating film,
Forming a source electrode over the surface of each base region and over the surface of each source region;
The method for manufacturing a silicon carbide semiconductor device according to any one of claims 7 to 9. The silicon carbide semiconductor layer is a layer formed by epitaxial growth from an n-type silicon carbide semiconductor substrate;
The silicon carbide semiconductor substrate is removed before forming the aluminum layer on the surface of the silicon carbide semiconductor layer;
A method for manufacturing a silicon carbide semiconductor device according to claim 10. The silicon carbide epitaxial layer is a layer formed by epitaxial growth from the silicon carbide semiconductor layer,
The surface of the silicon carbide semiconductor layer is at least partially removed before forming the aluminum layer on the surface;
A method for manufacturing a silicon carbide semiconductor device according to claim 10. The silicon carbide semiconductor layer is formed on the surface of an n-type silicon carbide epitaxial layer,
The silicon carbide epitaxial layer is formed on the surface of an n-type silicon carbide semiconductor substrate,
Forming an electrode layer in ohmic contact on the opposite surface of the silicon carbide semiconductor substrate on the opposite surface to the side in contact with the silicon carbide epitaxial layer;
The method for manufacturing a silicon carbide semiconductor device according to any one of claims 7 to 9. The opposite surface of the silicon carbide semiconductor substrate is at least partially removed prior to forming the electrode layer on the opposite surface;
A method for manufacturing a silicon carbide semiconductor device according to claim 13.