JP2016092771A - A/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cyclic A/D converter capable of improving an S/N ratio.SOLUTION: A residual voltage generating circuit 12 generates a residual voltage obtained by amplifying a difference voltage between a voltage that an input voltage is sample-and-hold processed and a predetermined analog voltage. An input switching circuit 12 inputs any one of an external signal voltage Vin and the voltage Vout outputted from the residual voltage generating circuit 12 into an A/D conversion circuit 2 and the residual voltage generating circuit 12. A control circuit 10 sets an analog voltage in the residual voltage generating circuit 12 to a voltage corresponding to a D/A conversion value of a digital conversion value outputted from the A/D conversion circuit 2, and performs an A/D conversion operation by cycling the external signal voltage Vin through an input switching circuit 13, the A/D conversion circuit 2, and the residual voltage generating circuit 12. At the time of performing, a sample voltage is accumulated by performing a plurality of sample-and-hold processing, and the control circuit allows the residual voltage to be generated by the residual voltage generating circuit 12 based on the voltage as an accumulated result.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a cyclic A / D converter.

  A pressure sensor, an acceleration sensor, or the like configured using a semiconductor has a very small detection signal level, and therefore, an amplified signal is generally output to the outside as a sensor signal. In addition, since such sensor signals are subjected to signal processing such as correction of linearity after A / D conversion, a high S / N ratio (Signal to Noise ratio) is also obtained for A / D conversion processing. Required. As a cyclic A / D converter used for A / D conversion of a sensor signal, for example, a configuration in which resolution can be set flexibly and a configuration in which various output formats of signals can be supported are disclosed in Patent Documents 1 and 2. Is disclosed.

JP 2011-228778 A JP 2011-205109 A

However, in these A / D converters, no special measures are taken to improve the S / N ratio, and basically, the input signal is sampled and held and A / D converted. As a result, the input signal is in a state where the on-resistance of each switch, the thermal noise generated by the amplifier, etc. are superimposed as it is, and it is difficult to say that the S / N ratio is good.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a cyclic A / D converter capable of improving the S / N ratio.

  According to the A / D converter of the first aspect, the residual voltage generating circuit generates a residual voltage obtained by amplifying a difference voltage between a voltage obtained by sample-holding the input voltage and a predetermined analog voltage. The input switching circuit inputs one of the external signal voltage and the voltage output from the residual voltage generation circuit to the A / D conversion circuit and the residual voltage generation circuit.

  The control circuit uses the analog voltage in the residual voltage generation circuit as a voltage corresponding to the D / A conversion value of the digital conversion value output from the A / D conversion circuit, and converts the external signal voltage to the input switching circuit, A / The A / D conversion operation is performed by circulating through the D conversion circuit and the residual voltage generation circuit. However, at that time, the sample hold process is executed a plurality of times to accumulate the sample voltage, the residual voltage is generated by the residual voltage generation circuit for the voltage that is the result of the accumulation, and the A / D conversion operation is executed.

  That is, when the sample hold process is executed a plurality of times and the sample voltage is accumulated, noise components included in the sample voltage due to each circuit element and the like are averaged and suppressed. / N ratio is improved. Therefore, the accuracy of the conversion value obtained can be improved by A / D converting the accumulated sample voltage.

  According to the A / D converter of the eighth aspect, the residual voltage generation circuit generates a residual voltage obtained by amplifying a difference voltage between the input voltage of the A / D conversion circuit and a predetermined analog voltage. The input circuit inputs the voltage output from the residual voltage generation circuit to the A / D conversion circuit and the residual voltage generation circuit. The input switching circuit switches whether or not the external signal charge is input to the input terminal of the operational amplifier.

  The control circuit inputs an external signal charge to the residual voltage generation circuit via the input switching circuit, and executes a voltage conversion operation for outputting a voltage corresponding to the external signal charge from the residual voltage generation circuit. After the voltage conversion operation is repeated a plurality of times, the analog voltage in the residual voltage generation circuit is set to the D / A conversion value of the digital conversion value output from the A / D conversion circuit, and the conversion voltage of the external signal charge is input. The A / D conversion operation is performed by circulating through the circuit, the A / D conversion circuit, and the residual voltage generation circuit.

  That is, in the configuration of claim 8 as well, by repeating the voltage conversion operation of the external signal charge a plurality of times, the noise component contained in the external signal charge due to each circuit element or the like is averaged and suppressed. Therefore, the S / N ratio is improved. Therefore, the accuracy of the conversion value obtained can be improved by A / D converting the accumulated sample voltage.

Electrical configuration diagram of the cyclic A / D converter showing the first embodiment Timing chart showing sample hold processing and A / D conversion operation (A) is an example of a sample and hold process, (b) is a frequency characteristic of a filter corresponding to the sample and hold process of (a), and (c) is a diagram showing a noise component reduction rate by the filter of (b). Electrical configuration diagram of a cyclic A / D converter showing a second embodiment Timing chart showing sample hold processing and A / D conversion operation Electrical configuration diagram of a cyclic A / D converter showing a third embodiment Timing chart showing sample hold processing and A / D conversion operation Electrical configuration diagram of a cyclic A / D converter showing a fourth embodiment Electrical configuration diagram of the cyclic A / D converter showing the fifth embodiment Electrical configuration diagram of a cyclic A / D converter showing a sixth embodiment Timing chart showing C / V conversion operation and A / D conversion operation Electrical configuration diagram of a cyclic A / D converter showing a seventh embodiment Electrical configuration diagram of a cyclic A / D converter showing an eighth embodiment Timing chart showing C / V conversion operation and A / D conversion operation Electrical configuration of a cyclic A / D converter showing a ninth embodiment Electrical configuration of a cyclic A / D converter showing the tenth embodiment Electrical configuration diagram of a cyclic A / D converter showing an eleventh embodiment

(First embodiment)
The cyclic A / D converter 1 according to the first embodiment shown in FIG. 1 is based on the configuration disclosed in FIG. 1 of Patent Document 1, and the same reference numerals as those in FIG. doing. That is, the A / D converter 1 includes an A / D conversion circuit 2, an operational amplifier 4 (operational amplifier), a control circuit 10, a capacitor array circuit 11, a residual voltage generation circuit 12, an input switching circuit 13, and the like. Yes.

  However, the switches S8 to S10 are omitted because they are not used in the present embodiment, and one ends of the capacitors CF1 and CF2 are directly connected to the output terminal of the operational amplifier 4 and the other ends are directly connected to the common line 14. In addition, the low-level reference voltage line Vrefm to which the switches S6 and S7 are switched and connected is set to a potential different from the ground (GND). In addition, in the present embodiment, a configuration part that switches the ADC / DAC function by the control circuit 10 and outputs the D / A converted digital value to the outside is unnecessary. In the present embodiment, the content of control by the control circuit 10 is different from that in Patent Document 1.

  Next, the operation of this embodiment will be described. In Patent Document 1, the control circuit 10 first performs a sample-hold process on the input signal voltage Vin (external signal voltage) applied to the signal input terminal 3 and immediately performs the first A / D conversion operation (FIG. 1). 4 first step).

  On the other hand, in the present embodiment, as shown in FIG. 2, the control circuit 10 repeatedly performs the sample-and-hold process a plurality of times, so that capacitors CS1, CS2 (first and second capacitors), CF1, CF2 The sample voltage is accumulated by the charge for charging the (third capacitor). Then, A / D conversion is performed on the accumulated sample voltage in the same manner as in Patent Document 1. Hereinafter, the above processing procedure will be described in detail.

<Reset and sample phase Sa1>
In this phase, the switch S1 is turned off, the switches S2 and S3 are turned on, the switches S4 and S5 are turned off, the switches S6 and S7 are turned on, and the switch S11 is turned on. At this time, the charge QCS charged in the capacitors CS1 and CS2 is
QCS = (CS1 + CS2) × Vin (1)
The charge QCF charged in the capacitors CF1 and CF2 is
QCF = (CF1 + CF2) × 0 = 0 (2)
It becomes.

<Hold phase H1>
In the subsequent hold phase, for example, the switch S6 is switched to the reference voltage Vrefp (high level) side, the switch S7 is switched to the reference voltage Vrefm (low level) side, and the switch S11 is turned off. At this time, the charge QCS charged in the capacitors CS1 and CS2 is
QCS = CS1 × Vrefp + CS2 × Vrefm (3)
The charge QCF charged in the capacitors CF1 and CF2 is
QCF = (CF1 + CF2) × Vout (4)
It becomes.

となる。そして、（６）式において、ＣＦ１＝ＣＦ２＝ＣＳ１＝ＣＳ２，
Ｖrefp＝Ｖref／２，Ｖrefm＝−Ｖref／２に設定すれば、Ｖout＝Ｖinとなる。尚、例えばＶref＝５Ｖであれば、Ｖrefp＝２．５Ｖ，Ｖrefm＝−２．５Ｖになる。 Here, according to the law of conservation of charge, the sum of the expressions (1) and (2) that are the total charges of the phase Sa1 and the sum of the expressions (3) and (4) that are the total charges of the phase H1 are equal. ,
(CS1 + CS2) × Vin = CS1 × Vrefp + CS2 × Vrefm
+ (CF1 + CF2) × Vout (5)
It becomes. When the output voltage Vout of the operational amplifier 4 is obtained from the equation (5),

It becomes. In the equation (6), CF1 = CF2 = CS1 = CS2,
If Vrefp = Vref / 2 and Vrefm = −Vref / 2 are set, Vout = Vin. For example, if Vref = 5V, Vrefp = 2.5V and Vrefm = −2.5V.

<Sample phase Sa2>
In this phase, the switches S2 and S3 are turned off, the switches S4 and S5 are turned on, and the switches S6 and S7 are set to the output voltage Vout side. At this time, the charge QCS charged in the capacitors CS1 and CS2 is the same as the equation (1), and the charge QCF charged in the capacitors CF1 and CF2 is
QCF = (CF1 + CF2) × Vin (7)
It becomes.

となるが、各コンデンサの容量及び基準電圧Ｖrefp，Ｖrefmについて上述した設定条件より、Ｖout＝２・Ｖinとなる。 <Hold phase H2>
In the subsequent hold phase H2, each switch is switched to the same state as in the phase H1. At this time, the charge QCS charged in the capacitors CS1 and CS2 and the charge QCF charged in the capacitors CF1 and CF2 are the same as the equations (3) and (4), respectively. Then, from the law of conservation of charge,
(CS1 + CS2) × Vin + (CF1 + CF2) × Vin
= CS1 * Vrefp + CS2 * Vrefm (8)
It becomes. When the output voltage Vout of the operational amplifier 4 is obtained from the equation (8),

However, Vout = 2 · Vin from the setting conditions described above for the capacitance of each capacitor and the reference voltages Vrefp and Vrefm.

  Thereafter, when the sample phase and the hold phase are repeatedly executed in the same manner, the output voltage Vout in the A-th sample phase SaA becomes (A-1) Vin, and the output voltage Vout in the A-th hold phase HA becomes A · Vin. . Then, a series of sample and hold processes are completed in the hold phase HA, and the switch S1 is switched to the output terminal side of the operational amplifier 4, and the first A / D Vin is applied to the voltage A · Vin by the 1.5-bit A / D conversion circuit 2. D conversion operation is performed. The subsequent A / D conversion operation is the same as that of Patent Document 1.

Next, the noise suppression effect accompanying the above operation will be described. As described above, the on-resistance of each switch constituting the A / D converter 1 and the operational amplifier 4 and the like generate noise (thermal noise, etc.). Therefore, the analog voltage signal handled in the A / D conversion operation includes The noise is superimposed. For example, as shown in FIG. 3A, it is assumed that the sample-and-hold process is repeated six times and then the operation shifts to the A / D conversion operation. At this time, if the control for repeating the sample hold process six times is expressed by a transfer function H (z),
H (z) = (1 + z ⁻¹ + z ⁻² + z ⁻³ + z ⁻⁴ + z ⁻⁵ ) / 6 (10)
It becomes. That is, the above transfer function H (z) corresponds to an FIR (Finite Impulse Response) filter. Note that 1/6 is a coefficient for adjusting the gain.

  As shown in FIG. 3B, the frequency characteristic of the transfer function H (z) is as follows. When the sampling frequency is fs, as shown in FIG. 3B, the frequency fs / 2 is separated from the frequency ± fs / 5 and ± 2 fs / 5. It becomes the characteristic which a notch arises. Further, the gain in the pass band gradually attenuates from the frequency 0 and fs to the frequency fs / 2. The noise component is suppressed by this filter characteristic.

ここで、以上のようにして最終的に得られるＡ／Ｄ変換値は、電圧Ａ・ＶinをＡ／Ｄ変換したものである。したがって、外部信号電圧ＶinのＡ／Ｄ変換値は、得られたデータに１／Ａを乗じて求める。 FIG. 3C shows the reduction rate of noise output when the number of repetitions (number of additions) of the sample and hold process is changed for a random number generated on Excel (registered trademark) which is a spreadsheet software. Show. When the sample hold process is repeated 6 times, the reduction rate is a little over 40%, which is about 1 / √ (6) times. Note that the general expression of the transfer function H (z) when the number of additions is A is expressed by Expression (11).

Here, the A / D conversion value finally obtained as described above is an A / D conversion of the voltage A · Vin. Therefore, the A / D conversion value of the external signal voltage Vin is obtained by multiplying the obtained data by 1 / A.

  As described above, according to the present embodiment, the residual voltage generation circuit 12 generates a residual voltage obtained by amplifying a difference voltage between a voltage obtained by sample-holding an input voltage and a predetermined analog voltage. The input switching circuit 12 inputs either the external signal voltage Vin or the voltage Vout output from the residual voltage generation circuit 12 to the A / D conversion circuit 2 and the residual voltage generation circuit 12. The control circuit 10 changes the analog voltage in the residual voltage generation circuit 12 to a voltage corresponding to the D / A conversion value of the digital conversion value output from the A / D conversion circuit 2 and switches the input of the external signal voltage Vin. An A / D conversion operation is performed by circulating through the circuit 13, the A / D conversion circuit 2, and the residual voltage generation circuit 12.

  Then, the control circuit 10 of the present embodiment causes the sample and hold process to be executed a plurality of times, accumulates the sample voltage, causes the residual voltage generation circuit 12 to generate a residual voltage for the voltage resulting from the accumulation, and performs an A / D conversion operation. Execute. As a result, noise components included in the sample voltage due to each circuit element and the like are averaged and suppressed, so that the S / N ratio is improved. Therefore, the accuracy of the obtained converted value can be improved by A / D converting the accumulated sample voltage.

  Further, the residual voltage generation circuit 12 is connected to the common line 14 via the switches S2 and S3, and connected to the ground via the switches S4 and S5, with one end of the capacitors CS1 and CS2 as a common side electrode, and the other end. Is the non-common side electrode, and the capacitor array circuit 11 connected to any one of the reference voltage terminal 5, the ground and the input switching circuit 13 via the switches S6 and S7, and the voltage of the common line 14 as an input, the residual voltage An operational amplifier 4 that outputs Vout and capacitors CF1 and CF2 connected between input and output terminals of the operational amplifier 4 are provided.

  Then, the control circuit 10 performs the initial sample processing by setting the electric charge according to the external signal voltage Vin to the capacitors CS1 and CS2 via the input switching circuit 13, and subsequently the non-common of the capacitors CS1 and CS2 The side electrodes are connected to either the reference voltage terminal 5 or the ground, respectively, and hold processing is performed by performing charge redistribution between the capacitors CS1 and CS2 and the capacitors CF1 and CF2. In the second and subsequent sample processing, the other ends of the capacitors CS1 and CS2 are connected to the output terminal of the operational amplifier 4. Therefore, the sample and hold process can be repeatedly executed only by the control circuit 10 performing switching control of the switches S1 to S7 and S11.

  In the hold process, the control circuit 10 connects the non-common side electrode of the capacitor CS1 to the high-level reference voltage terminal 5 (Vrefp), and connects the non-common side electrode of the capacitor CS2 to the low-level reference voltage Vrefm. I tried to do it. Thereby, before and after the sample process and the hold process, the potential of the common line 14 determined by, for example, the charge QCS represented by the equation (3) becomes equal to the reference voltage of the operational amplifier 4; Therefore, the inside of the A / D converter 1 can be suppressed from being saturated due to an increase in the charge charge.

(Second Embodiment)
Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and different parts will be described. As shown in FIG. 4, the A / D converter 21 according to the second embodiment has a configuration in which an external signal voltage Vin is supplied to the signal input terminal 3 via an input buffer (driver) 22. That is, when the sample hold process is repeatedly executed, the sampling frequency is lowered accordingly.

  Therefore, the external signal voltage Vin is settled faster through the input buffer 22, and the sample phase and hold phase are executed faster. In addition, for example, as shown in FIG. 5, by setting the number of repetitions of the sample hold process to the minimum two times, a decrease in the sampling frequency is suppressed.

(Third embodiment)
As shown in FIG. 6, the A / D converter 23 of the third embodiment is similar to the A / D converter 21 of the second embodiment in that a switch S12, a capacitor CF3 (fourth A series circuit of a capacitor) and a switch S12. A switch S12 (bar) is connected between both ends of the capacitor CF3 and the ground. The control circuit 24 also controls the on / off of the switches S12 and S12 (bar). The two switches S12 are simultaneously turned on and off, and the on / off of the switch S12 (bar) is controlled to be opposite to that of the switch S12.

  Next, the operation of the third embodiment will be described. As shown in FIG. 7, the switch S12 is turned on during a period in which the sample hold process is repeatedly executed. That is, the capacitor CF3 is connected in parallel to the capacitors CF1 and CF2. Then, during the A / D conversion operation after the A-th hold phase HA ends, the switch S12 is turned off and the switch S12 (bar) is turned on. That is, the capacitor CF3 is disconnected from the capacitors CF1 and CF2. Hereinafter, it demonstrates similarly to 1st Embodiment.

<Reset and sample phase Sa1>
In this phase, the charge QCS charged in the capacitors CS1 and CS2 is
QCS = (CS1 + CS2) × Vin (12)
The charge QCF charged in the capacitors CF1 to CF3 is
QCF = (CF1 + CF2 + CF3) × 0 = 0 (13)
It becomes.

<Hold phase H1>
In this phase, the charge QCS charged in the capacitors CS1 and CS2 is
QCS = CS1 × Vrefp + CS2 × Vrefm (14)
The charge QCF charged in the capacitors CF1 to CF3 is
QCF = (CF1 + CF2 + CF3) × Vout (15)
It becomes.

となる。そして、（１７）式において、ＣＦ１＝ＣＦ２＝ＣＦ３＝ＣＳ１＝ＣＳ２，
Ｖrefp＝Ｖref／２，Ｖrefm＝−Ｖref／２に設定すれば、Ｖout＝２・Ｖin／３となる。 From the law of conservation of charge,
(CS1 + CS2) × Vin = CS1 × Vrefp + CS2 × Vrefm
+ (CF1 + CF2 + CF3) × Vout (16)
It becomes. When the output voltage Vout of the operational amplifier 4 is obtained from the equation (16),

It becomes. In the equation (17), CF1 = CF2 = CF3 = CS1 = CS2,
If Vrefp = Vref / 2 and Vrefm = −Vref / 2 are set, Vout = 2 · Vin / 3.

<Sample phase Sa2>
In this phase, the charges QCS charged in the capacitors CS1 and CS2 are the same as in the equation (12), and the charges QCF charged in the capacitors CF1 to CF3 are
QCF = (CF1 + CF2 + CF3) × 2 · Vin / 3 (18)
It becomes.

となるが、各コンデンサの容量及び基準電圧Ｖrefp，Ｖrefmについて上述した設定条件より、Ｖout＝２・（２・Ｖin／３）となる。 <Hold phase H2>
In the subsequent hold phase H2, each switch is switched to the same state as in the phase H1. At this time, the charge QCS charged in the capacitors CS1 and CS2 and the charge QCF charged in the capacitors CF1 and CF2 are the same as the equations (14) and (15), respectively. Then, from the law of conservation of charge,
(CS1 + CS2) × Vin + (CF1 + CF2 + CF3) × 2 · Vin / 3
= CS1 × Vrefp + CS2 × Vrefm + (CF1 + CF2 + CF3) × Vout
... (19)
It becomes. When the output voltage Vout of the operational amplifier 4 is obtained from the equation (19),

However, Vout = 2 · (2 · Vin / 3) from the setting conditions described above for the capacitance of each capacitor and the reference voltages Vrefp and Vrefm.

  Thereafter, when the sample phase and the hold phase are repeatedly executed in the same manner, the output voltage Vout in the Ath sample phase SaA becomes (A-1) · (2 · Vin / 3), and the output voltage in the Ath hold phase HA. Vout becomes A · (2 · Vin / 3). That is, the output voltage Vout is 2/3 as compared with the first embodiment.

  As described above, according to the third embodiment, the capacitor CF3 that can be connected in parallel to the capacitors CF1 and CF2 via the switch S12 is provided, and the control circuit 24 performs the capacitor CF3 when executing the sample hold processing. Are connected in parallel to the capacitors CF1 and CF2. Therefore, it is possible to suppress voltage saturation within the A / D converter 23.

(Fourth embodiment)
As shown in FIG. 8, the A / D converter 25 of the fourth embodiment has a digital processing unit 26 (data processing unit) arranged on the output side of the adder 8. As described in the first embodiment, the A / D conversion value finally obtained in the A / D converter 1 is obtained by A / D converting the voltage A · Vin. By multiplying 1 / A, an A / D conversion value corresponding to the voltage Vin is output to the outside. For example, by writing and setting the number of repetitions of the sample and hold process (the number of additions of the voltage Vin) A in the memory 27, the control circuit 10A executes the sample and hold process according to the number of times A. The digital processing unit 26 also multiplies the A / D conversion value by the coefficient 1 / A based on the number of times A set in the memory 27.

Note that the A / D conversion value and the noise level when the sample-and-hold processing of the voltage Vin is repeated A times, A / D conversion is performed with M bits, and 1 / A is multiplied are expressed as follows.
A / D conversion value: Vout [LSB @ Mbit]
Noise level: Vn / √ (A) × [LSB @ Mbit]
If the sample and hold process is performed only once, the noise level is Vn [LSB @ Mbit].
As described above, according to the fourth embodiment, the A / D converter 25 includes the digital processing unit 26 that divides the A / D conversion value by the number of executions of the sample hold process and outputs the result. There is no need to perform A / D conversion value division processing outside the D converter 24.

(Fifth embodiment)
As shown in FIG. 9, the A / D converter 31 of the fifth embodiment has a configuration corresponding to the case where the external signal voltage Vin is input as the differential signals Vinp and Vinm. It corresponds. The A / D conversion circuit 32 includes positive and negative input terminals, and a switch S1p is connected to the positive input terminal, and a switch S1m is connected to the negative input terminal. The operational amplifier 34 (operational amplifier) that constitutes the residual voltage generation circuit 33 is also configured to support differential input / output, and a switch S11p is connected between the inverting input terminal and the positive output terminal, and the non-inverting input terminal. And a negative output terminal are connected to a switch S11m.

  Then, the positive external signal voltage Vinp and the positive output voltage Voutp of the operational amplifier 34 are switched and input to the positive input terminal of the A / D conversion circuit 32 via the switch S1p. Further, the negative side input signal is switched to the negative side external signal voltage Vinm and the negative side output voltage Voutm of the operational amplifier 34 via the switch S1m.

  One end of the capacitors CF1p and CF2p is connected to the positive output terminal of the operational amplifier 34, and the other end is connected to the inverting input terminal of the operational amplifier 34. One ends of the capacitors CS1p and CS2p are connected to the switches S6p and S7p, respectively, and the other ends are connected to the inverting input terminal of the operational amplifier 34 via the switches S2p and S3p, respectively. The other ends of the capacitors CS1p and CS2p are connected to the ground via switches S4p and S5p, respectively.

  The non-inverting input terminal side of the operational amplifier 34 is configured symmetrically with the inverting input terminal side by capacitors CF1m, CF2m, CS1m, CS2m and switches S2m to S7m. The capacitor array circuit 35 includes capacitors CS1p, CS2p, CS1m, and CS2m. The input switching circuit 36 includes switches S1p to S7p and S1m to S7m. The control circuit 37 controls on / off of the switches S1p to S7p, S1m to S7m, and the switches S11p and S11m.

  When it is necessary to execute the sample and hold process faster as in the second embodiment, the external signal voltages on the positive side (Vsp) and negative side (Vsm) are supplied by the differential driver (input buffer) 38. In response, the positive external signal voltage Vinp and the negative external signal voltage Vinm may be output. As in the first embodiment, the A / D converter 31 performs sample / hold processing a plurality of times on the difference voltage between the positive external signal voltage Vinp and the negative external signal voltage Vinm, and then performs A / D conversion. Do.

  As described above, according to the fifth embodiment, the A / D converter 31 performs A / D conversion by repeating the sample and hold process a plurality of times for the difference voltage between the input signal voltages Vinp and Vinm. The noise component can be suppressed similarly to the above, and the common mode noise from the outside can be effectively removed. Therefore, erroneous conversion due to noise can be further prevented.

(Sixth embodiment)
10 and 11 show a sixth embodiment, and shows a case where the present invention is applied to the configuration of Patent Document 2. FIG. The cyclic A / D converter 41 shown in FIG. 10 is based on the configuration disclosed in FIG. 1 of Patent Document 2, and the same reference numerals as those in FIG. Yes. That is, the A / D converter 41 includes a switching circuit 105 (input circuit), a multiplying D / A converter (residual voltage generation circuit) 106, an A / D conversion circuit 107, a control circuit 108, and an operational amplifier 109 (operational amplifier). ), A switch S17 (reset switch circuit) is added to the configuration of Patent Document 2 including the capacitor array circuit 110 and the like, and the switch S17 is connected between the signal input terminal 103 and the ground.

  The control circuit 108 also clearly indicates that it also has a function as a drive circuit that applies drive voltages VDD (high level) and VGND (low level) to the sensor element 101 (signal source) of the capacitive acceleration sensor. ing. Two NOT gates 42 and 43 are connected in series to the output terminal of the control circuit 108, the output terminal of the NOT gate 42 is connected to the terminal FE2 of the sensor element 101, and the output terminal of the NOT gate 43 is the same terminal. Connected to FE1. The sensor element 101 is represented by a series circuit of two capacitors CE1 and CE2 in an equivalent circuit, and the terminals FE1 and FE2 are both ends of the series circuit.

  The A / D converter 41 performs C / V conversion on the signal charge Sin (change in capacitance of the capacitors CE1 and CE2, which corresponds to the external signal charge) input to the signal input terminal 103, and amplifies the amplified signal charge. The converted voltage is A / D converted and an N-bit A / D conversion code is output. The A / D converter 41 can also amplify the signal voltage Vin input to the signal input terminal 104, A / D convert the amplified voltage, and output an N-bit A / D conversion code. It is.

Next, the operation of the sixth embodiment will be described.
(1) C / V Conversion Operation In phase A shown in FIG. 11, the control circuit 108 executes a C / V conversion operation (corresponding to a voltage conversion operation) prior to the amplification operation and the A / D conversion operation. That is, the driving voltage VDD is applied to the terminal FE1 and the driving voltage VGND is applied to the terminal FE2 of the sensor element 101, and the switching circuit 105 is switched to the multiplying D / A converter 106 side and the switches S10 and S11 are switched to the switching circuit 105 side. .

  Further, the switches S1 (input switching circuit), S2, S13, S14, and S16 are turned on, the switches S3, S12 (switch circuit), S15, and S17 are turned off, and the capacitors CG (first integrating capacitor), CS10, and CS11 ( The charge of the array capacitor) and CF (second integration capacitor) is initialized. This charge initialization operation corresponds to “reset” of the C / V conversion operation.

In the subsequent phase, the level of the drive voltage applied to the terminals FE1 and FE2 is inverted, the switch S14 is turned off, and the capacitor CF is set with the signal charge Sin (Sampling). This charge setting operation corresponds to “conversion” of the C / V conversion operation. Here, from the charge conservation law, the total charge in phase A is equal to the total charge in phase B.
CE1 x VDD + CE2 x VGND
= CG * Vo1 + CE1 * VGND + CE1 * VDD (20a)
Vo1 is the output voltage of the operational amplifier 109 in phase B.

Further, when the capacitance change of the sensor element 101 at this time is ΔC1,
Since CE1 = CE + ΔC1 / 2 and CE2 = CE−ΔC1 / 2, the output voltage Vo1 is obtained from the equation (20a).
Vo1 = ΔC1 / CG (VDD−VGND) (21)
It becomes.

  In the next phase C (reset phase), the level of the drive voltage applied to the terminals FE1 and FE2 is inverted again to turn on the switch S17 and turn off the switch S1 (reset). In the subsequent phase D (conversion phase), the level of the drive voltage applied to the terminals FE1 and FE2 is inverted again to turn off the switch S17 and turn on the switch S1 (conversion). Thereafter, after repeatedly executing phases C and D in the same manner, (2) amplification operation and (3) A / D conversion operation are executed. These operations are executed in the same manner as in Patent Document 2.

From the charge conservation law, the total charge in phase C is equal to the total charge in phase D.
CE1 x VDD + CE2 x VGND + Vo1
= CG * Vo2 + CE1 * VGND + CE1 * VDD (22)
Vo2 is an output voltage of the operational amplifier 109 in the phase D.

In addition, when the capacitance change of the sensor element 101 at this time is ΔC2,
Since CE1 = CE + ΔC2 / 2 and CE1 = CE−ΔC2 / 2, when the output voltage Vo2 is obtained from the equation (22),
Vo2 = Vo1 + ΔC2 / CG (VDD−VGND) (23)
It becomes.

となる。すなわち、出力電圧ＶｏＮは、電位差（ＶＤＤ−ＶＧＮＤ）にゲインΔＣｘ／ＣＧを乗じてＮ回加算した電圧である。 Therefore, the output voltage VoN of the operational amplifier 109 after performing the C / V conversion operation N times is

It becomes. That is, the output voltage VoN is a voltage obtained by multiplying the potential difference (VDD−VGND) by the gain ΔCx / CG and adding N times.

  As described above, according to the sixth embodiment, the multiplying D / A converter 106 generates a residual voltage obtained by amplifying the difference voltage between the input voltage of the A / D conversion circuit 107 and a predetermined analog voltage, The switch S5 inputs the voltage Vo output from the D / A converter 106 to the A / D conversion circuit 107 and the D / A converter 106. The switch S1 switches whether to input the signal charge Sin to the input terminal of the D / A converter 106.

  The control circuit 108 inputs the signal charge Sin to the D / A converter 106 via the switch S1, and repeats the C / V conversion operation for outputting a voltage corresponding to the signal charge Sin from the D / A converter 106 a plurality of times. And execute. The output voltage Vo is set to the D / A conversion value of the digital conversion value output from the A / D conversion circuit 107, and the conversion voltage of the signal charge Sin is changed to the switching circuit 105, the A / D conversion circuit 107, and D. The A / D conversion operation is performed by circulating through the / A converter 106.

  Specifically, in the D / A converter 106, one end of the capacitors CS10 and CS11 is connected to the common line 111 as a common side electrode, and the other end is connected to a plurality of reference voltage lines (Vrefp, Vrefm) as non-common side electrodes. The capacitor array circuit 110 to be connected, the operational amplifier 109 that receives the voltage of the common line 111, the switch S12 that is interposed in the signal path from the common line 111 to the operational amplifier 109, and the input / output terminal of the operational amplifier 109 can be connected. An integrating capacitor CF, CG was provided.

  The control circuit 108 includes a switch S17 for discharging the signal charge Sin to the ground and resetting it. The control circuit 108 turns off the switch S17 to initialize the capacitors CF and CG. Subsequently, the capacitor CG is connected to the input / output terminal of the operational amplifier 109. In addition, while the switch S17 is turned off, charges corresponding to the signal charge Sin are set in the capacitors CF and CG via the switch S1. Further, the first C / V conversion operation is executed by outputting the conversion voltage Vo corresponding to the terminal voltages of the capacitors CF and CG from the operational amplifier 109.

  In the subsequent C / V conversion operation, the switch S1 is turned off to turn on the switch S17 without inputting the signal charge Sin, and the switch S17 is turned off and the switch S1 is turned on to turn on the signal charge. Phase D in which Sin is input is repeatedly executed. Thereby, the conversion voltage Vo can be accumulated and the noise level can be suppressed as in the first embodiment. Therefore, the accuracy of the A / D conversion value can be improved.

(Seventh embodiment)
The cyclic A / D converter 51 of the seventh embodiment shown in FIG. 12 has a configuration corresponding to the case where the signal charge is input as the differential signal charges Sinp and Sinm in the configuration of the sixth embodiment. This corresponds to the configuration disclosed in FIG. That is, the A / D converter 51 includes switches S1p and S1m (input switching circuit), switching circuits 105p and 105m (input circuit), an A / D conversion circuit 132, and a multiplying D / A converter (residual voltage generation circuit). ) 133, an operational amplifier 134 (operational amplifier), a control circuit 135, a capacitor array circuit 110p, 110m, and the like. In this configuration, switches S17p, S17m (reset switch circuit) are added. The control circuit 135 outputs a drive voltage to the terminal FE of the sensor element 101 (a common connection point between the capacitors CE1 and CE2) via the NOT gates 42 and 43.

The operation timing chart of the A / D converter 51 is the same as that shown in FIG. 11 of the sixth embodiment, and ON / OFF of the corresponding switches on the positive side and the negative side is similarly controlled. From the charge conservation law, the total charge in phase A is equal to the total charge in phase B.
CE1 × VDD = CG × Vop1 + CE1 × VGND (25)
CE2 × VDD = CG × Vom1 + CE2 × VGND (26)
Vop1 and Vom1 are the positive and negative output voltages of the operational amplifier 134 in the phase B.

When (Vop1−Vom1) is obtained by subtracting equation (26) from equation (25),
Vop1−Vom1 = (CE1−CE2) / CG × (VDD−VGND) (27)
Since CE1 = CE + ΔC1 / 2 and CE2 = CE−ΔC1 / 2,
Vop1−Vom1 = ΔC1 / CG × (VDD−VGND) (28)
It becomes.

Also, from the charge conservation law, the total charge in phase C and the total charge in phase D are equal,
CE1 × VDD + CG × Vop1 = CG × Vop2 + CE1 × VGND (29)
CE2 × VDD + CG × Vom1 = CG × Vom2 + CE2 × VGND (30)
Vop2 and Vom2 are the positive and negative output voltages of the operational amplifier 134 in phase B.

When (Vop2-Vom2) is obtained by subtracting equation (30) from equation (29),
Vop2-Vom2 = (Vop1-Vom1)
+ (CE1-CE2) / CG × (VDD−VGND) (31)
Also, since CE1 = CE + ΔC2 / 2 and CE1 = CE−ΔC2 / 2,
Vop2-Vom2 = (Vop1-Vom1)
+ ΔC2 / CG × (VDD−VGND) (32)
It becomes.

となる。すなわち、差電圧（ＶopN−ＶomN）は、電位差（ＶＤＤ−ＶＧＮＤ）にゲインΔＣｘ／ＣＧを乗じてＮ回加算した電圧である。 Therefore, the differential voltage (VopN−VomN) after the C / V conversion operation is repeated N times is

It becomes. That is, the difference voltage (VopN−VomN) is a voltage obtained by multiplying the potential difference (VDD−VGND) by N times by multiplying the gain ΔCx / CG.

  As described above, according to the seventh embodiment, the A / D converter 51 includes the switches S1p and S1m, the switches S17p and S17m, the switching circuits 105p and 105m, the A / D conversion circuit 132, and the multiplying D / A conversion. The device 133 is configured to be capable of differential operation. As a result, noise components can be suppressed as in the sixth embodiment, and common mode noise from the outside can also be effectively removed. Therefore, erroneous conversion due to noise can be further prevented.

(Eighth embodiment)
As shown in FIG. 13, the A / D converter 51A of the eighth embodiment is obtained by slightly changing the connection of the A / D converter 51 of the seventh embodiment, and one end of the switch S17p is changed to the ground. It is connected to the non-inverting input terminal of the operational amplifier 134 (the output side terminal of the signal charge Sinm in the switch S1m). One end of the switch S17m is also replaced with the ground, and the inverting input terminal of the operational amplifier 134 (the output of the signal charge Sinp in the switch S1p). Side terminal).

  Next, the operation of the eighth embodiment will be described. As shown in FIG. 14, the phase B1 (first C / V conversion operation) immediately after the phase A and the drive voltage are switched to VGND are the same as in the seventh embodiment. Therefore, the difference voltage (Vop1−Vom1) obtained from the equation that holds for the phase A and the phase B1 based on the law of conservation of charge is the same as the equation (28).

The control circuit 135A switches each switch to the phase C state slightly faster than the timing for switching the drive voltage to VDD. This state is defined as phase B2 (second C / V conversion operation) switched from phase B1. Thereafter, the state where the drive voltage is switched to VDD is referred to as phase C of the eighth embodiment. In this case, from the charge conservation law for the total charge in phase B2 and the total charge in phase C,
CE1 * VGND + CG * Vop1 = CG * Vop2 + CE1 * VDD (34)
CE2 × VGND + CG × Vom1 = CG × Vom2 + CE2 × VDD (35)
When (Vop2−Vom2) is obtained by subtracting (35) from (34), (32) is obtained. Therefore, the differential voltage (VopN−VomN) after the C / V conversion operation is repeatedly executed N times is the same as the equation (33).

  As described above, according to the eighth embodiment, when the sensor elements 101 alternately apply the drive voltages VDD and VGND to the terminal FE that is a common connection point of the series circuit of the capacitors CE1 and CE2, both ends of the series circuit are provided. The positive and negative signal charges Sinp and Sinm are generated at the terminals FE1 and FE2. Then, the A / D converter 51A includes switches S17p and S17m for switching between the input side terminals of the signal charges Sinp and Sinm in the switches S1p and S1m and the non-inverting input terminal and the inverting input terminal of the operational amplifier 134, respectively. Is provided.

  The control circuit 135A applies a drive voltage to the terminal FE of the sensor element 101 and turns off the switches S1p and S1m to initialize the capacitors CFp, CGp, CFm, and CGm. Subsequently, the capacitors CGp and CGm are connected between the input and output terminals of the operational amplifier 134, and with the switches S17p and S17m turned off, the charges corresponding to the signal charges Sinp and Sinm are passed through the switches S1p and S1m. The first C / V conversion operation is executed by setting the CGm and outputting the conversion voltages Vop1 and Vom1 according to the terminal voltages of the capacitors CFp to CGm from the operational amplifier 134.

  In the subsequent C / V conversion operation, the switches S17p and S17m are turned on, the switches S1p and S1m are turned off, the signal charge Sinp is input to the non-inverting input terminal of the operational amplifier 134, and the signal charge Sinm is input to the inverting input of the operational amplifier 134. A first C / V conversion operation in which charge is transferred by setting a drive voltage at a level different from that of the first C / V conversion operation to the terminal FE, and switches S17p and S17m are turned off and switches S1p, After S1m is turned on and the signal charge Sinp is input to the inverting input terminal of the operational amplifier 134 and the signal charge Sinm is input to the non-inverting input terminal of the operational amplifier 134, a driving voltage of a level different from the first C / V conversion operation is set. Then, the second C / V conversion operation for performing charge transfer is repeatedly executed.

  As a result, the C / V conversion operation is performed every time the edge of the drive voltage applied to the terminal FE of the sensor element 101 changes, so that the reset phase in the seventh embodiment becomes unnecessary. Therefore, the execution time of the C / V conversion operation necessary to obtain the conversion voltage Vo at the same level is ½ that of the seventh embodiment, and the A / D conversion result can be obtained more quickly.

(Ninth embodiment)
As shown in FIG. 15, the A / D converter 61 of the ninth embodiment performs C / V conversion on the signal charge Sin generated by the sensor element 101 using the configuration of the first embodiment. In this case, the terminal FE, which is a common connection point of the capacitors CE and CE2 constituting the sensor element 101, is connected to the inverting input terminal of the operational amplifier 4 through the switch S12 and to the ground through the switch S13. Further, the control circuit 62 applies a drive voltage to both ends of the sensor element 101 via NOT gates 42 and 43 as in the sixth embodiment. If comprised in this way, capacitance change (DELTA) C of the sensor element 101 can be added to the capacity | capacitance of capacitor | condenser CF1, CF2, and A / D conversion can be carried out.

(10th Embodiment)
As illustrated in FIG. 16, the A / D converter 71 of the tenth embodiment performs C / V conversion on the signal charge Sin generated by the sensor element 101 using the configuration of the fifth embodiment. In this case, one end FE1 of the sensor element 101 is connected to the inverting input terminal of the operational amplifier 34 via the switch S13p and to the ground via the switch S14p. Further, the other end FE2 of the sensor element 101 is connected to the non-inverting input terminal of the operational amplifier 34 via the switch S13m, and is connected to the ground via the switch S14m.

  Then, the control circuit 72 applies a drive voltage to the terminal FE of the sensor element 101 via the NOT gates 42 and 43 as in the ninth embodiment. With this configuration, the capacitance change ΔC of the sensor element 101 can be added to the capacitance of the capacitors CF1p, CF2p, CF1m, and CF2m to perform A / D conversion.

(Eleventh embodiment)
As shown in FIG. 17, the A / D converter 81 according to the eleventh embodiment is similar to the eighth embodiment except that one end of each of the switches S14p and S14m is replaced with the ground in the configuration of the tenth embodiment. The configuration is connected to the non-inverting input terminal and the inverting input terminal. With this configuration, the time required for C / V conversion can be shortened in the configuration of the tenth embodiment as in the eighth embodiment.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above or described in drawing, The following deformation | transformation or expansion is possible.
The low-level reference voltage Vrefm is not necessarily a negative voltage, and may be, for example, a ground level, or may be a potential lower than the reference voltage Vrefp.
The resolution of the A / D conversion circuit 2 is not limited to 1.5 bits and can be changed as appropriate.

The digital processing unit 26 of the fourth embodiment may be applied to the configurations of the second, third, and seventh to eleventh embodiments.
In the fourth embodiment, the memory 27 may be provided as necessary, and the number of additions A may be a fixed value.
For example, in the hold processing according to the first embodiment, the reference voltage applied to the non-common side electrodes of the capacitors CS1 and CS2 may be set to a high level or both may be set to a low level.

  In the drawings, 1 is an A / D converter, 2 is an A / D converter circuit, 4 is an operational amplifier (operational amplifier), 5 is a reference voltage terminal (reference voltage line), 10 is a control circuit, 11, 11p, and 11m are capacitors. An array circuit, 12 is a residual voltage generation circuit, 13 is an input switching circuit, 14 is a common line, 25 is a digital signal processing unit (signal processing unit), CS1, CS1p, CS1m are first capacitors, CS2, CS2p, CS2m are The second capacitor, CF1, CF2, CF, CFp, and CFm are third capacitors, GND is a ground terminal (reference voltage line), and S31, S31p, and S31m are switches (input switching circuits).

Claims (13)

An A / D conversion circuit (2, 21, 32);
A residual voltage generation circuit (12, 33) for generating a residual voltage obtained by amplifying a difference voltage between a voltage obtained by sampling and holding an input voltage and a predetermined analog voltage;
An input switching circuit (13, 35) for inputting any one of an external signal voltage and a voltage output from the residual voltage generation circuit to the A / D conversion circuit and the residual voltage generation circuit;
The residual voltage generation circuit is controlled, and an analog voltage in the residual voltage generation circuit is set to a voltage corresponding to a D / A conversion value of a digital conversion value output from the A / D conversion circuit. A control circuit (10, 62, 72) that performs an A / D conversion operation by circulating a voltage through the input switching circuit, the A / D conversion circuit, and the residual voltage generation circuit;
The control circuit executes the A / D conversion operation by causing the residual voltage generation circuit to generate a residual voltage for the voltage obtained as a result of the accumulation by performing the sample hold process a plurality of times and accumulating the sample voltage. An A / D converter characterized by the above. The residual voltage generation circuit includes:
The first and second capacitors (CS1, CS2) are provided, one end of the first and second capacitors is connected to the common line as a common side electrode, and the other end is a plurality of reference voltage lines as non-common side electrodes, A capacitor array circuit (11) connected to any of the input switching circuits;
An operational amplifier (4, 34) for inputting the voltage of the common line and outputting the residual voltage;
A third capacitor (CF1, CF2) connected between the input and output terminals of the operational amplifier,
The control circuit performs an initial sample process by setting a charge corresponding to the external signal voltage to the first and second capacitors via the input switching circuit,
Subsequently, the non-common side electrodes of the first and second capacitors are respectively connected to any of the plurality of reference voltage lines, and electric charges are generated between the first and second capacitors and the third capacitor. Hold process by redistribution,
2. The A / D converter according to claim 1, wherein in the second and subsequent sample processing, the other ends of the first and second capacitors are connected to an output terminal of the operational amplifier. The reference voltage provided by the plurality of reference voltage lines is a binary level of high and low;
In the hold process, the control circuit connects the non-common side electrode of one of the first and second capacitors to the high-level reference voltage line, and connects the other non-common side electrode to the low level. The A / D converter according to claim 2, wherein the A / D converter is connected to a reference voltage line. A fourth capacitor (CF3) connectable in parallel to the third capacitor;
4. The A / D converter according to claim 2, wherein the control circuit connects the fourth capacitor to the third capacitor in parallel when executing the sample hold processing. 5.   The A / D converter according to any one of claims 1 to 4, wherein an input buffer (22) is arranged on an input side of the residual voltage generation circuit.   6. The A / D conversion circuit (32), the residual voltage generation circuit (33), and the input switching circuit (35) are configured to be capable of differential operation, respectively. The A / D converter according to any one of the above.   The A / D according to any one of claims 1 to 6, further comprising a data processing unit (26) for dividing and outputting an A / D conversion value by the number of executions of the sample and hold process. converter. An A / D conversion circuit (107);
A residual voltage generation circuit (106) for generating a residual voltage obtained by amplifying a difference voltage between the input voltage of the A / D conversion circuit and a predetermined analog voltage;
An input circuit (105) for inputting a voltage output from the residual voltage generation circuit to the A / D conversion circuit and the residual voltage generation circuit;
An input switching circuit (S1) for switching whether or not to input an external signal charge to the input terminal of the residual voltage generation circuit;
The external signal charge is input to the residual voltage generation circuit via the input switching circuit, and a voltage conversion operation for outputting a voltage corresponding to the external signal charge from the residual voltage generation circuit is repeatedly performed a plurality of times,
After that, the analog voltage in the residual voltage generation circuit is set as the D / A conversion value of the digital conversion value output from the A / D conversion circuit, and the conversion voltage of the external signal charge is set as the input circuit, the A / D An A / D converter comprising: a control circuit (108, 135) that executes an A / D conversion operation by circulating through a D conversion circuit and the residual voltage generation circuit. The residual voltage generation circuit includes:
One or a plurality of array capacitors (CS10, CS11) are provided, and one end of each array capacitor is connected to the common line (111) as a common side electrode, and the other end is connected to a plurality of reference voltage lines as a non-common side electrode. A capacitor array circuit (110),
An operational amplifier (109, 134) that receives the voltage of the common line as an input;
A switch circuit (S12) interposed in a signal path from the common line to the operational amplifier;
9. An A / D converter according to claim 8, comprising an integrating capacitor (CF, CG) connectable between input and output terminals of the operational amplifier. A reset switch circuit (S17) for discharging and resetting the external signal charge to the ground;
The control circuit (108)
Turning off the reset switch circuit to initialize the integrating capacitor;
Subsequently, the integration capacitor is connected between the input and output terminals of the operational amplifier, and the charge corresponding to the external signal charge is set in the integration capacitor via the input switching circuit with the reset switch circuit turned off. The first voltage conversion operation is executed by outputting a conversion voltage corresponding to the terminal voltage of the integration capacitor from the operational amplifier,
The subsequent voltage conversion operation includes a reset phase in which the reset switch circuit is turned on without inputting the external signal charge by the input switching circuit,
10. The A / D converter according to claim 9, wherein the reset switch circuit is turned off and a conversion phase in which the external signal charge is input by the input switching circuit is repeatedly executed. 11.   The A / D conversion circuit (132), the residual voltage generation circuit (133), the input circuit (105p, 105m), the input switching circuit (S1p, S1m) and the reset switch circuit (S17p, S17m) are respectively 11. The A / D converter according to claim 10, wherein the A / D converter is configured to be capable of differential operation. An equivalent circuit of the signal source (101) that generates the external signal charge is represented by a series circuit of two capacitors (CE1, CE2), and a binary level drive voltage is applied to a common connection point (FE) of the two capacitors. It generates positive and negative external signal charges at both ends of the series circuit when applied alternately.
The A / D conversion circuit (132), the residual voltage generation circuit (133), the input circuit, and the input switching circuit (105p, 105m) are each configured to be capable of differential operation,
Positive side and negative side for intermittent connection between the external signal charge input side terminal in the positive side and negative side input switching circuit and the external signal charge output side terminal in the negative side and positive side input switching circuit, respectively A switch circuit (S17p, S17m) is provided.
The control circuit (135) applies the drive voltage to the signal source,
Turning off the positive and negative switch circuits to initialize the integrating capacitor;
Subsequently, the integration capacitor is connected between the input and output terminals of the operational amplifier, and with the switch circuit interposed in the signal path turned off, the charge corresponding to the external signal charge is passed through the input switching circuit. Set the integration capacitor, and execute the first voltage conversion operation by outputting the conversion voltage according to the terminal voltage of the integration capacitor from the operational amplifier,
In the subsequent voltage conversion operation, the first voltage conversion operation is performed at the common connection point of the signal source without turning on the positive and negative side switch circuits and inputting the external signal charge by the input switching circuit. A first voltage conversion operation for setting a driving voltage of a level different from that and performing charge transfer;
After the positive-side and negative-side switch circuits are turned off and the external signal charge is input by the input switching circuit, the charge transfer is performed by setting a drive voltage at a level different from that of the first voltage conversion operation. The A / D converter according to claim 9, wherein the two-voltage conversion operation is repeatedly executed.   The A / D converter according to any one of claims 8 to 12, further comprising a data processing unit that divides an A / D conversion value by the number of executions of the voltage conversion process and outputs the divided value.

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