JP2016091362A - Information processing device, information processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device, an information processing method and a program for the purpose which can efficiently execute an instruction with a relatively small amount of hardware even when there are many arithmetic resources.SOLUTION: A first time until timing when the influence of a scheduled instruction with a use resource coinciding therewith on an instruction of an instruction issue standby buffer 210 disappears is calculated, and the first time is stored in an inter-instruction dependence counter 213. Counter set value generation means 232 calculates a second time until timing when a path conflict in a computing element pipeline does not occur, and stores the second time in a path conflict counter 214. Scheduling determination instruction influence reflection means 231 calculates a previous instruction influence reflection value showing an influence which is given by an execution-determined instruction to an instruction selected just after. A conflict arbitration means 221 compares a value of the inter-instruction dependence counter 213, with a value of the path conflict counter, and with the previous instruction influence reflection value to calculate an execution waiting time of the shortest instruction.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program therefor.

  Patent Document 1 provides a busy management counter corresponding to a calculation resource and a register, inputs a busy management counter value of a related calculation resource in an execution waiting instruction execution determination, and calculates a timing at which it can be issued at the fastest speed from the value. A technique is disclosed in which a subsequent instruction having a relation of R → W (read → write) can be issued at the fastest timing by determining the issue waiting time.

  Patent Document 2 discloses a vector processing device capable of overtaking and issuing instructions using a busy flag.

  Patent Document 3 discloses an information processing apparatus that can perform processing without reducing the usage efficiency of a pipeline arithmetic unit even when the update of the busy flag is delayed.

JP 2012-173755 A JP 2008-269067 A JP 2011-060048 A

  Patent Document 1 assumes a busy management counter for each computing resource, and there is a problem in that the amount of hardware required increases when there are many computing resources. In addition, when the number of computing resources increases, there is a problem that it is difficult to implement a high-speed clock when realizing a function of selecting and comparing values from the corresponding busy management counter.

  Patent Document 2 uses a busy flag and has the same problem as Patent Document 1.

  Also, Patent Document 3 uses a busy flag and has the same problem as Patent Document 1.

  Thus, in the above-mentioned patent document, it is necessary to provide the number of busy management counters corresponding to the operation resources and registers. Therefore, the amount of hardware increases as the number of management targets increases. Also, as the number of management targets increases, the number of busy management counters also increases. Therefore, it is necessary to input and compare a number of busy management counter values when determining the execution of an instruction. For this reason, there is a problem that the circuit delay increases and it is difficult to cope with a high-speed clock.

  Therefore, an object of the present invention is to solve the above-described problem that the amount of hardware increases as the number of computing resources to be managed increases, making it difficult to cope with a high-speed clock.

  An information processing apparatus according to the present invention is an information processing apparatus in which pipeline processing means controls pipeline processing execution means for executing pipeline processing of an arithmetic unit pipeline, wherein the pipeline control means is configured to wait for issuing an instruction. A counter corresponding to the first time is calculated in the inter-instruction dependency counter by calculating a first time until an instruction existing in the buffer matches a resource to be used and when the influence of the scheduled instruction is eliminated. Counter set value generation means for storing a value, calculating a second time until a timing at which no path contention occurs in the computing unit pipeline, and storing a counter value corresponding to the second time in a path contention counter; A schedule to calculate the value that reflects the effect of the immediately preceding instruction, indicating the effect that the confirmed instruction has on the instruction selected immediately after The calculation instruction waiting time of the shortest instruction is calculated by comparing the counter value of the instruction for determining the influence of the ringing instruction, the counter value of the inter-instruction dependency counter, the counter value of the path conflict counter, and the reflection value of the immediately preceding instruction influence. Competing mediation means.

  The information processing method of the present invention calculates the first time until the timing at which the influence of the scheduled instruction that the resource to be used matches with the instruction existing in the instruction issue waiting buffer is eliminated, and the inter-instruction dependency The counter value corresponding to the first time is stored in the counter, the second time until the timing at which no path contention occurs in the computing unit pipeline is calculated, and the path contention counter corresponds to the second time. The counter value is stored, and the immediately preceding instruction influence reflection value indicating the influence of the instruction that has been confirmed to be executed on the immediately selected instruction is calculated, and the counter value of the inter-instruction dependency counter and the counter value of the path conflict counter are calculated. And the previous instruction influence reflection value is compared to calculate the execution waiting time of the shortest instruction.

  The computer program according to the present invention calculates a first time until a timing at which the influence of a scheduled instruction that matches resources used for an instruction existing in an instruction issuance waiting buffer is eliminated, and an inter-instruction dependency counter A counter value corresponding to the first time is stored, a second time until a timing at which no path contention occurs in the computing unit pipeline is calculated, and a counter corresponding to the second time is calculated in a path contention counter A process of storing a value, a process of calculating an immediately preceding instruction influence reflecting value indicating an influence of an instruction whose execution has been confirmed on an immediately selected instruction, a counter value of the inter-instruction dependency counter, and the path contention counter And a process of calculating the execution waiting time of the shortest instruction by comparing the counter value of To be executed by a computer.

  The present invention can efficiently execute instructions with a relatively small amount of hardware even when there are many computing resources.

FIG. 1 is a block diagram illustrating an example of the configuration of the information processing apparatus according to the first embodiment. FIG. 2 is a diagram illustrating an example of the configuration of the pipeline processing execution unit. FIG. 3 is a diagram illustrating an example of the configuration of the pipeline control unit. FIG. 4 is a time chart showing the operation of the information processing apparatus. FIG. 5 shows a decoding table (counter value decoding correspondence table) used for decoding the counter value. FIG. 6 is a diagram showing details of the operation of FIG. 4 for each clock. FIG. 7 is a diagram showing details of the operation of FIG. 4 for each clock. FIG. 8 is a diagram showing details of the operation of FIG. 4 for each clock. FIG. 9 is a diagram showing details of the operation of FIG. 4 for each clock. FIG. 10 is a diagram showing details of the operation of FIG. 4 for each clock. FIG. 11 is a time chart showing the operation of the information processing apparatus in the case of a configuration with only four scheduled instruction buffers. FIG. 12 is a time chart showing the operation of the information processing apparatus when different instruction sequences are used. FIG. 13 is a block diagram illustrating an example of the configuration of the information processing apparatus according to the second embodiment. FIG. 14 is a block diagram illustrating an example of the configuration of the information processing apparatus according to the third embodiment.

  A first embodiment for carrying out the invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating an example of the configuration of the information processing apparatus 1 according to the first embodiment.

  The information processing apparatus 1 includes a pipeline processing execution unit 10 and a pipeline control unit 20.

  FIG. 2 is a diagram illustrating an example of the configuration of the pipeline processing execution unit 10.

  The pipeline processing execution unit 10 includes a configuration of an arithmetic pipeline that is a control target of the present embodiment.

  When the issuance of a vector instruction is confirmed, the arithmetic pipe control unit 160 sends a vector pipe control signal.

  The arithmetic registers V0 to V3: 100 to 103 are VL (Vector Length: vector length that can be specified for each instruction) in accordance with instructions (register reading instruction and register storing instruction) from the arithmetic pipe control unit 160. ) Continuously, data reading and writing operations are performed. The arithmetic registers V0 to V3: 100 to 103 correspond to continuous data reading, and in this example, a maximum of 4 elements can be read or written continuously over 4 cycles. The number of consecutive elements can be specified for each instruction.

  Operand selectors 110, 111, 112, and 113 exist for each input of the arithmetic unit, and select an operation register output instructed from operation pipe control unit 160 according to an instruction (operand selector instruction) from operation pipe control unit 160. To do.

  The product-sum operation unit 120 executes a calculation for VL in accordance with an instruction (operation execution instruction) from the operation pipe control unit 160. The product-sum operation unit 120 outputs the operation result to the crossbar (X-bar) 106 via the signal line 900.

  The logical operation unit 130 executes an operation for VL in accordance with an instruction (operation execution instruction) from the operation pipe control unit 160. The logical operator 130 outputs the operation result to the crossbar 106 via the signal line 901.

  The crossbar 106 selects data to be written in the arithmetic registers 100, 101, 102, and 103 according to an instruction (X-bar selection instruction) from the arithmetic pipe control unit 160, and outputs the data continuously for VL.

  The store data selector 105 selects read data from the operation registers 100, 101, 102, and 103 in accordance with an instruction (Store Select instruction) from the operation pipe control unit 160, and outputs the data to the store path to the main memory.

  The load buffers 150 and 151 store the data read from the memory by the load instruction based on the load buffer read instruction until the data is filled (filled) in order to efficiently use the arithmetic registers 100 to 103. According to the transfer execution instruction to 103, the specified number of elements are transferred continuously.

  FIG. 3 is a diagram illustrating an example of the configuration of the pipeline control unit 20.

  The instruction buffer buffer 201 buffers an instruction and sends out the instruction if the instruction issuance waiting buffer 210 has a free space.

  The inter-instruction dependency check unit 202 checks the dependency between the instruction scheduled to be stored in the instruction issue standby buffer 210 and the preceding instruction stored in the instruction issue standby buffer 210 and the scheduled instruction buffer 240. Then, the inter-instruction dependency check unit 202 determines that there is a dependency between the instruction scheduled to be stored in the instruction issuance standby buffer 210 and the instruction stored in the instruction issuance standby buffer 210. In 212, a value indicating that there is a dependency relationship is set. In addition, the inter-instruction dependency check unit 202, when there is a dependency relation and a path conflict relation between the instruction scheduled to be stored in the instruction issue standby buffer 210 and the scheduled instruction buffer 240, is a timing at which each relation is canceled. Time (first time and second time) is calculated (counted). Furthermore, the inter-instruction dependency check unit 202 sets values (also referred to as counter values) corresponding to the calculated first time and second time in the inter-instruction dependency counter 213 and the path conflict counter 214.

  The load buffer fill determination unit 203 confirms that the number of elements designated by the load instruction has been loaded from the memory into the load buffer 204, and when all the elements for executing the load instruction have been prepared, the filled flag 215 Has a function of setting a predetermined flag value.

  The instruction issue standby buffer 210 includes an instruction storage buffer 211, an inter-instruction dependency flag 212, an inter-instruction dependency counter 213, a path contention counter 214, and a filled flag 215. In FIG. 3, the instruction and counter value stored in each buffer and counter at the lower side of the figure are sequentially stored so as to be the oldest instruction and counter value. The inter-instruction dependency flag 212 does not have a buffer located at the bottom, but this is because the instruction stored in the instruction storage buffer 211 at this position is the oldest instruction and has the highest priority. This is because it has been determined.

  The instruction storage buffer 211 is a buffer that stores an instruction body in the instruction issue standby buffer 210.

  The inter-instruction dependency flag 212 indicates the inter-instruction dependency stored in the instruction storage buffer 211. When the stored value is “1”, there is a dependency between two instructions and the instruction schedule order is changed. If the stored value is “0”, there is no dependency relationship, so that the instruction received in advance is overtaken depending on the situation. It should be noted that the old instruction stored in the lower buffer of the instruction storage buffer 211 should be scheduled without being restricted by the new instruction stored above it. That is, it is not necessary to maintain the dependency relationship between the old instruction and the new instruction. In other words, as shown in FIG. 3, the new instruction has a dependency on more old instructions, and as a result, the bit width of the inter-instruction dependency flag 212 is different for each instruction.

  The inter-instruction dependency counter 213 holds a value corresponding to the first time until the timing at which the dependency for the instruction scheduled to be issued is resolved. The value is a value calculated and stored by the inter-instruction dependency check unit 202. The inter-instruction dependency counter 213 selects the smallest value that satisfies all of the relations W → R, W → W, and R → W at the timing when the instruction is stored in the instruction storage buffer 211 or when the issue of the preceding instruction is confirmed. (W: write, R: read). As a method for selecting the smallest value, any one of a method using a circuit for comparing the magnitudes of values, a method of taking a logical product by expanding values into bits, and a method of mixing them may be selected. The inter-instruction dependency counter 213 subtracts 1 every cycle and stops subtraction when it becomes 0.

  The path conflict counter 214 holds a value corresponding to the second time until a timing at which no conflict occurs due to a data transfer path such as an arithmetic unit or a store path for an instruction scheduled to be issued. The value is a value calculated and stored by the inter-instruction dependency check unit 202. The path contention counter 214 sets a value at the timing when the instruction is stored in the instruction storage buffer 211 or when the preceding instruction is issued. Depending on the configuration of the arithmetic pipeline, there may be a conflict at a plurality of points in the data transfer path. In this case, the path conflict counter 214 selects and sets the smallest value that avoids the conflict. As a method for selecting the smallest value, the path contention counter 214 may be a method using a circuit for comparing the magnitudes of values, a method of taking a logical product by expanding values into bits, or a method of mixing them. good. The path contention counter 214 decrements by 1 every cycle and stops subtraction when it becomes 0. In a device that operates with a high-speed clock, a configuration in which a plurality of path contention counters 214 are provided may be considered when there are many contention confirmation points and a circuit delay to be compared becomes a problem.

  The Filled flag 215 is a flag indicating that all elements for executing the load instruction are prepared. When an operation instruction or a store instruction not related to load is set in the instruction storage buffer 211, the Filled flag 215 sets “1”.

  The instruction execution scheduling unit 220 selects an instruction that can be scheduled from the instructions held in the instruction storage buffer 211, and calculates the earliest execution timing while maintaining consistency between instructions.

  For example, (1) the inter-instruction dependency flag 212 is 0, (2) the inter-instruction dependency counter 213 is 7 or less, and (3) the path contention counter 214 is 7 Hereinafter, (4) the value of the Filled flag 215 is 1.

  Note that the values of (2) and (3) are the values of the present embodiment, and other threshold values can be taken. The instruction execution scheduling unit 220 selects the oldest instruction among the instructions satisfying all of these conditions, and issues the counter values of the inter-instruction dependency counter 213 and the path contention counter 214 corresponding to the instruction to issue instructions. Read from standby buffer 210. Then, the instruction execution scheduling unit 220 converts the read counter value into a decoded value based on the table of FIG. Further, the instruction execution scheduling unit 220 determines the fastest execution waiting timing in consideration of the dependency relationship between the selected instruction and the instruction that has been issued immediately before that instruction (immediately preceding instruction). Note that if scheduling becomes impossible due to dependency with the immediately preceding instruction or path conflict (when “1” does not exist in the decoded bit pattern), the instruction execution scheduling unit 220 cancels the scheduling and is effective. Does not output strict instructions.

  The contention arbitration unit 221 compares the counter value of the inter-instruction dependency counter 213, the counter value of the path contention counter 214, and the immediately preceding instruction influence reflection value (described later), and calculates the instruction execution waiting time that is the shortest. To do. The contention arbitration unit 221 is, for example, a fixed priority arbiter circuit with the lowest priority.

  The scheduling confirmed instruction influence reflecting unit 231 calculates the influence of the instruction that has been confirmed on the instruction selected immediately thereafter, determines the earliest timing at which the influence is eliminated, performs decoding, and sends it to the instruction execution scheduling unit 220. (Influence value reflecting the effect of the previous instruction).

  The counter set value generation unit 232 determines the time until the earliest timing when the resource used by the instruction whose scheduling has been confirmed and the resource used by the instruction existing in the instruction issuance standby buffer 210 are affected. The value corresponding to that time is calculated and set in the counter (inter-instruction dependency counter 213) of the instruction issuance standby buffer 210. For example, when both the relationship of W → R and the relationship of R → W exist, the counter set value generation unit 232 calculates the earliest timing at which both effects are eliminated. Also, in the path contention counter 214, if there is an influence on a plurality of paths, the counter set value generation unit 232 calculates the time until the earliest timing at which the influence does not occur in all the paths, and the instruction issue waiting buffer 210 Set to the counter (path conflict counter 214).

  The scheduled instruction buffer 240 has a function of holding an instruction whose scheduling is determined by the instruction execution scheduling unit 220 until there is no influence on subsequent instructions. The scheduled instruction storage register 241 stores an instruction for which scheduling has been determined. The counter (entry period counter) 242 is a counter corresponding to the scheduled instruction storage register 241, and a value corresponding to the time until the timing at which the influence on the subsequent instruction is eliminated is set in this counter. The counter 242 is subtracted for each cycle, and is reset when it reaches a value that does not affect subsequent instructions (in this example, “1”).

  The execution standby buffer 250 stores the instruction whose scheduling is fixed by the instruction execution scheduling unit 220, and issues an instruction to execute the instruction after the designated time has elapsed. The execution waiting instruction storage register 251 stores an instruction waiting for execution. The execution standby instruction counter 252 stores the instruction execution timing, and outputs an instruction execution instruction of the corresponding instruction to the operation pipe control unit 160 when a predetermined value, for example, the counter value becomes “0”. When the counter values of a plurality of instructions simultaneously become “0”, the execution standby instruction counter 252 starts executing at the same time.

  Here, the store data selector 105, the crossbar 106, the operand selectors 110, 111, 112, 113, the sum-of-products calculator 120, the logic calculator 130, the calculation pipe control unit 160, the inter-instruction dependency check unit 202, and the load buffer Fill determination The unit 203, the contention arbitration unit 221, the scheduling confirmed instruction influence reflection unit 231, and the counter set value generation unit 232 are configured by hardware circuits such as logic circuits, for example.

  Also, arithmetic registers 100, 101, 102, 103, load buffers 150, 151, instruction buffer buffer 201, instruction issue standby buffer 210, instruction storage buffer 211, inter-instruction dependency flag 212, inter-instruction dependency counter 213, path contention Counter 214, Filled flag 215, execution fixed instruction register 222, execution waiting time 223, scheduled instruction buffer 240, scheduled instruction storage register 241, counter 242, execution standby buffer 250, execution standby instruction storage register 251, execution standby instruction counter 252 is configured by a storage device such as a semiconductor memory, for example. Further, the information processing apparatus 1 may be realized by a computer apparatus. In this case, the store data selector 105, the crossbar 106, the operand selectors 110, 111, 112, 113, the product-sum calculator 120, the logic calculator 130, the calculation pipe control unit 160, the inter-instruction dependency check unit 202, and the load buffer Fill determination The unit 203, the contention arbitration unit 221, the scheduling confirmation instruction influence reflection unit 231, and the counter set value generation unit 232 are realized by the processor of the information processing apparatus 1 being a computer executing a program on a memory (not shown). May be. The program may be stored in a nonvolatile memory.

  FIG. 4 is a time chart showing the operation of the information processing apparatus 1.

  6 to 10 show details of the operation of FIG. 4 for each clock.

Here, it is assumed that the following instruction sequence is executed. In either case, it is assumed that the instruction is vector length = 4 (VL = 4). Instructions 1) to 5) are as follows.
1) ADD V0 ← V0 + V3
2) AND V3 ← V0 & V1
3) LD V0 ← M
4) LD V1 ← M
5) AND V2 ← V0 & V1
here,
ADD, +: addition AND, &: logical product LD, M: load V0 to V3: operation registers 100, 101, 102, 103 of the pipeline processing execution unit 10 are shown. The arrow “←” is indicated by “<−” in the frame of the instruction sequence in FIG.

  In the instruction sequence, the right side and the left side across the arrow are paired to describe the operation of each instruction. For example, in the instruction 1), “+” and “ADD”, and in the instructions 3) and 4), “M (means“ memory access ”)” and “LD”.

  FIG. 5 shows a decoding table (counter value decoding correspondence table) used for decoding the counter value.

  The decode table indicates a decode value corresponding to the counter value on the left side. A portion having a decode value of “1” indicates that issue scheduling is possible. In this example, scheduling is impossible when the counter value is “8” or more, and so on. The decode table in FIG. 5 is used in the following description.

  Hereinafter, the operation of the information processing apparatus 1 will be described in the order of clock counts with the passage of time, using the time chart of FIG. 4 and FIGS.

Clock1:
Instruction 1) is stored in the instruction buffer buffer 201. At this time, since no instruction is stored in the instruction issue standby buffer 210 (instruction storage buffer 211), the output of the inter-instruction dependency check unit 202 (hereinafter simply referred to as output) has a dependency with the preceding instruction. “000000” indicating that there is no output is output.

  The output indicates the presence / absence of the dependency relationship between the instruction stored in the instruction buffer buffer 201 and each instruction in the instruction storage buffer 211 by 1/0. For example, 211 # 0, 211 # in order from the left end. Dependencies with 1, 211 # 2 (hereinafter omitted) are sequentially shown.

Clock2:
Instruction 1) is stored in instruction storage buffer 211 # 0, and instruction buffer buffer 201 receives instruction 2). Since there is a relationship of W → R between the instruction 1) and the instruction 2), the output 202 is “100000”.

  When an instruction is stored in the instruction storage buffer 211, “1” is set in the Filled flag 215 on the assumption that conditions other than the load instruction are met.

  The instruction 1) stored in the instruction storage buffer 211 # 0 is selected as the schedule with the highest priority. Then, from the corresponding counter values of the inter-instruction dependency counter 213 and the path conflict counter 214, a value of “0” is read out and decoded. At this time, “11111111” is obtained according to the decoding table of FIG.

  Since there is no instruction for which the schedule has been confirmed immediately before, the instruction execution scheduling unit 220 receives “11111111” (immediate instruction effect reflection value) having no effect from the scheduling confirmation instruction effect reflection unit 231 and logically ANDs them all. “11111111” is supplied to the leading 0 circuit (leading 0 circuit), the waiting time is calculated, and “10000000” (waiting time) is generated. “10000000” indicates that the leftmost bit is “1” and can be issued after 0 cycles.

Clock3:
Since the instruction 1) is determined to be executed and the waiting time is “0”, the subtraction is not performed and the waiting time becomes “0” and is stored in the execution determined instruction register 222. Instruction 2) is stored in instruction storage buffer 211 # 1, and instruction buffer buffer 201 receives instruction 3). There is a relationship of W → W and a relationship of R → W between the instruction 3) and the instruction 1), and there is a relationship of R → W between the instruction 3) and the instruction 2). Both are “110000” indicating that there is a dependency.

  Since the instruction 2) is not a load instruction, the Filled flag 215 is set to “1”.

  Since the execution of the instruction 1) is confirmed, the instruction execution scheduling unit 220 selects the instruction 2) having the highest priority from the instruction storage buffer 211 excluding the instruction 1) and performs scheduling.

  The counter value is “0” for both the inter-instruction dependency counter 213 and the path conflict counter 214, and therefore “11111111” is output according to FIG. 5.

  Next, since the execution of the instruction 1) is confirmed immediately before, the scheduling confirmed instruction influence reflection unit 231 calculates the influence of the instruction 1) on the instruction 2) selected immediately after. The instruction 1) and the instruction 2) are different in the arithmetic unit to be used. Therefore, there are two relations, that is, the relation W → R for the V0 register and the relation R → W for the V3 register. In the case of the relationship of W → R, since it can be calculated by the equation of waiting time + preceding instruction TAT, 0 + 5 = 5. In the case of the relationship of R → W, since it can be calculated by the equation of waiting time−following instruction TAT + 1, 0−3 + 1 = −2, but 0 or less is 0. Considering “5” and “0” obtained from the two relationships, “5”, which is the earliest execution time satisfying the data consistency, is selected (that is, as long as “5” exists, other “ Even if it is “0”, it is necessary to wait for the count of “5” to be completed). The scheduling confirmation instruction influence reflection unit 231 decodes “5” according to FIG. 5 to obtain “00000111”. Then, the instruction execution scheduling unit 220 (contention arbitration unit 221) inputs “00000111” obtained by ANDing the three values “11111111”, “11111111”, and “00000111” to the leading 0 circuit, and outputs “00000100”. Get. This means that the execution waiting time is 5 and can be issued after 5 cycles.

Clock4:
The instruction 2) for which the execution waiting time is calculated in Clock 3 is stored in the execution fixed instruction register 222, and “00001000” meaning 5-1 = 4 is stored as the execution waiting time.

  In addition, the instruction 1) stored in the execution fixed instruction register 222 at Clock3 moves to the execution standby buffer 250 (specifically, the execution standby instruction storage register 251 is described below). As for the execution waiting time, “0” after encoding is set in the execution waiting instruction counter 252. Since the value of the execution standby instruction counter 252 is “0”, execution of the corresponding instruction 1) is next started at Clock 5.

  The instruction 1) is also stored in the scheduled instruction buffer 240 (specifically, the scheduled instruction storage register 241, which will be described below). At this time, 0 + 5 + 4 = 9 calculated by the execution waiting time + operation TAT (ADD) + VL is also set in the corresponding counter 242.

  Instruction 3) is stored in the instruction storage buffer 211. Since there is a dependency of R → W on the instruction 2), the instruction 2) is executed when the corresponding bit is set to “1”. In response to being stored in the fixed instruction register 222, it is canceled, and the inter-instruction dependency flag 212 is set to “0”.

  After the execution of the instruction 1) is confirmed, the inter-instruction dependency counter 213 corresponding to the instruction 2) is set to “4” in consideration of subtraction for each cycle from “5” calculated by 0 + 5 = 5. The

  The instruction 3) is stored in the instruction storage buffer 210. The instruction 3) is a load instruction. If all the load data elements from the original memory are not prepared, the Filled flag 215 is not set to "1". However, since it is assumed that all load data elements exist in the load buffer for the sake of simplification of description, “1” is set in the Filled flag 215.

  For this reason, the instruction 3) is selected as schedulable because there is no dependency.

  Since the instruction 3) has an R → W dependency on the V0 register with the instruction 2) stored in the execution confirmation instruction register 222 immediately before, the calculation of R → W: waiting time−following instruction TAT + 1 is performed. -3 + 1 = 2 is decoded to obtain “00111111” (immediate instruction effect reflection value). The contention arbitration unit 221 takes the logical product of the values decoded from the counter values (the value of the inter-instruction dependency counter 213: “11111111” and the value of the path contention counter 214: “11111111”) and inputs the logical product to the leading0 circuit. And “00100000” is obtained.

  Hereinafter, characteristic operations will be described.

Clock5:
At the same time that the instruction 1) is executed and deleted from the execution waiting buffer 250, the instruction 2) is set as the execution waiting time “4”.

  At the same time, instruction 2) is set in the scheduled instruction buffer 240 with a value of execution latency + operation TAT (AND) + VL = 4 + 3 + 4 = 11.

  The instruction 3) is stored in the execution fixed instruction register 222 together with the calculated “1”.

  When the instruction 4) is stored in the instruction storage buffer 210, “1” calculated from the dependency relationship with the instruction 2) whose execution is confirmed is set in the inter-instruction dependency counter 213.

  The instruction 3) of the immediately-preceding execution confirmation instruction 222 is not affected by the dependency relationship such as the transfer path from the load buffer is different from the instruction 4) (the counter decode value of the path conflict counter 214 is “11111111”). "11111111" (immediate instruction reflected value) is obtained, and "01111111" indicating "1" of the value read from the inter-instruction dependency relation counter 213 is ANDed and input to reading0, "01000000" is obtained. The instruction 3) is stored in the execution confirmation instruction register 222 together with “1” after subtraction.

Clock 6 (stored data diagram is omitted):
As shown in FIG. 4, the instruction 3) is stored in the execution standby buffer 250 together with the value “1”. The instruction 4) is stored in the fixed instruction register 222 together with “0” after subtraction.

Clock 7 (stored data diagram is omitted):
The counter value of the execution standby instruction counter 252 corresponding to the instruction 3) is subtracted to “0”. The instruction 4) is stored in the execution standby buffer 250 together with the counter value “0” of the execution standby instruction counter 252. Since both the instruction 3) and the instruction 4) have the counter value of the execution standby instruction counter 252 being “0”, they can be executed simultaneously in the next cycle.

  Although the following description is omitted, in this way, in the instruction issue control system of this embodiment, it is possible to perform scheduling for issuing a plurality of instructions simultaneously.

  Next, an operation when the same instruction sequence as that in FIG. 4 is executed when a configuration with only four scheduled instruction buffers 240 is assumed will be described with reference to FIG.

  FIG. 11 is a time chart showing the operation of the information processing apparatus 1 when the number of scheduled instruction buffers 240 is only four.

  In the following, a description will be given focusing on characteristic points different from the operation of FIG.

  At Clock 6, the instruction 5) is read from the instruction storage buffer 210. At this time, three of the four scheduled instruction buffers 240 are used, and since the instruction 4) is stored in the execution fixed instruction register 222, it is determined that a total of four are used. Therefore, the instruction 5) is not stored in the execution confirmation instruction register 222 at the next Clock7.

  From Clock 8 to Clock 10, the situation where all four scheduled instruction buffers 240 are used remains the same.

  In Clock 11, the counter 242 corresponding to the instruction 1) stored in the scheduled instruction buffer 240 indicates “2” (details are omitted). Since it is known that the counter value is reset in the next cycle when the counter value is “1”, the instruction 5) is stored in the execution confirmation instruction register 222 in the next cycle.

  In Clock 12, the instruction 5) is stored in the execution confirmation instruction register 222.

  In Clock 13, the instruction 5) is stored in the execution standby buffer 250 together with the value “0”, and the execution of the instruction is started in the next Clock 14.

  As described above, the information processing apparatus 1 can issue instructions while maintaining register consistency even when the number of buffers is limited.

  Next, an operation for scheduling an instruction sequence different from the above-described instruction will be described with reference to FIG.

  FIG. 12 is a time chart showing the operation of the information processing apparatus 1 when different instruction sequences are used.

Here, it is assumed that the following instruction sequence is executed. Both instructions are vector length = 4 (VL = 4). The instructions 1) to 4) are as follows.
1) LD V1 ← M
2) MPY V2 ← V0 * V1
3) LD V0 ← M
4) AND V1 ← V0 & V3
here,
MPY, *: indicates multiplication. The arrow “←” is indicated by “<−” in the frame of the instruction sequence in FIG. The description of the same symbols as those in the above instruction sequence is omitted.

  What is characteristic about this instruction sequence is that the register read in the instruction 2) is reused for writing the load data in the instruction 3) and used in the AND instruction in the instruction 4). Therefore, as in this example, even when there is an R → W dependency on the V0 register between the instruction 2) and the instruction 3), the execution of the instruction 3) is started before the instruction 2). Can be scheduled to be used efficiently.

  In FIG. 12, the instruction 2) starts executing at Clock8, while the instruction 3) starts executing at Clock7 one cycle before.

  As described above, in the present embodiment, the prepared counters 213 and 214 are provided for each issue waiting instruction. Thus, for example, when the number of operation registers is 32 and the number of issued standby instruction buffers is 16, normally, busy management for at least register consistency, read path, and write path are managed. Because it is necessary, a counter that manages at least 32 * 3 = 96 busys is necessary. However, in the present embodiment, since 16 * 2 = 32 counters are sufficient, the amount of hardware for 64 counters can be reduced.

In addition, by decoding the counter value according to the decoding table, and inputting the bit string after the logical product to the leading 0 circuit to calculate the shortest waiting time that is consistent with the data consistency, high efficiency corresponding to the high clock can be obtained. Issuance control. This embodiment
The decoding table that realizes the bit string that can use the logical product and the leading0 circuit is characteristic, and mainly the instruction execution scheduling unit 220, the contention arbitration circuit 221, the scheduling fixed instruction influence reflection unit 231, and the counter set value generation unit 232 cooperate. And realized.

  The information processing apparatus 1 according to the present embodiment has the following effects.

  The effect is that instructions can be executed efficiently with a relatively small amount of hardware even when there are many computing resources.

The reason is that a counter that manages the issue suppression period for the preceding instruction is prepared for each issue waiting instruction, the inter-instruction dependency counter that temporally manages the inter-instruction dependency, and the busy of the arithmetic pipeline. This is because a waiting time is calculated in consideration of the path contention counter to be managed and the effect on the instruction that has been confirmed immediately before execution, and a mechanism is provided for calculating the timing that can be executed at the fastest speed by comparing these three values.
<Second Embodiment>
Next, the second best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 13 is a block diagram illustrating an example of the configuration of the information processing apparatus 30 according to the second embodiment.

  The information processing apparatus 30 has the same configuration as the information processing apparatus 1 of the first embodiment, and the arrangement of data stored in the load buffers 150 and 151 is different.

  When load data is stored in the load buffers 150 and 151, the data arrangement to be stored may be changed as shown in FIG. When load data is arranged as shown in FIG. 13, data is read alternately from the load buffer 150 and the load buffer 151.

  At this time, with the load of L0-0 to L0-3 scheduled at a certain timing, the bit string used when scheduling the instructions of L1-0 to L1-3 is decoded as “00010101”, thereby calculating The registers 100 to 103 (crossbar 106) can also cope with alternate reading (showing the timing when the place where “1” stands is empty).

  By the way, the above is the performance improvement when the load data is stored in the plurality of load buffers 150 and 151. However, even when a plurality of arithmetic units are used, the performance improvement can be similarly performed.

  For example, when there are two arithmetic units having the same function and one of the two units is selected, it can be handled by expressing the logical sum of the bit strings of the respective arithmetic units.

  For example, “00111111” is obtained from the logical sum of “00111111” and “00001111”. This indicates that it is possible to schedule a computing unit that has a fast resource availability.

  The information processing apparatus 30 according to the present embodiment has the following effects.

  The effect can improve the performance of pipeline processing.

The reason is that data is read alternately from the two load buffers.
<Third embodiment>
FIG. 14 is a block diagram illustrating an example of the configuration of the information processing apparatus 40 according to the third embodiment.

  The information processing apparatus 40 includes a pipeline control unit 50 and a pipeline processing execution unit 60.

  The pipeline control unit 50 controls the pipeline processing execution unit 60.

  The pipeline processing execution unit 60 executes pipeline processing of the arithmetic unit pipeline.

  The pipeline control unit 50 calculates the first time until the timing at which the influence of the scheduled instruction that matches the resource used for the instruction existing in the instruction issue waiting buffer is eliminated, and the inter-instruction dependency counter The counter value corresponding to the first time is stored, the second time until the timing at which the path contention does not occur in the arithmetic unit pipeline is calculated, and the counter value corresponding to the second time is stored in the path contention counter A counter set value generation unit 51, a scheduling fixed instruction influence reflection unit 52 that calculates the influence of the instruction that has been confirmed to be executed on the instruction selected immediately after that, and the inter-instruction dependency Compare the counter value of the counter, the counter value of the path contention counter, and the value that reflects the effect of the immediately preceding instruction, and execute the shortest instruction Chi calculates the time, including a conflict arbitration unit 53.

  The information processing apparatus 40 according to the present embodiment has the following effects.

  The effect is that instructions can be executed efficiently with a relatively small amount of hardware even when there are many computing resources.

  The reason is that a counter that manages the issue suppression period for the preceding instruction is prepared for each issue waiting instruction, the inter-instruction dependency counter that temporally manages the inter-instruction dependency, and the busy of the arithmetic pipeline. This is because a waiting time is calculated in consideration of the path contention counter to be managed and the effect on the instruction that has been confirmed immediately before execution, and a mechanism is provided for calculating the timing that can be executed at the fastest speed by comparing these three values.

  As mentioned above, although embodiment of this invention was described with reference to drawings, this invention is not limited to the said embodiment. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 10 Pipeline process execution part 100, 101, 102, 103 Operation register 105 Store data selector 106 Crossbar 110, 111, 112, 113 Operand selector 120 Multiply-add operation unit 130 Logical operation unit 150, 151 Load buffer 160 Operation Pipe control unit 20 Pipeline control unit 201 Instruction buffer buffer 202 Inter-instruction dependency check unit 203 Load buffer Fill determination unit 210 Instruction issue waiting buffer 211 Instruction storage buffer 212 Inter-instruction dependency flag 213 Inter-instruction dependency counter 214 Path contention counter 215 Filled flag 220 Instruction execution scheduling unit 221 Contention arbitration unit 222 Execution fixed instruction register 223 Execution waiting time 231 Effect of scheduling fixed instruction Reflection unit 232 Counter set value generation unit 240 Scheduled instruction buffer 241 Scheduled instruction storage register 242 Counter 250 Execution standby buffer 251 Execution standby instruction storage register 252 Execution standby instruction counter 30 Information processing device 40 Information processing device 50 Pipeline control unit 51 Counter set value generation unit 52 Scheduling confirmation instruction effect reflection unit 53 Contention arbitration unit 60 Pipeline processing execution unit

Claims (10)

An information processing apparatus in which pipeline processing means controls pipeline processing execution means for executing pipeline processing of an arithmetic unit pipeline,
The pipeline control means comprises:
A first time until the timing at which the influence of the scheduled instruction is eliminated and the influence of the scheduled instruction is eliminated with respect to the instruction existing in the instruction issue waiting buffer is calculated, and the inter-instruction dependency counter is set to the first time. A counter set value for storing a corresponding counter value, calculating a second time until a timing at which no path contention occurs in the arithmetic unit pipeline, and storing a counter value corresponding to the second time in a path contention counter Generating means;
A scheduling fixed instruction influence reflecting means for calculating an immediately preceding instruction influence reflecting value indicating an influence of an instruction determined to be executed on an instruction selected immediately after;
Competing arbitration means for comparing the counter value of the inter-instruction dependency counter, the counter value of the path contention counter, and the immediately preceding instruction influence reflection value to calculate the execution waiting time of the shortest instruction Information processing apparatus.   Using the counter value of the inter-instruction dependency counter, the counter value of the path contention counter, and a value obtained by decoding the immediately preceding instruction influence reflection value, the contention arbitration unit calculates the shortest instruction waiting time. The information processing apparatus according to claim 1.   The contention arbitration means calculates a logical product of the counter value of the inter-instruction dependency counter, the counter value of the path contention counter, and the immediately preceding instruction influence reflection value, and sets the execution waiting time of the shortest instruction. The information processing apparatus according to claim 1 or 2 to calculate.   The information processing apparatus according to claim 2, wherein the decoded value is leading0. A first time until the timing at which the influence of the scheduled instruction is eliminated and the influence of the scheduled instruction is eliminated with respect to the instruction existing in the instruction issue waiting buffer is calculated, and the inter-instruction dependency counter is set to the first time. Storing a corresponding counter value, calculating a second time until a timing at which no path contention occurs in the computing unit pipeline, and storing a counter value corresponding to the second time in a path contention counter;
Calculate the previous instruction influence reflection value indicating the influence of the instruction that has been confirmed to be executed on the instruction selected immediately after,
An information processing method of calculating a shortest instruction execution waiting time by comparing a counter value of the inter-instruction dependency counter, a counter value of the path contention counter, and the immediately preceding instruction influence reflection value.   6. The waiting time of the shortest instruction is calculated by using a counter value of the inter-instruction dependency counter, a counter value of the path contention counter, and a value obtained by decoding the immediately preceding instruction influence reflection value. The information processing method described.   6. The execution waiting time of the shortest instruction is calculated by calculating a logical product of a counter value of the inter-instruction dependency counter, a counter value of the path contention counter, and the immediately preceding instruction influence reflection value. Or the information processing method of 6. A first time until the timing at which the influence of the scheduled instruction is eliminated and the influence of the scheduled instruction is eliminated with respect to the instruction existing in the instruction issue waiting buffer is calculated, and the inter-instruction dependency counter is set to the first time. A process of storing a corresponding counter value, calculating a second time until a timing at which no path contention occurs in the arithmetic unit pipeline, and storing a counter value corresponding to the second time in a path contention counter;
A process for calculating the immediately preceding instruction influence reflection value indicating the influence of the instruction that has been confirmed to be executed on the instruction selected immediately after;
Comparing the counter value of the inter-instruction dependency counter, the counter value of the path contention counter, and the immediately preceding instruction influence reflection value, and causing the computer to execute the process of calculating the shortest instruction execution waiting time program.   Processing for calculating the waiting time of the shortest instruction using the counter value of the inter-instruction dependency counter, the counter value of the path contention counter, and a value obtained by decoding the immediately preceding instruction influence reflection value in the computer The program according to claim 8 to be executed.   Processing to calculate the execution waiting time of the shortest instruction by calculating a logical product of the counter value of the inter-instruction dependency counter, the counter value of the path contention counter, and the immediately preceding instruction influence reflection value; The program according to claim 8 or 9, wherein the program is executed.

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