JP2016085162A - Semiconductor integrated circuit, failure detection method of semiconductor integrated circuit, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable highly-reliable error detection by an external device with fewer additional ports.SOLUTION: A semiconductor integrated circuit includes: a control circuit section which has duplicated logic circuits in a chip, outputs output data of one logic circuit or data based on the output data to the outside of the chip, and generates an error detection code from the output data of the other logic circuit or data based on the output data; and a failure detection section which is provided outside of the chip of the control circuit section, generates the error detection code from the data output to the outside of the chip from the control circuit section, compares the generated error detection code with the error detection code generated by the control circuit section, and detects an error.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor integrated circuit, a failure detection method for a semiconductor integrated circuit, and an electronic apparatus.

  Many LSIs (Large Scale Integration) are used in devices such as home appliances, AV (Audio Visual) devices, mobile phones, automobiles, and industrial machines. An LSI is a semiconductor integrated circuit in which an electronic circuit is built on a thin semiconductor substrate called a wafer. LSI is an important component indispensable for high performance, high functionality, miniaturization, low power consumption and low cost of equipment. In an electronic device (electronic device) using an LSI, it is important to detect a control error in order to ensure reliability. As a cause of this control error, for example, an LSI failure can be cited. Therefore, a control error can be detected by detecting a failure of the LSI.

  There are various methods for detecting an LSI failure. As one of them, a method (dual lock step method) in which the logic circuit is duplicated to perform the same processing and the outputs are always compared is often used. The LSI has a port for inputting / outputting data to / from an external device. However, even when the logic circuit is duplicated internally, it is difficult to duplicate the ports even from the viewpoint of cost. Therefore, only one of the duplicated logic circuits is connected to the output port, and an error is detected by constantly comparing the output of one logic circuit and the output of the other logic circuit with a comparison circuit in the same chip. Conceivable.

  On the other hand, there is a CRC (Cyclic Redundancy Check) as a data communication error detection method. In the CRC method, an arbitrary length data stream is input, and a fixed length check code is generated according to a predetermined generator polynomial. The transmission side adds a CRC to the data stream for transmission, and the reception side generates a CRC from the received data stream, and compares the generated CRC with the received CRC. If the comparison results match, it is determined that the data communication is correct, and if they do not match, the data communication is determined to be incorrect.

  As this type of prior art, a technique described in Patent Document 1 is known. Patent Document 1 states that “an error detection circuit is provided in each of the subsystems, a check code is calculated from data received by these error detection circuits, and error processing is performed when the check code does not match the received check code. "I did it."

JP 2006-146320 A

  A method of detecting errors by comparing outputs of logic circuits duplicated in a chip within the same chip is effective when the logic circuit and the error detection circuit do not fail simultaneously. This is because if the logic circuit and the error detection circuit fail at the same time, the error detection circuit determines that the outputs of the two logic circuits do not match, and the error cannot be detected. When the logic circuit and the error detection circuit are in the same chip, there is a possibility that the logic circuit and the error detection circuit fail at the same time due to common resources such as a power supply and a clock. Thus, there is a limit to reliability in error detection inside the chip.

  In the prior art described in Patent Document 1, the first system for generating data and check code and the second system for checking these are independent, and the first system and the second system fail at the same time. However, the application target is a communication data stream. When the application target is a communication data stream, an error detection code can be added to the data stream for transmission.

  However, when the target of application is a bus output in which access is completed every bus cycle or a general-purpose output that changes over a long time period, an error detection code cannot be added to these outputs for transmission. Therefore, although the prior art described in Patent Document 1 can detect an error in a data stream, it is not possible to check for an error in a bus output in which access is completed every bus cycle or in a general-purpose output that changes in a long time period. Can not.

  As is clear from the above, error detection within the chip is limited in reliability, so that error detection by an external device (LSI external circuit) is effective. However, if the control output of the LSI is duplicated, the number of ports to be added increases. Since the number of LSI ports is limited, the number of ports that can be added is limited.

  Accordingly, an object of the present invention is to provide a semiconductor integrated circuit capable of performing highly reliable error detection by an external device with a small number of ports added, a failure detection method thereof, and an electronic apparatus having the semiconductor integrated circuit. And

In order to solve the above problems, for example, the configuration described in the claims is adopted.
The present application includes a plurality of means for solving the above problems.
It has a doubled logic circuit in the chip, outputs the output data of one logic circuit or data based on the output data to the outside of the chip, and outputs from the output data of the other logic circuit or data based on the output data. A control circuit unit for generating an error detection code;
Provided outside the chip of the control circuit unit, generate an error detection code from data output from the control circuit unit to the outside of the chip, the generated error detection code and the error detection code generated by the control circuit unit, A fault detection unit that detects errors by comparing
It is characterized by providing.

According to the present invention, highly reliable error detection can be performed by an external device with a small number of ports added.
Problems, configurations, and effects other than those described above will be clarified by the following description of embodiments.

1 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a first embodiment. 3 is an example of a timing chart showing a timing relationship regarding generation of a check code and writing of a check code register in the semiconductor integrated circuit according to the first embodiment; 3 is an example of a timing chart showing a timing relationship of serial communication of a check code from a control LSI to a failure detection LSI in the semiconductor integrated circuit according to the first embodiment. 3 is an example of a flowchart illustrating an example of a processing procedure of a failure detection method in the semiconductor integrated circuit according to the first embodiment. FIG. 9 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a second embodiment. 12 is an example of a timing chart showing a timing relationship of serial communication of a check code from a failure detection LSI to a control LSI in a semiconductor integrated circuit according to a second embodiment. 12 is an example of a flowchart illustrating an example of a processing procedure of a failure detection method in a semiconductor integrated circuit according to a second embodiment. FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a third embodiment. FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a fourth embodiment. FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a fifth embodiment. FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a sixth embodiment. FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to a seventh embodiment. FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to an eighth embodiment. It is an example of the block diagram which shows the outline of a structure of an example of the electronic device of this invention.

  Hereinafter, modes for carrying out the present invention (hereinafter referred to as “embodiments”) will be described in detail. The present invention is not limited to the embodiment. In the present specification and drawings, the same components or components having substantially the same function are denoted by the same reference numerals, and redundant description is omitted.

<Semiconductor integrated circuit according to an embodiment of the present invention>
A semiconductor integrated circuit according to an embodiment of the present invention includes a control circuit unit, a memory unit, and a failure detection unit. The control circuit unit and the failure detection unit operate in synchronization. The control circuit unit has a doubled logic circuit in the chip, and outputs the output data of one logic circuit or data based on the output data to the outside of the chip. Here, “chip” refers to an IC chip in which an integrated circuit is packaged. The data output from the control circuit unit to the outside of the chip may be the output data of one logic circuit itself, or the data output from the one logic circuit after passing through another circuit. In some cases, data is output to the outside.

  Data when the output data itself of one logic circuit is output to the outside of the chip is supplied to a device (device) to be controlled by the semiconductor integrated circuit and used for controlling the device. Data when the output data of one logic circuit is output to the outside of the chip after passing through another circuit is supplied to the memory unit via the bus when the other circuit is a bus control circuit, for example. Stored in the memory unit. The data stored in the memory unit is read out to one of the logic circuits via the bus control circuit as necessary.

  The control circuit unit further generates an error detection code (hereinafter referred to as “check code”) from the output data of the other logic circuit or data based on the output data. As an example of the check code (error detection code), a CRC having a short code and a high error detection rate can be used. The data for which the check code is to be generated (the output data of the other logic circuit or data based on the output data) may be the output data itself of the other logic circuit, or may be another circuit (for example, a bus control circuit). ). The control circuit unit outputs the generated check code to the outside of the chip, specifically, to the failure detection unit.

  The failure detection unit is provided outside the chip of the control circuit unit. The failure detection unit takes in the output data of one logic circuit outputted from the control circuit unit to the outside of the chip or data based on the output data, and generates a check code from the taken-in data. Also, a check code output from the control circuit unit is captured. Specifically, the check code transmitted by the control circuit unit is received. The failure detection unit performs error detection by comparing the check code generated by itself with the check code generated by the control circuit unit. A failure of the control circuit unit can be detected by error detection by the failure detection unit. When an error is detected, for example, a process for resetting the control circuit unit is performed.

  As described above, the semiconductor integrated circuit according to the present embodiment employs a configuration in which a failure detection unit is provided as an external device (external circuit) outside the chip of the control circuit unit having a dual logic circuit in the chip. Yes. Then, in the failure detection unit that is an external device, a check code is generated from the output data of one logic circuit or data based on the output data, and the generated check code is compared with the check code generated by the control circuit unit. Error detection.

  That is, the semiconductor integrated circuit according to the present embodiment employs a system in which a failure detection unit is provided as an external device outside the chip of the control circuit unit, and error detection is performed by the external device (that is, the failure detection unit). Then, the control circuit unit and the failure detection unit generate check codes twice, transfer (send) the check code generated by the control circuit unit to the failure detection unit, and the failure detection unit compares both check codes. Thus, error detection is performed.

  In this way, the control circuit unit captures the comparison result from the port (terminal) that outputs the check code to the failure detection unit, the port that outputs a signal for synchronizing with the failure detection unit, and the failure detection unit. It is only necessary to add three ports. That is, error detection (failure detection) can be performed at a high detection rate by an external device with a small number of ports added.

  Moreover, in the semiconductor integrated circuit according to the present embodiment, it is not necessary to add a check code to data output from the control circuit unit to the bus. For this reason, error detection can be performed for a bus output that cannot be added with an error detection code and that is completed in every bus cycle, or for a general-purpose output that changes over a long time period. As described above, according to the semiconductor integrated circuit of the present embodiment, highly reliable error detection can be realized by the failure detection unit that is an external device with a small number of ports added.

  The control circuit unit and the failure detection unit are composed of LSI. Hereinafter, the control circuit unit is described as a control LSI, and the failure detection unit is described as a failure detection LSI. Hereinafter, specific examples of the semiconductor integrated circuit according to the present embodiment will be described with reference to the drawings.

[Example 1]
FIG. 1 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the first embodiment. The semiconductor integrated circuit 1A according to the first embodiment includes a control LSI 2 that is a control circuit unit, a memory unit 3, and a failure detection LSI 4 that is a failure detection unit.

(Control LSI)
The control LSI 2 includes a first logic circuit 5_1 and a second logic circuit 5_2 that are duplicated in the chip, a first bus control circuit 6_1 and a second bus control circuit 6_2 that are duplicated, and a failure detection circuit 7. Have.

  In the control LSI 2, the first logic circuit 5_1 and the second logic circuit 5_2 have the same function and execute the same process while synchronizing the clocks. As the first logic circuit 5_1 and the second logic circuit 5_2, for example, a configuration using a CPU (Central Processing Unit) and a cache memory can be considered. The input signal IN of the control LSI 2 is input to the first logic circuit 5_1 and the second logic circuit 5_2 via the input port P10.

  The first bus control circuit 6_1 and the second bus control circuit 6_2 are provided in each subsequent stage of the first logic circuit 5_1 and the second logic circuit 5_2. The first bus control circuit 6_1 and the second bus control circuit 6_2 have the same function and execute the same processing while synchronizing the clocks. When the first logic circuit 5_1 accesses the memory unit 3, the first logic circuit 5_1 outputs a memory access signal S1 to the first bus control circuit 6_1. In response to the memory access signal S1, the first bus control circuit 6_1 accesses the memory unit 3 by outputting a control signal and an address signal from the output port P11 to the bus 11.

  When the memory access is write (write), the first bus control circuit 6_1 outputs write data to the bus 11 via the output port P11, and writes the write data in the memory unit 3. When the memory access is read (read), read data is read from the memory unit 3 to the bus 12. Then, the first bus control circuit 6_1 takes in the read data from the bus 12 via the input port P12 and causes the first logic circuit 5_1 to read it.

  The second logic circuit 5_2 performs the same operation as the first logic circuit 5_1. That is, when accessing the memory unit 3, the second logic circuit 5_2 outputs a memory access signal S2 to the second bus control circuit 6_2. In response to the memory access signal S2, the second bus control circuit 6_2 outputs a control signal and an address signal as the bus copy signal S3 and causes the failure detection circuit 7 to read it. When the memory access is a write, the second bus control circuit 6_2 outputs the write data as the bus copy signal S3 and causes the failure detection circuit 7 to read it. When the memory access is read, the second bus control circuit 6_2 fetches the read data from the bus 12 via the input port P12 and causes the second logic circuit 5_2 to read it.

  The failure detection circuit 7 includes an encoding circuit 71, a master check code capture register (hereinafter referred to as “MCCR”) 72, a transmission circuit 73, and a control circuit 74. The encoding circuit 71 has a master check code register (hereinafter referred to as “MCR”) 711, encodes the bus copy signal S 3, and updates the MCR 711 every clock cycle of the bus 11.

  The encoding circuit 71 generates a fixed-length check code C11 according to a predetermined generator polynomial. For the encoding of the encoding circuit 71, the above-described error detection method of data communication such as CRC can be applied. The encoding circuit 71 performs these operations with the bus copy signal S3 and the check code C11 of the MCR 711 as inputs, and updates the check code C11 of the MCR 711 by writing back the operation result to the MCR 711. By doing so, the value of the bus copy signal S3 for each clock cycle is reflected in the MCR 711.

  The control circuit 74 outputs the MCR update signal S11 to the MCR 711, outputs the MCCR write signal S12 to the MCCR 72, and outputs the transmission request signal S13 to the transmission circuit 73. The MCR 711 is initialized to all “0” by the logical value “0” of the MCR update signal S11, and the check code C11 is written by the logical value “1” of the MCR update signal S11. The MCCR 72 receives the MCCR write signal S12 output from the control circuit 74, takes in the check code C11 from the MCR 711, and holds it as the check code C12. That is, the MCCR 72 is a code register that holds a check code (error detection code) generated by the encoding circuit 71.

  The transmission circuit 73 receives the transmission request signal S13 output from the control circuit 74 and outputs the check code C12 held in the MCCR 72 to the serial interface 13 via the serial port P13. More specifically, the transmission circuit 73 sends the check code C12 held in the MCCR 72 from the serial port P13 to the serial interface 13 over a plurality of clock cycles with a bit number smaller than the bit number of the check code C12. Output.

(Fault detection LSI)
The failure detection LSI 4 operates in synchronization with the clock clk output from the control LSI 2 via the output port P14 and input from the input port P21, and checks the bus 11. The failure detection LSI 4 includes an encoding circuit 41, a checker check code capture register (hereinafter referred to as “CCCR”) 42, and a reception circuit 43. The failure detection LSI 4 further includes a checker reception register (hereinafter referred to as “CRR”) 44, a comparison circuit 45, and a control circuit 46.

  The encoding circuit 41 has a checker check code register (hereinafter referred to as “CCR”) 411, encodes the data of the bus 11 input via the input port P22, and converts the CCR 411 into the clock of the bus 11. Update every cycle. For the encoding of the encoding circuit 41, the same method as the encoding circuit 71 of the control LSI 2, for example, CRC is applied. That is, the encoding circuit 41 generates a check code according to the same generator polynomial as the encoding circuit 71 of the control LSI 2.

  The control circuit 46 outputs a CCR update signal S21 to the CCR 411, outputs a CCCR write signal S22 to the CCCR 42, and outputs a comparison permission signal S23 to the comparison circuit 45. The CCR 411 is initialized to all “0” by the logical value “0” of the CCR update signal S21, and the check code C21 is written by the logical value “1” of the CCR update signal S21. The CCCR 42 receives the CCCR write signal S22 output from the control circuit 46, takes in the check code C21 of the CCR 411, and holds it as the check code C22.

  The update of the MCR 711 in the control LSI 2 and the update of the CCR 411 in the failure detection LSI 4 are executed in synchronization. Specifically, the control circuit 74 on the control LSI 2 side and the control circuit 46 on the failure detection LSI 4 side are synchronized by the control signal CS. The control signal CS is output from the control LSI 2 to the outside of the chip through the output port P15, and input to the failure detection LSI 4 through the input port P23. Under the control by the control signal CS, the control circuit 74 and the control circuit 46 are synchronized, so that the MCR update signal S11 in the control LSI 2 and the CCR update signal S21 in the failure detection LSI 4 are output in synchronization. .

  Similarly, the writing of the check code C11 to the MCCR 72 in the control LSI 2 and the writing of the check code C21 to the CCCR 42 in the failure detection LSI 4 are executed in synchronization. Specifically, the control circuit 74 and the control circuit 46 are synchronized under the control of the control signal CS, so that the MCCR write signal S12 in the control LSI 2 and the CCCR write signal S22 in the failure detection LSI 4 are synchronized. Is output.

  In the failure detection LSI 4, the reception circuit 43 receives the check code C12 transmitted by the transmission circuit 73 of the control LSI 2 from the serial interface 13 via the serial port P24. The receiving circuit 43 supplies the received check code C12 to the CRR 44 as the check code C23. The CRR 44 holds the check code C23 supplied from the receiving circuit 43 as the check code C24. The comparison circuit 45 compares the check code C22 held in the CCCR 42 with the check code C24 held in the CRR 44, and outputs an error signal Se corresponding to the comparison result.

  Specifically, the comparison circuit 45 compares the check code C22 and the check code C24 when the comparison permission signal S23 output from the control circuit 46 is the logical value “1”. Then, the comparison circuit 45 sets the logic value of the error signal Se to ‘1’ when the comparison results do not match, and sets the logic value of the error signal Se to ‘0’ when they match. The error signal Se is output from the failure detection LSI 4 to the outside of the chip via the output port P25, and then input to the control LSI 2 via the input port P16. In response to this error signal Se, the control circuit 74 of the failure detection circuit 7 resets the control LSI 2 and the failure detection LSI 4 when the logical value of the error signal Se is “1”.

  FIG. 2 is an example of a timing chart showing a timing relationship regarding check code generation and check code register writing in the semiconductor integrated circuit 1A according to the first embodiment. FIG. 2A shows the timing relationship on the control LSI 2 side, and FIG. 2B shows the timing relationship on the failure detection LSI 4 side.

  The timing chart of FIG. 2A shows the timing relationship among the clock clk, the value (data) of the bus 11, the bus copy signal S3, the check code C11, the check code C12, the MCR update signal S11, and the MCCR write signal S12. The timing chart of FIG. 2B shows the timing relationship among the clock clko, the value of the bus 11, the check code C21, the check code C22, the CCR update signal S21, and the CCCR write signal S22. In the check code C12 of FIG. 2A and the check code C22 of FIG. 2B, the hatched portion represents the data held last time.

  In the timing chart of FIG. 2A, the clock clk is a bus clock of the control LSI 2. It is assumed that the value of the bus 11 and the bus copy signal S3 change every clock clk. If the control LSI 2 is not faulty, the value is the same every clock clk. The check code C11 of the MCR 71 is initialized to all "0" in the next clock cycle when the MCR update signal S11 has the logic value "0", and is updated with the logic value "1". In the cycle in which the clock clk is 1, the MCR update signal S11 has the logical value “0”. Therefore, in the cycle in which the clock clk is 2, the check code C11 becomes all “0”.

  In a cycle in which the clock clk is 2, the MCR update signal S11 has a logical value “1”. Therefore, the value (B1O2) of the bus copy signal S3 and the check code (MC2) generated from the value of the check code C11 (all ‘0’) are written in the MCR 711 in the next cycle. In the cycle in which the clock clk is 5, the MCCR write signal S12 becomes the logical value “1”, so that the value (MC4) of the check code C11 in this cycle is held in the MCCR 72 as the check code C12 in the next cycle.

  In the timing chart of FIG. 2B, the clock clko is a clock input from the control LSI 2 to the failure detection LSI 4. The check code C21 of the CCR 411 is initialized to all “0” in the next clock cycle when the CCR update signal S21 is a logical value “0”, and is updated with a logical value “1”. In the cycle in which the clock clko is 1, the CCR update signal S21 has the logical value “0”. Therefore, in the cycle in which the clock clko is 2, the check code C21 becomes “0”.

In a cycle in which the clock clko is 2, the CCR update signal S21 has a logical value “1”.
Therefore, the check code (CC2) generated by the encoding circuit 41 from the value of the bus 11 (B0O2) and the value of the check code C21 (all “0”) is written to the CCR 411 in the next cycle. In the cycle in which the clock clko is 5, the CCCR write signal S22 has a logical value “1”, so that the value (CC4) of the check code C21 in this cycle is held in the CCCR 42 as the check code C22 in the next cycle.

  FIG. 3 is an example of a timing chart showing the timing relationship of serial communication of a check code from the control LSI 2 to the failure detection LSI 4 in the semiconductor integrated circuit 1A according to the first embodiment. FIG. 3A shows the timing relationship on the control LSI 2 side, and FIG. 3B shows the timing relationship on the failure detection LSI 4 side.

  The timing chart of FIG. 3A shows the timing relationship between the clock clk, the check code C11, the serial data of the serial interface 13, and the transmission request signal S13. The timing chart of FIG. 3B shows the timing relationship among the clock clko, the serial data of the serial interface 13, the check code C24, the check code C22, the error signal Se, and the comparison permission signal S23.

  In the timing chart of FIG. 3A, when the transmission request signal S13 output from the control circuit 74 in the cycle in which the clock clk is 3 becomes the logical value “1”, the transmission circuit 73 outputs to the serial interface 13 via the serial port P13. Start. This serial communication is performed over a plurality of successive cycles, and after outputting a pattern called a preamble indicating the start of communication, data of a check code C12 is output. Here, it is assumed that the preamble is output when the clock clk is 4 to 11 and the data is output when the clock clk is 12 to 21.

  In the timing chart of FIG. 3B, the receiving circuit 43 monitors the serial interface 13. Then, when the reception circuit 43 detects the preamble in the cycle when the clock clko is 4 to 11, the data is input in the cycle where the subsequent clock clko is 12 to 21, and the received check code C12 is written in the CRR 44 as the check code C23. In a cycle in which the clock clko is 22, the control circuit 46 sets the comparison permission signal S23 to the logical value “1”. In response to this, the comparison circuit 45 compares the check code C24 held in the CRR 44 with the check code C22 held in the CCCR 42, and outputs an error signal Se corresponding to the comparison result. The error signal Se has a logical value “0” if the comparison results match, and a logical value “1” if they do not match.

(Failure detection method)
Next, processing of a failure detection method in the semiconductor integrated circuit 1A according to the first embodiment (that is, a failure detection method executed in the semiconductor integrated circuit 1A), which is an example of a failure detection method of the semiconductor integrated circuit, will be described.
FIG. 4 is an example of a flowchart illustrating an example of a processing procedure of a failure detection method in the semiconductor integrated circuit 1A according to the first embodiment. FIG. 4 shows a processing flow on the control LSI 2 side and a processing flow on the failure detection LSI 4 side.

  First, the processing procedure on the control LSI 2 side will be described. In the control LSI 2, the first bus control circuit 6_1 outputs the output data from the output port P11 to the bus 11 (step S101). In parallel with the processing of step S101, the encoding circuit 71 of the failure detection circuit 7 performs data based on the output data of the second logic circuit 5_2, specifically, the output data (bus copy signal S3 of the second bus control circuit 6_2). ) To generate a check code C11 (step S102).

  Next, the MCCR 72 receives the MCCR write signal S12 output from the control circuit 74, and holds the check code C11 generated by the encoding circuit 71 as the check code C12 (step S103). Subsequently, the transmission circuit 73 receives the transmission request signal S13 output from the control circuit 74 and outputs the check code C12 held in the MCCR 72 to the serial interface 13. That is, the transmission circuit 73 transmits the check code C12 to the failure detection LSI 4 (step S104).

  Next, a processing procedure on the failure detection LSI 4 side will be described. In the failure detection LSI 4, the encoding circuit 41 takes in the output data of the first bus control circuit 6_1 output from the control LSI 2 to the bus 11, that is, the data of the bus 11 (step S201). Next, the encoding circuit 41 generates a check code C21 from the data on the bus 11 and holds it in the CCR 411 (step S202). Next, the CCCR 42 receives the CCCR write signal S22 output from the control circuit 46, takes in the check code C21 held in the CCR 411, and holds it as the check code C22 (step S203).

  The receiving circuit 43 monitors whether or not the check code C12 is transmitted from the control LSI 2, and when receiving the check code C12 from the control LSI 2, supplies the received check code C12 to the CRR 44 as the check code C23 (step S204). . Subsequently, the CRR 44 holds the check code C23 supplied from the receiving circuit 43 as the check code C24 (step S205).

  Next, the comparison circuit 45 receives the comparison permission signal S23 output from the control circuit 46, and compares the check code C22 held in the CCCR 42 with the check code C24 held in the CRR 44. Specifically, the comparison circuit 45 determines whether or not the check code C22 and the check code C24 match when the comparison permission signal S23 is the logical value “1” (step S206).

  Then, the comparison circuit 45 determines that there is no error when the check code C22 and the check code C24 match (in the case of YES in step S206), that is, there is no failure in the control LSI 2, and a series of processing for failure detection Exit. The comparison circuit 45 determines that there is an error when the check code C22 and the check code C24 do not match (in the case of NO in step S206), that is, there is a failure in the control LSI 2, and the logical value “1”. An error signal Se is sent to the control LSI 2. That is, an error notification is sent from the failure detection LSI 4 to the control LSI 2 (step S207).

(Effect of Example 1)
As described above, the semiconductor integrated circuit 1A according to the first embodiment includes the first logic circuit 5_1 and the second logic circuit 5_2, and the first bus control circuit 6_1 and the second bus control circuit 6_2, that is, the logic circuit. And the bus control circuit (bus controller) are doubled. In the semiconductor integrated circuit 1A adopting this duplex configuration, the control LSI 2 outputs the output data of the first bus control circuit 6_1 to the outside of the chip, that is, to the bus 11. The control LSI 2 generates a check code from data based on the output data of the second logic circuit 5_2 that has passed through the second bus control circuit 6_2, and transmits the generated check code to the failure detection LSI 4 that is an external device.

  On the other hand, the failure detection LSI 4 takes in the output data of the first bus control circuit 6_1 output from the control LSI 2 to the bus 11, that is, data on the bus 11, and generates a check code from the fetched data. Further, the failure detection LSI 4 receives the check code generated from the control LSI 2 and transmitted from the control LSI 2. Then, the failure detection LSI 4 performs error detection by comparing the check code generated by itself with the check code generated by the control LSI 2.

  According to the semiconductor integrated circuit 1A according to the first embodiment having such a configuration, the behavior of the output of the duplex bus controller (the first bus control circuit 6_1 and the second bus control circuit 6_2) (the behavior of the bus 11). Can be checked by the failure detection LSI 4 which is an external device. Further, error detection can be performed for a bus output or a general-purpose output to which an error detection code cannot be added. Also, the number of ports added to the control LSI 2 can be reduced. In the semiconductor integrated circuit 1A according to the first embodiment, it is only necessary to add three ports of the serial port P13, the output port P15, and the input port P16. The serial port P13 is a port that outputs a check code to the failure detection LSI 4. The output port P15 is a port that outputs a control signal CS for synchronizing with the failure detection LSI 4. The input port P16 is a port that takes in the error signal Se from the failure detection LSI 4.

[Example 2]
FIG. 5 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the second embodiment. Similar to the semiconductor integrated circuit 1A according to the first embodiment, the semiconductor integrated circuit 1B according to the second embodiment includes a first logic circuit 5_1 and a second logic circuit 5_2 that are duplicated in the chip, and a first that is duplicated. The bus control circuit 6_1 and the second bus control circuit 6_2 are included. The point of duplication of the logic circuit and the bus control circuit is the same in each embodiment described later.

  The semiconductor integrated circuit 1A according to the first embodiment is configured to perform error detection by comparing check codes only with the failure detection LSI 4, whereas the semiconductor integrated circuit 1B according to the second embodiment has a control function. The LSI 2 is also configured to perform error detection. That is, the semiconductor integrated circuit 1B transfers the check code generated by the failure detection LSI 4 to the control LSI 2 by serial communication, and the control LSI 2 compares the check code generated by itself with the check code generated by the failure detection LSI 4. It has a configuration. The specific configuration will be described below.

(Control LSI)
In the control LSI 2, the failure detection circuit 7 compares the reception circuit 75 and a master reception register (hereinafter referred to as “MRR”) 76 in addition to the encoding circuit 71, MCCR 72, transmission circuit 73 and control circuit 74. Circuit 77. The control circuit 74 outputs a comparison permission signal S14 to the comparison circuit 77.

  The receiving circuit 75 receives the check code C22 transferred from the failure detection LSI 4 via the serial interface 13_2 via the input port P17 and outputs it as the check code C13. The MRR 76 holds the check code C13 output from the receiving circuit 75 as the check code C14. The comparison circuit 77 receives the comparison permission signal S14 output from the control circuit 74, compares the check code C12 held in the MCCR 72 with the check code C14 held in the MRR 76, and according to the comparison result. An error signal Se2 is output.

  Specifically, the comparison circuit 77 compares the check code C12 and the check code C14 when the comparison permission signal S14 output from the control circuit 74 is a logical value “1”. Then, the comparison circuit 77 sets the logical value of the error signal Se2 to ‘1’ if the comparison results do not match, and sets the logical value of the error signal Se2 to ‘0’ if they match. The error signal Se2 is input to the control circuit 74. Upon receiving this error signal Se2, the control circuit 74 resets the control LSI 2 and the failure detection LSI 4 when the logical value of the error signal Se2 is “1”. In FIG. 5, the error signal Se notified from the failure detection LSI 4 to the control LSI 2 is shown as Se1, and the serial interface 13 from the control LSI 2 to the failure detection LSI 4 is shown as the serial interface 13_1. The same applies to the following embodiments.

(Fault detection LSI)
On the other hand, the failure detection LSI 4 includes a transmission circuit 47 in addition to the encoding circuit 41, CCCR 42, reception circuit 43, CRR 44, comparison circuit 45 and control circuit 46. The control circuit 46 outputs a transmission request signal S24 to the transmission circuit 47.

  The transmission circuit 47 receives the transmission request signal S24 output from the control circuit 46, and outputs the check code C22 held in the CCCR 42 to the serial interface 13_2 via the serial port P26. More specifically, the transmission circuit 47 sends the check code C22 held in the CCCR 42 from the serial port P26 to the serial interface 13_2 over a plurality of clock cycles with a bit number smaller than the bit number of the check code C22. Output.

  FIG. 6 is an example of a timing chart illustrating a timing relationship of serial communication of a check code from the failure detection LSI 4 to the control LSI 2 in the semiconductor integrated circuit 1B according to the second embodiment. FIG. 6A shows the timing relationship on the failure detection LSI 4 side, and FIG. 6B shows the timing relationship on the control LSI 2 side.

  The timing chart of FIG. 6A shows the timing relationship between the clock clko, the check code C22, the serial data of the serial interface 13, and the transmission request signal S24. The timing chart of FIG. 6B shows the timing relationship between the clock clk, the serial data of the serial interface 13, the check code C14, the check code C12, the error signal Se2, and the comparison permission signal S14.

  In the timing chart of FIG. 6A, when the transmission request signal S24 output from the control circuit 46 in the cycle of the clock clko becomes 3 becomes the logical value “1”, the transmission circuit 47 outputs to the serial interface 13_2 via the serial port P25. Start. This serial communication is performed over a plurality of consecutive cycles, and after outputting the preamble, the data of the check code C22 is output. Here, it is assumed that the preamble is output in the cycle when the clock clko is 4 to 11 and the data is output in the cycle where the clock clko is 12 to 21.

  In the timing chart of FIG. 6B, the receiving circuit 75 monitors the serial interface 13_2. When the reception circuit 75 detects the preamble in a cycle in which the clock clk is 4 to 11, the data is received in a cycle in which the subsequent clock clk is 12 to 21, and the received check code C22 is written in the MRR 76 as the check code C13. In the cycle in which the clock clk is 22, the control circuit 74 sets the comparison permission signal S14 to the logical value “1”. In response to this, the comparison circuit 77 compares the check code C14 held in the MRR 76 with the check code C12 held in the MCCR 72, and outputs an error signal Se2 corresponding to the comparison result. The error signal Se has a logical value “0” if the comparison results match, and a logical value “1” if they do not match.

(Failure detection method)
Next, processing of the failure detection method in the semiconductor integrated circuit 1B according to the second embodiment, which is another example of the failure detection method of the semiconductor integrated circuit, will be described.
FIG. 7 is an example of a flowchart illustrating an example of a processing procedure of a failure detection method in the semiconductor integrated circuit 1B according to the second embodiment. FIG. 7 shows a processing flow on the control LSI 2 side and a processing flow on the failure detection LSI 4 side.

  First, the processing procedure on the control LSI 2 side will be described. In the control LSI 2, the first bus control circuit 6_1 outputs the output data from the output port P11 to the bus 11 (step S301). In parallel with the process of step S301, the encoding circuit 71 of the failure detection circuit 7 generates a check code C11 from the output data (bus copy signal S3) of the second bus control circuit 6_2 (step S302).

  Next, the MCCR 72 receives the MCCR write signal S12 output from the control circuit 74, and holds the check code C11 generated by the encoding circuit 71 as the check code C12 (step S303). Subsequently, the transmission circuit 73 receives the transmission request signal S13 output from the control circuit 74, and transmits the check code C12 held in the MCCR 72 to the failure detection LSI 4 by serial communication (step S304).

  The reception circuit 75 monitors whether or not the check code C22 is transmitted from the failure detection LSI 4. When the check code C22 is received from the failure detection LSI 4, the reception circuit 75 supplies the received check code C22 to the MRR 76 as the check code C13 (step S1). S305). Subsequently, the MRR 76 holds the check code C13 supplied from the receiving circuit 75 as the check code C14 (step S306).

  Next, the comparison circuit 77 receives the comparison permission signal S14 output from the control circuit 74, and compares the check code C12 held in the MCCR 72 with the check code C14 held in the MRR 76. Specifically, the comparison circuit 77 determines whether or not the check code C12 matches the check code C14 when the comparison permission signal S14 is the logical value “1” (step S307).

  The comparison circuit 77 determines that there is no error when the check code C12 and the check code C14 match (in the case of YES in step S307), that is, the failure detection LSI 4 has no failure, and a series of failure detection is performed. The process ends. The comparison circuit 77 determines that there is an error when the check code C12 and the check code C14 do not match (NO in step S307), that is, the failure detection LSI 4 has a failure, and the logical value “1”. Error signal Se2 is sent to the control circuit 74. That is, an error notification is sent from the comparison circuit 77 to the control circuit 74 (step S308).

  Next, a processing procedure on the failure detection LSI 4 side will be described. In the failure detection LSI 4, the encoding circuit 41 takes in the output data of the first bus control circuit 6_1 output from the control LSI 2 to the bus 11, that is, the data of the bus 11 (step S401). Next, the encoding circuit 41 generates a check code C21 from the data on the bus 11 and holds it in the CCR 411 (step S402).

  Next, the CCCR 42 receives the CCCR write signal S22 output from the control circuit 46, takes in the check code C21 held in the CCR 411, and holds it as the check code C22 (step S403). Subsequently, the transmission circuit 47 receives the transmission request signal S24 output from the control circuit 46, and transmits the check code C22 held in the CCCR 42 to the control LSI 2 by serial communication (step S404).

  The receiving circuit 43 monitors whether or not the check code C12 is transmitted from the control LSI 2. When the check code C12 is received from the control LSI 2, the receiving circuit 43 supplies the received check code C12 to the CRR 44 as the check code C23 (step S405). . Subsequently, the CRR 44 holds the check code C23 supplied from the receiving circuit 43 as the check code C24 (step S406).

  Next, the comparison circuit 45 receives the comparison permission signal S23 output from the control circuit 46, and compares the check code C22 held in the CCCR 42 with the check code C24 held in the CRR 44. Specifically, the comparison circuit 45 determines whether or not the check code C22 and the check code C24 match when the comparison permission signal S23 is the logical value “1” (step S407).

  The comparison circuit 45 determines that there is no error when the check code C22 and the check code C24 match (in the case of YES in step S407), that is, there is no failure in the control LSI 2, and a series of processing for failure detection Exit. The comparison circuit 45 determines that there is an error when the check code C22 and the check code C24 do not match (NO in step S407), that is, there is a failure in the control LSI 2, and the logical value “1” is obtained. An error signal Se2 is sent to the control LSI 2. That is, an error notification is sent from the failure detection LSI 4 to the control LSI 2 (step S408).

(Effect of Example 2)
Also in the semiconductor integrated circuit 1B according to the second embodiment described above, basically the same effects as those of the semiconductor integrated circuit 1A according to the first embodiment can be obtained. That is, error detection can be performed for bus outputs and general-purpose outputs to which no error detection code can be added. Further, although the number of ports is increased by one (port P17) compared to the first embodiment, the check code comparison is duplicated, so that the failure of the failure detection LSI 4 is also detected in addition to the failure of the control LSI 2. Since it can be detected, the reliability of failure detection can be further improved.

[Example 3]
FIG. 8 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the third embodiment. The semiconductor integrated circuit 1C according to the third embodiment enables the check timing of the bus 11 in the semiconductor integrated circuit 1A according to the first embodiment to be programmable. The semiconductor integrated circuit 1C according to the third embodiment is different from the semiconductor integrated circuit 1A according to the first embodiment in the configuration of the failure detection circuit 7 in the control LSI 2. The configuration of the failure detection LSI 4 is the same as that of the semiconductor integrated circuit 1A according to the first embodiment.

(Control LSI)
In addition to the encoding circuit 71, the MCCR 72, the transmission circuit 73, and the control circuit 74, the failure detection circuit 7 includes duplicated master check setting registers (hereinafter referred to as “MCSR”) 78_1, 78_2, And a comparison circuit 79.

  The first MCSR 78_1 holds timing information of the MCR update signal S11 output from the control circuit 74 to the MCR 711. The second MCSR 78_2 holds timing information of the MCCR write signal S12 output from the control circuit 74 to the MCCR 72. That is, the first MCSR 78_1 and the second MCSR 78_2 are timing information registers that hold timing information for initialization of the encoding circuit 71 and timing information for writing a check code to the MCCR (code register) 72. Based on the timing information held in the first MCSR 78_1 and the second MCSR 78_2, the timings of the MCR update signal S11 and the MCCR write signal S12 are set.

  Various methods are conceivable as the method of setting each timing of the MCR update signal S11 and the MCCR write signal S12. For example, in the timing chart of FIG. 2, the MCR update signal S11 is a pattern of a logical value “0” for one cycle followed by a logical value “1” for M cycles, and a pattern generation cycle M + 1 is set. Further, the MCCR write signal S12 is set to a pattern of N cycles of logical value '0' followed by one cycle of logical value '1', and a pattern generation cycle N + 1 is set.

  With this timing setting, the operation timing can be set as follows. That is, the operation timing can be set so that the MCR 711 and the CCR 411 are initialized in a cycle of M + 1 cycles, and the check code C11 is written in the MCCR 72 and the check code C21 is written in the CCCR 42 in a cycle of N + 1 cycles. Further, the operation timing can be set so that the comparison circuit 45 of the failure detection LSI 4 compares the check codes C22 and C24.

  The first logic circuit 5_1 sets timing information for the first MCSR 78_1 by the setting signal S31. The second logic circuit 5_2 sets timing information for the second MCSR 78_2 by the setting signal S32. The control circuit 74 generates the MCR update signal S11 at a timing based on the set value of the first MCSR 78_1. The comparison circuit 79 compares the set value of the first MCSR 78_1 with the set value of the second MCSR 78_2, and inputs the comparison result to the control circuit 74. The control circuit 74 resets the control LSI 2 and the failure detection LSI 4 when the comparison result of the comparison circuit 79 does not match.

  From the above, it can be seen that the first MCSR 78_1 and the second MCSR 78_2 are registers that can set the initialization timing for generating the check codes C11 and C21 and the check code fetch timing for the MCCR 72 and the CCCR 42. By having the first MCSR 78_1 and the second MCSR 78_2, the check timing of the bus 11 can be programmed based on the programs set in the first logic circuit 5_1 and the second logic circuit 5_2.

(Effect of Example 3)
Also in the semiconductor integrated circuit 1C according to the third embodiment described above, basically the same effects as those of the semiconductor integrated circuit 1A according to the first embodiment can be obtained. That is, error detection can be performed for bus outputs and general-purpose outputs to which no error detection code can be added. In addition, since the initialization timing for generating the check code and the check code fetch timing for the MCCR 72 and the CCCR 42 can be set, the check timing for the bus 11 can be programmed. Thereby, since the user can arbitrarily set the check timing of the bus 11, it is possible to improve the usability of the user.

[Example 4]
FIG. 9 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the fourth embodiment. The semiconductor integrated circuit 1D according to the fourth embodiment enables the check timing of the bus 11 in the semiconductor integrated circuit 1B according to the second embodiment to be programmable. The semiconductor integrated circuit 1D according to the fourth embodiment is different from the semiconductor integrated circuit 1D according to the second embodiment in the configuration of the failure detection circuit 7 in the control LSI 2. The configuration of the failure detection LSI 4 is the same as that of the semiconductor integrated circuit 1D according to the second embodiment.

(Control LSI)
The failure detection circuit 7 includes a duplexed first MCSR 78_1 and second MCSR 78_2, and a comparison circuit 79 in addition to the encoding circuit 71, the MCCR 72, the transmission circuit 73, and the control circuit 74. The first MCSR 78_1 sets timing information of the MCR update signal S11 output from the control circuit 74 to the MCR 711. The second MCSR 78_2 sets timing information of the MCCR write signal S12 output from the control circuit 74 to the MCCR 72. The above configuration is the same as that of the third embodiment, and the function of each component is the same as that of the third embodiment.

(Effect of Example 4)
As described above, the semiconductor integrated circuit 1D according to the fourth embodiment can basically obtain the same effects as those of the semiconductor integrated circuit 1B according to the second embodiment. In other words, error detection can be performed on bus outputs and general-purpose outputs that cannot be added with an error detection code, and check code comparison is duplicated, so that reliability of error detection is improved. Can be improved more. In addition, according to the semiconductor integrated circuit 1D according to the fourth embodiment, the check timing of the bus 11 can be programmed, so that it is possible to improve the usability of the user.

[Example 5]
FIG. 10 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the fifth embodiment. The fifth embodiment is a modification of the first embodiment.

  The semiconductor integrated circuit 1A according to the first embodiment employs a configuration in which output data of the first bus control circuit 6_1 and the second bus control circuit 6_2 are targeted for error detection. In contrast, the semiconductor integrated circuit 1E according to the fifth embodiment employs a configuration in which the memory access signals S1 and S2 output from the first logic circuit 5_1 and the second logic circuit 5_2 are targeted for error detection. Therefore, the memory access signal S1 is output from the first logic circuit 5_1 to the outside of the chip via the output port P18, and is input to the failure detection LSI 4 via the input port P22. On the other hand, the memory access signal S2 is input from the second logic circuit 5_2 to the encoding circuit 71 of the failure detection circuit 7. In the semiconductor integrated circuit 1E according to the fifth embodiment, the control LSI 2 generates the check code C11 from the memory access signal S2 of the second logic circuit 5_2, and the failure detection LSI 4 checks from the memory access signal S1 of the first logic circuit 5_1. A code C21 is generated.

  As described in the first embodiment, the first logic circuit 5_1 and the second logic circuit 5_2 have the same function, and execute the same processing while synchronizing clocks. Therefore, the memory access signal S1 output from the first logic circuit 5_1 and the memory access signal S2 output from the second logic circuit 5_2 are the same internal signal and are subject to error detection. The memory access signals S1 and S2 are digital data and are a kind of output data of the first logic circuit 5_1 and the second logic circuit 5_2.

  The difference between the fifth embodiment and the first embodiment is that the output data (memory access signals S1 and S2) of the first logic circuit 5_1 and the second logic circuit 5_2 is subject to error detection in the fifth embodiment. The output data of the first bus control circuit 6_1 and the second bus control circuit 6_2 is targeted for error detection. Therefore, the configurations of the failure detection circuit 7 and the failure detection LSI 4 in the control LSI 2 are the same as those of the semiconductor integrated circuit 1A according to the first embodiment.

(Effect of Example 5)
The semiconductor integrated circuit 1E according to the fifth embodiment described above can basically obtain the same effects as those of the semiconductor integrated circuit 1A according to the first embodiment. Further, the outputs of the first logic circuit 5_1 and the second logic circuit 5_2 are targeted for error detection. Therefore, even when the first bus control circuit 6_1 and the second bus control circuit 6_2 are not operating, that is, even when the first bus control circuit 6_1 and the second bus control circuit 6_2 do not perform bus access, error detection is performed. It can be carried out.

[Example 6]
FIG. 11 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the sixth embodiment. The sixth embodiment is a modification of the second embodiment.

  The semiconductor integrated circuit 1F according to the sixth embodiment is similar to the fifth embodiment in the semiconductor integrated circuit 1B according to the second embodiment. The memory access signals S1 and S2 output from the first logic circuit 5_1 and the second logic circuit 5_2 are as follows. Is used as an error detection target. That is, in the semiconductor integrated circuit 1F according to the sixth embodiment, the control LSI 2 generates the check code C11 from the memory access signal S2 of the second logic circuit 5_2, and the failure detection LSI 4 checks from the memory access signal S1 of the first logic circuit 5_1. A code C21 is generated.

(Effect of Example 6)
The semiconductor integrated circuit 1F according to the sixth embodiment described above can basically obtain the same effects as those of the semiconductor integrated circuit 1B according to the second embodiment. In addition, according to the semiconductor integrated circuit 1F according to the sixth embodiment, the output data of the first logic circuit 5_1 and the second logic circuit 5_2 are targeted for error detection. Therefore, the first bus control circuit 6_1 and the second bus control circuit Error detection can be performed even when 6_2 does not perform bus access.

[Example 7]
FIG. 12 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the seventh embodiment. The seventh embodiment is a modification of the fifth embodiment, and is a combination of the technique of the fifth embodiment and the technique of the third embodiment.

  That is, the semiconductor integrated circuit 1G according to the seventh embodiment adopts a configuration in which the check timing of the memory access signals S1 and S2 that are internal signals of the control LSI 2 can be programmed in the semiconductor integrated circuit 1E according to the fifth embodiment. . Specifically, in the semiconductor integrated circuit 1G according to the seventh embodiment, the memory access signals S1 and S2 are targeted for error detection. The failure detection circuit 7 includes duplicated MCSRs 78_1 and 78_2 and a comparison circuit 79 in addition to the encoding circuit 71, the MCCR 72, the transmission circuit 73, and the control circuit 74. The functions of the first MCSR 78_1, the second MCSR 78_2, and the comparison circuit 79 are the same as those in the third embodiment.

(Effect of Example 7)
Also in the semiconductor integrated circuit 1G according to the seventh embodiment described above, basically the same effects as those of the semiconductor integrated circuit 1E according to the fifth embodiment can be obtained. Further, according to the semiconductor integrated circuit 1G according to the seventh embodiment, the check timing of the internal signal of the control LSI 2 can be programmed, so that the user convenience can be improved.

[Example 8]
FIG. 13 is an example of a block diagram illustrating a configuration of a semiconductor integrated circuit according to the eighth embodiment. The eighth embodiment is a modification of the sixth embodiment, and is a combination of the technique of the sixth embodiment and the technique of the fourth embodiment.

  That is, the semiconductor integrated circuit 1H according to the eighth embodiment adopts a configuration in which the check timing of the memory access signals S1 and S2 that are internal signals of the control LSI 2 can be programmed in the semiconductor integrated circuit 1F according to the sixth embodiment. . Specifically, the semiconductor integrated circuit 1H according to the eighth embodiment targets the memory access signals S1 and S2 for error detection. The failure detection circuit 7 includes duplicated MCSRs 78_1 and 78_2, and a comparison circuit 79 in addition to the encoding circuit 71, the MCCR 72, the transmission circuit 73, and the control circuit 74. The functions of the first MCSR 78_1, the second MCSR 78_2, and the comparison circuit 79 are the same as those in the third embodiment.

(Effect of Example 8)
Also in the semiconductor integrated circuit 1H according to the eighth embodiment described above, basically the same effects as those of the semiconductor integrated circuit 1F according to the sixth embodiment can be obtained. Further, according to the semiconductor integrated circuit 1H according to the eighth embodiment, the check timing of the internal signal of the control LSI 2 can be programmed, so that it is possible to improve the usability for the user.

  In addition, this invention is not limited to an above-described Example, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations.

<Electronic Device of the Present Invention>
The semiconductor integrated circuits 1A to 1H according to the first to eighth embodiments described above can be used as control devices for electronic devices in appliances such as home appliances, AV equipment, mobile phones, automobiles, and industrial machines.

  FIG. 14 is an example of a block diagram illustrating the outline of the configuration of an example of the electronic apparatus according to the invention. Here, as an example, a case where the electronic device of the present invention is used in an automobile will be described as an example. In automobiles, electronic devices are used for electronic control at various locations. Here, an electronic device used for electronic control of the engine is illustrated.

  In FIG. 14, the electronic device 80 uses the automobile engine 90 as a device to be controlled, and controls the engine 90 based on various sensor signals supplied from the sensor unit 100. The sensor unit 100 includes various sensors such as a vehicle speed sensor, an accelerator opening sensor, and a throttle sensor. The vehicle speed sensor supplies a vehicle speed signal corresponding to the speed of the automobile to the electronic device 80. The accelerator opening sensor supplies an accelerator opening signal corresponding to the opening of the accelerator pedal to the electronic device 80. The throttle sensor supplies a throttle opening signal corresponding to the opening of the throttle valve to the electronic device 80.

  The electronic device 80 includes a control device 81, an A / D (analog / digital) conversion unit 82 disposed in the previous stage of the control device 81, and a D / A (digital / analog) conversion disposed in the subsequent stage of the control device 81. Part 83. Sensor signals such as a vehicle speed signal, an accelerator opening signal, and a throttle opening signal supplied from the sensor unit 100 to the electronic device 80 are analog signals. The A / D conversion unit 82 converts sensor signals such as an analog vehicle speed signal, an accelerator opening signal, and a throttle opening signal into a digital signal and inputs the digital signal to the control device 81.

  The control device 81 is composed of an LSI and performs arithmetic processing for generating various control signals for controlling the engine 90 based on sensor signals such as a digital vehicle speed signal, an accelerator opening signal, and a throttle opening signal. . The various control signals include a fuel injection valve control signal, an ignition timing control signal, a throttle valve control signal, and the like for controlling the fuel injection amount, injection timing, ignition timing, throttle valve opening, and the like. The D / A converter 83 converts control signals such as a digital fuel injection valve control signal, an ignition timing control signal, and a throttle valve control signal output from the control device 81 into analog signals.

  The electronic device 80 supplies control signals such as an analog fuel injection valve control signal, an ignition timing control signal, and a throttle valve control signal to the engine 90, and controls the engine 90 based on these control signals. Specifically, the electronic device 80 controls the injection amount and injection timing of the fuel injection valve by the fuel injection valve control signal, controls the ignition timing by the spark plug by the ignition timing control signal, or by the throttle valve control signal Control the opening of the throttle valve.

  In the electronic device 80 of the engine 90 configured as described above, the control device 81 is configured by using the semiconductor integrated circuits 1A to 1H according to the first to eighth embodiments. The semiconductor integrated circuits 1A to 1H according to the first to eighth embodiments can realize highly reliable error detection by an external device with a small number of ports added. Therefore, by using the semiconductor integrated circuits 1A to 1H according to the first to eighth embodiments as the control device 81, it is possible to contribute to improvement in reliability of engine control by the electronic device 80.

  Here, the electronic device 80 using the engine 90 as a device to be controlled has been described as an example, but is not limited to this application example. In the automobile, electronic control is used in various places other than the engine 90, and the semiconductor integrated circuits 1A to 1H according to the first to eighth embodiments can be used as a control device for the electronic device.

  1A, 1B, 1C, 1D, 1E, 1F, 1G, 1H ... semiconductor integrated circuit, 2 ... control LSI (control circuit unit), 4 ... failure detection LSI (failure detection unit), 5_1 ... first logic circuit, 5_2 ... Second logic circuit, 80 ... electronic device

Claims (5)

It has a doubled logic circuit in the chip, outputs the output data of one logic circuit or data based on the output data to the outside of the chip, and outputs from the output data of the other logic circuit or data based on the output data. A control circuit unit for generating an error detection code;
Provided outside the chip of the control circuit unit, generate an error detection code from data output from the control circuit unit to the outside of the chip, the generated error detection code and the error detection code generated by the control circuit unit, A fault detection unit that detects errors by comparing
A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 1, wherein the control circuit unit has a function of detecting an error by comparing an error detection code generated by the control circuit unit with an error detection code generated by the failure detection unit. circuit. The control circuit unit is
An encoding circuit for generating the error detection code;
A code register for holding the error detection code generated by the encoding circuit;
A timing information register that holds timing information for initialization of the encoding circuit and timing information for writing the error detection code to the code register;
The semiconductor integrated circuit according to claim 1, wherein timing information held in the timing information register can be set from the duplicated logic circuit. Outputting the output data of one logic circuit or data based on the output data in the control circuit unit having the logic circuit duplicated in the chip; and
Generating an error detection code from output data of the other logic circuit or data based on the output data in the control circuit unit;
Generating an error detection code from data output from the control circuit unit to the outside of the chip in a failure detection unit provided outside the chip of the control circuit unit;
A step of detecting an error by comparing the error detection code generated by the failure detection unit and the error detection code generated by the control circuit unit, and performing the respective processes. Method. A semiconductor integrated circuit that controls the device to be controlled;
The semiconductor integrated circuit is:
It has a doubled logic circuit in the chip, outputs the output data of one logic circuit or data based on the output data to the outside of the chip, and outputs from the output data of the other logic circuit or data based on the output data. A control circuit unit for generating an error detection code;
Provided outside the chip of the control circuit unit, generate an error detection code from data output from the control circuit unit to the outside of the chip, the generated error detection code and the error detection code generated by the control circuit unit, And a failure detection unit that detects an error by comparing the electronic devices.

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