JP2016076616A - Semiconductor device, manufacturing apparatus and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To mitigate stress between substrates and to prevent occurrence of cracks and the like.SOLUTION: A stress relaxation layer having a first substrate, a second substrate and a lattice structure between the first substrate and the second substrate is provided. The stress relaxation layer is a layer which impregnates a material having the lattice structure with a resin and formed in a sheet shape. The coefficient of linear expansion of the stress relaxation layer is a substantially intermediate value between that of the first substrate and that of the second substrate. The inventive technique can be applied to an image pickup device.SELECTED DRAWING: Figure 3

Description

  The present technology relates to a semiconductor device, a manufacturing apparatus, and a manufacturing method. Specifically, the present invention relates to a semiconductor device, a manufacturing apparatus, and a manufacturing method that can suppress the occurrence of solder joint cracks and the like.

  Corresponding to the recent trend toward downsizing and higher functionality of electronic devices, there is a demand for technological development for downsizing and higher density in mounting technology. In response to such demands for miniaturization and high density, LSI packages in which connection terminals are arranged on the lower surface of the package are mainly used.

  There are various usage environments for electronic devices equipped with LSI packages, and in many cases, they are exposed to severe temperature environments due to heat generation of the devices. When an electronic device is subjected to thermal stress, distortion may occur in the solder joint part that is mechanically weakest due to a difference in coefficient of linear expansion of the structural material, leading to destruction.

  In other words, BGA (Ball Grid Array) type LSIs are connected by soldering the terminals provided on the bottom of the package to the printed circuit board with solder, but the fine solder joints are subject to stress such as thermal stress and drop impact. Mechanical reliability is low because it is directly received.

  Therefore, it has been proposed to fill the solder connection portion on the lower surface of the BGA with a reinforcing underfill resin when mounting such a package (see, for example, Patent Documents 1 and 2).

  Patent Document 1 proposes to provide a stress relaxation layer on the back surface and the front surface of the circuit formation surface of the semiconductor chip. In Patent Document 2, it is proposed to provide layers or the like for relaxing stress at a plurality of locations such as between substrates and around the substrate.

JP 2009-188392 A JP 2010-50361 A

  According to the proposals in Patent Document 1 and Patent Document 2, in order to obtain a structure for relieving stress, a plurality of treatments such as application of a plurality of resins are required.

  As a method for relieving stress, it is conceivable to use a substrate having a low coefficient of linear expansion, but such a substrate tends to be more expensive than a generally used substrate material. Therefore, there is a possibility that the cost of the chip itself is increased by using such a substrate having a low linear expansion coefficient.

  It is desired that a configuration for relaxing stress can be obtained without increasing the number of steps and without increasing the cost.

  This technique is made in view of such a situation, and makes it possible to obtain a configuration for relaxing stress without increasing the number of steps and without increasing the cost. .

  A semiconductor device according to an aspect of the present technology includes a first substrate, a second substrate, and a stress relaxation layer having a lattice structure between the first substrate and the second substrate.

  The stress relaxation layer may be a layer formed in a sheet shape in which a material having a lattice structure is impregnated with a resin.

  The linear expansion coefficient of the stress relaxation layer may be a value approximately between the linear expansion coefficient of the first substrate and the linear expansion coefficient of the second substrate.

  The connection terminal that connects the first substrate and the second substrate may be located in a lattice of the lattice structure of the stress relaxation layer.

  An image sensor can be arranged on the first substrate, and a circuit for processing a signal from the image sensor can be arranged on the second substrate.

  A manufacturing apparatus according to one aspect of the present technology attaches a stress relaxation layer having a lattice structure to a first substrate having an image sensor or a second substrate on which a circuit for processing a signal from the image sensor is arranged, The first substrate and the second substrate are separated into pieces in a state where the stress relaxation layer is located between the first substrate and the second substrate.

  In the manufacturing method according to one aspect of the present technology, a stress relaxation layer having a lattice structure is attached to a first substrate or a second substrate, and the stress relaxation is performed between the first substrate and the second substrate. Including the step of singulation with the layer in place.

  In the semiconductor device according to one aspect of the present technology, a stress relaxation layer having a lattice structure is provided between the first substrate and the second substrate.

  In the manufacturing apparatus and manufacturing method according to one aspect of the present technology, the semiconductor device is manufactured.

  According to one aspect of the present technology, a configuration for relieving stress can be obtained without increasing the number of steps and without increasing the cost.

  Note that the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure showing composition of one embodiment of a semiconductor device to which this art is applied. It is a figure for demonstrating a stress relaxation layer. It is a figure which shows the structure of a semiconductor device. It is a figure for demonstrating a stress relaxation layer. It is a figure for demonstrating manufacture of a semiconductor device. It is a figure for demonstrating the structure of an imaging device. It is a figure for demonstrating the usage example of an imaging device.

Hereinafter, modes for carrying out the present technology (hereinafter referred to as embodiments) will be described. The description will be given in the following order.
1. 1. Configuration of semiconductor device 2. Stress relaxation layer 3. Manufacture of semiconductor devices 4. Configuration of imaging device Examples of using imaging devices

<Configuration of semiconductor device>
FIG. 1 is a diagram illustrating a configuration of an embodiment of a semiconductor device to which the present technology is applied. 1A is a perspective plan view of the semiconductor device, and FIG. 1B is a schematic cross-sectional view along the line XX ′ in FIG. 1A.

  The semiconductor device includes an image sensor chip 1 having a pixel region 4 and a translucent cover member 2 fixed to the image sensor chip 1 via a fixing member 3. As will be described later, this semiconductor device is obtained by fixing a semiconductor wafer and a translucent substrate with a fixing member 3 and then cutting them into individual pieces. The imaging element chip 1 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge Coupled Device) image sensor, and the pixel region 4 has a plurality of conversion elements and a plurality of transistors that convert incident light into electric charges. Etc.

  A microlens 12 and a color filter 13 are disposed on the semiconductor substrate 11 of the imaging element chip 1. A conductive film 16, an insulating film 18, and an insulating member 19 are disposed below the semiconductor substrate 11 (on the side opposite to the light incident side). Al (aluminum), Cu (copper), or the like is used for the conductive film 16, an oxide film, a nitride film, or the like is used for the insulating film 18, and a solder resist or the like is used for the insulating member 19.

  The imaging element chip 1 has a through electrode 15 that penetrates a first main surface on the light-transmitting cover member side that is the light incident side of the semiconductor substrate 11 and a second main surface opposite to the first main surface. . The through electrode 15 is constituted by a part of the conductive film 16. The through electrode 15 is electrically connected to the surface electrode 14 in the wiring structure. Further, in order to be electrically connected to the circuit board 21, the imaging element chip 1 has a wiring 17 constituted by a part of the conductive film 16.

  Further, the image sensor chip 1 has a connection terminal 20 for connection to an external circuit board 21 that is electrically connected to the wiring 17 disposed on the side opposite to the translucent cover member 2. The connection terminal 20 is composed of a solder ball. The circuit board 21 is a board on which a circuit for processing a signal from the image sensor chip 1 is arranged.

  The translucent cover member 2 shows a configuration after the translucent substrate is separated into pieces, and is composed of a cover glass 31. When the alpha ray emission amount from the translucent cover member 2 is larger than a predetermined value, there is a possibility that the image pickup device chip 1 malfunctions and the image quality deteriorates. In order to cope with such a case, an oxide film (not shown) for reducing irradiation of alpha rays may be provided between the cover glass 31 and the imaging element chip 1.

  A stress relaxation layer 22 is provided between the imaging element chip 1 and the circuit board 21. The stress relaxation layer 22 is provided so that cracks and the like do not occur during linear expansion. The stress relaxation layer 22 will be further described.

<About stress relaxation layer>
In order to explain the stress relaxation layer 22, reference is made to FIG. FIG. 2 shows a state where the stress relaxation layer 22 is not present. As shown in FIG. 2A, the back surface of the semiconductor substrate 11 and the front surface of the circuit board 21 are connected by connection terminals 20.

  The semiconductor substrate 11, the connection terminal 20, and the circuit board 21 are made of different materials. For example, the semiconductor substrate 11 is made of a material such as silicon, the connection terminal 20 is made of solder, and the circuit board 21 is made of FR4 (Flame Retardant Type 4) or the like.

  FR4 is a material in which a glass fiber cloth is impregnated with an epoxy resin and subjected to thermosetting treatment to form a plate, and has both flame retardancy and low electrical conductivity. This FR4 plate as a base material and a copper foil attached thereto is called a glass epoxy substrate or the like, and is used as a material for a printed circuit board.

  Thus, since the semiconductor substrate 11, the connection terminal 20, and the circuit board 21 are each comprised with a different material, linear expansion coefficient etc. differ, for example. For example, when the semiconductor substrate 11 is made of silicon, the linear expansion coefficient of silicon is about 2.6 ppm, and when the circuit board 21 is made of FR4, the linear expansion coefficient of FR4 is about 15 to 20 ppm.

  In FIG. 2A, the linear expansion coefficient is represented by the length of the arrow. As described above, since the linear expansion coefficient of the semiconductor substrate 11 is smaller than the linear expansion coefficient of the circuit board 21, the arrow of the semiconductor substrate 11 in the arrow shown in FIG. Is also shown small.

  When heat is applied to the semiconductor device shown in FIG. 2A, the circuit board 21 expands more than the semiconductor substrate 11 due to the difference in linear expansion coefficient. The connection terminal 20 is connected to both the semiconductor substrate 11 and the circuit board 21. Therefore, when heat is applied to the semiconductor device and the semiconductor substrate 11 and the circuit board 21 expand with different sizes, cracks or the like may occur in the connection terminals 20. In particular, as shown in FIG. 2B, cracks tend to occur in the vicinity of the connection terminal 20 and the circuit board 21 or in the vicinity of the connection terminal 20 and the semiconductor substrate 11 in the outer peripheral portion of the semiconductor device.

  As described above, due to the difference in coefficient of linear expansion between the semiconductor substrate 11 and the circuit board 21, stress on the connection terminal 20 is generated, and there is a possibility that a crack is generated near the connection terminal 20. Such a situation impairs connection reliability and must be prevented.

  Therefore, in order to reduce the stress applied to the connection terminal 20, the stress relaxation layer 22 is provided. A configuration of a semiconductor device having the stress relaxation layer 22 is shown in FIG. FIG. 3 is a diagram simply showing the semiconductor substrate 11, the connection terminals 20, and the circuit board 21, as in FIG.

  As shown in FIG. 3, a connection terminal 20 and a stress relaxation layer 22 are provided between the semiconductor substrate 11 and the circuit board 21. The stress relaxation layer 22 includes a material having a lattice structure (hereinafter referred to as a lattice material 51) and a resin 52.

  FIG. 4 shows a view of the semiconductor device as viewed from above. In FIG. 4, the connection terminal 20 and the stress relaxation layer 22 are shown. The lattice material 51 of the stress relaxation layer 22 is configured in a lattice shape as shown in FIG. The lattice material 51 has a lattice structure in the direction of the same surface as the back surface of the semiconductor substrate 11 or the front surface of the circuit substrate 21. In other words, it has a lattice structure in the horizontal direction.

  Then, in the direction perpendicular to the back surface of the semiconductor substrate 11 or the front surface of the circuit substrate 21, as shown in FIG. 3, a three-dimensional configuration is provided, and a lattice structure is provided in a plurality of layers.

  The lattice material 51 is configured in a lattice shape, and the connection terminals 20 are positioned in the lattice. Further, a resin 52 is filled so as to fill between the lattice material 51 and the connection terminals 20 and between the lattices. A fibrous material can be used for the lattice material 51, and the stress relaxation layer 22 can be a sheet shape in which a fibrous material is impregnated with a resin.

  The lattice material 51 has a lattice structure made of, for example, glass cloth, and the sheet-like stress relaxation layer 22 can be formed by including a resin in the glass cloth. The lattice material 51 is a fibrous material obtained by thinning a ceramic, glass, iron alloy, or the like, and is assumed to be insulating or coated. It is possible to select according to desired characteristics such as the thickness of the stress relaxation layer 22 and the linear expansion coefficient.

  As the resin, polymer resins such as polyimide, benzocyclobutene, fluorinated polyimide, and porous PTFE can be used.

  The linear expansion coefficient of the stress relaxation layer 22 is set to an intermediate value between the linear expansion coefficient of the semiconductor substrate 11 and the linear expansion coefficient of the circuit board 21. For example, when the semiconductor device 11 has a linear expansion coefficient of about 2.6 ppm and the circuit board 21 has a linear expansion coefficient of about 15 to 20 ppm, the stress relaxation layer 22 has a linear expansion coefficient of about 10 ppm. Is done.

  The linear expansion coefficient of the stress relaxation layer 22 is determined by the lattice material 51 and the resin 52. It is easier to adjust the linear expansion coefficient of the stress relaxation layer 22 with the lattice material 51 and the resin 52 than the adjustment of the linear expansion coefficient of the stress relaxation layer 22 with the resin 52 alone, and the desired linear expansion coefficient. It becomes easy to adjust to. For example, the linear expansion coefficient of the stress relaxation layer 22 can be adjusted by adjusting the material of the lattice material 51, the density of the lattice structure, and the like.

  As described above, by providing the stress relaxation layer 22 between the semiconductor substrate 11 and the circuit substrate 21, even if heat is applied to the semiconductor device and the semiconductor device 11 expands, the difference in linear expansion coefficient between the semiconductor substrate 11 and the circuit substrate 21 can be reduced. Since it can be relaxed by the stress relaxation layer 22, it is possible to prevent the occurrence of cracks or the like due to the difference in linear expansion coefficient between the semiconductor substrate 11 and the circuit substrate 21.

  Further, by constituting the stress relaxation layer 22 with the lattice material 51 having a lattice structure and the resin 52, it is more certain that a crack or the like is generated due to the difference in linear expansion coefficient between the semiconductor substrate 11 and the circuit substrate 21. It becomes possible to prevent.

  Here, the stress relaxation layer 22 is provided between the semiconductor substrate 11 and the circuit board 21, the semiconductor substrate 11 has an image sensor, and the circuit board 21 has a circuit for processing a signal from the image sensor. Although the description will be continued on the assumption that the substrate is a substrate, the scope of application of the present technology is not limited only between such a substrate and the substrate.

  The present technology can be applied to a case where a plurality of substrates having different linear expansion coefficients are connected and a stress relaxation layer is provided in order to relieve stress generated due to a difference in linear expansion coefficient between the substrates. Further, it can be applied to an apparatus in which substrates are soldered together.

<Manufacture of semiconductor devices>
Next, a manufacturing method of the semiconductor device (FIG. 1) provided with the stress relaxation layer 22 shown in FIGS. 3 and 4 will be described with reference to FIGS. 5 is simplified compared to FIG.

  First, as shown in FIG. 5A, a plurality of pixel regions and the like shown in FIG. 1 are formed on a substrate 61 formed of a silicon single crystal, and a semiconductor wafer 60 having a plurality of pixel regions 4 is prepared. The pixel region and the like are formed by a semiconductor element manufacturing process.

  As shown in FIG. 5B, a cover glass 31 (translucent substrate 70) is prepared. The cover glass 31 is preferably such that the behavior of linear expansion with respect to temperature is as similar to that of Si (substrate 61 formed of silicon single crystal) as much as possible. For example, as the type of the cover glass 31, quartz glass, borosilicate glass, or the like can be used.

  The translucent substrate 70 manufactured in the same size as the semiconductor wafer 60 is overlapped and fixed. The semiconductor wafer 60 and the translucent substrate 70 are fixed by the fixing member 3. A liquid adhesive can be used for the fixing member 3. Further, for example, the fixing member 3 is made of a transparent resin, and the transparent resin is cured, so that the semiconductor wafer 60 and the translucent substrate 70 can be fixed (adhered).

  By selecting a silicon resin, an acrylic resin, an epoxy resin, a dendrimer, or a copolymer thereof as the transparent adhesive as the fixing member 3, a process after the bonding of the semiconductor wafer 60 and the translucent substrate 70 (for example, There is no problem in heat resistance / chemical resistance / light resistance even in a heat treatment or UV irradiation treatment or a reliability test, and the imaging characteristics are not affected.

  As shown in FIG. 5E, the thickness of the semiconductor wafer 60 is reduced. As a method for reducing the thickness, one or more of back grinding, CMP (chemical mechanical polishing), and etching are selected. At this time, the semiconductor wafer 60 is thinned to a state where a through electrode, which is a subsequent process, can be formed.

  As shown in FIG. 5F, the through electrode 15 is formed in the semiconductor wafer 60. In the through electrode 15, a through hole is formed by etching in order to open a wiring portion of a multilayer wiring (not shown) formed on the surface of the semiconductor wafer. Then, an insulating film such as a silicon oxide film is formed, and the insulating film in the through hole is etched and opened. For example, a through electrode is formed in the through hole by Cu plating, and the semiconductor wafer is opposite to the light-transmitting substrate. Wiring is formed on the surface (back surface). Then, a solder resist as an insulating member is formed on the back surface of the semiconductor wafer, an opening is formed on the wiring, and a solder ball as the connection terminal 20 is formed.

  As shown in FIG. 5G, the stress relaxation layer 22 is placed on the side of the semiconductor wafer 60 where the connection terminals 20 are formed. The stress relaxation layer 22 is formed in a sheet shape, and is formed in the same size as the semiconductor wafer 60. Such a stress relaxation layer 22 is affixed on the semiconductor wafer 60.

  Here, the description will be made on the assumption that the sheet-like stress relaxation layer 22 is pasted on the semiconductor wafer 60 on which the connection terminals 20 are formed. However, as the step of pasting the stress relaxation layer 22 on the circuit board 21. Also good.

  Here, the stress relaxation layer 22 is in the form of a sheet, and the description will be continued assuming that the stress relaxation layer 22 is stuck on the semiconductor wafer 60. However, the stress relaxation layer 22 may be formed by other methods. For example, the lattice material 51 is placed on the semiconductor wafer 60, the resin 52 is dropped, the semiconductor wafer 60 is spun, and the resin 52 has a uniform thickness so that the stress relaxation layer 22 is formed. May be.

  Further, for example, after the lattice material 51 is placed on the semiconductor wafer 60, the circuit board 21 is bonded, and then the resin 52 is filled between the semiconductor wafer 60 and the circuit board 21. The stress relaxation layer 22 may be formed.

  As shown in FIG. 5H, the wafer of the circuit board 21 is stuck on the semiconductor wafer 60 to which the stress relaxation layer 22 is stuck. The circuit board 21 and the semiconductor wafer 60 are connected to each other by the connection terminal 20.

  Note that when the circuit board 21 and the semiconductor wafer 60 are connected to each other, the connection terminal 20 has a lower height than before connection. Therefore, the stress relaxation layer 22 is formed in a sheet shape having a thickness slightly lower than that of the connection terminal 20 before connection.

  As shown in FIG. 5I, the integrated semiconductor wafer 60, translucent substrate 70, and circuit substrate 21 are cut into individual pieces. In FIG. 5I, reference numeral 81 represents a cutting position. As a cutting method, blade dicing, laser dicing, or the like can be applied. Laser dicing is a preferred method because it is excellent in workability of a thinned semiconductor wafer, can reduce the width of cutting, and can suppress the occurrence of burrs on the cut surface.

  As shown in FIG. 5J, the semiconductor device is completed through the above-described steps.

  Here, the semiconductor wafer 60, the stress relaxation layer 22, and the circuit board 21 have been described as being separated after being connected. However, after the semiconductor wafer 60 and the stress relaxation layer 22 are connected, the individual pieces are separated. The process sequence may be such that the circuit board 21 is pasted on the stress relaxation layer 22 that has been made into individual pieces.

  That is, the order of the steps for manufacturing the semiconductor device can be changed as appropriate, and the above-described steps are examples.

  According to the present technology, as described above, even if the stress relaxation layer 22 includes the lattice material 51 having the lattice structure, the number of manufacturing steps of the semiconductor device is not increased or complicated. Therefore, it is possible to prevent an increase in manufacturing cost by diverting an existing manufacturing process.

  In addition, even when heat is applied in a product test after manufacturing, as described above, the stress relaxation layer 22 absorbs the difference in linear expansion coefficient between the semiconductor substrate 11 and the circuit substrate 21, and cracks are generated. It is possible to more reliably prevent the occurrence of the above.

  According to the present technology, as described above, since it is possible to prevent the occurrence of cracks and the like, it is possible to improve the quality and reliability of the semiconductor device.

<Configuration of imaging device>
The semiconductor device described above includes an image capturing unit (photoelectric conversion) such as an imaging device such as a digital still camera or a video camera, a portable terminal device having an imaging function such as a mobile phone, and a copying machine using the imaging device for an image reading unit. The present invention can be applied to all electronic devices using semiconductor devices.

  FIG. 6 is a block diagram illustrating an example of a configuration of an electronic apparatus according to the present technology, for example, an imaging apparatus. As illustrated in FIG. 6, an imaging apparatus 200 according to the present technology includes an optical system including a lens group 201 and the like, an imaging element (imaging device) 202, a DSP circuit 203, a frame memory 204, a display device 205, a recording device 206, and an operation. A system 207, a power supply system 208, and the like are included. A DSP circuit 203, a frame memory 204, a display device 205, a recording device 206, an operation system 207, and a power supply system 208 are connected to each other via a bus line 209.

  The lens group 201 takes in incident light (image light) from a subject and forms an image on the imaging surface of the imaging element 202. The imaging element 202 converts the amount of incident light imaged on the imaging surface by the lens group 201 into an electrical signal in units of pixels and outputs it as a pixel signal.

  The display device 205 includes a panel type display device such as a liquid crystal display device or an organic EL (electroluminescence) display device, and displays a moving image or a still image captured by the image sensor 202. The recording device 206 records a moving image or a still image captured by the image sensor 202 on a recording medium such as a DVD (Digital Versatile Disk) or an HDD (Hard disk drive).

  The operation system 207 issues operation commands for various functions of the imaging apparatus under operation by the user. The power supply system 208 appropriately supplies various power supplies serving as operation power supplies for the DSP circuit 203, the frame memory 204, the display device 705, the recording device 206, and the operation system 207 to these supply targets.

  The imaging apparatus having the above-described configuration can be used as an imaging apparatus such as a video camera, a digital still camera, and a camera module for mobile devices such as a mobile phone. In the imaging device, the above-described semiconductor device can be used as the imaging element 202.

  <Usage example of semiconductor device>

  FIG. 7 is a diagram illustrating a usage example in which the above-described semiconductor device is used.

  The semiconductor device described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays as follows.

・ Devices for taking images for viewing, such as digital cameras and mobile devices with camera functions ・ For safe driving such as automatic stop and recognition of the driver's condition, Devices used for traffic, such as in-vehicle sensors that capture the back, surroundings, and interiors of vehicles, surveillance cameras that monitor traveling vehicles and roads, and ranging sensors that measure distances between vehicles, etc. Equipment used for home appliances such as TVs, refrigerators, air conditioners, etc. to take pictures and operate the equipment according to the gestures ・ Endoscopes, equipment that performs blood vessel photography by receiving infrared light, etc. Equipment used for medical and health care ・ Security equipment such as security surveillance cameras and personal authentication cameras ・ Skin measuring instrument for photographing skin and scalp photography Such as a microscope to do beauty Equipment used for sports-Equipment used for sports such as action cameras and wearable cameras for sports applications-Used for agriculture such as cameras for monitoring the condition of fields and crops apparatus

  In addition, the effect described in this specification is an illustration to the last, and is not limited, Moreover, there may exist another effect.

  The embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

  In addition, this technique can also take the following structures.

(1)
A first substrate;
A second substrate;
A semiconductor device comprising: a stress relaxation layer having a lattice structure between the first substrate and the second substrate.
(2)
The semiconductor device according to (1), wherein the stress relaxation layer is a layer formed in a sheet shape in which a material having a lattice structure is impregnated with a resin.
(3)
The semiconductor device according to (1) or (2), wherein a linear expansion coefficient of the stress relaxation layer is a value approximately halfway between a linear expansion coefficient of the first substrate and a linear expansion coefficient of the second substrate.
(4)
The semiconductor device according to any one of (1) to (3), wherein a connection terminal that connects the first substrate and the second substrate is located in a lattice of the lattice structure of the stress relaxation layer.
(5)
An image sensor is disposed on the first substrate,
The semiconductor device according to any one of (1) to (4), wherein a circuit that processes a signal from the imaging element is disposed on the second substrate.
(6)
Applying a stress relaxation layer having a lattice structure to the first substrate or the second substrate,
The manufacturing apparatus which separates into pieces in a state where the stress relaxation layer is located between the first substrate and the second substrate.
(7)
Applying a stress relaxation layer having a lattice structure to the first substrate or the second substrate,
The manufacturing method including the step of separating into pieces in a state where the stress relaxation layer is located between the first substrate and the second substrate.

  DESCRIPTION OF SYMBOLS 1 Image pick-up element chip, 2 Translucent cover member, 3 Fixing member, 4 Pixel area | region, 11 Semiconductor substrate, 12 Microlens, 13 Color filter, 14 Surface electrode, 15 Through electrode, 16 Conductive film, 17 Wiring, 18 Insulating film , 19 Insulating member, 20 Connection terminal, 21 Circuit board, 22 Stress relaxation layer, 31 Cover glass, 51 Lattice material, 52 Resin

Claims (7)

A first substrate;
A second substrate;
A semiconductor device comprising: a stress relaxation layer having a lattice structure between the first substrate and the second substrate. The semiconductor device according to claim 1, wherein the stress relaxation layer is a layer formed in a sheet shape in which a material having a lattice structure is impregnated with a resin. The semiconductor device according to claim 1, wherein a linear expansion coefficient of the stress relaxation layer is a value approximately in the middle of a linear expansion coefficient of the first substrate and a linear expansion coefficient of the second substrate. The semiconductor device according to claim 1, wherein a connection terminal that connects the first substrate and the second substrate is located in a lattice of the lattice structure of the stress relaxation layer. An image sensor is disposed on the first substrate,
The semiconductor device according to claim 1, wherein a circuit for processing a signal from the image sensor is disposed on the second substrate. Applying a stress relaxation layer having a lattice structure to the first substrate or the second substrate,
The manufacturing apparatus which separates into pieces in a state where the stress relaxation layer is located between the first substrate and the second substrate. A stress relaxation layer having a lattice structure is attached to the first substrate or the second image pickup device substrate,
The manufacturing method including the step of separating into pieces in a state where the stress relaxation layer is located between the first substrate and the second substrate.

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