JP2015220250A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that can enhance the current driving capability of a driver transistor disposed on a cell shelf.SOLUTION: A semiconductor device has: power supply wires L1 to L4 extending in a Y-direction along a cell shelf CT; power supply wires L5 to L8 which extend in an X-direction so as to traverse the cell shelf CT and are connected to the power supply wires L1 to L4 via through hole conductor TH2, respectively; a driver transistor M1 for connecting the power wires L1 and L2 in response to a control signal S1; and a driver transistor M2 for connecting the power supply wires L3 and L4 in response to a control signal S2. The driver transistors M1 and M2 are arranged in the X-direction in the same cell shelf CT. According to the above configuration, the parasitic resistance components of the driver transistors M1, M2 laid out in the cell shelf CT can be reduced, so that the current driving capability of the driver transistors M1, M2 can be enhanced.

Description

  The present invention relates to a semiconductor device, and more particularly to a standard cell type semiconductor device.

  In recent years, semiconductor devices using a so-called pseudo power supply method have been widely known in order to reduce current consumption during standby. As described in Patent Documents 1 and 2, the pseudo power supply method is a method in which a sub power supply wiring is provided separately from the main power supply wiring. In the standby mode, the main power supply wiring is turned off by turning off the driver transistor. Sub power supply wiring is disconnected from Thereby, it is possible to reduce the off-leakage current of the logic circuit connected to the sub power supply wiring.

  On the other hand, in many semiconductor devices, a so-called standard cell system is adopted. The standard cell system is a system in which a pair of power supply wires extending in parallel is defined as a cell shelf, and standard cells including P-channel MOS transistors and N-channel MOS transistors are repeatedly arranged on the cell shelf.

  In the standard cell method, since the cell shelf height is constant, when laying out a transistor that requires a large driving capability, it is necessary to divide the source and drain regions into multiple parts and fold the gate wiring. is there. A transistor that requires a large driving capability corresponds to a driver transistor used in a pseudo power supply system.

JP 2000-48568 A JP 2011-222919 A

  However, a driver transistor used in the pseudo power supply method is required to have a very large current driving capability. For this reason, if the driver transistor is arranged on the cell shelf in the same layout as a general logic circuit, the shape of the driver transistor along the extending direction of the cell shelf becomes very long. For this reason, there has been a problem that the parasitic resistance increases and the current driving capability of the driver transistor decreases.

  A semiconductor device according to an aspect of the present invention is provided in a cell shelf extending in a first direction and having a predetermined width in a second direction intersecting the first direction, and a first wiring layer, The first, second, third and fourth power supply lines extending in the first direction along the cell shelf and provided in a second wiring layer different from the first wiring layer; First, fifth, sixth, seventh, and eighth power lines extending in the second direction so as to cross the cell shelf, and a first line that connects the first power line and the fifth power line A through-hole conductor, a second through-hole conductor connecting the second power wiring and the sixth power wiring, and a third through hole connecting the third power wiring and the seventh power wiring A conductor, a fourth through-hole conductor connecting the fourth power supply wiring and the eighth power supply wiring, and the cell A first driver transistor for connecting the first power supply wiring and the second power supply wiring in response to a first control signal; and provided in the cell shelf and responding to a second control signal. And a second driver transistor connecting the third power supply wiring and the fourth power supply wiring, and the first driver transistor and the second driver transistor are mutually in the first direction. It is arranged.

  A semiconductor device according to another aspect of the present invention includes first and second cell shelves each extending in a first direction and having a predetermined width in a second direction intersecting the first direction, 1st, 2nd, 3rd and 4th power supply wiring, 1st, 2nd and 3rd signal wiring, provided in the 1st cell shelf, the 1st in response to the 1st control signal A first driver transistor for connecting the second power supply wiring and the second power supply wiring; and the third power supply wiring and the fourth driver transistor provided in the first cell shelf in response to a second control signal. A second driver transistor for connecting a power supply line and a second driver transistor provided in the second cell shelf for connecting the first power supply line and the second signal line based on the level of the first signal line. 1 transistor and the second cell shelf, the level of the first signal wiring Therefore, the second power source wiring is provided on the second cell shelf, and the second power source wiring is connected to the second power source wiring based on the level of the second signal wiring. A third transistor connecting the wiring and the third signal wiring; and the third power wiring and the third signal provided on the second cell shelf and based on a level of the second signal wiring. A fourth transistor for connecting wiring, wherein the first driver transistor and the second driver transistor are arranged in the first direction, and the first and third transistors and the second transistor are connected to each other. The fourth transistor is arranged in the second direction with respect to each other.

  According to the present invention, the parasitic resistance component of the driver transistor laid out on the cell shelf can be reduced. As a result, the current driving capability of the driver transistor can be improved.

1 is a schematic plan view for explaining a layout of a semiconductor device 10 according to an embodiment of the present invention. 2 is a block diagram for explaining a circuit configuration of a semiconductor device 10; FIG. It is a circuit diagram for demonstrating the principle of a pseudo power supply system. It is a typical top view which shows an example of the circuit block BLK using a standard cell system. It is a schematic plan view showing a power supply network formed on the circuit block BLK. It is a top view which shows the example which has arrange | positioned the inverter circuits 41 and 42 to the cell shelf CT. It is sectional drawing along the AA line of FIG. It is a top view which shows the structure of the driver transistors M1 and M2 by the prototype examined in the process which completes this invention. It is sectional drawing along the BB line of FIG. It is an operation | movement waveform diagram for demonstrating the influence of the parasitic resistance by a 1st metal wiring layer. FIG. 3 is a plan view showing a configuration of driver transistors M1, M2 according to an embodiment of the present invention. It is sectional drawing along CC line of FIG. It is sectional drawing along the DD line of FIG. It is sectional drawing along the EE line of FIG. It is sectional drawing along the FF line of FIG. 9 is a graph showing resistance values of resistors R3 and R4, where (a) shows resistance values when the prototype layout shown in FIG. 8 is adopted, and (b) shows the layout according to the embodiment shown in FIG. In this case, the resistance value is shown. It is a schematic diagram for demonstrating the influence at the time of reducing the width | variety of cell shelf CT, (a) shows the case where the layout by a prototype is employ | adopted, (b) shows the case where the layout by this embodiment is employ | adopted. ing. It is a graph which shows the relationship between the width | variety in the X direction of cell shelf CT, and the channel width which can be formed. It is a top view which shows the structure by the 1st modification of driver transistor M1, M2. It is a top view which shows the structure by the 2nd modification of driver transistor M1, M2. It is a typical top view which shows the layout of the circuit block BLK by a modification. FIG. 10 is a plan view showing a configuration according to a third modification of driver transistors M1, M2. It is a typical top view for demonstrating the layout of the semiconductor device 10a by the 1st modification. It is a typical top view for demonstrating the layout of the semiconductor device 10b by the 2nd modification.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic plan view for explaining a layout of a semiconductor device 10 according to an embodiment of the present invention.

  The semiconductor device 10 according to the present embodiment is a DRAM (Dynamic Random Access Memory), and is integrated on a semiconductor substrate 2 having a rectangular planar shape as shown in FIG. However, the semiconductor device according to the present invention is not limited to the DRAM, and the present invention can be applied to other types of semiconductor devices.

  The semiconductor device 10 according to the present embodiment includes two channels CHA and CHB. The channels CHA and CHB can be accessed independently from the outside, and each of the channels CHA and CHB includes a memory cell array, an access control circuit, an external terminal, and the like. All the circuits are basically separated between the channels CHA and CHB. Therefore, channels CHA and CHB operate in synchronization with different clock signals, and different external terminals are used for reception of command address signal CA and input / output of data DQ. That is, each channel CHA, CHB can be regarded as one independent DRAM, and in this respect, it is distinguished from an access unit called a bank.

  As shown in FIG. 1, the semiconductor device 10 includes a pad row PA arranged in the X direction along one edge EG1 in the Y direction of the semiconductor substrate 2 and the other edge EG2 in the Y direction of the semiconductor substrate 2. And a pad row PB arranged in the X direction. The pad row PA consists of external terminals assigned to the channel CHA, and the pad row PB consists of external terminals assigned to the channel CHB.

  A peripheral circuit of the channel CHA is arranged in the vicinity of the pad row PA, and a peripheral circuit of the channel CHB is arranged in the vicinity of the pad row PB. The peripheral circuits include command address control circuits 21A and 21B, data input / output circuits 22A and 22B, access control circuits 31A and 31B, and the like. In the example shown in FIG. 1, data input / output circuits 22A and 22B are arranged on both sides in the X direction, and command address control circuits 21A and 21B are arranged so as to be sandwiched therebetween. The access control circuits 31A and 31B are arranged between the memory cell arrays 30A and 30B, the command address control circuits 21A and 21B, and the data input / output circuits 22A and 22B, and the memory cell array 30A divided into a plurality of areas. , 30B.

  FIG. 2 is a block diagram for explaining a circuit configuration of the semiconductor device 10.

  As shown in FIG. 2, the semiconductor device 10 includes a command address terminal 11A, a data input / output terminal 12A and power supply terminals 13A and 14A belonging to the channel CHA, a command address terminal 11B, a data input / output terminal 12B and a power supply belonging to the channel CHB. Terminals 13B and 14B are provided. The command address terminal 11A, the data input / output terminal 12A, and the power supply terminals 13A and 14A are included in the pad row PA. On the other hand, the command address terminal 11B, the data input / output terminal 12B, and the power supply terminals 13B and 14B are included in the pad row PB.

  The command address terminal 11A is an external terminal to which a command address signal CAA corresponding to the channel CHA is input, and is connected to the command address control circuit 21A. The command address control circuit 21A receives the command address signal CAA and controls the operation of the access control circuit 31A. In the read operation, the access control circuit 31A reads data from the memory cell array 30A and supplies it to the data input / output circuit 22A. The data input / output circuit 22A outputs the read data DQA to the outside from the data input / output terminal 12A. On the other hand, the access control circuit 31A writes data DQA inputted from the outside via the data input / output terminal 12A and the data input / output circuit 22A to the memory cell array 30A during the write operation.

  The command address terminal 11B is an external terminal to which a command address signal CAB corresponding to the channel CHB is input, and is connected to the command address control circuit 21B. The command address control circuit 21B receives the command address signal CAB and controls the operation of the access control circuit 31B. The access control circuit 31B reads data from the memory cell array 30B during the read operation and supplies it to the data input / output circuit 22B. The data input / output circuit 22B outputs the read data DQB from the data input / output terminal 12B to the outside. On the other hand, the access control circuit 31B writes data DQB input from the outside via the data input / output terminal 12B and the data input / output circuit 22B to the memory cell array 30B during the write operation.

  Thus, the channel CHA and the channel CHB are configured by independent circuit blocks. For this reason, it can be handled from the outside as two DRAMs. However, some circuits such as the calibration circuit 23A and the reset circuit 24B are shared. Specifically, the calibration circuit 23A is provided only on the channel CHA side, and the calibration operation using the calibration terminal ZQ is executed only on the channel CHA. The result of the calibration operation is reflected in common to the data input / output circuits 22A and 22B of the channels CHA and CHB. The reset circuit 24B is provided only on the channel CHB side, and the reset signal RST supplied from the outside to the reset terminal 15B is received by the channel CHB. When the reset signal RST is activated, both the channels CHA and CHB are reset.

  The power supply terminals 13A and 13B are terminals to which a power supply potential VDD is supplied from the outside. The power terminals 14A and 14B are terminals to which a power supply potential VSS (ground potential) is supplied from the outside. The power supply terminal 13A is assigned to the channel CHA and the power supply terminal 13B is assigned to the channel CHB. However, as shown in FIG. 2, the power supply terminals 13A and 13B are short-circuited inside the chip via the power supply wiring VL. Yes. Similarly, the power supply terminal 14A is assigned to the channel CHA, and the power supply terminal 14B is assigned to the channel CHB. However, as shown in FIG. 2, the power supply terminals 14A and 14B are provided inside the chip via the power supply line SL. It is short-circuited.

  The power supply lines VL and SL are connected to command address control circuits 21A and 21B, data input / output circuits 22A and 22B, memory cell arrays 30A and 30B, access control circuits 31A and 31B, and the like. As a result, the power supply potentials VDD and VSS are supplied to the circuit blocks as operation power supplies.

  In the semiconductor device 10 according to the present embodiment, the pseudo power supply method is adopted in some circuit blocks. The circuit block using the pseudo power supply method is not particularly limited, but the pseudo power supply method can be applied to the command address control circuits 21A and 21B and the access control circuits 31A and 31B.

  FIG. 3 is a circuit diagram for explaining the principle of the pseudo power supply system.

  As shown in FIG. 3, in the pseudo power supply method, the main power supply wiring L1 and the sub power supply wiring L2 are used as the power supply wiring for supplying the high power supply potential VDD, and the low power supply potential VSS is supplied. The main power supply wiring L3 and the sub power supply wiring L4 are used as the power supply wiring. The main power supply wiring L1 is a wiring that is always supplied with the power supply potential VDD, and the main power supply wiring L3 is a wiring that is always supplied with the power supply potential VSS.

  On the other hand, the sub power supply line L2 is connected to the main power supply line L1 via the driver transistor M1. The driver transistor M1 is composed of a P-channel MOS transistor, and has a source connected to the main power supply line L1 and a drain connected to the sub power supply line L2. The control signal S1 is supplied to the gate electrode of the driver transistor M1. As a result, when the control signal S1 is activated to the low level, the power supply potential VDD is supplied to the sub power supply line L2 via the driver transistor M1. On the other hand, during the period when the control signal S1 is inactivated to the high level, the sub power supply line L2 is disconnected from the main power supply line L1 and is in a floating state.

  Similarly, the sub power supply line L4 is connected to the main power supply line L3 via the driver transistor M2. The driver transistor M2 is formed of an N-channel MOS transistor, and has a source connected to the main power supply line L3 and a drain connected to the sub power supply line L4. The control signal S2 is supplied to the gate electrode of the driver transistor M2. As a result, when the control signal S2 is activated to a high level, the power supply potential VSS is supplied to the sub power supply line L4 via the driver transistor M2. On the other hand, during the period in which the control signal S2 is inactivated to the low level, the sub power supply line L4 is disconnected from the main power supply line L3 and is in a floating state.

  The control signal S1 and the control signal S2 are complementary signals, and are activated to a low level and a high level, respectively, in the active state. As a result, the power supply potential VDD is supplied to the sub power supply wiring L2, and the power supply potential VSS is supplied to the sub power supply wiring L4. On the other hand, in the standby state, they are deactivated to the high level and the low level, respectively, and the sub power supply lines L2 and L4 are both in the floating state.

  A desired logic circuit LOG is connected to the power supply lines L1 to L4. FIG. 3 shows two stages of inverter circuits 41 and 42 connected in series as the simplest example. The input node of the first-stage inverter circuit 41 is connected to the signal wiring 51, and the output node is connected to the signal wiring 52. The input node of the second-stage inverter circuit 42 is connected to the signal wiring 52, and the output node is connected to the signal wiring 53. An input signal IN is supplied to the signal wiring 51, and an output signal OUT is output from the signal wiring 53.

  As shown in FIG. 3, the inverter circuit 41 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1. The source of the transistor P1 is connected to the main power supply line L1, and the drain is connected to the signal line 52. The source of the transistor N1 is connected to the sub power supply line L4, and the drain is connected to the signal line 52. The gate electrodes of the transistors P1 and N1 are connected to the signal wiring 51 in common.

  Similarly, the inverter circuit 42 includes a P-channel MOS transistor P2 and an N-channel MOS transistor N2. The source of the transistor P2 is connected to the sub power supply line L2, and the drain is connected to the signal line 53. The source of the transistor N2 is connected to the main power supply line L3, and the drain is connected to the signal line 53. The gate electrodes of the transistors P2 and N2 are commonly connected to the signal wiring 52.

  With this configuration, when the driver transistors M1 and M2 are both in an active state, that is, when the power supply potential VDD is supplied to the sub power supply line L2 and the power supply potential VSS is supplied to the sub power supply line L4. The logic level of the output signal OUT changes correctly based on the logic level of the input signal IN.

  On the other hand, when the driver transistors M1 and M2 are both in the standby state, that is, when the sub power supply lines L2 and L4 are in the floating state, both the inverter circuits 41 and 42 are deactivated. The Here, if the logic level of the input signal IN during standby is low, the transistors P1 and N2 are turned on, so that the logic level of the output signal OUT can be maintained at low level. Since no power is supplied to the sources of the transistors N1 and P2, almost no off-leakage current flows.

  As described above, when the pseudo power supply method is used, it is possible to perform a normal logical operation in the active state and maintain a predetermined logical level while reducing the off-leakage current in the standby state.

  However, when the pseudo power supply method is employed, the driver transistor is required to have a very large current driving capability. This is because the source potential (VDD) needs to be supplied to many P-channel MOS transistors included in the logic circuit LOG for the driver transistor M1, and many of the driver transistors M2 included in the logic circuit LOG. This is because it is necessary to supply the source potential (VSS) to the N-channel MOS transistor. Specifically, the driver transistors M1 and M2 require a channel width that is three to six times the total channel width of the transistors constituting the logic circuit LOG. For this reason, when the driver transistors M1 and M2 and the logic circuit LOG are mixed and laid out, the occupation ratio of the driver transistors M1 and M2 increases.

  FIG. 4 is a schematic plan view showing an example of a circuit block BLK using the standard cell method. FIG. 5 is a schematic plan view showing a power supply network formed on the circuit block BLK.

  In the circuit block BLK shown in FIG. 4, a plurality of cell shelves CT extending in the Y direction are arranged in the X direction, a logic circuit LOG is arranged in a predetermined cell shelf CT, and other cell shelves CT are arranged in the other cell shelf CT. Driver transistors M1 and M2 are arranged. The width of the cell shelf CT in the X direction is constant.

  Then, as shown in FIG. 5, a mesh-like power supply network is constructed on the circuit block BLK, whereby the power supply potential VDD or VSS is supplied to the sources of the transistors constituting each logic circuit LOG. In FIG. 5, the wiring indicated by the solid line extending in the Y direction is the higher power supply line L1 or L2, and the wiring indicated by the broken line extending in the Y direction is the lower power supply wiring L3 or L4. It is. Here, the power supply lines L1 to L4 extending in the Y direction are provided along the boundary of the cell shelf CT.

  The power supply wirings L1 to L4 are connected to power supply wirings L5 to L8 located in the upper layers, respectively. In FIG. 5, the wiring indicated by the solid line extending in the X direction is the higher power supply wiring L5 or L6, and the wiring indicated by the broken line extending in the X direction is the lower power supply wiring L7 or L8. It is. The power supply lines L1 to L4 are connected to the power supply lines L5 to L8 via through-hole conductors (not shown), thereby forming a mesh-shaped power supply network.

  FIG. 6 is a plan view showing an example in which the inverter circuits 41 and 42 shown in FIG. 3 are arranged on the cell shelf CT. FIG. 7 is a cross-sectional view taken along the line AA in FIG.

  As shown in FIG. 6, a cell shelf CT in which logic circuits LOG such as inverter circuits 41 and 42 are arranged is divided into two in the X direction, and one is used as a P channel region PTR and the other is used as an N channel region NTR. The P channel region PTR is a region where a P channel type MOS transistor is formed, and power supply lines L1 and L2 for supplying a power supply potential VDD which is a source potential are arranged above the P channel region PTR. The N-channel region NTR is a region where an N-channel MOS transistor is formed, and power supply lines L3 and L4 for supplying a power supply potential VSS which is a source potential are arranged above the N-channel region NTR.

A well contact region WCN and a substrate contact region SCN extending in the Y direction are formed between the P channel region PTR and the N channel region NTR. The well contact region WCN is an N ⁺ diffusion layer for supplying a substrate potential to an N well region 62 described later, and the substrate contact region SCN is a P ⁺ diffusion layer for supplying a substrate potential to a semiconductor substrate 61 described later. It is.

  As shown in FIG. 7, the P channel region PTR is constituted by an N well region 62 formed in a P type semiconductor substrate 61. A P-type source region 63 and a drain region 64 are formed on the surface of the N well region 62. A channel region is formed between the source region 63 and the drain region 64, and a gate electrode G is disposed above the channel region via a gate insulating film 65. Thereby, a P-channel MOS transistor is configured. The source region 63 and the drain region 64 are connected to the wiring W via the contact conductor CE. The wiring W is formed in a tungsten wiring layer located above the gate wiring layer.

  Although not shown, the N channel region NTR is constituted by a P type semiconductor substrate 61, and an N type source region and a drain region are formed on the surface thereof. A gate electrode is disposed above the channel region via a gate insulating film, thereby forming an N-channel MOS transistor. Also in the N-channel MOS transistor, the source region and the drain region are connected to the wiring W through the contact conductor CE.

  As shown in FIG. 7, the source region 63 of the transistor P1 is connected to the main power supply wiring L1 via the contact conductor CE, the wiring W, and the through-hole conductor TH1. Although not shown, the source region 63 of the transistor P2 is connected to the sub power supply wiring L2 via the contact conductor CE, the wiring W, and the through-hole conductor TH1. Similarly, the source region 63 of the transistor N1 is connected to the sub power supply wiring L4 via the contact conductor CE, the wiring W, and the through-hole conductor TH1, and the source region 63 of the transistor N2 is connected to the contact conductor CE, the wiring W, and the through-hole. It is connected to the main power supply wiring L3 through the conductor TH1.

  Further, as shown in FIG. 6, the gate electrodes G of the transistors P <b> 1 and N <b> 1 are connected to the signal wiring 51. The drain regions 64 of the transistors P1 and N1 are connected to the signal wiring 52 through the contact conductor CE and the wiring W. The signal wiring 52 is connected to the gate electrodes G of the transistors P2 and N2. The drain regions 64 of the transistors P2 and N2 are connected to the signal wiring 53 through the contact conductor CE and the wiring W.

  As described above, the cell shelf CT in which the logic circuit LOG is formed is divided into two in the X direction, and a P-channel MOS transistor is formed on one side and an N-channel MOS transistor is formed on the other side.

  FIG. 8 is a plan view showing the configuration of prototype driver transistors M1 and M2 studied in the course of completing the present invention. FIG. 9 is a cross-sectional view taken along line BB in FIG.

  As shown in FIGS. 8 and 9, the prototype driver transistors M1 and M2 are arranged adjacent to each other in the X direction in one cell shelf CT, similarly to the logic circuit LOG shown in FIGS. Yes. That is, the cell shelf CT is divided into two in the X direction, the driver transistor M1 is formed in the P channel region PTR, and the driver transistor M2 is formed in the N channel region NTR. The power supply lines L1 and L2 are arranged extending in the Y direction above the P channel region PTR. In addition, power supply lines L3 and L4 are arranged extending in the Y direction above the N channel region NTR.

  The driver transistor M1 has a configuration in which a plurality of source regions 63 and a plurality of drain regions 64 are alternately arranged in the Y direction, whereby a plurality of channels are formed. A gate electrode G is formed above each channel region via a gate insulating film 65. A control signal S1 is commonly supplied to these gate electrodes G. The plurality of source regions 63 are commonly connected to the main power supply wiring L1 through the contact conductor CE, the wiring W, and the through-hole conductor TH1. The plurality of drain regions 64 are commonly connected to the sub power supply wiring L2 via the contact conductor CE, the wiring W, and the through-hole conductor TH1. As a result, a configuration in which a large number of transistors are connected in parallel can be obtained, so that a large current driving capability can be obtained.

  The driver transistor M2 has a configuration in which a plurality of source regions 63 and a plurality of drain regions 64 are alternately arranged in the Y direction, whereby a plurality of channels are formed. A gate electrode G is formed above each channel region via a gate insulating film 65. A control signal S2 is commonly supplied to these gate electrodes G. The plurality of source regions 63 are commonly connected to the main power supply wiring L3 via the contact conductor CE, the wiring W, and the through-hole conductor TH1. The plurality of drain regions 64 are commonly connected to the sub power supply wiring L4 via the contact conductor CE, the wiring W, and the through-hole conductor TH1. As a result, a configuration in which a large number of transistors are connected in parallel can be obtained, so that a large current driving capability can be obtained.

  These power supply wirings L1 to L4 are formed in a first metal wiring layer located above the tungsten wiring layer. In the first metal wiring layer, wiring extending mainly in the Y direction is formed. A second metal wiring layer is provided further above the first metal wiring layer. In the second metal wiring layer, wiring extending mainly in the X direction is formed. For example, aluminum is used as the material of the first metal wiring layer and the second metal wiring layer.

  As shown in FIG. 8, power supply wirings L5 to L8 are formed in the second metal wiring layer. The power supply lines L5 to L8 are connected to the power supply lines L1 to L4 through the through-hole conductors TH2, respectively. Therefore, the power supply lines L1 and L5 have the same potential, the power supply lines L2 and L6 have the same potential, the power supply lines L3 and L7 have the same potential, and the power supply lines L4 and L8 have the same potential. Since the power supply lines L1 to L4 extend in the Y direction and the power supply lines L5 to L8 extend in the X direction, a mesh-shaped power supply network is constructed by connecting them with the through-hole conductor TH2. .

  Since the power supply wirings L5 to L8 are formed in the upper second metal wiring layer, the wiring width is wider than the power supply wirings L1 to L4, and the wiring thickness is also thicker than the power supply wirings L1 to L4. For this reason, the power supply lines L5 to L8 have lower resistance than the power supply lines L1 to L4, and function as so-called power supply trunk lines.

  In the example shown in FIG. 8, the through-hole conductor TH2 that connects the power supply lines L1 and L2 and the power supply lines L5 and L6 is provided in a region 71 located on one side and a region 73 located on the other side of the driver transistor M1. ing. This is because the power supply lines L5 and L6 are provided extending in the X direction so as to pass through the regions 71 and 73. On the other hand, the through-hole conductor TH2 that connects the power supply wirings L3 and L4 and the power supply wirings L7 and L8 is provided in a region 72 located in the center of the driver transistor M2 in the Y direction. This is because the power supply lines L7 and L8 are provided extending in the X direction so as to pass through the region 72.

  As a result, for the driver transistor M1, the wiring resistance in the region 72 is higher than the wiring resistance in the regions 71 and 73. Conversely, for the driver transistor M 2, the wiring resistance in the regions 71 and 73 is higher than the wiring resistance in the region 72. This is because the resistance values of the power supply lines L1 to L4 formed in the first metal wiring layer are relatively high, and the parasitic resistance due to the first metal wiring layer increases as the distance in the Y direction from the through-hole conductor TH2 increases. Because it becomes.

  As described above, the prototype driver transistors M1 and M2 shown in FIGS. 8 and 9 have a problem that the current drive capability is lowered because the parasitic resistance due to the first metal wiring layer is large.

  FIG. 10 is an operation waveform diagram for explaining the influence of the parasitic resistance due to the first metal wiring layer.

  In FIG. 10, the symbol IN is the waveform of the input signal IN shown in FIG. 3, and the symbols OUT1 and OUT2 are the waveforms of the output signal OUT shown in FIG. First, when the parasitic resistance due to the first metal wiring layer is small, when the input signal IN changes from the low level to the high level, the output signal OUT1 changes from the low level to the high level at a predetermined slew rate with a predetermined delay time. . However, when the parasitic resistance due to the first metal wiring layer is large, the driving capability of the logic circuit LOG is lowered, so that the slew rate of the output signal OUT1 is lowered, and the time until it reaches the high level from the low level becomes long. As a result, the signal transmission time increases from the design value.

  FIG. 11 is a plan view showing the configuration of the driver transistors M1, M2 according to the embodiment of the present invention. FIG. 12 is a cross-sectional view taken along the line CC in FIG. 13 is a cross-sectional view taken along the line DD of FIG. FIG. 14 is a cross-sectional view taken along line EE in FIG. 15 is a cross-sectional view taken along line FF in FIG. 12 to 15, the tungsten wiring layer is omitted.

  As shown in FIGS. 11 to 15, the driver transistors M1 and M2 according to the present embodiment are arranged in the Y direction in the same cell shelf CT. In the example shown in FIG. 11, two driver transistors M1 formed in the regions 81 and 83 and one driver transistor M2 formed in a region 82 sandwiched between the driver transistors M1 are shown. Thus, in the present embodiment, the arrangement method of the driver transistors M1 and M2 in the cell shelf CT is different from that of the logic circuit LOG. For this reason, the pattern of the N well region 62 formed in the semiconductor substrate 61 also needs to have a pattern shape different from that of the cell shelf CT in which the logic circuit LOG is formed.

  In the regions 81 and 83, an N-well region 62 is formed in the entire width in the X direction of the cell shelf CT, whereby the entire width in the X direction of the cell shelf CT is used as the P channel region PTR. On the other hand, in the region 82, the semiconductor substrate 61 is exposed to the full width in the X direction of the cell shelf CT, and thus the full width in the X direction of the cell shelf CT is used as the N channel region NTR. The P channel region PTR and the N channel region NTR are arranged in the Y direction which is the extending direction of the cell shelf CT in the same cell shelf CT.

  Above the P channel region PTR, power supply lines L1 and L2 are arranged extending in the Y direction. In addition, power supply lines L3 and L4 are arranged extending in the Y direction above the N channel region NTR. In the example shown in FIG. 11, two power supply lines L1 and L2 are arranged on both sides in the P channel region PTR, and two power supply lines L3 and L4 are arranged on both sides in the N channel region NTR. The main power supply line L1 and the main power supply line L3 are located on the extension line, and the sub power supply line L2 and the sub power supply line L4 are located on the extension line. Thus, the power supply wirings L1 to L4 have a configuration divided for each region. However, it may be laid out such that the main power supply line L1 and the sub power supply line L4 are positioned on the extension line, and the sub power supply line L2 and the main power supply line L3 are positioned on the extension line.

  The driver transistor M1 has a configuration in which a plurality of source regions 63 and a plurality of drain regions 64 are alternately arranged in the Y direction, whereby a plurality of channels are formed. A gate electrode G is formed above each channel region via a gate insulating film 65. A control signal S1 is commonly supplied to these gate electrodes G. As shown in FIG. 12, the plurality of source regions 63 are connected in common to the main power supply wiring L1 through the through-hole conductor TH1. As shown in FIG. 13, the plurality of drain regions 64 are commonly connected to the sub power supply line L2 through the through-hole conductor TH1. As a result, a configuration in which a large number of transistors are connected in parallel can be obtained, so that a large current driving capability can be obtained.

  The driver transistor M2 has a configuration in which a plurality of source regions 63 and a plurality of drain regions 64 are alternately arranged in the Y direction, whereby a plurality of channels are formed. A gate electrode G is formed above each channel region via a gate insulating film 65. A control signal S2 is commonly supplied to these gate electrodes G. As shown in FIG. 14, the plurality of source regions 63 are connected in common to the main power supply wiring L3 through the through-hole conductor TH1. As shown in FIG. 15, the plurality of drain regions 64 are commonly connected to the sub power supply line L4 through the through-hole conductor TH1. As a result, a configuration in which a large number of transistors are connected in parallel can be obtained, so that a large current driving capability can be obtained.

  As shown in FIG. 11, power supply wirings L5 to L8 are formed in the second metal wiring layer. The power supply lines L5 to L8 are connected to the power supply lines L1 to L4 through the through-hole conductors TH2, respectively. Therefore, the power supply lines L1 and L5 have the same potential, the power supply lines L2 and L6 have the same potential, the power supply lines L3 and L7 have the same potential, and the power supply lines L4 and L8 have the same potential. Since the power supply lines L1 to L4 extend in the Y direction and the power supply lines L5 to L8 extend in the X direction, a mesh-like power supply network is constructed by connecting them with the through-hole conductor TH2.

  Since the power supply wirings L5 to L8 are formed in the upper second metal wiring layer, the wiring width is wider than the power supply wirings L1 to L4, and the wiring thickness is also thicker than the power supply wirings L1 to L4. For this reason, the power supply lines L5 to L8 have lower resistance than the power supply lines L1 to L4, and function as so-called power supply trunk lines. Power supply lines L5 and L6 are provided extending in the X direction so as to pass through P channel region PTR. Power supply lines L7 and L8 are provided extending in the X direction so as to pass through N channel region NTR.

  In the present embodiment, in the P-channel region PTR, through-hole conductors TH2 that connect the two main power supply lines L1 and the main power supply line L5 can be provided, and the two sub power supply lines L2 and the sub power supply lines can be provided. Through-hole conductors TH2 that connect L6 can be provided. Thereby, the resistance line segment by the through-hole conductor TH2 can be further reduced. In addition, since the length of the P channel region PTR in the Y direction is significantly reduced as compared with the prototype shown in FIG. 8, the lengths of the power supply lines L1 and L2 having relatively high resistance values can be shortened.

  Similarly, in the N channel region NTR, through-hole conductors TH2 for connecting the two main power supply lines L3 and L7 can be provided, and the two sub power supply lines L4 and the sub power supply lines L8 can be provided. A through-hole conductor TH2 to be connected can be provided. Thereby, the resistance line segment by the through-hole conductor TH2 can be further reduced. Moreover, since the length of the N channel region NTR in the Y direction is significantly reduced as compared with the prototype shown in FIG. 8, the lengths of the power supply lines L3 and L4 having relatively high resistance values can be shortened.

  With the above structure, in this embodiment, the parasitic resistance line segments of the driver transistors M1 and M2 can be significantly reduced. As a result, according to the present embodiment, the current drive capability of the driver transistors M1 and M2 can be increased.

  FIG. 16 is a graph showing the resistance values of the resistors R3 and R4, (a) shows the resistance values when the prototype layout shown in FIG. 8 is adopted, and (b) shows the embodiment shown in FIG. The resistance value when the layout is adopted is shown. As shown in FIG. 3, the resistor R3 is a resistance component existing between the main power supply line L3 and the driver transistor M2, and the resistor R4 is present between the sub power supply line L4 and the driver transistor M2. It is a resistance component.

  In FIG. 16A, the vertical axis represents measurement points, and the horizontal axis represents resistance values. Specifically, one end in the Y direction of the power supply wirings L3 and L4 located on the driver transistor M2 shown in FIG. 8 is set as the point 1, the other end in the Y direction is set as the point 31, and the power supply wirings L3 and L4 are set in the Y direction. The resistance value at each point when divided into 30 is shown.

  Similarly, the vertical axis in FIG. 16B indicates the measurement point, and the horizontal axis indicates the resistance value. Specifically, one end in the Y direction of the power supply wirings L3 and L4 located on the driver transistor M2 shown in FIG. 11 is set as the point 1, the other end in the Y direction is set as the point 11, and the power supply wirings L3 and L4 are set in the Y direction. The resistance value at each point when divided into 10 is shown. The distance between adjacent points is the same in FIG. 16 (a) and FIG. 16 (b).

  As shown in FIG. 16A, when the prototype layout is adopted, the resistance value becomes higher at the end portion, and the total resistance value R3 + R4 reaches about 7Ω at the end portion. On the other hand, as shown in FIG. 16B, in the case where the prototype layout is adopted, it is less than 6Ω even at the point 1 having the highest resistance value, and the reduction of the parasitic resistance is achieved. I understand.

  16A and 16B show the resistors R3 and R4 existing in the driver transistor M2, but the same effect can be obtained for the resistors R1 and R2 existing in the driver transistor M1.

  FIG. 17 is a schematic diagram for explaining the influence when the width of the cell shelf CT is reduced. FIG. 17A shows a case where a prototype layout is adopted, and FIG. 17B shows a layout according to the present embodiment. Shows the case.

  As shown in FIG. 17A, when the width in the X direction of the cell shelf CT extending in the Y direction is reduced due to the progress of miniaturization, the well contact region WCN and the substrate contact region SCN necessary for element isolation. Occupancy increases. This is because the width in the X direction necessary for element isolation hardly changes even when miniaturization proceeds. For this reason, when the width in the X direction of the cell shelf CT is reduced, the widths in the X direction of the P-channel region PTR and the N-channel region NTR in which the transistors are arranged are mainly reduced, and the driving capability of the transistor is greatly reduced. To do.

  On the other hand, as shown in FIG. 17B, in the layout according to the present embodiment, the well contact region WCN and the substrate contact region SCN necessary for element isolation extend in the X direction. When the width at is reduced, the region necessary for element isolation is also reduced accordingly. For this reason, it is possible to suppress a decrease in the driving capability of the transistor as compared with the prototype layout.

  FIG. 18 is a graph showing the relationship between the width of the cell shelf CT in the X direction and the channel width that can be formed. The horizontal axis indicates the width of the cell shelf CT in the X direction, and the vertical axis indicates the channel width that can be formed.

  As shown in FIG. 18, when the width of the cell shelf CT in the X direction is reduced, the channel width that can be formed is reduced in both the layout according to the prototype and the layout according to the embodiment. However, the reduction rate is larger for the prototype layout. For this reason, when the width of the cell shelf CT in the X direction is equal to or smaller than a predetermined value, the layout according to the present embodiment can secure a larger channel width. Since semiconductor devices are expected to be further miniaturized in the future, it can be said that it is more advantageous to adopt the layout according to the present embodiment for the driver transistors M1 and M2 that require a large channel width.

  FIG. 19 is a plan view showing the configuration of the first modification of the driver transistors M1 and M2 according to the present embodiment.

  As shown in FIG. 19, in the first modification, power supply lines L1 to L4 are provided extending in the X direction so as to cross the P channel region PTR and the N channel region NTR. That is, the power supply lines L1 to L4 are not divided for each region. Since the other points are the same as the layout shown in FIG. 11, the same elements are denoted by the same reference numerals, and redundant description is omitted. If the configuration shown in FIG. 19 is employed, the power supply lines L1 to L4 can be arranged without being divided in the extending direction of the cell shelf CT, similarly to the cell shelf CT in which the logic circuit LOG is formed. .

  FIG. 20 is a plan view showing a configuration according to a second modification of the driver transistors M1 and M2 according to the present embodiment.

  As shown in FIG. 20, the second modification is different from the layout shown in FIG. 19 in that the power supply lines L1 to L4 are arranged at the substantially central portion in the X direction of the cell shelf CT. . Since the other points are the same as those in the layout shown in FIG. 19, the same elements are denoted by the same reference numerals, and redundant description is omitted. If the configuration shown in FIG. 20 is adopted, it is possible to arrange other wiring using the first metal wiring layer at the end in the X direction of the cell shelf CT.

  FIGS. 21A to 21C are schematic plan views showing layouts of circuit blocks BLK according to modifications.

  In the layouts shown in FIGS. 21A to 21C, unlike the layout shown in FIG. 4, the logic circuit LOG and the driver transistors M1 and M2 are mixed in the same cell shelf CT. Thus, it is not necessary to completely distinguish the cell shelf CT for the logic circuit LOG and the driver transistors M1 and M2, and both may be mixed in one cell shelf CT. In this case, as shown in FIG. 21A, the region where the driver transistors M1 and M2 are formed may be laid out so as to extend in the X direction. As shown in FIG. The layout in which the regions where M1 and M2 are formed may extend in the X direction and the Y direction. Furthermore, as shown in FIG. 21C, the region where the driver transistors M1 and M2 are formed may be laid out at an arbitrary position.

  FIG. 22 is a plan view showing a configuration according to a third modification of the driver transistors M1 and M2 according to the present embodiment.

  As shown in FIG. 22, in the third modification, a P channel region PTR constituting the driver transistor M1 is arranged in the region 91, and an N channel region NTR constituting the driver transistor M2 is arranged in the region 93. A logic circuit LOG is arranged in a region 92 located between the two. Such a layout can be adopted when the driver transistors M1 and M2 and the logic circuit LOG are mixed in one cell shelf CT as shown in FIGS.

  The configuration of the driver transistor M1 formed in the region 91 is the same as the configuration of the driver transistor M1 shown in FIG. Similarly, the configuration of the driver transistor M2 formed in the region 93 is the same as the configuration of the driver transistor M2 shown in FIG. For this reason, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  Then, the power supply lines L1 and L2 are extended from the region 91 to the region 92, thereby supplying the power supply potential VDD to the logic circuit LOG. Further, the power supply wirings L3 and L4 are extended from the region 93 to the region 92, thereby supplying the power supply potential VSS to the logic circuit LOG. The logic circuit LOG is provided with two P-channel MOS transistors P1 and P2 and two N-channel MOS transistors N1 and N2. According to such a layout, the power supply potentials VDD and VSS can be directly supplied from the driver transistors M1 and M2 to the logic circuit LOG without going through the second metal wiring layer.

  FIG. 23 is a schematic plan view for explaining the layout of the semiconductor device 10a according to the first modification.

  Unlike the semiconductor device 10 shown in FIG. 1, the semiconductor device 10a according to the first modification is a DRAM having a one-channel configuration. A command address terminal 11, power supply terminals 13, 14 and a reset terminal 15 are arranged in the pad row CAP arranged in the X direction along the one edge EG1. In the pad row DQP arranged in the X direction along the other edge EG2, a data input / output terminal 12, power supply terminals 13 and 14, a calibration terminal ZQ, and the like are arranged.

  A command address control circuit 21 and the like are disposed in the vicinity of the pad column CAP, and a data input / output circuit 22 and the like are disposed in the vicinity of the pad column PB. Further, a memory cell array 30 and an access control circuit 31 are arranged between the command address control circuit 21 and the data input / output circuit 22.

  Thus, the present invention can also be applied to a DRAM having a single channel configuration.

  FIG. 24 is a schematic plan view for explaining the layout of the semiconductor device 10b according to the second modification.

  The semiconductor device 10b according to the second modification is a logic semiconductor device such as ASCI or MPU. Various external terminals are arranged in the pad row PARY along the edges EG1 and EG2. Between the edges EG1 and EG2, circuit blocks BLK each having a predetermined function are arranged. These circuit blocks BLK adopt a standard cell system and are constituted by a large number of cell shelves CT extending in the Y direction.

  As described above, the present invention can also be applied to a logic semiconductor device.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

2 Semiconductor substrate 10, 10a, 10b Semiconductor device 11, 11A, 11B Command address terminal 12, 12A, 12B Data input / output terminal 13, 13A, 13B, 14, 14A, 14B Power supply terminal 15, 15B Reset terminal 21, 21A, 21B Command address control circuit 22, 22A, 22B Data input / output circuit 23A Calibration circuit 24B Reset circuit 30, 30A, 30B Memory cell array 31, 31A, 31B Access control circuit 41, 42 Inverter circuits 51-53 Signal wiring 61 Semiconductor substrate 62 N Well region 63 source region 64 drain region 65 gate insulating films 71 to 73, 81 to 83, 91 to 93 region BLK circuit block CAP, DQP, PA, PB, PARY pad row CE contact conductor CHA, CHB channel C Cell shelf EG1, EG2 Edge G Gate electrodes L1-L8, SL, VL Power supply wiring LOG Logic circuit M1, M2 Driver transistor N1, N2, P1, P2 Transistor NTR N-channel region PTR P-channel region R1-R4 Resistance SCN Substrate contact region TH1, TH2 Through-hole conductor W Wiring WCN Well contact region ZQ Calibration terminal

Claims (20)

A cell shelf extending in a first direction and having a predetermined width in a second direction intersecting the first direction;
First, second, third and fourth power supply lines provided in the first wiring layer and extending in the first direction along the cell shelf;
Fifth, sixth, seventh and eighth power supply wirings provided in a second wiring layer different from the first wiring layer and extending in the second direction so as to cross the cell shelf;
A first through-hole conductor connecting the first power supply wiring and the fifth power supply wiring;
A second through-hole conductor connecting the second power supply wiring and the sixth power supply wiring;
A third through-hole conductor connecting the third power supply wiring and the seventh power supply wiring;
A fourth through-hole conductor connecting the fourth power supply wiring and the eighth power supply wiring;
A first driver transistor provided on the cell shelf and connecting the first power supply wiring and the second power supply wiring in response to a first control signal;
A second driver transistor provided on the cell shelf and connecting the third power supply wiring and the fourth power supply wiring in response to a second control signal;
The semiconductor device, wherein the first driver transistor and the second driver transistor are arranged in the first direction. The first and second through-hole conductors are provided at positions overlapping the first driver transistor in plan view,
2. The semiconductor device according to claim 1, wherein the third and fourth through-hole conductors are provided at a position overlapping the second driver transistor in plan view. A plurality of the first and second power supply wirings are provided on the first driver transistor,
A plurality of the third and fourth power supply lines are provided on the second driver transistor,
The first through-hole conductor is provided for each of the plurality of first power lines,
The semiconductor device according to claim 2, wherein the second through-hole conductor is provided for each of the plurality of second power supply wirings. The first power supply wiring is provided on one extension line of the third and fourth power supply wirings,
The semiconductor device according to claim 3, wherein the second power supply wiring is provided on the other extension line of the third and fourth power supply wirings.   3. The semiconductor device according to claim 2, wherein the first, second, third, and fourth power supply wirings are provided on the first and second driver transistors, respectively.   The said 1st, 2nd, 3rd, and 4th power supply wiring is extended in the said 1st direction in the center part in the said 2nd direction of the said cell shelf, The Claim 1 characterized by the above-mentioned. Semiconductor device.   7. The semiconductor device according to claim 1, wherein no other transistor is provided in the cell shelf in the second direction of the first and second driver transistors. 8. . In the first driver transistor, a plurality of source regions and a plurality of drain regions are alternately arranged in the first direction, the plurality of source regions are commonly connected to the first power supply wiring, The drain region is commonly connected to the second power supply wiring, and the first control signal is input to the gate electrode.
In the second driver transistor, a plurality of source regions and a plurality of drain regions are alternately arranged in the first direction, the plurality of source regions are commonly connected to the third power supply wiring, 8. The semiconductor according to claim 1, wherein a drain region is commonly connected to the fourth power supply wiring, and the second control signal is input to a gate electrode. 9. apparatus.   9. The semiconductor device according to claim 1, wherein the first wiring layer is positioned below the second wiring layer. 10. A first logic circuit provided on the cell shelf and connected to the first power supply wiring and the fourth power supply wiring;
10. The apparatus according to claim 1, further comprising a second logic circuit provided on the cell shelf and connected to the second power supply wiring and the third power supply wiring. The semiconductor device described.   The semiconductor device according to claim 10, wherein an output signal of the first logic circuit is input to the second logic circuit. The first logic circuit includes a first transistor connected to the first power supply line, and a second transistor connected to the fourth power supply line,
The second logic circuit includes a third transistor connected to the second power supply wiring, and a fourth transistor connected to the third power supply wiring,
The semiconductor device according to claim 10, wherein the first and third transistors and the second and fourth transistors are arranged in the second direction. The first driver transistor, the first transistor, and the third transistor are first conductivity type MOS transistors,
13. The semiconductor device according to claim 12, wherein the second driver transistor, the second transistor, and the fourth transistor are second conductivity type MOS transistors. First and second cell shelves each extending in a first direction and having a predetermined width in a second direction intersecting the first direction;
First, second, third and fourth power supply lines;
First, second and third signal wirings;
A first driver transistor provided in the first cell shelf and connecting the first power supply wiring and the second power supply wiring in response to a first control signal;
A second driver transistor provided in the first cell shelf and connecting the third power supply wiring and the fourth power supply wiring in response to a second control signal;
A first transistor provided in the second cell shelf and connecting the first power supply wiring and the second signal wiring based on a level of the first signal wiring;
A second transistor provided in the second cell shelf and connecting the fourth power supply wiring and the second signal wiring based on a level of the first signal wiring;
A third transistor provided in the second cell shelf and connecting the second power supply wiring and the third signal wiring based on a level of the second signal wiring;
A fourth transistor provided on the second cell shelf and connecting the third power supply wiring and the third signal wiring based on a level of the second signal wiring;
The first driver transistor and the second driver transistor are arranged in the first direction with respect to each other;
The semiconductor device, wherein the first and third transistors and the second and fourth transistors are arranged in the second direction.   15. The semiconductor device according to claim 14, wherein no other transistor is provided on the cell shelf in the second direction of the first and second driver transistors. The first driver transistor, the first transistor, and the third transistor are formed in a first conductivity type well or substrate,
16. The semiconductor device according to claim 14, wherein the second driver transistor, the second transistor, and the fourth transistor are formed in a second conductivity type well or substrate.   The first cell shelf includes the first conductivity type well or substrate in which the first driver transistor is formed and the second conductivity type well or substrate in which the second driver transistor is formed. The semiconductor device according to claim 16, further comprising a first isolation region to be isolated, wherein the first isolation region extends in the second direction.   The second cell shelf includes the first conductivity type well or substrate on which the first and third transistors are formed, and the second conductivity type well on which the second and fourth transistors are formed. The semiconductor device according to claim 17, further comprising: a second isolation region that separates the substrate, wherein the second isolation region extends in the first direction.   19. The width of the first cell shelf in the second direction is equal to the width of the second cell shelf in the second direction. 19. Semiconductor device. A fifth power supply wiring connected to the first power supply wiring;
A sixth power supply wiring connected to the second power supply wiring;
A seventh power supply line connected to the third power supply line;
And an eighth power supply line connected to the fourth power supply line,
The first to fourth power supply wires extend in the first direction,
The semiconductor device according to claim 14, wherein the fifth to eighth power supply wires extend in the first direction.

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