JP2015204534A - A/d conversion circuit and solid state image sensor - Google Patents

Abstract

An A / D conversion circuit and a solid-state imaging device that improve the resolution by acquiring phase information and suppress the decrease in A / D conversion accuracy are provided. A ramp signal generation unit that generates a ramp wave, a phase signal generation unit that outputs a plurality of phase clocks whose phases are changed, and a voltage of a signal to be converted and a voltage of the ramp wave are compared. A comparator that outputs a comparison result signal that sequentially changes from the first reference voltage to the second reference voltage through the first intermediate voltage and the second intermediate voltage; A signal generator comprising: a first logic circuit that switches a logic state of the first timing signal; and a second logic circuit that switches a logic of the second timing signal at a second intermediate voltage or higher; A latch unit that outputs phase information of the phase clock according to the timing at which the logic is switched, and an encoding unit that generates a digital value according to the magnitude of the voltage of the signal to be converted based on the phase information.[Selection] Figure 2

Description

  The present invention relates to an A / D conversion circuit and a solid-state imaging device.

  In recent years, CMOS (Complementary Metal Oxide Semiconductor) solid-state imaging devices have attracted attention and have been put to practical use as solid-state imaging devices. This CMOS solid-state imaging device can be manufactured using a general semiconductor manufacturing process, whereas a CCD (Charge Coupled Device) solid-state imaging device is manufactured by a dedicated manufacturing process. . For this reason, the CMOS solid-state imaging device can be made multifunctional by incorporating various functional circuits in the sensor, such as SOC (System On Chip).

  In recent years, as a solid-state imaging device mounted on a digital camera, a digital video camera, an endoscope, or the like, an analog-to-digital converter (hereinafter referred to as “hereinafter” “column”) is provided for each column of a pixel array unit arranged in a matrix. A solid-state imaging device incorporating an A / D conversion circuit ”, that is, a so-called column ADC type solid-state imaging device has been developed and commercialized. A single slope (SS) single A / D conversion method is known as one of the A / D conversion methods of an A / D conversion circuit built in such a solid-state imaging device.

  In this SS type A / D conversion method, a reference voltage called a ramp wave that changes in a stepwise manner is compared with a signal voltage to be subjected to A / D conversion, and comparison is started, that is, A / D conversion. A time interval (a pulse signal having a pulse width with a time axis size corresponding to the signal voltage) is generated that represents a period from when the reference is started until the reference voltage and the signal voltage become the same voltage. Then, by counting this time interval with a reference clock having a predetermined frequency, the count value corresponding to the magnitude of the signal voltage is converted to an A / D converted digital value, that is, the signal voltage is converted to A / D. Convert.

  Therefore, in the SS type A / D conversion method, the resolution when performing A / D conversion depends on the frequency of the reference clock for counting the time interval. Therefore, in order to increase the resolution of the SS type A / D conversion type A / D conversion circuit, it is necessary to increase the frequency of the reference clock, and the SS type A / D conversion type A / D conversion circuit. There is a problem that power consumption increases.

  Therefore, in recent years, SS + time conversion (TDC: Time to Digital Converter) type A / D that realizes improvement in resolution of A / D conversion by acquiring phase information in the reference clock of this SS type A / D conversion method. A D conversion method has been proposed (see Non-Patent Document 1). In this SS + TDC type A / D conversion method, by using the reference clock and a plurality of clocks in which the phase of the reference clock is changed, the phases of the respective clocks at the timing of the instant at which the time interval ends are measured. Improves the resolution of D conversion.

  If this SS + TDC type A / D conversion method is used, the resolution can be improved according to the number of phase information. For example, if there are two pieces of phase information, the resolution can be increased by 1 bit, if there are four pieces of phase information, the resolution can be increased by two bits,..., If there are 16 pieces of phase information, the resolution can be increased by four bits. . Thus, in the SS + TDC type A / D conversion method, the resolution, that is, the number of bits of the digital value to be output after A / D conversion can be increased by increasing the number of phase information.

  However, in the SS + TDC type A / D conversion method, as described above, the relationship between the increasing number of bits and the number of necessary phase information is not a linear relationship, and the necessary number of phase information for the increasing number of bits is not. The number increases exponentially. That is, even if the phase information is increased, the increased number of phase information does not contribute linearly to the improvement in resolution. For this reason, in the SS + TDC type A / D conversion method, in order to ensure the necessary resolution (number of bits), it is necessary to provide the reference clock with a large amount of phase information, and the phase of the reference clock is changed. More clocks (with superimposed phase information) are required. In the A / D conversion circuit using the SS + TDC type A / D conversion system, it is necessary to provide a lot of latch circuits in order to hold the phase information of each clock.

  In the column ADC type solid-state imaging device in which such an SS + TDC type A / D conversion type A / D conversion circuit is incorporated for each column, the above-described many latch circuits are provided for each column. In this column ADC type solid-state imaging device, each latch circuit that holds the phase information of each clock continues to operate during the time interval, that is, during A / D conversion. For this reason, there exists a problem that the power consumption of a column ADC type solid-state imaging device will increase. In particular, when the frequency of the reference clock is high and the number of clocks in which the phase of the reference clock is changed is large, that is, when there is a lot of phase information, the power consumption of the column ADC type solid-state imaging device further increases. End up.

  For this reason, Non-Patent Document 1 proposes a method for suppressing an increase in power consumption by intermittently operating the respective latch circuits provided in the A / D conversion circuit of the SS + TDC type A / D conversion method. More specifically, the operation of each latch circuit is stopped from the timing at which A / D conversion is started until the timing at which the reference voltage and the signal voltage become the same voltage, that is, during the time interval. The latch circuits are operated for a predetermined period from the end of the time interval until each latch circuit holds the phase information of the corresponding clock. As a result, during most of the period during which A / D conversion is performed, the operation of each latch circuit is stopped, and the power consumption of the A / D conversion circuit of the SS + TDC type A / D conversion system is reduced. be able to.

  Here, in Non-Patent Document 1, a predetermined period for operating the latch circuit is used to delay the signal of the time interval using a delay line in which a plurality of logic negation circuits (INV circuits) are connected in series. The timing of the instant when the time interval ends is determined by delaying the signal of the time interval with a delay line.

Hokkaido University Graduate School of Information Science, Daisuke Uchida, Hayato Someya, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano, “Low power operation by single slope ADC with multi-phase TDC”, ITE Technical Report Vol. 37, no. 29, Video Information Media Society, p. 97-100, July 5, 2013

  However, as described above, the column ADC type solid-state imaging device includes an SS + TDC type A / D conversion type A / D conversion circuit in each column. Therefore, for example, when the A / D conversion is performed for each column of pixel signals output from pixels in a certain row, the SS + TDC type A / D conversion system A / D conversion circuit of each column is supplied with a corresponding pixel. When signal voltages having similar levels are input as pixel signals, the time interval ends at the same time. In other words, the timing of the moment when the time interval ends comes all at once. In this case, it is conceivable that the delay lines provided in the A / D conversion circuits of the respective SS + TDC type A / D conversion systems start to operate at the same time, and the power supply voltage fluctuates. Then, as the power supply voltage fluctuates, the delay time shifts for each delay line, that is, each latch circuit provided in each SS + TDC type A / D conversion type A / D conversion circuit corresponds. The timing for retaining the phase information of the clock differs for each A / D conversion circuit of the SS + TDC type A / D conversion method.

  Here, in the column ADC type solid-state imaging device, when a power supply circuit is arranged at one end of the pixel array unit, the power supply voltage supplied to each column (column) circuit is the pixel array unit. The closer to the center column from the end row of the line, that is, the more the circuit arranged in the row farther from the power source, the more voltage drop occurs due to the current consumed by the circuit in the previous row and the wiring resistance to it, It is also conceivable that the supplied power supply voltage is lowered. For the same reason, the ground voltage may increase as it approaches the center column from the column at the end of the pixel array section, that is, as the circuit is arranged in a column far from the ground. . For example, even if the power supply voltage VDD = 1.5 [V] and the ground voltage GND = 0 [V] are supplied to the circuit corresponding to the end column close to the power supply circuit of the pixel array portion, the pixel It is also conceivable that the circuit corresponding to the center column of the array section has a power supply voltage VDD = 1.2 [V] and a ground voltage GND = 0.3 [V]. This decrease in power supply voltage and increase in ground voltage occur at the same time interval, that is, the A / D conversion of the SS + TDC type A / D conversion method in which the timing at which the phase information is held comes at the same timing. The more circuits there are, the higher the possibility that they will occur. Even if the resolution of A / D conversion is improved, the A / D conversion accuracy will decrease as a result.

  For example, consider a case where each pixel outputs a signal voltage having a substantially constant level as a pixel signal, such as when a uniform image is captured by a column ADC type solid-state imaging device. In this case, since the same level of signal voltage is input to all SS + TDC type A / D conversion type A / D conversion circuits, delays provided to all SS + TDC type A / D conversion type A / D conversion circuits. Each of the line and the latch circuit starts to operate almost simultaneously. As a result, bounce (transient voltage ringing centering on the power supply voltage and the ground voltage) occurs between the power supply voltage and the ground voltage in the vicinity of the central column of the pixel array section. Then, since the delay line has a configuration in which a plurality of INV circuits are connected in series, the delay time of each INV circuit changes in accordance with the change in the bounce (bounce size) of the power supply voltage and the ground voltage. Cumulatively, the overall delay time will be greatly shifted. As a result, each latch circuit cannot hold the phase information of the corresponding clock at an accurate (same) timing, and the A / D conversion accuracy is lowered. In the column ADC type solid-state imaging device, the A / D conversion accuracy differs for each column of the pixel array unit, thereby degrading the overall image quality.

  The present invention has been made on the basis of the above problem recognition, and in an A / D conversion circuit that improves resolution by acquiring phase information, an A / D that can suppress a decrease in A / D conversion accuracy. An object of the present invention is to provide a conversion circuit and a solid-state imaging device including the A / D conversion circuit.

  In order to solve the above problems, an A / D conversion circuit according to the present invention includes a ramp signal generation unit that generates a ramp wave that is an analog reference signal whose voltage monotonously decreases or monotonously increases at a constant rate with respect to time. Generating a reference clock and a plurality of clocks in which the phases of the reference clock are changed, outputting the generated clocks as respective phase clocks, and the voltage of the input signal to be converted When the result of comparing the voltage of the ramp wave and the voltage of the ramp wave satisfies a predetermined condition, the voltage is changed from the first reference voltage to the first intermediate voltage and the second voltage at a constant rate with respect to time. A comparison unit that outputs an analog comparison result signal that sequentially changes to the second reference voltage, and an output voltage when the voltage of the comparison result signal becomes equal to or higher than the first intermediate voltage. The first logic circuit that switches the logic state of the first timing signal to be switched, and the logic state of the second timing signal that is output when the voltage of the comparison result signal becomes equal to or higher than the second intermediate voltage A signal generation unit including a second logic circuit; and a first timing at which a logic state of the first timing signal switches corresponding to each of the phase clocks, or a logic state of the second timing signal A plurality of latch circuits for latching the respective logic states of the phase clock in accordance with at least one of the second timings at which the clock signal is switched, and the logic states of the phase clocks latched by the respective latch circuits are A latch unit that outputs the phase information, and a digital signal corresponding to the voltage level of the signal to be converted based on the phase information. Comprising an encoding unit for generating Le values, and characterized in that.

  Further, each of the plurality of latch circuits in the A / D conversion circuit of the present invention latches the logic state of the corresponding phase clock from the first timing to the second timing. .

  In the A / D conversion circuit of the present invention, the latch circuit corresponding to the reference clock included in the phase clock may be configured such that the comparison unit compares the voltage of the signal to be converted and the voltage of the ramp wave. The logic state of the reference clock is latched from the start to the second timing, and each of the latch circuits corresponding to other than the reference clock included in the phase clock starts from the first timing to the second timing. The logic state of the corresponding phase clock is latched until the timing of 2, and the A / D conversion circuit counts the number of clocks of the reference clock based on the phase information latched by the latch circuit corresponding to the reference clock. And a counter having a counter that outputs the counted value, and the encoding unit includes: Generating a digital value corresponding to the magnitude of the voltage of the signal to be converted, based on each of the phase information latched by the latch circuit corresponding to other than a quasi-clock and the count value; To do.

  In the A / D conversion circuit of the present invention, the first logic circuit may be configured such that a first threshold voltage for switching a logic state of the first timing signal is predetermined as the first intermediate voltage. A second transistor circuit, wherein a second threshold voltage for switching a logic state of the second timing signal is predetermined to the second intermediate voltage. The power supply voltage of the first transistor circuit and the power supply voltage of the second transistor circuit are different voltages.

  In the A / D conversion circuit of the present invention, the first logic circuit may be configured such that a first threshold voltage for switching a logic state of the first timing signal is predetermined as the first intermediate voltage. A second transistor circuit, wherein a second threshold voltage for switching a logic state of the second timing signal is predetermined to the second intermediate voltage. The L / W ratio of the first transistor circuit and the L / W ratio of the second transistor circuit are different L / W ratios.

  In the A / D conversion circuit of the present invention, the first logic circuit may be configured such that a first threshold voltage for switching a logic state of the first timing signal is predetermined as the first intermediate voltage. A second transistor circuit, wherein a second threshold voltage for switching a logic state of the second timing signal is predetermined to the second intermediate voltage. The power supply voltage of the first transistor circuit and the power supply voltage of the second transistor circuit are different voltages, and the L / W ratio of the first transistor circuit and the second transistor circuit The L / W ratio of the transistor circuit is a different L / W ratio.

  The solid-state imaging device of the present invention includes a pixel array unit in which a plurality of pixels that output pixel signals corresponding to the amount of incident light are arranged in a two-dimensional matrix, and the pixels arranged in the pixel array unit. A plurality of A / D conversion circuits according to the present invention, which are arranged for each column or for each of a plurality of columns and perform analog-to-digital conversion of the pixel signals in the corresponding columns as signals to be converted. Each of the ramp signal generation unit and the phase signal generation unit of the circuit is arranged in common for all the A / D conversion circuits.

  According to the present invention, in the A / D conversion circuit that improves the resolution by acquiring the phase information, it is possible to suppress the decrease in the A / D conversion accuracy.

It is the block diagram which showed schematic structure of the solid-state imaging device by embodiment of this invention. 1 is a block diagram showing a schematic configuration of an A / D conversion circuit of a first embodiment provided in a solid-state imaging device of the present embodiment. 3 is a timing chart showing the operation timing of the A / D conversion circuit of the first embodiment provided in the solid-state imaging device of the present embodiment. It is the block diagram which showed schematic structure of the A / D conversion circuit of 2nd Embodiment with which the solid-state imaging device of this embodiment was equipped. It is a timing chart which showed the operation timing of the A / D conversion circuit of a 2nd embodiment with which the solid imaging device of this embodiment was equipped. It is a circuit diagram showing the 1st composition of the signal generation part with which the A / D conversion circuit of the 1st embodiment was equipped. It is a timing chart which showed the operation timing of the signal generation part of the 1st composition. It is a circuit diagram showing the 2nd composition of the signal generation part with which the A / D conversion circuit of the 1st embodiment was equipped. It is the layout figure which showed an example of the layout in the signal generation part of the 2nd structure.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of the solid-state imaging device according to the present embodiment. A solid-state imaging device 1 illustrated in FIG. 1 includes a pixel array unit 10, a column A / D conversion circuit 20, a ramp signal generation unit 41, a phase signal generation unit 43, a control signal generation unit 50, and a vertical scanning circuit. Part 200 and a horizontal scanning circuit part 300.

  The solid-state imaging device 1 uses the respective pixel signals output from the respective pixels 101 in the pixel array unit 10 (hereinafter referred to as “pixel signal Signal”) in the SS + TDC provided in the column A / D conversion circuit 20. A / D conversion (analog / digital conversion) is performed by an A / D conversion circuit (analog / digital converter) 30 (hereinafter referred to as “A / D conversion circuit 30”) using a type A / D conversion method, and a data output line 800 Are sequentially output as a digital signal DOUT.

  The vertical scanning circuit unit 200 outputs a pixel drive signal for driving the pixels 101 in the pixel array unit 10 in units of rows of the pixel array unit 10 in accordance with the control signal input from the control signal generation unit 50.

  The pixel array unit 10 is a pixel array unit in which a plurality of pixels 101 are arranged two-dimensionally in the row direction and the column direction. Each of the pixels 101 includes a photoelectric conversion element, and the photoelectric conversion element included in each pixel 101 generates a pixel signal Signal corresponding to the amount of light incident within a certain accumulation time. Then, the pixel array unit 10 outputs the generated pixel signal Signal to the column A / D conversion circuit 20 for each row of the pixel array unit 10 in accordance with the pixel drive signal input from the vertical scanning circuit unit 200. .

  The ramp signal generation unit 41 is an analog reference signal whose voltage monotonously decreases at a constant rate with respect to time from the timing of starting A / D conversion in accordance with the control signal input from the control signal generation unit 50. A certain ramp wave Ramp is generated. Then, the ramp signal generation unit 41 outputs the generated ramp wave Ramp to the column A / D conversion circuit 20.

  The phase signal generation unit 43 generates a reference clock according to the control signal input from the control signal generation unit 50. The phase signal generator 43 generates a plurality of clocks in which the phase of the reference clock is changed. Then, the phase signal generation unit 43 outputs the generated clocks to the column A / D conversion circuit 20 from the timing at which A / D conversion is started. In the solid-state imaging device 1 shown in FIG. 1, eight types of clocks (hereinafter referred to as “phase clocks”) CK-0 to CK-7 in which the phases of the reference clock and the reference clock are changed are generated, and the column A / D is generated. A phase signal generation unit 43 configured to output to the conversion circuit 20 is shown.

  The control signal generation unit 50 controls driving of the vertical scanning circuit unit 200, the ramp signal generation unit 41, the phase signal generation unit 43, the column A / D conversion circuit 20, and the horizontal scanning circuit unit 300. Output a control signal.

  The column A / D conversion circuit 20 includes a plurality of A / D conversion circuits 30 having the same configuration as the number of columns of the pixels 101 arranged in the pixel array unit 10. In the solid-state imaging device 1 of the present embodiment, one ramp signal generation unit 41 and one phase signal generation unit 43 are shared by all the A / D conversion circuits 30 included in the column A / D conversion circuit 20. It is prepared one by one.

  Each A / D conversion circuit 30 corresponding to each column of the pixel array unit 10 receives the pixel signal Signal (analog signal) input from the pixel array unit 10 in accordance with the control signal input from the control signal generation unit 50. A / D conversion (analog / digital conversion). Each of the A / D conversion circuits 30 outputs a digital value corresponding to the magnitude of the A / D converted pixel signal Signal to the data output line 800 in accordance with the column selection signal input from the horizontal scanning circuit unit 300. Output.

  Note that the solid-state imaging device 1 according to the present embodiment corresponds to each of the columns of the pixels 101 arranged in the pixel array unit 10 between the pixel array unit 10 and the column A / D conversion circuit 20, for example, A configuration including a plurality of signal processing circuits that perform analog processing such as CDS (Correlated Double Sampling) processing may be employed. In this case, each of the signal processing circuits performs analog processing on the pixel signal Signal (analog signal) input from the pixel array unit 10, and then converts the processed analog signal to the column A / D conversion circuit 20. Output to. Each of the A / D conversion circuits 30 in the column A / D conversion circuit 20 performs A / D conversion on the analog signal processed by the corresponding signal processing circuit.

  In accordance with the control signal input from the control signal generation unit 50, the horizontal scanning circuit unit 300 converts the digital value that is A / D converted by each A / D conversion circuit 30 provided in the column A / D conversion circuit 20. The output to the data output line 800 is controlled. The horizontal scanning circuit unit 300 includes a column selection signal for selecting a digital value to be output to the data output line 800 for each column of the pixel array unit 10 in each column A / D conversion circuit 20. The data is sequentially output to the D conversion circuit 30.

  The digital value A / D converted by the A / D conversion circuit 30 output to the data output line 800 is sequentially output to the outside of the solid-state imaging device 1 as a digital signal DOUT output by the solid-state imaging device 1.

<First Embodiment>
Next, the A / D conversion circuit 30 of the first embodiment in the column A / D conversion circuit 20 provided in the solid-state imaging device 1 of the present embodiment will be described. FIG. 2 is a block diagram showing a schematic configuration of the A / D conversion circuit 30 of the first embodiment provided in the solid-state imaging device 1 of the present embodiment. The A / D conversion circuit 30 illustrated in FIG. 2 includes a comparison unit 301, a signal generation unit 302, a latch unit 303, and an encoding unit 304. 2 shows a ramp signal generation unit 41 that outputs a ramp wave Ramp to the A / D conversion circuit 30, and phase signal generation that outputs eight types of phase clocks CK-0 to CK-7 whose phases have been changed. This is also shown together with part 43. The A / D conversion circuit 30 according to the first embodiment includes a component that counts the time interval with a reference clock (a clock having a phase change of 0 ° among a plurality of phase clocks CK), that is, As with the conventional A / D conversion circuit of the SS type A / D conversion system, a count unit which is a component for outputting a digital value in a state where the resolution is not improved is also provided. Is omitted.

  The A / D conversion circuit 30 performs A / D conversion (analog-digital conversion) on the pixel signal Signal (analog signal) input from the pixel array unit 10 based on the ramp wave Ramp and the phase clocks CK-0 to CK-7. And a digital value corresponding to the magnitude of the pixel signal Signal is output.

  The comparison unit 301 compares the voltage of the pixel signal Signal to be subjected to A / D conversion input from the pixels 101 in the corresponding column in the pixel array unit 10 and the ramp wave Ramp input from the ramp signal generation unit 41. Compare with voltage. That is, the time interval is measured. The comparison unit 301 includes a comparator COMP that compares the voltages of two input signals.

  In the comparator COMP, the pixel signal Signal output from the pixel 101 is input to the positive terminal as the input signal Vin1, and the ramp wave Ramp is input to the negative terminal as the input signal Vin2. Then, the comparator COMP outputs the first reference voltage at a constant rate with respect to time when the magnitude relationship between the voltage of the input signal Vin2 and the voltage of the input signal Vin1 coincides, that is, from the timing when the time interval ends. The comparison result signal CO-0 that is an analog signal that increases from 1 to the second reference voltage is output to the signal generator 302.

  The signal generation unit 302 receives each signal indicating that the voltage of the comparison result signal CO-0 input from the comparison unit 301 has become a predetermined first intermediate voltage and a predetermined second intermediate voltage. Is output. The signal generation unit 302 includes two buffer circuits (a first buffer BUFF1 and a second buffer BUFF2) that switch the logic of an output signal when the input signal becomes equal to or higher than a predetermined voltage.

  When the voltage of the input comparison result signal CO-0 becomes equal to or higher than the first intermediate voltage, the first buffer BUFF1 switches the logic of the first timing signal CO-1 that is a signal indicating this. . In addition, the second buffer BUFF2 receives the logic of the second timing signal CO-2 that is a signal representing this when the voltage of the input comparison result signal CO-0 becomes equal to or higher than the second intermediate voltage. Switch. The first buffer BUFF1 outputs the first timing signal CO-1 and the second buffer BUFF2 outputs the second timing signal CO-2 to the latch unit 303, respectively. Note that the first intermediate voltage is higher than the first reference voltage and lower than the second reference voltage, and the second intermediate voltage is higher than the first intermediate voltage and higher than the second reference voltage. Is also a low voltage. Therefore, when the comparison result signal CO-0 is input from the comparison unit 301, first, when the voltage of the comparison result signal CO-0 becomes equal to or higher than the first intermediate voltage, the first buffer BUFF1 outputs. The second timing signal CO− output from the second buffer BUFF2 when the logic of the first timing signal CO-1 is switched and then the voltage of the comparison result signal CO-0 becomes equal to or higher than the second intermediate voltage. The logic of 2 switches.

  The configuration of the signal generation unit 302 corresponds to a configuration for delaying a signal of a time interval configured by a delay line in a conventional SS + TDC A / D conversion type A / D conversion circuit.

  The latch unit 303 receives a plurality of phase clocks CK-0 to CK-7, which are changed in phase, input from the phase signal generation unit 43, and the first timing signal CO-1 input from the signal generation unit 302 and the first timing signal CO-1 2 is held (latched) at a timing based on the timing signal CO-2. That is, the latch unit 303 has the phase clocks CK-0 to CK-7 at the instants when the time interval ends based on the first timing signal CO-1 and the second timing signal CO-2. Holds phase information representing the phase of the. Then, the latch unit 303 outputs each phase information of the phase clocks CK-0 to CK-7 to the encoding unit 304. The latch unit 303 includes a plurality of latch circuits D-0 to D-7 and an AND circuit (AND circuit) AND-L.

  The AND circuit AND-L latches the phase information of each of the phase clocks CK-0 to CK-7 based on the first timing signal CO-1 and the second timing signal CO-2, that is, A control signal HOLD-L representing a predetermined period for operating the latch circuits D-0 to D-7 is generated. More specifically, the AND circuit AND-L includes the latch circuit D-0 from the timing when the logic of the first timing signal CO-1 is switched to the timing when the logic of the second timing signal CO-2 is switched. A control signal HOLD-L for operating .about.D-7 is generated. The AND circuit AND-L outputs the generated control signal HOLD-L to each of the latch circuits D-0 to D-7.

  Each of the latch circuits D-0 to D-7 corresponds to each of the phase clocks CK-0 to CK-7, and is input according to the control signal HOLD-L input from the AND circuit AND-L. The logic state of the phase clock CK is latched as phase information. More specifically, each of the latch circuits D-0 to D-7 operates only during a period indicating that the control signal HOLD-L is an operating period, and the logic state of the phase clock CK during the operation Are latched as phase information. Note that each of the latch circuits D-0 to D-7 stops operating during a period indicating that the control signal HOLD-L is not in an operating period.

  The encoding unit 304 encodes the phase information input from the latch unit 303 and generates a digital value represented by the phase information. In other words, the encoding unit 304 generates a digital value corresponding to the magnitude of the pixel signal Signal based on the phase information input from the latch unit 303. The encoding unit 304 includes an encoder 3041. Note that the encoding unit 304 indicates a period from when the A / D conversion is started to the time when the magnitude relationship between the voltage of the input signal Vin2 and the voltage of the input signal Vin1 matches, that is, the time interval (not shown). The count value counted by the counting unit using the reference clock output from the phase signal generation unit 43 (the clock having a phase change of 0 ° among the plurality of phase clocks CK) is also input. At this time, regardless of the first timing signal CO-1 and the second timing signal CO-2, the reference clock generated by the phase signal generation unit 43 is always input to a count unit (not shown).

  The encoder 3041 generates a digital value obtained by encoding a count value input from a count unit (not shown) and a digital value encoded by phase information input from the latch unit 303. The encoder 3041 outputs the generated digital value to the data output line 800 as a digital value A / D converted by the A / D conversion circuit 30 in accordance with the column selection signal input from the horizontal scanning circuit unit 300. . At this time, the encoder 3041 sets the digital value obtained by encoding the count value input from the count unit (not shown) as the higher digital value of the digital value A / D converted by the A / D conversion circuit 30, and the latch unit 303. The digital value obtained by encoding the phase information input from is output as a lower digital value of the digital value A / D converted by the A / D conversion circuit 30.

  Note that a digital value obtained by encoding a count value input from a count unit (not shown) corresponds to a digital value output from an A / D conversion circuit of a conventional SS type A / D conversion method, and is input from a latch unit 303. The digital value obtained by encoding the phase information corresponds to a digital value whose resolution is improved in the conventional SS + TDC type A / D conversion type A / D conversion circuit.

  With such a configuration, the A / D conversion circuit 30 has a plurality of clocks (phase clocks) in which the phases of the reference clock and the reference clock are changed, similarly to the conventional SS + TDC type A / D conversion type A / D conversion circuit. CK) can be used to output a digital value with improved resolution. However, in the A / D conversion circuit 30, the signal generation unit 302 is configured to delay the timing at which the time interval configured by the delay line in the conventional SS + TDC type A / D conversion circuit A / D conversion circuit ends. This is realized by two buffer circuits (first buffer BUFF1 and second buffer BUFF2). For this reason, in the conventional delay line, each of a plurality of logic negation circuits (INV circuits) connected in series in the delay line performs the operation of switching the logic at the same time. In the realized configuration of the signal generation unit 302, the number of operating elements is small (one buffer circuit is composed of two INV circuits), and the logic of each of the two buffer circuits is not switched simultaneously. Thereby, in the A / D conversion circuit 30, the power supply voltage does not fluctuate due to the configuration in which the timing at which the time interval ends is delayed. Therefore, in the A / D conversion circuit 30, the timing at which the latch circuits D-0 to D-7 in the latch unit 303 hold the logical state of the corresponding phase clock CK as phase information does not differ.

  Next, the operation of the A / D conversion circuit 30 of the first embodiment in the column A / D conversion circuit 20 provided in the solid-state imaging device 1 of the present embodiment will be described. FIG. 3 is a timing chart showing the operation timing of the A / D conversion circuit 30 of the first embodiment provided in the solid-state imaging device 1 of the present embodiment. Note that FIG. 3 shows a timing chart in which the time axis of the timing at the moment when the time interval ends is lengthened for ease of explanation.

  When the A / D conversion circuit 30 receives the pixel signal Signal to be A / D converted from the pixel 101 and starts A / D conversion according to the control signal input from the control signal generation unit 50, the time t1 Starts A / D conversion. Then, the ramp signal generation unit 41 generates a ramp wave Ramp whose voltage monotonously decreases at a constant rate with respect to time from the start voltage to the end voltage of the ramp wave Ramp from the time t1, and the A / D conversion circuit 30 Output to. Accordingly, the pixel signal Signal is input as the input signal Vin1 and the ramp wave Ramp is input as the input signal Vin2 to the comparator COMP in the comparison unit 301. Then, the comparator COMP starts measuring the time interval.

  Further, the phase signal generation unit 43 generates phase clocks CK-0 to CK-7 in which the phase of the reference clock and the reference clock is changed from time t1 and outputs the phase clocks CK-0 to CK-7 to the A / D conversion circuit 30. Accordingly, the corresponding phase clocks CK-0 to CK-7 are input to the latch circuits D-0 to D-7 in the latch unit 303, respectively.

  At this time, each of the first timing signal CO-1 output from the first buffer BUFF1 in the signal generator 302 and the second timing signal CO-2 output from the second buffer BUFF2 is “Low”. Is a level. Therefore, the control signal HOLD-L output from the AND circuit AND-L in the latch unit 303 is at the “Low” level. Thereby, each of the latch circuits D-0 to D-7 is in a state where the corresponding phase clocks CK-0 to CK-7 are input, but the operation of latching the phase information is stopped.

  Thereafter, the comparator COMP receives the comparison result signal CO-0 from the time t2 when the magnitude relationship between the voltage of the input signal Vin2 and the voltage of the input signal Vin1 coincides, that is, from the timing when the time interval ends. Start logic inversion. More specifically, the comparator COMP starts to output the comparison result signal CO-0, which increases at a constant rate with respect to time from the first reference voltage to the second reference voltage, to the signal generation unit 302. To do.

  Thereafter, the first buffer BUFF1 in the signal generation unit 302 receives the first timing signal CO-1 at time t3 when the voltage of the comparison result signal CO-0 becomes equal to or higher than a predetermined first intermediate voltage. Switch the logic of. More specifically, the first buffer BUFF1 switches the first timing signal CO-1 from the “Low” level to the “High” level. For this reason, the control signal HOLD-L output from the AND circuit AND-L is also at the “High” level. As a result, each of the latch circuits D-0 to D-7 starts an operation of latching the phase information of the corresponding phase clocks CK-0 to CK-7 input, and encodes each latched phase information. Sequentially output to 304.

  Thereafter, the second buffer BUFF2 in the signal generation unit 302 receives the second timing signal CO-2 at the time t4 when the voltage of the comparison result signal CO-0 becomes equal to or higher than a predetermined second intermediate voltage. Switch the logic of. More specifically, the second buffer BUFF2 switches the second timing signal CO-2 from the “Low” level to the “High” level. For this reason, the control signal HOLD-L output from the AND circuit AND-L becomes the “Low” level again. Thus, each of the latch circuits D-0 to D-7 completes the operation of latching the phase information of the corresponding phase clocks CK-0 to CK-7 that are input, and holds the phase information at this time. Here, the phase information held by each of the latch circuits D-0 to D-7 is output to the encoding unit 304.

  The encoder 3041 in the encoding unit 304 generates a digital value obtained by encoding the input phase information, and sets the digital value obtained by encoding the count value input from the count unit (not shown) as a higher-order digital value. A digital value obtained by combining the digital value generated in step S4 as the lower-order digital value is output as a digital value obtained by A / D conversion by the A / D conversion circuit 30.

  By such an operation, the A / D conversion circuit 30 is similar to the conventional SS + TDC type A / D conversion type A / D conversion circuit, and a plurality of clocks (phase clocks) in which the phases of the reference clock and the reference clock are changed. CK) is used to output a digital value with improved resolution. At this time, in the A / D conversion circuit 30, each of the first buffer BUFF1 and the second buffer BUFF2 receives the first timing signal CO-1 and the second timing signal CO according to the comparison result signal CO-0. The timing for switching each logic of -2 is delayed. That is, as shown in FIG. 3, each of the first buffer BUFF1 and the second buffer BUFF2 extends the time interval period to the first time interval period and the second time interval period, respectively. To do. Then, during the first time interval, that is, during the latch circuit stop period from time t1 to time t3 shown in FIG. 3, the “Low” level indicating that the control signal HOLD-L is not in operation. By doing so, each of the latch circuits D-0 to D-7 stops the operation of latching the phase information. Thereafter, during the period from the end of the first time interval to the end of the second time interval, that is, during the latch circuit operation period from time t3 to time t4 shown in FIG. 3, the control signal HOLD− The operation of latching the phase information by each of the latch circuits D-0 to D-7 is performed by setting L to "High" level indicating that the latch circuits D-0 to D-7 are operating. Make it. Thereby, also in the A / D conversion circuit 30, the latch circuits D-0 to D-7 are intermittently operated similarly to the conventional SS + TDC type A / D conversion type A / D conversion circuit. Power consumption during conversion can be suppressed. Note that the latch circuit operation period represents the timing at the moment when the time interval ends.

  According to the first embodiment, a ramp signal generation unit (ramp signal generation) that generates a ramp wave (ramp wave Ramp) that is an analog reference signal whose voltage monotonously decreases or monotonically increases at a constant rate with respect to time. 41), a reference clock and a plurality of clocks in which the phases of the reference clock are changed, and the generated clocks are output as respective phase clocks (phase clocks CK-0 to CK-7). The result of comparing the phase signal generation unit (phase signal generation unit 43), the voltage of the input signal to be converted (pixel signal Signal, input signal Vin1) and the voltage of the ramp wave Ramp (input signal Vin2), Since the predetermined condition (the magnitude relationship is coincident) is satisfied, the voltage is changed from the first reference voltage to the first intermediate voltage at a constant rate with respect to time. And a comparison unit (comparator COMP in the comparison unit 301) that outputs an analog comparison result signal (comparison result signal CO-0) that sequentially changes to the second reference voltage through the second intermediate voltage, and the comparison result When the voltage of the signal CO-0 becomes equal to or higher than the first intermediate voltage, a first logic circuit (first logic circuit) that switches the logic state of the first timing signal (first timing signal CO-1) to be output. A buffer BUFF1) and a second timing signal for switching the logic state of the second timing signal (second timing signal CO-2) to be output when the voltage of the comparison result signal CO-0 becomes equal to or higher than the second intermediate voltage. Corresponding to each of the phase clocks CK-0 to CK-7 and the logic of the first timing signal CO-1 and the signal generation unit (signal generation unit 302) including the logic circuit (second buffer BUFF2). Condition The logical states of the phase clocks CK-0 to CK-7 in accordance with at least one timing of the first timing when the clock signal is switched or the second timing when the logic state of the second timing signal CO-2 is switched And a plurality of latch circuits (latch circuits D-0 to D-7), and the logic states of the phase clocks CK-0 to CK-7 latched by the latch circuits D-0 to D-7, A latch unit (latch unit 303) that outputs as phase information, and an encode unit (encode) that generates a digital value corresponding to the voltage level of the signal to be converted (pixel signal Signal, input signal Vin1) based on the phase information. Unit 304), an A / D conversion circuit (A / D conversion circuit 30) is configured.

  Further, according to the first embodiment, each of the plurality of latch circuits D-0 to D-7 has the corresponding phase clocks CK-0 to CK-7 from the first timing to the second timing. An A / D conversion circuit 30 that latches the logic state is configured.

  As described above, according to the first embodiment, an increase in power consumption during A / D conversion can be suppressed similarly to the conventional SS + TDC type A / D conversion type A / D conversion circuit. . Similarly to the conventional SS + TDC A / D conversion type A / D conversion circuit, a digital value with improved resolution using a reference clock and a plurality of clocks (phase clocks) in which the phase of the reference clock is changed. Can be output. In addition, in the first embodiment, it is possible to suppress a variation in timing for latching the phase information of the phase clock in order to improve the resolution. In the first embodiment, in order to improve the resolution, the conventional SS + TDC type A / D conversion type A / D conversion circuit delays the timing at which the time interval constituted by the delay line ends. This is because the configuration is realized by the signal generation unit 302 configured by two buffer circuits (a first buffer BUFF1 and a second buffer BUFF2). That is, in the first embodiment, unlike the conventional configuration in which the function of delaying the timing at which the time interval ends is realized by a plurality of INV circuits connected in series in the delay line, generally 2 This is because the configuration is realized by using two buffer circuits each composed of one INV circuit.

  More specifically, conventionally, as described above, when a bounce occurs between the power supply voltage and the ground voltage due to, for example, taking a uniform image with a column ADC type solid-state imaging device, this power supply voltage and Due to the bounce of the ground voltage, changes in the delay time of the respective INV circuits constituting the delay line are accumulated, and the time for delaying the timing at which the time interval ends is greatly shifted. In other words, the accumulation of changes in the delay time corresponding to the number of INV circuits constituting the delay line has greatly shifted the time for delaying the timing at which the time interval ends.

  On the other hand, in the first embodiment, one buffer circuit is composed of two INV circuits. For this reason, even if a bounce occurs between the power supply voltage and the ground voltage, the cumulative amount of change in the delay time of the INV circuit is smaller than that of the conventional delay line, that is, two INV circuits. Only the change in the delay time is accumulated, and the timing at which the respective latch circuits in the latch unit hold the phase information of the corresponding phase clock is not greatly shifted. In addition, in the first embodiment, unlike the conventional delay line, the plurality of INV circuits do not perform the operation of switching the logic almost simultaneously, but only the two INV circuits perform the operation of switching the logic almost simultaneously. There are fewer factors that cause bounce between the power supply voltage and the ground voltage than in the conventional delay line configuration. That is, in the first embodiment, the signal generation unit 302 does not cause a bounce between the power supply voltage and the ground voltage.

  Thereby, in the first embodiment, each latch circuit can hold the phase information of the corresponding phase clock at an accurate (same) timing, and the A / D of the conventional SS + TDC type A / D conversion method can be used. A decrease in A / D conversion accuracy can be suppressed as compared with the D conversion circuit. In the column ADC type solid-state imaging device provided with the A / D conversion circuit of the first embodiment for each column of the pixel array unit, A / D conversion is performed for each column of the pixel array unit. There is no difference in accuracy, that is, the A / D conversion accuracy for each column of the pixel array section can be made uniform, and the overall image quality can be improved.

<Second Embodiment>
Next, the A / D conversion circuit of the second embodiment in the column A / D conversion circuit 20 provided in the solid-state imaging device 1 of the present embodiment will be described. In the A / D conversion circuit 30 of the first embodiment shown in FIG. 2, a configuration is shown in which a count unit (not shown) for counting the time interval period and the latch unit 303 operate independently. The A / D conversion circuit of the second embodiment is an A / D conversion circuit having a configuration in which a count unit and a latch unit operate in association with each other. In the following description, the A / D conversion circuit of the second embodiment is referred to as “A / D conversion circuit 31”. FIG. 4 is a block diagram showing a schematic configuration of the A / D conversion circuit 31 of the second embodiment provided in the solid-state imaging device 1 of the present embodiment. The A / D conversion circuit 31 shown in FIG. 4 includes a comparison unit 301, a signal generation unit 302, a latch unit 313, a count unit 315, and an encoding unit 314. 4, the ramp signal generation unit 41 that outputs the ramp wave Ramp to the A / D conversion circuit 31 and the phase signal generation that outputs eight types of phase clocks CK-0 to CK-7 whose phases are changed. This is also shown together with part 43. In the A / D conversion circuit 31 of the second embodiment, the phase clock CK-7 is a reference clock (a clock whose phase change is 0 ° among the plurality of phase clocks CK).

  The components of the A / D conversion circuit 31 of the second embodiment include the same components as the components of the A / D conversion circuit 30 of the first embodiment. Therefore, in the constituent elements of the A / D conversion circuit 31 of the second embodiment, the same reference numerals are given to the same constituent elements as the constituent elements of the A / D conversion circuit 30 of the first embodiment, A detailed description of each component will be omitted.

  Instead of the A / D conversion circuit 30 of the first embodiment, the A / D conversion circuit 31 is provided in the pixel array unit 10 in the column A / D conversion circuit 20 provided in the solid-state imaging device 1 of the present embodiment. A plurality of pixels 101 are provided as many as the number of columns of the pixels 101 arranged in the. The A / D conversion circuit 31 is input from the pixel array unit 10 based on the ramp wave Ramp and the phase clocks CK-0 to CK-7, similarly to the A / D conversion circuit 30 of the first embodiment. The pixel signal Signal (analog signal) is A / D converted (analog / digital conversion), and a digital value corresponding to the magnitude of the pixel signal Signal is output.

  The first buffer BUFF1 provided in the signal generation unit 302 outputs the first timing signal CO-1 and the second buffer BUFF2 outputs the second timing signal CO-2 to the latch unit 313, respectively.

  Similarly to the latch unit 303 provided in the A / D conversion circuit 30 of the first embodiment, the latch unit 313 includes a plurality of phase clocks CK-0 to CK in which the phase input from the phase signal generation unit 43 is changed. -7 is latched at the instant of the end of the time interval based on the first timing signal CO-1 and the second timing signal CO-2 input from the signal generator 302, and the phase clock CK-0 The phase information representing each phase of ˜CK-7 is held. Then, the latch unit 313 outputs each phase information of the phase clocks CK-0 to CK-7 to the count unit 315. The latch unit 313 includes a plurality of latch circuits D-0 to D-7, a logical product circuit (AND circuit) AND-L, and a logical product circuit (AND circuit) AND-C.

  The logical product circuit AND-L switches the logic of the first timing signal CO-1 similarly to the logical product circuit AND-L in the latch unit 303 included in the A / D conversion circuit 30 of the first embodiment. The control signal HOLD-L for operating the latch circuits D-0 to D-7 is generated from the timing until the timing when the logic of the second timing signal CO-2 is switched, and the generated control signal HOLD-L is And output to each of the latch circuits D-0 to D-6.

  The AND circuit AND-C is a timing for latching the phase information of the phase clock CK-7 based on the control signal Enable and the second timing signal CO-2 input from the control signal generator 50, that is, a latch circuit. A control signal HOLD-C representing a predetermined period for operating D-7 is generated. More specifically, the AND circuit AND-C performs the second timing from the timing at which the logic of the control signal Enable indicating the timing at which A / D conversion is started, that is, from the timing at which A / D conversion is started. A control signal HOLD-C for operating the latch circuit D-7 is generated until the timing at which the logic of the signal CO-2 is switched. Then, the AND circuit AND-C outputs the generated control signal HOLD-C to the latch circuit D-7.

  Each of the latch circuits D-0 to D-6 is the same as the phase clock CK− in the same manner as the latch circuits D-0 to D-6 in the latch unit 303 provided in the A / D conversion circuit 30 of the first embodiment. Corresponding to each of 0 to CK-6, the logic state of the input phase clock CK is latched as phase information in accordance with the control signal HOLD-L input from the AND circuit AND-L. More specifically, each of the latch circuits D-0 to D-6 operates for a period indicating that the control signal HOLD-L is an operating period, and the logical state of the operating phase clock CK. Are latched as phase information. Each of the latch circuits D-0 to D-6 is similar to the latch circuit D-0 to D-6 in the latch unit 303 provided in the A / D conversion circuit 30 of the first embodiment. The operation is stopped during a period indicating that HOLD-L is not an operating period.

  The latch circuit D-7 corresponds to the phase clock CK-7, that is, the reference clock, and the logic of the input phase clock CK-7 according to the control signal HOLD-C input from the AND circuit AND-C. The state is latched as phase information. More specifically, the latch circuit D-7 operates only during a period indicating that the control signal HOLD-C is an operating period, and uses the logical state of the operating phase clock CK-7 as phase information. Latch. The latched phase information is sequentially output from the latch circuit D-7 while the logic state of the phase clock CK-7 is latched as phase information. That is, the reference clock (phase clock CK-7) is output from the latch circuit D-7. Note that the latch circuit D-7 stops operating during a period indicating that the control signal HOLD-C is not in an operating period.

  The count unit 315 counts the reference clock included in the phase information input from the latch unit 313, that is, the phase clock CK-7. Then, the count unit 315 adds the counted value (count value) of the counted phase clock CK-7 to the phase information of the phase clock CK-0 to CK-7 input from the latch unit 313, and sends it to the encoding unit 314. Output. The count unit 315 includes a counter 3151.

  The counter 3151 counts the number of input phase clocks CK-7, that is, the number of reference clocks. Then, the counter 3151 outputs the counted value to the encoding unit 314. Here, the counter 3151 corresponds to a configuration in which the time interval is counted by the reference clock in the configuration of the conventional SS type A / D conversion type A / D conversion circuit. Therefore, the count value counted by the counter 3151 corresponds to a count value for generating a digital value in a state where the resolution is not improved in the conventional A / D conversion circuit of the SS type A / D conversion method.

  The encoding unit 314 encodes the phase information input from the latch unit 313 and generates a digital value represented by the phase information, similarly to the encoding unit 304 provided in the A / D conversion circuit 30 of the first embodiment. . That is, the encoding unit 314 generates a digital value corresponding to the magnitude of the pixel signal Signal based on the phase information input from the latch unit 313. However, the count value obtained by counting the reference clock (phase clock CK-7) output by the phase signal generation unit 43 and counted by the counter 3151 in the count unit 315 is also input to the encoding unit 314 together with the phase information. The encoding unit 314 includes an encoder 3141.

  The encoder 3141 generates a digital value obtained by encoding the count value input from the count unit 315 and a digital value obtained by encoding the phase information input from the latch unit 313 via the count unit 315. Then, the encoder 3141 outputs the generated digital value to the data output line 800 as a digital value A / D converted by the A / D conversion circuit 31 in accordance with the column selection signal input from the horizontal scanning circuit unit 300. . At this time, similarly to the encoder 3041 in the encoding unit 304 included in the A / D conversion circuit 30 of the first embodiment, the encoder 3141 converts the digital value obtained by encoding the count value input from the counting unit 315 into an A A digital value obtained by A / D converting the digital value obtained by encoding the phase information input from the latch unit 313 as a digital value on the upper side of the digital value A / D converted by the / D conversion circuit 31 Output as the lower-order digital value.

  Also in the A / D conversion circuit 31 of the second embodiment, the digital value obtained by encoding the count value input from the count unit 315 is obtained by the A / D conversion circuit of the conventional SS type A / D conversion method. A digital value obtained by encoding phase information input from the latch unit 313 corresponds to a digital value with improved resolution in a conventional SS + TDC A / D conversion type A / D conversion circuit. .

  With such a configuration, the A / D conversion circuit 31 receives the reference clock and a plurality of clocks (phase clock CK) obtained by changing the phase of the reference clock, like the A / D conversion circuit 30 of the first embodiment. It is possible to output a digital value with improved resolution. Similarly to the A / D conversion circuit 30 of the first embodiment, the A / D conversion circuit 31 includes two buffer circuits (a first buffer BUFF1 and a second buffer BUFF2) in the signal generation unit 302. The timing at which the time interval ends is delayed. Therefore, similarly to the A / D conversion circuit 30 of the first embodiment, the A / D conversion circuit 31 does not cause fluctuations in the power supply voltage, and the latches in the latch unit 313 are at the same timing. The logic state of the phase clock CK to which each of the circuits D-0 to D-7 corresponds can be held as phase information.

  Next, the operation of the A / D conversion circuit 31 of the second embodiment in the column A / D conversion circuit 20 provided in the solid-state imaging device 1 of the present embodiment will be described. FIG. 5 is a timing chart showing the operation timing of the A / D conversion circuit 31 of the second embodiment provided in the solid-state imaging device 1 of the present embodiment. FIG. 5 also shows a timing chart in which the time axis of the timing at the moment when the time interval ends is lengthened for ease of explanation.

  When the A / D conversion circuit 31 receives the pixel signal Signal to be A / D converted from the pixel 101 and starts A / D conversion in accordance with the control signal input from the control signal generation unit 50, the time t1 Starts A / D conversion. At this time, the control signal generation unit 50 sets the control signal Enable to the “High” level. Then, the ramp signal generation unit 41 generates a ramp wave Ramp from time t1 and outputs the ramp wave Ramp to the A / D conversion circuit 31. Accordingly, the pixel signal Signal is input as the input signal Vin1 and the ramp wave Ramp is input as the input signal Vin2 to the comparator COMP in the comparison unit 301. Then, the comparator COMP starts measuring the time interval.

  Further, the phase signal generation unit 43 generates the reference clock and the phase clocks CK-0 to CK-7 in which the phase of the reference clock is changed from time t1, and outputs the generated clocks to the A / D conversion circuit 31. Accordingly, the corresponding phase clocks CK-0 to CK-7 are input to the latch circuits D-0 to D-7 in the latch unit 313, respectively.

  At this time, each of the first timing signal CO-1 output from the first buffer BUFF1 in the signal generator 302 and the second timing signal CO-2 output from the second buffer BUFF2 is “Low”. Is a level. Therefore, the control signal HOLD-L output from the AND circuit AND-L in the latch unit 313 is at the “Low” level. Thereby, each of the latch circuits D-0 to D-6 is in a state where the corresponding phase clocks CK-0 to CK-6 are input, but the operation of latching the phase information is stopped.

  On the other hand, the control signal Enable is at “High” level, and the second timing signal CO-2 is at “Low” level. For this reason, the control signal HOLD-C output from the AND circuit AND-C in the latch unit 313 is at the “High” level. Thereby, the latch circuit D-7 starts an operation of latching the phase information of the corresponding phase clock CK-7, and sequentially outputs the phase information of the latched phase clock CK-7 to the count unit 315. The counter 3151 in the count unit 315 starts counting the phase clock CK-7 included in the phase information input from the latch unit 313, and outputs the counted value to the encoding unit 314.

  Thereafter, the comparator COMP receives the comparison result signal CO-0 from the time t2 when the magnitude relationship between the voltage of the input signal Vin2 and the voltage of the input signal Vin1 coincides, that is, from the timing when the time interval ends. Inversion of logic is started, and a comparison result signal CO-0 that increases at a constant rate with respect to time from the first reference voltage to the second reference voltage is output to the signal generator 302.

  Thereafter, the first buffer BUFF1 in the signal generation unit 302 receives the first timing signal CO-1 at time t3 when the voltage of the comparison result signal CO-0 becomes equal to or higher than a predetermined first intermediate voltage. Is switched from the “Low” level to the “High” level. For this reason, the control signal HOLD-L output from the AND circuit AND-L is also at the “High” level. As a result, each of the latch circuits D-0 to D-6 starts an operation of latching the phase information of the corresponding phase clocks CK-0 to CK-6 inputted, and the latched phase information is counted. Sequentially output to 315.

  Thereafter, the second buffer BUFF2 in the signal generation unit 302 receives the second timing signal CO-2 at the time t4 when the voltage of the comparison result signal CO-0 becomes equal to or higher than a predetermined second intermediate voltage. Is switched from the “Low” level to the “High” level. For this reason, the control signal HOLD-L output from the AND circuit AND-L becomes the “Low” level again. Thereby, each of the latch circuits D-0 to D-6 completes the operation of latching the phase information of the corresponding phase clocks CK-0 to CK-6 input, and holds the phase information at this time. Here, the phase information held by each of the latch circuits D-0 to D-6 is output to the count unit 315.

  On the other hand, the control signal Enable is at “High” level, and the second timing signal CO-2 is at “High” level. For this reason, the control signal HOLD-C output from the AND circuit AND-C is also at the “Low” level. Thereby, the latch circuit D-7 also completes the operation of latching the phase information of the corresponding phase clock CK-7, and holds the phase information at this time. Here, the phase information of the phase clock CK-7 held by the latch circuit D-7 is also output to the count unit 315. The counter 3151 completes the counting of the phase clock CK-7 based on the phase information of the phase clock CK-7 input from the latch unit 313, and the phase clocks CK-0 to CK- input from the latch unit 313. 7 and the count value of the counted phase clock CK-7 are combined with the phase information 7 and output to the encoding unit 314.

  In the A / D conversion circuit 31 of the second embodiment, the operation of latching the phase information by the latch circuit D-7 is completed, that is, the operation of the latch circuit D-7 is stopped, so that the counter 3151 is stopped. Is configured to complete (stop) the counting of the phase clock CK-7 by, for example, a configuration for separately stopping the counting of the phase clock CK-7 by the counter 3151 according to the control signal HOLD-C is provided. It may be configured. In this case, at the operation timing of the A / D conversion circuit 31 shown in FIG. 5, when the control signal HOLD-C is at “High” level, the counter 3151 counts the phase clock CK-7.

  The encoder 3141 in the encoding unit 314 receives the phase information of the phase clocks CK-0 to CK-7 input from the latch unit 313 via the counting unit 315 and the count value of the phase clock CK-7. Generate an encoded digital value. Then, the encoder 3141 uses the digital value obtained by encoding the count value input from the count unit 315 as a higher-order digital value, and obtains phase information of the phase clocks CK-0 to CK-7 input via the count unit 315. A digital value obtained by combining a digital value generated by encoding as a lower-order digital value is output as a digital value A / D converted by the A / D conversion circuit 31.

  By such an operation, the A / D conversion circuit 31 receives the reference clock and a plurality of clocks (phase clock CK) in which the phases of the reference clock are changed, like the A / D conversion circuit 30 of the first embodiment. Used to output a digital value with improved resolution. At this time, in the A / D conversion circuit 31, as in the A / D conversion circuit 30 of the first embodiment, each of the first buffer BUFF1 and the second buffer BUFF2 corresponds to the comparison result signal CO-0. By delaying the timing for switching the logic of each of the first timing signal CO-1 and the second timing signal CO-2, the time interval period can be changed between the first time interval period and the second time interval period. Extend to each period (see FIG. 5). In the A / D conversion circuit 31, the “Low” level of the control signal HOLD-L during the latch circuit stop period of the first time interval period (period from time t1 to time t3 shown in FIG. 5). Thus, each of the latch circuits D-0 to D-6 stops the operation of latching the phase information. Thereafter, during the latch circuit operation period from the end of the first time interval to the end of the second time interval (the period from time t3 to time t4 shown in FIG. 5), the control signal HOLD− The operation of latching the phase information by each of the latch circuits D-0 to D-6 is performed according to the "High" level of L. Thereby, also in the A / D conversion circuit 31, the power consumption at the time of A / D conversion can be suppressed by intermittently operating the latch circuits D-0 to D-6. Note that the latch circuit operation period shown in FIG. 5 also represents the timing at the instant when the time interval ends.

  Further, in the A / D conversion circuit 31, the “High” level of the control signal HOLD-C during the second time interval, that is, during the A / D conversion period from time t1 to time t4 shown in FIG. Thus, the latch circuit D-7 performs an operation of latching the phase information of the phase clock CK-7 (reference clock), and the counter 3151 counts the phase clock CK-7. Thereafter, after time t4 when the A / D conversion period ends, the A / D conversion circuit 31 stops the operation of the latch circuit D-7 latching the phase information according to the “Low” level of the control signal HOLD-C. The counting of the phase clock CK-7 by the counter 3151 is completed. That is, in the A / D conversion circuit 31, the counting of the phase clock CK-7 by the counter 3151 is stopped by stopping the operation of the latch circuit D-7 latching the phase information. Thereby, in the A / D conversion circuit 31, power consumption after the A / D conversion period ends can be suppressed.

  According to the second embodiment, the latch circuit D-7 corresponding to the reference clock (phase clock CK-7) included in the phase clocks CK-0 to CK-7 includes the comparator COMP in the comparison unit 301. The reference clock (phase clock CK-7) from the start of comparison between the voltage of the signal to be converted (pixel signal Signal, input signal Vin1) and the voltage of the ramp wave Ramp (input signal Vin2) to the second timing. Each of the latch circuits D-0 to D-6 other than the reference clock (phase clock CK-7) included in the phase clocks CK-0 to CK-7 is latched from the first timing. Until the second timing, the logic states of the corresponding phase clocks CK-0 to CK-6 are latched, and the A / D conversion circuit 30 is connected to the reference clock (phase clock CK 7) A counter (counter 3151) that counts the number of clocks of the reference clock (phase clock CK-7) based on the phase information latched by the latch circuit D-7 corresponding to 7) and outputs the counted value. The encoding unit 304 includes phase information latched by the latch circuits D-0 to D-6 corresponding to other than the reference clock (phase clock CK-7), and a count. Based on each of the values, an A / D conversion circuit 30 that generates a digital value corresponding to the voltage level of the signal to be converted (pixel signal Signal, input signal Vin1) is configured.

  As described above, according to the second embodiment, similarly to the first embodiment, the resolution is improved by using the reference clock and a plurality of clocks (phase clocks) in which the phases of the reference clock are changed. When a digital value is output, an increase in power consumption during A / D conversion and after A / D conversion is suppressed, and fluctuation in timing for latching phase information of a plurality of phase clocks during A / D conversion is suppressed. be able to. Thereby, also in the second embodiment, each latch circuit can hold the phase information of the corresponding phase clock at an accurate (same) timing as in the first embodiment, and the conventional SS + TDC A decrease in A / D conversion accuracy can be suppressed as compared with a type A / D conversion type A / D conversion circuit. Also in the column ADC type solid-state imaging device provided with the A / D conversion circuit of the second embodiment for each column of the pixel array unit, the pixel array unit of the pixel array unit is similar to the first embodiment. The A / D conversion accuracy for each column can be made uniform, and the overall image quality can be improved.

  As described above, the signal generation unit 302 included in the A / D conversion circuit 30 of the first embodiment and the A / D conversion circuit 31 of the second embodiment includes the first buffer BUFF1 and the second buffer. Due to the configuration of the two buffer circuits with BUFF2, the timing at which the time interval ends is delayed by a different time to determine the timing at which the time interval ends. In other words, in the conventional delay line, each of a plurality of INV circuits connected in series in the delay line switches the logic almost simultaneously, thereby delaying the timing at which the time interval ends. The signal generation unit 302 uses two buffer circuits that are generally composed of two INV circuits to delay the timing at which the time interval ends, as in the case of the conventional delay line. More specifically, each of the first buffer BUFF1 and the second buffer BUFF2 receives the first timing signal CO-1 and the second timing signal CO-2 according to the comparison result signal CO-0. The logic switching timing is delayed (see FIGS. 3 and 5).

<First Configuration Example of Signal Generation Unit>
Here, an example of a more specific configuration of the signal generation unit 302 provided in the A / D conversion circuit 30 of the first embodiment and the A / D conversion circuit 31 of the second embodiment will be described. Note that the signal generator 302 has the same configuration regardless of whether the signal generator 302 is included in the A / D conversion circuit 30 of the first embodiment or the A / D conversion circuit 31 of the second embodiment. And behave. Therefore, in the following description, it is assumed that the signal generation unit 302 is provided in the A / D conversion circuit 30 of the first embodiment.

  FIG. 6 is a circuit diagram showing a first configuration of the signal generation unit 302 provided in the A / D conversion circuit 30 of the first embodiment. FIG. 6 also shows a comparison unit 301 that outputs the comparison result signal CO-0 to the signal generation unit 302 of the first configuration. The configuration of the signal generation unit 302 of the first configuration shown in FIG. 6 is input from the comparison unit 301 by making the power supply voltage of the first buffer BUFF1 and the power supply voltage of the second buffer BUFF2 different. The time for delaying the comparison result signal CO-0 is different.

  In the signal generating unit 302 of the first configuration, the first buffer BUFF1 includes a preceding INV circuit INV1-1 including a P-channel MOS transistor PMOS1-1 and an N-channel MOS transistor NMOS1-1, and a P-channel. It is composed of a subsequent INV circuit INV1-2 composed of a MOS transistor PMOS1-2 and an N-channel MOS transistor NMOS1-2.

  In the first buffer BUFF1, the P-channel MOS transistor PMOS1-1 has a gate terminal as an input terminal for the comparison result signal CO-0, a source terminal as the power supply VCC1, and a drain terminal as the drain terminal of the N-channel MOS transistor NMOS1-1. Are connected to the gate terminal of the P-channel MOS transistor PMOS1-2 and to the gate terminal of the N-channel MOS transistor NMOS1-2, respectively. The N-channel MOS transistor NMOS1-1 has a gate terminal connected to the input terminal of the comparison result signal CO-0 and a source terminal connected to the ground GND. The P-channel MOS transistor PMOS1-2 has a source terminal connected to the power supply VCC1, and a drain terminal connected to the drain terminal of the N-channel MOS transistor NMOS1-2 and the output terminal of the first timing signal CO-1. . The N-channel MOS transistor NMOS1-2 has a source terminal connected to the ground GND and a drain terminal connected to the output terminal of the first timing signal CO-1.

  In the signal generator 302 having the first configuration, the second buffer BUFF2 includes a preceding INV circuit INV2-1 including a P-channel MOS transistor PMOS2-1 and an N-channel MOS transistor NMOS2-1. It is composed of a subsequent INV circuit INV2-2 composed of a P-channel MOS transistor PMOS2-2 and an N-channel MOS transistor NMOS2-2.

  In the second buffer BUFF2, the P-channel MOS transistor PMOS2-1 has a gate terminal as the input terminal for the comparison result signal CO-0, a source terminal as the power supply VCC2, and a drain terminal as the drain terminal of the N-channel MOS transistor NMOS2-1. Are connected to the gate terminal of the P-channel MOS transistor PMOS2-2 and the gate terminal of the N-channel MOS transistor NMOS2-2, respectively. The N-channel MOS transistor NMOS2-1 has a gate terminal connected to the input terminal for the comparison result signal CO-0 and a source terminal connected to the ground GND. The P-channel MOS transistor PMOS2-2 has a source terminal connected to the power supply VCC2, and a drain terminal connected to the drain terminal of the N-channel MOS transistor NMOS2-2 and the output terminal of the second timing signal CO-2. . The N-channel MOS transistor NMOS2-2 has a source terminal connected to the ground GND and a drain terminal connected to the output terminal of the second timing signal CO-2.

  As described above, in the signal generation unit 302 having the first configuration, the power supply VCC1 is used as the power supply for the front-stage INV circuit INV1-1 and the rear-stage INV circuit INV1-2 constituting the first buffer BUFF1, and the second A power supply VCC2 is used as a power source for the preceding INV circuit INV2-1 and the succeeding INV circuit INV2-2 that constitute the buffer BUFF2. Note that the voltage of the power supply VCC1 is lower than the voltage of the power supply VCC2. Thus, the threshold voltage for switching the logic of the input signal by the INV circuit INV1-1 and INV circuit INV1-2, and the threshold voltage for the switching of the logic of the input signal by the INV circuit INV2-1 and INV circuit INV2-2. The voltage becomes a different voltage. That is, the logic of the first buffer BUFF1 and the second buffer BUFF2 is switched with different voltages. As a result, the logic of the first timing signal CO-1 output from the first buffer BUFF1 is switched first, and then the logic of the second timing signal CO-2 output from the second buffer BUFF2 is switched. become.

  More specifically, when the comparison result signal CO-0 is input from the comparison unit 301, first, the voltage of the comparison result signal CO-0 input to the first buffer BUFF1 is set to the logic level of the INV circuit INV1-1. The INV circuit INV1-1 outputs the first timing signal CO-1-sub in which the logic of the input comparison result signal CO-0 is switched. When the voltage of the first timing signal CO-1-sub becomes a threshold voltage for switching the logic of the INV circuit INV1-2, the logic of the input first timing signal CO-1-sub is changed. The switched first timing signal CO-1 is output from the INV circuit INV1-2. Thereafter, when the voltage of the comparison result signal CO-0 further increases and the voltage of the comparison result signal CO-0 input to the second buffer BUFF2 becomes a threshold voltage for switching the logic of the INV circuit INV2-1. The INV circuit INV2-1 outputs the second timing signal CO-2-sub in which the logic of the input comparison result signal CO-0 is switched. When the voltage of the second timing signal CO-2-sub becomes a threshold voltage for switching the logic of the INV circuit INV2-2, the logic of the input second timing signal CO-2-sub is changed. The INV circuit INV2-2 outputs the switched second timing signal CO-2.

  As described above, in the signal generation unit 302 having the first configuration, the first buffer BUFF1 and the second buffer BUFF2 switch the logic of the input comparison result signal CO-0 with different threshold voltages. The first timing signal CO-1 and the second timing signal CO-2 are output. Thereby, the latch unit 303 can determine the timing of the moment when the time interval ends.

  As shown in FIG. 6, the power source of the comparator COMP included in the comparison unit 301 that outputs the comparison result signal CO-0 to the signal generation unit 302 of the first configuration is the power source VCC2. This is because the comparator COMP outputs the comparison result signal CO-0 that increases from the voltage of the ground GND to the voltage of the power supply VCC2 to the signal generator 302 of the first configuration.

  According to the first configuration example of the signal generation unit, the first buffer BUFF1 has the first threshold voltage for switching the logic state of the first timing signal CO-1 set in advance as the first intermediate voltage. The first transistor circuit (INV circuit INV1-1 and INV circuit INV1-2), and the second buffer BUFF2 has a second threshold voltage for switching the logic state of the second timing signal CO-2. A second transistor circuit (INV circuit INV2-1 and INV circuit INV2-2) predetermined for the second intermediate voltage, the power supply voltage of the INV circuit INV1-1 and INV circuit INV1-2, and the INV circuit The A / D conversion circuit 30 is configured with a voltage different from the power supply voltage of the INV2-1 and the INV circuit INV2-2.

  With such a configuration, the signal generation unit 302 of the first configuration delays the timing at which the time interval configured by the delay line in the conventional SS + TDC A / D conversion type A / D conversion circuit ends. The configuration is realized by two buffer circuits of a first buffer BUFF1 and a second buffer BUFF2.

  Next, the operation of the signal generator 302 having the first configuration will be described. FIG. 7 is a timing chart showing the operation timing of the signal generator 302 having the first configuration. FIG. 7 also shows a timing chart in which the time axis of the timing at the moment when the time interval ends is lengthened for ease of explanation.

  In the following description, the voltage of the power supply VCC1 is lower than the voltage of the power supply VCC2. That is, the relationship between the voltage of the power supply VCC1 and the voltage of the power supply VCC2 will be described as the relationship VCC1 <VCC2. In addition, each INV circuit provided in each of the first buffer BUFF1 and the second buffer BUFF2 has a threshold voltage that is ½ of the input power supply voltage, that is, the voltage of the input signal. However, description will be made on the assumption that the logic of the input signal is switched (inverted) when the voltage becomes ½ of the power supply voltage.

  When the A / D conversion circuit 30 starts A / D conversion from time t1, the comparator COMP in the comparison unit 301 compares the input signal Vin1 (pixel signal Signal) with the input signal Vin2 (ramp wave Ramp). To start.

  At this time, an input is made to the preceding INV circuit INV1-1 constituting the first buffer BUFF1 and the preceding INV circuit INV2-1 constituting the second buffer BUFF2 in the signal generator 302 of the first configuration. The comparison result signal CO-0 is at the “Low” level. Therefore, the first timing signal CO-1 output from the subsequent INV circuit INV1-2 that forms the first buffer BUFF1, and the second output from the subsequent INV circuit INV2-2 that forms the second buffer BUFF2. Each of the timing signals CO-2 is “Low” level. That is, the INV circuit INV1-1 outputs the first timing signal CO-1-sub that is “High” level to the INV circuit INV1-2, and the INV circuit INV1-2 is the first timing signal that is “Low” level. Output CO-1. Further, the INV circuit INV2-1 outputs the second timing signal CO-2-sub having the “High” level to the INV circuit INV2-2, and the INV circuit INV2-2 has the “Low” level. Output CO-2.

  Thereafter, the comparator COMP starts from the time t2 when the magnitude relationship between the voltage of the input signal Vin2 and the voltage of the input signal Vin1 coincides, that is, from the timing when the time interval ends, from the first reference voltage (ground). The output of the comparison result signal CO-0 that increases at a constant rate with respect to time from the voltage of GND) to the second reference voltage (voltage of the power supply VCC2) is started.

  Thereafter, in the preceding stage INV circuit INV1-1 constituting the first buffer BUFF1, the voltage of the inputted comparison result signal CO-0 is the threshold voltage (voltage of 1/2 of the voltage of the power supply VCC1 = VCC1 / 2). At time t3 when the voltage reaches a certain first intermediate voltage, the first timing signal CO-1-sub at the “Low” level is output to the subsequent INV circuit INV1-2. As a result, the INV circuits INV1-2 at the subsequent stage output the first timing signal CO-1 at the “High” level.

  Thereafter, in the preceding stage INV circuit INV2-1 constituting the second buffer BUFF2, the voltage of the input comparison result signal CO-0 is the threshold voltage (1/2 voltage of the power supply VCC2 = VCC2 / 2). At time t4 when a certain second intermediate voltage is reached, the “Low” level second timing signal CO-2-sub is output to the subsequent INV circuit INV2-2. As a result, the subsequent INV circuit INV2-2 outputs the second timing signal CO-2 at "High" level.

  By such an operation, the first buffer BUFF1 provided in the signal generator 302 of the first configuration receives the input comparison result signal CO-0, and the comparator COMP outputs the comparison result signal CO-0. The first timing signal CO-1 delayed from the start time t2 until time t3 when the voltage of the comparison result signal CO-0 becomes the threshold voltage (first intermediate voltage) is output. That is, the first buffer BUFF1 delays the timing at which the logic of the comparison result signal CO-0 is switched from time t2 to time t3. Further, the second buffer BUFF2 provided in the signal generation unit 302 of the first configuration receives the input comparison result signal CO-0, and the time t2 when the comparator COMP starts outputting the comparison result signal CO-0. The second timing signal CO-2 delayed until time t4 when the voltage of the comparison result signal CO-0 becomes the threshold voltage (second intermediate voltage) is output. That is, the second buffer BUFF2 delays the timing at which the logic of the comparison result signal CO-0 switches from time t2 to time t4.

<Second Configuration Example of Signal Generation Unit>
Next, an example of another specific configuration of the signal generation unit 302 included in the A / D conversion circuit 30 of the first embodiment and the A / D conversion circuit 31 of the second embodiment will be described. In the following description, it is assumed that the signal generation unit 302 is provided in the A / D conversion circuit 30 of the first embodiment.

  FIG. 8 is a circuit diagram showing a second configuration of the signal generation unit 302 provided in the A / D conversion circuit 30 of the first embodiment. FIG. 8 also shows a comparison unit 301 that outputs the comparison result signal CO-0 to the signal generation unit 302 of the second configuration. The configuration of the signal generation unit 302 of the second configuration shown in FIG. 8 is different in the size of each transistor constituting the first buffer BUFF1 and the size of each transistor constituting the second buffer BUFF2. By setting the size, the time for delaying the comparison result signal CO-0 input from the comparison unit 301 is set to a different time.

  In the signal generator 302 of the second configuration, the first buffer BUFF1 is similar to the first buffer BUFF1 in the signal generator 302 of the first configuration, and includes a P-channel MOS transistor PMOS1-1 and an N-channel MOS transistor. The first stage INV circuit INV1-1 composed of the NMOS 1-1 and the second stage INV circuit INV1-2 composed of the P-channel MOS transistor PMOS1-2 and the N-channel MOS transistor NMOS1-2.

  In the first buffer BUFF1 of the signal generator 302 of the second configuration, the source terminal of the P-channel MOS transistor PMOS1-1 and the P-channel MOS in the first buffer BUFF1 of the signal generator 302 of the first configuration The power supply VCC1 connected to the source terminal of the transistor PMOS1-2 replaces the power supply VCC. The connection of the other terminals of the transistors constituting the first buffer BUFF1 of the signal generator 302 of the second configuration is the same as that of the first buffer BUFF1 of the signal generator 302 of the first configuration. Therefore, detailed description is omitted.

  Further, in the signal generating unit 302 of the second configuration, the second buffer BUFF2 is similar to the second buffer BUFF2 of the signal generating unit 302 of the first configuration and is connected to the P channel MOS transistor PMOS2-1 and the N channel. The first stage INV circuit INV2-1 including the MOS transistor NMOS2-1 and the second stage INV circuit INV2-2 including the P-channel MOS transistor PMOS2-2 and the N-channel MOS transistor NMOS2-2 are included. The

  In the second buffer BUFF2 of the signal generator 302 of the second configuration, the source terminal of the P channel MOS transistor PMOS1-1 and the P channel MOS in the second buffer BUFF2 of the signal generator 302 of the first configuration The power supply VCC2 connected to the source terminals of the transistors PMOS1-2 replaces the power supply VCC. The connection of the other terminals of the respective transistors constituting the second buffer BUFF2 of the signal generator 302 of the second configuration is the same as that of the second buffer BUFF2 of the signal generator 302 of the first configuration. Therefore, detailed description is omitted.

  As described above, in the signal generating unit 302 having the second configuration, the preceding INV circuit INV1-1 and the succeeding INV circuit INV1-2 that configure the first buffer BUFF1, and the preceding stage that configures the second buffer BUFF2. The power supply VCC is used as a power source for the INV circuit INV2-1 and the subsequent INV circuit INV2-2. That is, the signal generator 302 of the second configuration uses the same power supply VCC as the power supply for all INV circuits. As shown in FIG. 8, the power source of the comparator COMP included in the comparison unit 301 that outputs the comparison result signal CO-0 to the signal generation unit 302 of the second configuration is the power source VCC. For this reason, the comparator COMP outputs the comparison result signal CO-0 that increases from the voltage of the ground GND to the voltage of the power supply VCC to the signal generation unit 302 of the second configuration.

  Therefore, in the signal generation unit 302 having the second configuration, the logic of the first timing signal CO-1 output from the first buffer BUFF1 is switched first, and then the second buffer BUFF2 outputs the second buffer BUFF2. In order to switch the logic of the timing signal CO-2, the sizes of the transistors constituting the first buffer BUFF1 and the second buffer BUFF2 are set to different sizes. In other words, the L / W ratio obtained from the gate width W and the gate length L of each of the transistors constituting the first buffer BUFF1 and the second buffer BUFF2 is set to be different from each other, thereby being input from the comparator 301. The time for delaying the comparison result signal CO-0 is set to a different time.

  Here, the relationship between the gate width W and the gate length L of each of the transistors constituting the first buffer BUFF1 and the second buffer BUFF2 will be described. FIG. 9 is a layout diagram illustrating an example of a layout in the signal generation unit 302 having the second configuration. FIG. 9A shows an example of the layout of the preceding INV circuit INV1-1 constituting the first buffer BUFF1, and FIG. 9B shows the preceding INV circuit constituting the second buffer BUFF2. An example of the layout of INV2-1 is shown.

  First, the first buffer BUFF1 will be described with reference to FIG. As described above, the preceding stage INV circuit INV1-1 constituting the first buffer BUFF1 includes the P-channel MOS transistor PMOS1-1 and the N-channel MOS transistor NMOS1-1. In the signal generation unit 302 of the second configuration, the gate width W-NMOS1-1 of the N-channel MOS transistor NMOS1-1 is widened and the gate length L-NMOS1-1 is shortened. Further, the gate width W-PMOS1-1 of the P-channel MOS transistor PMOS1-1 is narrowed and the gate length L-PMOS1-1 is lengthened. That is, the L / W ratio of the N-channel MOS transistor NMOS1-1 is reduced and the L / W ratio of the P-channel MOS transistor PMOS1-1 is increased.

  Thereby, in the INV circuit INV1-1, the gate channel resistance of the N-channel MOS transistor NMOS1-1 is small, and the gate channel resistance of the P-channel MOS transistor PMOS1-1 is large. Therefore, the threshold voltage at which the INV circuit INV1-1 switches logic is equal to the gate channel resistance of the N-channel MOS transistor NMOS1-1 and the gate channel resistance of the P-channel MOS transistor PMOS1-1 constituting the INV circuit INV1-1. In this case, the voltage is lower than the threshold voltage in this case (this corresponds to a voltage that is ½ of the power supply voltage). Thereby, the INV circuit INV1-1 is inputted when the voltage of the comparison result signal CO-0 inputted to the first buffer BUFF1 becomes lower than ½ of the voltage of the power supply VCC. An operation is performed to output the first timing signal CO-1-sub in which the logic of the comparison result signal CO-0 is switched (inverted). That is, the INV circuit INV1-1 delays the comparison result signal CO-0 by a short time by operating at a stage where the voltage of the comparison result signal CO-0 increasing from the voltage of the ground GND to the voltage of the power supply VCC is low. I will let you.

  Subsequently, the second buffer BUFF2 will be described with reference to FIG. As described above, the preceding stage INV circuit INV2-1 constituting the second buffer BUFF2 is composed of the P-channel MOS transistor PMOS2-1 and the N-channel MOS transistor NMOS2-1. In the signal generation unit 302 of the second configuration, the gate width W-NMOS2-1 of the N-channel MOS transistor NMOS2-1 is narrowed and the gate length L-NMOS2-1 is lengthened. Further, the gate width W-PMOS 2-1 of the P-channel MOS transistor PMOS 2-1 is widened and the gate length L-PMOS 2-1 is shortened. That is, the L / W ratio of the N channel MOS transistor NMOS2-1 is increased, and the L / W ratio of the P channel MOS transistor PMOS2-1 is decreased.

  Thereby, in the INV circuit INV2-1, the gate channel resistance of the N-channel MOS transistor NMOS2-1 is large, and the gate channel resistance of the P-channel MOS transistor PMOS2-1 is small. For this reason, the threshold voltage at which the INV circuit INV2-1 switches logic is equal to the gate channel resistance of the N-channel MOS transistor NMOS2-1 and the gate channel resistance of the P-channel MOS transistor PMOS2-1 constituting the INV circuit INV2-1. In this case, the voltage is higher than the threshold voltage (which also corresponds to a voltage half of the power supply voltage). Thus, the INV circuit INV2-1 is input when the voltage of the comparison result signal CO-0 input to the second buffer BUFF2 is higher than ½ of the voltage of the power supply VCC. An operation is performed to output a second timing signal CO-2-sub in which the logic of the comparison result signal CO-0 is switched (inverted). That is, the INV circuit INV2-1 operates after the voltage of the comparison result signal CO-0 that increases from the voltage of the ground GND to the voltage of the power supply VCC becomes high, and the comparison result signal CO-0 is output for a long time. Will be delayed.

  As described above, in the signal generation unit 302 having the second configuration, the preceding INV circuit INV1-1 that constitutes the first buffer BUFF1 and the preceding INV circuit INV2-1 that constitutes the second buffer BUFF2. Each transistor has a different size. Thereby, the threshold voltage for switching the logic of the signal input to the INV circuit INV1-1 and the threshold voltage for switching the logic of the signal input to the INV circuit INV2-1 are different voltages. That is, the logic of the first buffer BUFF1 and the second buffer BUFF2 is switched with different voltages. As a result, in the signal generator 302 of the second configuration as well, the logic of the first timing signal CO-1 output from the first buffer BUFF1 is the same as that of the signal generator 302 of the first configuration. After that, the logic of the second timing signal CO-2 output from the second buffer BUFF2 is switched.

  In the signal generating unit 302 having the second configuration, each of the subsequent INV circuit INV1-2 configuring the first buffer BUFF1 and the subsequent INV circuit INV2-2 configuring the second buffer BUFF2. The size of the transistor is not particularly specified.

  According to the second configuration example of the signal generation unit, the first buffer BUFF1 has the first threshold voltage for switching the logic state of the first timing signal CO-1 set in advance as the first intermediate voltage. In addition, the first buffer circuit (the preceding INV circuit INV1-1 composed of the P-channel MOS transistor PMOS1-1 and the N-channel MOS transistor NMOS1-1) is provided, and the second buffer BUFF2 has a second timing. The second threshold voltage for switching the logic state of the signal CO-2 is configured by a second transistor circuit (a P-channel MOS transistor PMOS2-1 and an N-channel MOS transistor NMOS2-1, which is predetermined as a second intermediate voltage). The first stage INV circuit INV2-1), and the P channel constituting the INV circuit INV1-1. The L / W ratio of the N-channel MOS transistor PMOS1-1 and the N-channel MOS transistor NMOS1-1 and the L / W ratio of the P-channel MOS transistor PMOS2-1 and the N-channel MOS transistor NMOS2-1 constituting the INV circuit INV2-1 Are configured with A / D conversion circuits 30 having different L / W ratios.

  With this configuration, the signal generation unit 302 of the second configuration delays the timing at which the time interval configured by the delay line in the conventional SS + TDC A / D conversion type A / D conversion circuit ends. The configuration is realized by two buffer circuits of a first buffer BUFF1 and a second buffer BUFF2. Note that the operation of the signal generating unit 302 with the second configuration can be considered in the same way as the operation of the signal generating unit 302 with the first configuration, and thus detailed description thereof is omitted.

  In the signal generating unit 302 having the second configuration, each of the preceding INV circuit INV1-1 that constitutes the first buffer BUFF1 and the preceding INV circuit INV2-1 that constitutes the second buffer BUFF2. The configuration in which the time for delaying the comparison result signal CO-0 input from the comparison unit 301 is set to be different by changing the sizes of the transistors is shown. That is, the case where the size of the transistor of the preceding INV circuit constituting each buffer circuit is changed has been described. However, each transistor of the subsequent INV circuit INV1-2 that constitutes the first buffer BUFF1 and the subsequent INV circuit INV2-2 that constitutes the second buffer BUFF2, that is, each buffer circuit is configured. In addition to the preceding INV circuit, the transistors of the succeeding INV circuit may have different sizes so that the time for delaying the comparison result signal CO-0 may be different.

  In the signal generator 302 having the first configuration, the power supply voltages of the respective buffer circuits are set to different voltages, and in the signal generator 302 having the second configuration, the sizes of the transistors configuring the respective buffer circuits are set to different sizes. In the above, the configuration in which the time for delaying the comparison result signal CO-0 is set to a different time has been described. However, the configuration in which the time for delaying the comparison result signal CO-0 is set to a different time is the first configuration or the first configuration. It is not limited to the configuration of 2. For example, the time for delaying the comparison result signal CO-0 by changing the power supply voltage of each buffer circuit and the transistor size, that is, by combining the concept of the first configuration and the concept of the second configuration. Can also be at different times.

  According to the configuration example of the signal generation unit, the first buffer BUFF1 has a first threshold voltage at which the first threshold voltage for switching the logic state of the first timing signal CO-1 is predetermined as the first intermediate voltage. Transistor circuit (from the preceding stage INV circuit INV1-1 composed of P channel MOS transistor PMOS1-1 and N channel MOS transistor NMOS1-1, P channel MOS transistor PMOS1-2 and N channel MOS transistor NMOS1-2) The second buffer BUFF2 has a second threshold voltage for switching the logic state of the second timing signal CO-2 determined in advance as the second intermediate voltage. Second transistor circuit (P-channel MOS transistor PMOS2-1 and N-channel A first-stage INV circuit INV2-1 composed of a channel MOS transistor NMOS2-1, and a second-stage INV circuit INV2-2) composed of a P-channel MOS transistor PMOS2-2 and an N-channel MOS transistor NMOS2-2. The power supply voltage of the INV circuit INV1-1 and INV circuit INV1-2 is different from the power supply voltage of the INV circuit INV2-1 and INV circuit INV2-2, and further constitutes the INV circuit INV1-1. L / W ratio of P channel MOS transistor PMOS1-1 and N channel MOS transistor NMOS1-1, and L / W ratio of P channel MOS transistor PMOS2-1 and N channel MOS transistor NMOS2-1 constituting INV circuit INV2-1 Different from A / D conversion circuit 30 is constituted of a L / W ratio.

  According to the present embodiment, a pixel array unit (pixel array unit 10) in which a plurality of pixels (pixels 101) that output pixel signals according to the amount of incident light are arranged in a two-dimensional matrix, and the pixel array unit 10 A plurality of A / D conversion circuits 30 (or A / D conversion circuits 30) that perform analog-to-digital conversion on a pixel signal (pixel signal Signal) in a corresponding column as a signal to be converted. / D conversion circuit 31), and a ramp signal generation unit (ramp signal generation unit 41) and phase signal generation unit (phase signal generation unit 43) of the A / D conversion circuit 30 (or A / D conversion circuit 31). Are configured in common with all the A / D conversion circuits 30 (or A / D conversion circuits 31), and constitute a solid-state imaging device (solid-state imaging device 1).

  As described above, according to the mode for carrying out the present invention, the latch unit is provided in the A / D conversion circuit and latches phase information of a plurality of phase clocks in order to improve the resolution of A / D conversion. However, a timing signal having a time difference indicating the timing at which the phase information latch is started and the timing at which the phase information is latched (stopped) is converted into two logic circuits having different threshold voltages to operate (in the embodiment, a buffer circuit or a buffer circuit) Generated by the INV circuit). As a result, in the embodiment for carrying out the present invention, there is no need to operate a delay circuit (delay line) composed of a plurality of buffer circuits and INV circuits, which has been used in the conventional A / D conversion circuit, and the latch. A predetermined period required for the operation in which the unit latches the phase information can be determined. More specifically, the latching of phase information of the phase clock is started according to the operation of the logic circuit having a low threshold voltage, and the latching of the phase information of the phase clock is completed (stopped) according to the operation of the logic circuit having a high threshold voltage. The timing of the moment when each latch circuit provided in the latch unit performs the operation of latching the phase information of the corresponding phase clock can be determined. Thus, in the solid-state imaging device provided with the A / D conversion circuit according to the embodiment of the present invention for each column (column) of the pixels arranged in the pixel array unit, each A / D conversion circuit includes Each latch circuit included in each latch unit can latch the phase information of the corresponding phase clock at an accurate (same) timing, and a conventional A / D conversion circuit is provided for each pixel column. As compared with the solid-state imaging device, it is possible to suppress a decrease in A / D conversion accuracy.

  In the embodiment for carrying out the present invention, a signal for determining the timing of the moment when the latch circuit holds the phase information is generated with fewer components than the conventional delay circuit. For this reason, in a solid-state imaging device provided with a conventional A / D conversion circuit for each column of pixels, a transient bounce occurs in the power supply voltage and the ground voltage with the operation of the delay circuit. Even when the situation occurs, the solid-state imaging device provided with the A / D conversion circuit according to the embodiment of the present invention for each column of pixels has few factors causing the bounce. Thereby, in the solid-state imaging device provided with the A / D conversion circuit of the form for carrying out the present invention for each column (column) of pixels, the A / D conversion accuracy does not differ for each column. , A / D conversion accuracy for each column can be made uniform, and deterioration of the overall image quality can be suppressed.

  In the present embodiment, the case where the ramp signal generation unit 41 generates the ramp wave Ramp in which the voltage monotonously decreases at a constant rate with respect to time has been described. However, the ramp wave Ramp generated by the ramp signal generator 41 is not limited to this embodiment. For example, the ramp signal generation unit 41 may generate a ramp wave Ramp whose voltage monotonously increases at a constant rate with respect to time from the start of A / D conversion. In this case, the same effect can be obtained by changing the configuration and operation of each corresponding component (comparator COMP provided in the comparison unit 301) based on the same idea as the present invention. .

  In the present embodiment, the comparator COMP included in the comparison unit 301 outputs the comparison result signal CO-0 that increases from the first reference voltage to the second reference voltage at a constant rate with respect to time. Explained the case. However, the comparison result signal CO-0 output from the comparator COMP is not limited to this embodiment. For example, when the comparator COMP matches the magnitude of the voltage of the input signal Vin2 and the voltage of the input signal Vin1, that is, from the timing at which the time interval ends, the first reference voltage at a constant rate with respect to time. The comparison result signal CO-0 that decreases from 1 to the second reference voltage can also be output. Also in this case, based on the same idea as the present invention, the configuration and operation of each corresponding component are changed.

  For example, in the signal generator 302 having the second configuration shown in FIG. 8, the L / W ratio of the N-channel MOS transistor NMOS1-1 in the previous stage INV circuit INV1-1 constituting the first buffer BUFF1 is increased. The L / W ratio of the P-channel MOS transistor PMOS1-1 is reduced. Further, the L / W ratio of the N-channel MOS transistor NMOS2-1 in the previous stage INV circuit INV2-1 constituting the second buffer BUFF2 is reduced, and the L / W ratio of the P-channel MOS transistor PMOS2-1 is increased. Thereby, the INV circuit INV1-1 operates at a stage where the voltage of the comparison result signal CO-0 that decreases from the voltage of the power supply VCC to the voltage of the ground GND is high, and delays the comparison result signal CO-0 by a short time. The INV circuit INV2-1 operates after the voltage of the comparison result signal CO-0 becomes low, and can delay the comparison result signal CO-0 for a long time. Even with this configuration, the same effects as those of the present invention can be obtained.

  The A / D conversion circuit of the present invention is effective when provided for each column of pixels arranged in the pixel array section in the solid-state imaging device. For this reason, in this embodiment, the case where the A / D conversion circuit of the present invention is applied to a solid-state imaging device has been described. However, the application of the A / D conversion circuit of the present invention, that is, the system to which the A / D conversion circuit of the present invention can be applied is not limited to this embodiment. For example, even in a system that uses a single A / D conversion circuit of the present invention or a system that includes a plurality of single A / D conversion circuits of the present invention, the resolution can be reduced by acquiring phase information. The effect of the A / D conversion circuit of the present invention, which can achieve both the effect of being able to improve and the effect of being able to suppress the decrease in A / D conversion accuracy, is greater than that of the conventional A / D conversion circuit. Is also superior.

  The embodiment of the present invention has been described above with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes various modifications within the scope of the present invention. It is.

DESCRIPTION OF SYMBOLS 1 ... Solid-state imaging device 10 ... Pixel array part 101 ... Pixel 20 ... Column A / D conversion circuit (A / D conversion circuit)
30, 31 ... A / D conversion circuit (analog / digital converter)
301 ... Comparator COMP ... Comparator (Comparator)
302... Signal generation unit BUFF1... First buffer (signal generation unit, first logic circuit, first transistor circuit)
INV1-1, INV1-2 ... INV circuit (first logic circuit, first transistor circuit)
PMOS1-1 P channel MOS transistor (first transistor circuit)
NMOS 1-1... N-channel MOS transistor (first transistor circuit)
PMOS 1-2... P-channel MOS transistor NMOS 1-2... N-channel MOS transistor BUFF 2... Second buffer (signal generator, second logic circuit, second transistor circuit)
INV2-1, INV2-2 ... INV circuit (second logic circuit, second transistor circuit)
PMOS2-1 P channel MOS transistor (second transistor circuit)
NMOS2-1 ... N-channel MOS transistor (second transistor circuit)
PMOS 2-2... P channel MOS transistor NMOS 2-2... N channel MOS transistors 303 and 313... Latch part AND-L .. AND circuit and AND circuit (latch part)
AND-C ... AND circuit, AND circuit (latch part)
D-0 to D-7 ... Latch circuit (latch part)
304, 314... Encoding unit 3041, 3141... Encoder (encoding unit)
315: Count unit 3151: Counter (count unit)
41: Ramp signal generation unit 43 ... Phase signal generation unit 50 ... Control signal generation unit 200 ... Vertical scanning circuit unit 300 ... Horizontal scanning circuit unit 800 ... Data output line

Claims (7)

A ramp signal generator that generates a ramp wave that is an analog reference signal whose voltage monotonously decreases or monotonically increases at a constant rate with respect to time;
A phase signal generator that generates a reference clock and a plurality of clocks in which the phase of the reference clock is changed, and outputs the generated clocks as respective phase clocks;
Since the result of comparing the voltage of the input signal to be converted and the voltage of the ramp wave satisfies a predetermined condition, the voltage is proportional to the time from the first reference voltage, A comparison unit that outputs an analog comparison result signal that sequentially changes to the second reference voltage through the first intermediate voltage and the second intermediate voltage;
A first logic circuit that switches a logic state of the first timing signal to be output when the voltage of the comparison result signal is equal to or higher than the first intermediate voltage; and the voltage of the comparison result signal is the second voltage A signal generation unit including a second logic circuit that switches a logic state of the second timing signal to be output when the voltage becomes equal to or higher than the intermediate voltage;
Corresponding to each of the phase clocks, according to at least one timing of the first timing when the logic state of the first timing signal is switched or the second timing when the logic state of the second timing signal is switched. A plurality of latch circuits that latch the respective logical states of the phase clock, and a latch unit that outputs the logical state of the phase clock latched by each of the latch circuits as phase information;
Based on the phase information, an encoding unit that generates a digital value corresponding to the voltage level of the signal to be converted;
Comprising
An A / D conversion circuit characterized by the above. Each of the plurality of latch circuits latches the logic state of the corresponding phase clock from the first timing to the second timing.
The A / D conversion circuit according to claim 1. The latch circuit corresponding to the reference clock included in the phase clock is
The comparison unit latches the logic state of the reference clock from the start of comparison between the voltage of the signal to be converted and the voltage of the ramp wave to the second timing,
Each of the latch circuits corresponding to other than the reference clock included in the phase clock,
Latching the corresponding logic state of the phase clock from the first timing to the second timing;
The A / D conversion circuit is
A counting unit including a counter that counts the number of clocks of the reference clock based on the phase information latched by the latch circuit corresponding to the reference clock, and outputs the counted value;
Further comprising
The encoding unit is
Based on each of the phase information latched by the latch circuit corresponding to other than the reference clock and the count value, a digital value corresponding to the voltage level of the signal to be converted is generated.
The A / D conversion circuit according to claim 1. The first logic circuit includes:
A first transistor circuit in which a first threshold voltage for switching a logic state of the first timing signal is predetermined to the first intermediate voltage;
With
The second logic circuit includes:
A second transistor circuit in which a second threshold voltage for switching a logic state of the second timing signal is predetermined to the second intermediate voltage;
With
The power supply voltage of the first transistor circuit and the power supply voltage of the second transistor circuit are different voltages.
The A / D conversion circuit according to claim 2, wherein the A / D conversion circuit is provided. The first logic circuit includes:
A first transistor circuit in which a first threshold voltage for switching a logic state of the first timing signal is predetermined to the first intermediate voltage;
With
The second logic circuit includes:
A second transistor circuit in which a second threshold voltage for switching a logic state of the second timing signal is predetermined to the second intermediate voltage;
With
The L / W ratio of the first transistor circuit and the L / W ratio of the second transistor circuit are different L / W ratios.
The A / D conversion circuit according to claim 2, wherein the A / D conversion circuit is provided. The first logic circuit includes:
A first transistor circuit in which a first threshold voltage for switching a logic state of the first timing signal is predetermined to the first intermediate voltage;
With
The second logic circuit includes:
A second transistor circuit in which a second threshold voltage for switching a logic state of the second timing signal is predetermined to the second intermediate voltage;
With
The power supply voltage of the first transistor circuit and the power supply voltage of the second transistor circuit are different voltages,
further,
The L / W ratio of the first transistor circuit and the L / W ratio of the second transistor circuit are different L / W ratios.
The A / D conversion circuit according to claim 2, wherein the A / D conversion circuit is provided. A pixel array unit in which a plurality of pixels that output pixel signals according to the amount of incident light are arranged in a two-dimensional matrix; and
The analog-to-digital conversion according to any one of claims 1 to 6, wherein the pixel signal is arranged for each column or a plurality of columns of the pixels arranged in the pixel array unit, and the pixel signals of the corresponding columns are converted into signals to be converted. A plurality of A / D conversion circuits according to item 1,
With
Each of the ramp signal generation unit and the phase signal generation unit of the A / D conversion circuit is arranged in common for all the A / D conversion circuits.
A solid-state imaging device.

Images