JP2015204409A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Abstract

A silicon carbide semiconductor device capable of reducing the contact resistance between a silicon carbide substrate and an electrode while increasing the degree of integration of semiconductor elements and a method for manufacturing the same. In an atmosphere containing at least one of aluminum and boron, a portion of a buffer layer 17 on the third impurity region 14 and a part of the third impurity region 14 are removed to form a main surface 10a. A concave portion 8 is formed which is formed by the side portion 8a that is connected and the bottom portion 8b that is connected to the side portion 8a. The step of forming the recess 8 includes a step of connecting the bottom 8 b of the recess 8 and the second impurity region 13 and forming a fourth impurity region 18 having an impurity concentration higher than that of the second impurity region 13. An electrode 16 containing aluminum, in contact with fourth impurity region 18 at bottom 8b, in contact with third impurity region 14 at side 18a, and not in contact with third impurity region 14 at main surface 10a is formed. [Selection] Figure 1

Description

  The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same, and more particularly to a silicon carbide semiconductor device having an electrode in contact with a silicon carbide substrate and a method for manufacturing the same.

  In recent years, in order to enable a semiconductor device to have a high breakdown voltage, low loss, use under a high temperature environment, etc., silicon carbide is being adopted as a material constituting the semiconductor device. Silicon carbide is a wide band gap semiconductor having a larger band gap than silicon that has been widely used as a material for forming semiconductor devices. Therefore, by adopting silicon carbide as a material constituting the semiconductor device, it is possible to achieve a high breakdown voltage and a low on-resistance of the semiconductor device. In addition, a semiconductor device that employs silicon carbide as a material has an advantage that a decrease in characteristics when used in a high temperature environment is small as compared with a semiconductor device that employs silicon as a material.

  For example, Japanese Patent Laid-Open No. 8-8210 (Patent Document 1) describes a method for manufacturing a silicon carbide semiconductor element having an electrode that is in ohmic contact with a silicon carbide substrate. According to the method for manufacturing the silicon carbide semiconductor element, after the ion implantation is performed on the surface of the silicon carbide substrate, the surface layer is heated to a depth at which the concentration of ion species to be ion-implanted from the surface reaches a peak value. Oxidized. After the oxide layer formed by the thermal oxidation is removed, a metal electrode is formed on the exposed surface. Thus, an electrode having a low contact resistance can be formed on the surface of the silicon carbide substrate.

JP-A-8-8210

  According to the method for manufacturing a silicon carbide semiconductor element described in Japanese Patent Application Laid-Open No. 8-8210, the metal electrode is formed in contact with the main surface of the silicon carbide substrate. As the degree of integration of the semiconductor elements is increased, the area where the metal electrode is in contact with the main surface of the silicon carbide substrate is reduced, so that the contact resistance between the electrode and the silicon carbide substrate is increased. That is, it has been difficult to reduce the contact resistance between the silicon carbide substrate and the electrode while increasing the degree of integration of the semiconductor elements.

  An object of one embodiment of the present invention is to provide a silicon carbide semiconductor device capable of reducing the contact resistance between a silicon carbide substrate and an electrode while increasing the integration degree of semiconductor elements, and a method for manufacturing the same.

  A method for manufacturing a silicon carbide semiconductor device according to one embodiment of the present invention includes the following steps. A silicon carbide substrate having a main surface is formed. The silicon carbide substrate has a first impurity region having a first conductivity type, a second impurity region in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a first conductivity type. And a third impurity region separated from the first impurity region by the second impurity region. An insulating film having an opening in which the third impurity region is exposed is formed on the main surface of the silicon carbide substrate. A buffer layer is formed in contact with the third impurity region on the main surface and in contact with the insulating film in the opening. Removing a part of the buffer layer on the third impurity region and a part of the third impurity region in an atmosphere containing at least one of aluminum and boron; And a bottom formed by connecting the bottom part to each other. The step of forming the recess includes a step of forming a fourth impurity region having the second conductivity type, connecting the bottom of the recess and the second impurity region, and having an impurity concentration higher than that of the second impurity region. An electrode containing aluminum, in contact with the fourth impurity region at the bottom of the recess, in contact with the third impurity region at the side of the recess, and not in contact with the third impurity region at the main surface is formed.

  A silicon carbide semiconductor device according to one embodiment of the present invention includes a silicon carbide substrate, a buffer layer, and an electrode. The silicon carbide substrate is provided with a recess formed by a side portion connected to the main surface and a bottom portion connected to the side portion. The silicon carbide substrate has a first impurity region having a first conductivity type, a second impurity region in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and a first conductivity type. The third impurity region separated from the first impurity region by the second impurity region and the second conductivity type, connecting the bottom of the recess and the second impurity region, and having an impurity higher than that of the second impurity region And a fourth impurity region having a concentration. The buffer layer is in contact with the third impurity region on the main surface. The electrode is in contact with the fourth impurity region at the bottom of the recess and contains aluminum. The electrode is in contact with the third impurity region at the side of the recess and is not in contact with the third impurity region at the main surface.

  According to one aspect of the present invention, it is an object to provide a silicon carbide semiconductor device capable of reducing the contact resistance between a silicon carbide substrate and an electrode and a method for manufacturing the same while increasing the degree of integration of semiconductor elements.

1 is a schematic cross-sectional view schematically showing a structure of a silicon carbide semiconductor device according to a first embodiment of the present invention. It is an enlarged view of the area | region II in FIG. FIG. 3 is a diagram schematically showing an impurity concentration in a contact region along a direction X in FIG. 2. It is a cross-sectional schematic diagram which shows schematically the structure of the modification of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a flowchart which shows schematically the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. FIG. 3 is a schematic cross sectional view schematically showing a first step of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. It is a cross-sectional schematic diagram which shows schematically the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 5th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 6th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 7th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 8th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the 9th process of the manufacturing method of the silicon carbide semiconductor device which concerns on Embodiment 1 of this invention. It is a cross-sectional schematic diagram which shows schematically the structure of the silicon carbide semiconductor device which concerns on Embodiment 2 of this invention.

[Description of Embodiment of the Present Invention]
(1) The method for manufacturing silicon carbide semiconductor device 1 according to the embodiment includes the following steps. Silicon carbide substrate 10 having main surface 10a is formed. The silicon carbide substrate includes a first impurity region 12 having a first conductivity type, a second impurity region 13 in contact with the first impurity region 12 and having a second conductivity type different from the first conductivity type, and a first conductivity. And a third impurity region 14 having a shape and separated from the first impurity region 12 by the second impurity region 13. Insulating film 22 having opening 80 in which third impurity region 14 is exposed at main surface 10a of silicon carbide substrate 10 is formed. Buffer layer 17 is formed in contact with third impurity region 14 on main surface 10 a and in contact with insulating film 22 in opening 80. By removing a portion of the buffer layer 17 on the third impurity region 14 and a part of the third impurity region 14 in an atmosphere containing at least one of aluminum and boron, the side portion connected to the main surface 10a is removed. A concave portion 8 formed by 8a and a bottom portion 8b connected to the side portion 8a is formed. The step of forming the recess 8 includes a fourth impurity region 18 having the second conductivity type, connecting the bottom 8b of the recess 8 and the second impurity region 13 and having an impurity concentration higher than that of the second impurity region 13. Forming. An electrode 16 containing aluminum, in contact with the fourth impurity region 18 at the bottom 8b of the recess 8, in contact with the third impurity region 14 at the side 8a of the recess 8, and not in contact with the third impurity region 14 at the main surface 10a is formed. Is done.

  According to the method for manufacturing a silicon carbide semiconductor device described in (1) above, the electrode 16 that is in contact with the third impurity region 14 at the side 8a of the recess 8 and that is not in contact with the third impurity region 14 at the main surface 10a is formed. Is done. In order to reduce the contact resistance between the electrode 16 and the third impurity region 14, it is necessary to increase the contact area between the electrode 16 and the third impurity region 14 to some extent. In the case where the electrode 16 is in contact with the third impurity region 14 on the main surface 10a, the degree of integration of the semiconductor element is lowered when the contact area between the electrode 16 and the third impurity region 14 is increased. Therefore, by providing the electrode 16 so as to be in contact with the third impurity region 14 at the side 8a of the recess 8 and not to be in contact with the third impurity region 14 at the main surface 10a, without reducing the integration degree of the semiconductor element, The contact area between the electrode 16 and the third impurity region 14 can be increased. As a result, the contact resistance between the third impurity region 14 of the silicon carbide substrate 10 and the electrode 16 can be reduced while increasing the degree of integration of the semiconductor elements.

  According to the method for manufacturing the silicon carbide semiconductor device described in (1) above, the portion of the buffer layer 17 on the third impurity region 14 and the third impurity region in an atmosphere containing at least one of aluminum and boron. By removing a part of 14, a concave portion 8 formed by a side portion 8 a connected to the main surface 10 a and a bottom portion 8 b connected to the side portion 8 a is formed. The step of forming the recess 8 includes a step of connecting the bottom 8 b of the recess 8 and the second impurity region 13 and forming a fourth impurity region 18 having an impurity concentration higher than that of the second impurity region 13. Thereby, the impurity concentration in the portion of the fourth impurity region 18 in direct contact with the electrode 16 can be increased. Therefore, the contact resistance between the fourth impurity region 18 and the electrode 16 can be effectively reduced.

  (2) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to (1) above, the step of forming fourth impurity region 18 is performed using plasma. Thereby, since aluminum or boron can be effectively introduced into the bottom 8b of the recess 8, the fourth impurity region 18 having a high impurity concentration can be formed. As a result, the contact resistance between the electrode 16 and the fourth impurity region 18 can be reduced.

  (3) Preferably, the method for manufacturing silicon carbide semiconductor device 1 according to (1) or (2) further includes an annealing step of alloying electrode 16. Thereby, alloying of the electrode 16 and activation of the impurities contained in the fourth impurity region 18 can be performed simultaneously.

(4) Preferably, in the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (3), the step of forming recess 8 includes a silicon carbide substrate using a gas containing BCl ₃ and Cl _2. The process of processing is included. Thereby, recess 8 can be formed by effectively etching main surface 10a of silicon carbide substrate 10.

(5) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to (4) above, the step of forming recess 8 is after the step of processing silicon carbide substrate 10 using a gas containing BCl ₃ and Cl _2. And a step of treating the silicon carbide substrate 10 using a gas containing BCl ₃ . In the step of processing silicon carbide substrate 10 using a gas containing BCl ₃ , fourth impurity region 18 is formed. Recess 8 is formed by processing silicon carbide substrate 10 using a gas containing BCl ₃ and Cl ₂ , and then silicon carbide substrate 10 is processed using a gas containing BCl ₃ , thereby forming bottom 8b of recess 8. Boron can be introduced. As a result, the boron concentration in the portion of the fourth impurity region 18 in contact with the bottom 8b of the recess 8 can be increased, so that the contact resistance between the fourth impurity region 18 and the electrode 16 can be effectively reduced. it can.

(6) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to any of (1) to (5) above, after the step of forming fourth impurity region 18, the maximum impurity concentration of fourth impurity region 18 is achieved. The value is 1 × 10 ¹⁹ cm ⁻³ or more and 4 × 10 ²⁰ cm ⁻³ or less. By setting the maximum value of the impurity concentration of the fourth impurity region 18 to 1 × 10 ¹⁹ cm ⁻³ or more, the contact resistance between the fourth impurity region 18 and the electrode 16 can be effectively reduced. Moreover, the switching speed of silicon carbide semiconductor device 1 can be improved. By setting the maximum value of the impurity concentration of the fourth impurity region 18 to 4 × 10 ²⁰ cm ⁻³ or less, it is possible to suppress deterioration of the crystallinity of the upper surface of the fourth impurity region 18.

  (7) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (6) above, in the direction perpendicular to main surface 10a after the step of forming fourth impurity region 18. The distance between the position x1 indicating the maximum value a1 of the impurity concentration of the fourth impurity region 18 and the position x2 having the impurity concentration a2 that is 1/10 of the maximum value a1 is less than 0.1 μm. Thus, the series resistance of the fourth impurity region 18 itself can be reduced until the electrode 16 and the second impurity region 13 are connected, and the switching speed can be improved.

  (8) In the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (7), preferably, electrode 16 includes TiAlSi. This reduces both the contact resistance between the third impurity region 14 having the first conductivity type and the electrode 16 and the contact resistance between the fourth impurity region 18 having the second conductivity type and the electrode 16. can do.

  (9) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to any of (1) to (8), buffer layer 17 includes TiN. Thereby, the adhesiveness of the buffer layer 17 and the insulating film 22 can be improved.

  (10) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to any of (1) to (9) above, after the step of forming recess 8, recess 8 in a direction perpendicular to main surface 10 a is formed. The height H of the side portion 8a is not less than 0.1 μm and not more than 0.3 μm. The contact area between the electrode 16 and the third impurity region 14 can be increased by setting the height H of the side portion 8a of the recess 8 to 0.1 μm or more. As a result, the contact resistance between the electrode 16 and the third impurity region 14 can be reduced. By setting the height H of the side portion 8a of the recess 8 to 0.3 μm or less, the recess 8 can be prevented from penetrating the third impurity region 14.

  (11) Preferably in the method for manufacturing silicon carbide semiconductor device 1 according to any one of (1) to (10) above, the bottom of recess 8 in the direction parallel to main surface 10a after the step of forming recess 8 When the width of 8b is W1 (μm) and the width of the fourth impurity region 18 is W2 (μm), W2 (μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. . By setting W2 ([mu] m) to be W1-0.2 ([mu] m) or more, a necessary minimum width for obtaining a desired contact resistance can be ensured. By setting W2 (μm) to W1 + 0.2 (μm) or less, excessive impurity erosion to the side wall is suppressed, and a contact height H necessary for a desired contact resistance between the electrode 16 and the third impurity region 14 is secured. be able to.

  (12) Silicon carbide semiconductor device 1 according to the embodiment includes a silicon carbide substrate 10, a buffer layer 17, and an electrode 16. Silicon carbide substrate 10 is provided with a recess 8 formed by a side portion 8a connected to main surface 10a and a bottom portion 8b connected to side portion 8a. Silicon carbide substrate 10 includes first impurity region 12 having a first conductivity type, second impurity region 13 in contact with first impurity region 12 and having a second conductivity type different from the first conductivity type, The third impurity region 14 having a conductivity type and separated from the first impurity region 12 by the second impurity region 13 is connected to the bottom 8b of the recess 8 and the second impurity region 13 having the second conductivity type. And a fourth impurity region 18 having an impurity concentration higher than that of the second impurity region 13. Buffer layer 17 is in contact with third impurity region 14 at main surface 10a. The electrode 16 is in contact with the fourth impurity region 18 at the bottom 8b of the recess 8 and contains aluminum. The electrode 16 is in contact with the third impurity region 14 at the side 8a of the recess 8 and is not in contact with the third impurity region 14 at the main surface 10a.

  According to the silicon carbide semiconductor device described in (12) above, electrode 16 is in contact with third impurity region 14 at side 8a of recess 8 and is not in contact with third impurity region 14 at main surface 10a. In order to reduce the contact resistance between the electrode 16 and the third impurity region 14, it is necessary to increase the contact area between the electrode 16 and the third impurity region 14 to some extent. In the case where the electrode 16 is in contact with the third impurity region 14 on the main surface 10a, the degree of integration of the semiconductor element is lowered when the contact area between the electrode 16 and the third impurity region 14 is increased. Therefore, by providing the electrode 16 so as to be in contact with the third impurity region 14 at the side 8a of the recess 8 and not to be in contact with the third impurity region 14 at the main surface 10a, without reducing the integration degree of the semiconductor element, The contact area between the electrode 16 and the third impurity region 14 can be increased. As a result, the contact resistance between the third impurity region 14 of the silicon carbide substrate 10 and the electrode 16 can be reduced while increasing the degree of integration of the semiconductor elements.

(13) Preferably in silicon carbide semiconductor device 1 according to (12) above, the maximum value of the impurity concentration of fourth impurity region 18 is not less than 1 × 10 ¹⁹ cm ^{−3 and not} more than 4 × 10 ²⁰ cm ⁻³ . By setting the maximum value of the impurity concentration of the fourth impurity region 18 to 1 × 10 ¹⁹ cm ⁻³ or more, the contact resistance between the fourth impurity region 18 and the electrode 16 can be effectively reduced. Moreover, the switching speed of silicon carbide semiconductor device 1 can be improved. By setting the maximum value of the impurity concentration of the fourth impurity region 18 to 4 × 10 ²⁰ cm ⁻³ or less, it is possible to suppress deterioration of the crystallinity of the upper surface of the fourth impurity region 18.

  (14) Preferably in silicon carbide semiconductor device 1 according to (12) or (13) above, position x1 indicating the maximum value a1 of the impurity concentration of fourth impurity region 18 in the direction perpendicular to main surface 10a; The distance from the position x2 having the impurity concentration a2 that is 1/10 of the maximum value is less than 0.1 μm. Thus, the series resistance of the fourth impurity region 18 itself can be reduced until the electrode 16 and the second impurity region 13 are connected, and the switching speed can be improved.

  (15) In silicon carbide semiconductor device 1 according to any one of (12) to (14), preferably, electrode 16 includes TiAlSi. This reduces both the contact resistance between the third impurity region 14 having the first conductivity type and the electrode 16 and the contact resistance between the fourth impurity region 18 having the second conductivity type and the electrode 16. can do.

  (16) In silicon carbide semiconductor device 1 according to any of (12) to (15) above, preferably, buffer layer 17 includes TiN. Thereby, the adhesiveness of the buffer layer 17 and the insulating film 22 can be improved.

  (17) Preferably in silicon carbide semiconductor device 1 according to any of (12) to (16) above, height H of side portion 8a of recess 8 in the direction perpendicular to main surface 10a is 0.1 μm. It is 0.3 μm or less. The contact area between the electrode 16 and the third impurity region 14 can be increased by setting the height H of the side portion 8a of the recess 8 to 0.1 μm or more. As a result, the contact resistance between the electrode 16 and the third impurity region 14 can be reduced. By setting the height H of the side portion 8a of the recess 8 to 0.3 μm or less, the recess 8 can be prevented from penetrating the third impurity region 14.

(18) Preferably in silicon carbide semiconductor device 1 according to any of (12) to (17) above, the width of bottom 8b of recess 8 in the direction parallel to main surface 10a is W1 (μm), and the fourth When the width of the impurity region 18 is W2 (μm), W2 (μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. By setting W2 ([mu] m) to be W1-0.2 ([mu] m) or more, a necessary minimum width for obtaining a desired contact resistance can be ensured. By setting W2 (μm) to W1 + 0.2 (μm) or less, excessive impurity erosion to the side wall is suppressed, and a contact height H necessary for a desired contact resistance between the electrode 16 and the third impurity region 14 is secured. be able to.
[Details of the embodiment of the present invention]
Hereinafter, specific examples of embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. As for the negative index, “−” (bar) is attached on the number in crystallography, but in this specification, a negative sign is attached before the number.

(Embodiment 1)
First, the configuration of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) as silicon carbide semiconductor device 1 according to the first embodiment of the present invention will be described.

  Referring to FIG. 1, the silicon carbide semiconductor device according to the present embodiment is a planar MOSFET, and includes silicon carbide substrate 10, gate electrode 27, gate oxide film 15, interlayer insulating film 21, It mainly has a source electrode 16, a surface protective electrode 19, a drain electrode 20, and a back surface protective electrode 23. Silicon carbide substrate 10 has a first main surface 10a and a second main surface 10b opposite to first main surface 10a, and includes silicon carbide single crystal substrate 11 and silicon carbide single crystal substrate 11. And the silicon carbide epitaxial layer 5 provided in the main part.

  Silicon carbide single crystal substrate 11 is made of, for example, a polytype 4H hexagonal silicon carbide single crystal. The maximum diameter of first main surface 10a of silicon carbide substrate 10 is, for example, larger than 100 mm, preferably 150 mm or more. First main surface 10a of silicon carbide substrate 10 is, for example, a surface that is off by 8 ° or less from a {0001} plane or a {0001} plane. Specifically, the first main surface 10a is, for example, a surface that is off by about 8 ° or less from the (0001) surface or the (0001) surface, and the second main surface 10b is a (000-1) surface or ( 000-1) is a surface that is off by about 8 ° or less from the surface. Silicon carbide substrate 10 has a thickness of, for example, 700 μm or less, and preferably 500 μm or less.

Silicon carbide epitaxial layer 5 has a drift region 12, a body region 13, a source region 14, and a contact region 18. The drift region 12 is an n-type (first conductivity type) region containing a donor impurity such as nitrogen. The concentration of the donor impurity in the drift region 12 is, for example, about 5.0 × 10 ¹⁵ cm ⁻³ . The body region 13 is a region having p-type (second conductivity type). The acceptor impurity contained in body region 13 is, for example, Al (aluminum) or B (boron). The concentration of the acceptor impurity contained in body region 13 is, for example, about 1 × 10 ¹⁷ cm ⁻³ .

Source region 14 includes a donor impurity such as phosphorus and has n-type. The source region 14 is formed so as to be surrounded by the body region 13. The concentration of the donor impurity in the source region 14 is higher than the concentration of the donor impurity in the drift region 12. The concentration of the donor impurity in the source region 14 is, for example, 1 × 10 ¹⁹ cm ⁻³ . Source region 14 is separated from drift region 12 by body region 13.

Contact region 18 contains an acceptor impurity such as aluminum and has p type (second conductivity type). A side portion of the contact region 18 is provided so as to be surrounded by the source region 14, and a bottom portion of the contact region 18 is in contact with the body region 13. The concentration of acceptor impurities contained in contact region 18 is higher than the concentration of acceptor impurities contained in body region 13. The concentration of impurities such as Al or B in contact region 18 is, for example, 1 × 10 ²⁰ cm ⁻³ . That is, the contact region 18 connects the bottom 8 b of the recess 8 and the body region 13 and has a higher impurity concentration than the body region 13. Preferably, the maximum concentration of acceptor impurities such as aluminum included in contact region 18 is not less than 1 × 10 ¹⁹ cm ^{−3 and not} more than 4 × 10 ²⁰ cm ⁻³ .

  Gate oxide film 15 is formed in contact with first main surface 10a of silicon carbide substrate 10 so as to extend from the upper surface of one source region 14 to the upper surface of the other source region 14. Gate oxide film 15 is in contact with source region 14, body region 13, and drift region 12 at first main surface 10 a of silicon carbide substrate 10. Gate oxide film 15 is made of, for example, silicon dioxide. The thickness of the gate oxide film 15 is, for example, about 40 nm to 60 nm.

  Gate electrode 27 is arranged in contact with gate oxide film 15 so as to extend from one source region 14 to the other source region 14. Gate electrode 27 is provided on gate oxide film 15 so as to sandwich gate oxide film 15 between silicon carbide substrate 10. Gate electrode 27 is formed above source region 14, body region 13, and drift region 12 with gate oxide film 15 interposed therebetween. The gate electrode 27 is made of a conductor such as polysilicon doped with impurities or Al.

  Interlayer insulating film 21 is provided at a position facing first main surface 10a of silicon carbide substrate 10. Specifically, the interlayer insulating film 21 is provided in contact with each of the gate electrode 27 and the gate oxide film 15 so as to cover the gate electrode 27. The interlayer insulating film 21 electrically insulates the gate electrode 27 and the source electrode 16 from each other. The surface protective electrode 19 is provided so as to cover the interlayer insulating film 21 and to be in contact with the source electrode 16. The surface protection electrode 19 is electrically connected to the source region 14 through the source electrode 16. The surface protection electrode 19 is made of, for example, a material containing Al.

  Drain electrode 20 is provided in contact with second main surface 10b of silicon carbide substrate 10. The drain electrode 20 is made of a material capable of ohmic contact with the silicon carbide single crystal substrate 11 such as NiSi (nickel silicide). Thereby, drain electrode 20 is electrically connected to silicon carbide single crystal substrate 11. Back surface protective electrode 23 is formed in contact with the main surface of drain electrode 20 opposite to silicon carbide single crystal substrate 11. The back surface protective electrode 23 is made of, for example, a material containing Al.

  With reference to FIG. 2, the structure near the bottom surface of the source electrode 16 will be described in detail. As shown in FIG. 2, the silicon carbide substrate 10 is provided with a recess 8 formed by a side portion 8a connected to the first main surface 10a and a bottom portion 8b connected to the side portion 8a. Preferably, height H of side portion 8a of recess 8 in a direction perpendicular to first main surface 10a of silicon carbide substrate 10 is not less than 0.1 μm and not more than 0.3 μm. The width W1 of the bottom 8b of the recess 8 in the direction parallel to the first main surface 10a is, for example, not less than 2 μm and not more than 3 μm. The source region 14 constitutes at least a part of the side portion 8 a of the recess 8.

  Source electrode 16 includes, for example, aluminum, and preferably includes TiAlSi. The source electrode 16 is in contact with the source region 14 at the side 8 a of the recess 8 and is in contact with the contact region 18 at the bottom 8 b of the recess 8. Source electrode 16 is in contact with source region 14 at side 8 a of recess 8 and is not in contact with source region 14 at first main surface 10 a of silicon carbide substrate 10. The source electrode 16 is in ohmic contact with the source region 14. Source region 14 is covered with gate oxide film 15 and buffer layer 17 on first main surface 10a. Preferably, the source electrode 16 is in ohmic contact with the source region 14 at the side 8 a of the recess 8. Preferably, the source electrode 16 is in ohmic contact with the contact region 18 at the bottom 8 b of the recess 8. When first main surface 10a of silicon carbide substrate 10 is a {0001} plane or a plane that is off from the {0001} plane by about 8 ° or less, recess 8 extends in a direction substantially perpendicular to first main surface 10a. The contact resistance of the source electrode 16 in contact with the source region 14 in the side portion 8a is lower than the contact resistance of the source electrode 16 in contact with the source region 14 in the first main surface 10a.

  Buffer layer 17 is in contact with source region 14 at first main surface 10a of silicon carbide substrate 10. The buffer layer 17 is disposed inside the opening 80 formed in the insulating film 22 constituted by the interlayer insulating film 21 and the gate oxide film 15. Buffer layer 17 is provided to extend along a direction perpendicular to first main surface 10a of silicon carbide substrate 10. The buffer layer 17 is in contact with each of the gate oxide film 15 and the interlayer insulating film 21 at the side of the insulating film 22 constituting the opening 80. The buffer layer 17 is made of a material that does not contain aluminum, for example. Preferably, the buffer layer 17 contains titanium and nitrogen. Preferably, the buffer layer 17 is TiN. The buffer layer 17 can prevent the aluminum contained in the source electrode 16 from penetrating the insulating film 22 and short-circuiting the source electrode 16 and the gate electrode 27.

  The source electrode 16 is provided so as to extend from the bottom 8 b of the recess 8 along the side 8 a of the recess 8 in a direction parallel to the side 8 a of the recess 8. The source electrode 16 is in contact with the side portion of the buffer layer 17 on the surface extending along the side portion 8 a of the recess 8 and extends to the upper surface of the buffer layer 17. The source electrode 16 is in contact with a part of the upper surface of the buffer layer 17 and is not in contact with the interlayer insulating film 21. In other words, the end portion of the source electrode 16 provided in contact with the upper surface of the buffer layer 17 in the direction parallel to the first main surface 10 a is recessed from the boundary surface between the interlayer insulating film 21 and the buffer layer 17. Located on the side. The buffer layer 17 is provided between the source electrode 16 and the interlayer insulating film 21, and is provided between the source electrode 16 and the gate oxide film 15.

  The surface protective electrode 19 is in contact with the source electrode 16 in the recess 8. The source electrode 16 is provided between the side 8 a of the recess 8 and the surface protection electrode 19, and is provided between the bottom 8 b of the recess 8 and the surface protection electrode 19. The surface protection electrode 19 is formed so as to fill the recess formed by the source electrode 16. The surface protective electrode 19 is in contact with the upper surface of the interlayer insulating film 21 and a part of the upper surface of the buffer layer 17.

With reference to FIG. 3, the impurity concentration distribution of the contact region 18 will be described. As shown in FIG. 3, the concentration of the acceptor impurity included in contact region 18 changes in a direction X (see FIG. 2) perpendicular to first main surface 10a. The impurity concentration of the contact region 18 has a maximum value a1 at the first position x1. The maximum value a1 of the acceptor impurity concentration such as aluminum contained in the contact region 18 is, for example, 1 × 10 ²⁰ cm ⁻³ . The impurity concentration a2 is one-tenth the impurity concentration of the maximum value a1. The impurity concentration a2 is, for example, 1 × 10 ¹⁹ cm ⁻³ . In the direction X perpendicular to the first major surface 10a, the position having the impurity concentration a2 is the second position x2. In the direction X perpendicular to the first main surface 10a, the distance from the first position x1 to the second position x2 is preferably less than 0.1 μm. The second position x2 is located closer to the second main surface 10b than the first position x1. In other words, the first position x1 indicating the maximum value a1 of the impurity concentration of the contact region 18 in the direction X perpendicular to the first main surface 10a of the silicon carbide substrate 10 and 1/10 of the maximum value a1. The distance from the second position x2 having the impurity concentration a2 is preferably less than 0.1 μm. That is, the concentration of acceptor impurities such as aluminum included in the contact region 18 changes sharply along the direction X.

With reference to FIG. 4, the structure of a modification of the MOSFET according to the first embodiment will be described.
As shown in FIG. 4, the width W2 of the contact region 18 in the direction parallel to the first main surface 10a may be smaller than the width W1 of the bottom 8b of the recess 8. In this case, the source region 14 constitutes a part of the bottom 8 b of the recess 8. That is, the source electrode 16 is in contact with each of the source region 14 and the contact region 18 at the bottom 8 b of the recess 8, and is in contact with the source region 14 at the side 8 a of the recess 8. The width W2 of the bottom 8b of the contact region 18 may be larger than the width W1 of the bottom 8b of the recess 8. Preferably, when the width of the bottom 8b of the recess 8 in the direction parallel to the first main surface 10a of the silicon carbide substrate 10 is W1 (μm) and the width of the contact region 18 is W2 (μm), W2 ( μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. When the width W2 of the contact region 18 is larger than the width W1 of the bottom 8b of the recess 8, the contact region 18 may be in contact with a part of the side 8a of the recess 8.

  Next, the operation of MOSFET 1 according to the present embodiment will be described. Referring to FIG. 1, in the state where the voltage applied to gate electrode 27 is less than the threshold voltage, that is, in the off state, even if a voltage is applied between source electrode 16 and drain electrode 20, body region 13 and drift The pn junction formed with the region 12 is reverse-biased and becomes non-conductive. On the other hand, when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, an inversion layer is formed in the channel region CH in the vicinity of the body region 13 in contact with the gate oxide film 15. As a result, the source region 14 and the drift region 12 are electrically connected, and a current flows between the source electrode 16 and the drain electrode 20. As described above, the MOSFET 1 operates.

  Next, a method for manufacturing MOSFET 1 as the silicon carbide semiconductor device according to the present embodiment will be described.

First, a silicon carbide substrate preparation step (S10: FIG. 5) is performed. For example, silicon carbide single crystal substrate 11 is prepared by slicing an ingot made of a hexagonal silicon carbide single crystal having polytype 4H formed by a sublimation method. Next, silicon carbide epitaxial layer 5 is formed on silicon carbide single crystal substrate 11 by, for example, a CVD (Chemical Vapor Deposition) method. Specifically, a carrier gas containing hydrogen (H ₂ ) and a source gas containing monosilane (SiH ₄ ), propane (C ₃ H ₈ ), nitrogen (N ₂ ), and the like on the silicon carbide single crystal substrate 11 Is supplied, and silicon carbide single crystal substrate 11 is heated to, for example, about 1500 ° C. to 1700 ° C. Thereby, as shown in FIG. 6, silicon carbide epitaxial layer 5 is formed on silicon carbide single crystal substrate 11. As described above, silicon carbide substrate 10 having first main surface 10a and second main surface 10b opposite to first main surface 10a is prepared. Silicon carbide substrate 10 includes silicon carbide single crystal substrate 11 forming second main surface 10b, and silicon carbide epitaxial layer 5 provided on silicon carbide single crystal substrate 11 and forming first main surface 10a. Included (see FIG. 6).

  Next, an ion implantation step (S20: FIG. 5) is performed. Specifically, referring to FIG. 7, ion implantation is performed on first main surface 10 a of silicon carbide substrate 10. For example, Al (aluminum) ions are implanted into first main surface 10 a of silicon carbide substrate 10, whereby body region 13 is formed in silicon carbide epitaxial layer 5. Body region 13 is a p-type region containing an acceptor impurity such as aluminum. Next, for example, P (phosphorus) ions are implanted into the body region 13 to a depth shallower than the implantation depth of the Al ions, whereby the source region 14 is formed. Source region 14 is an n-type region containing a donor impurity such as phosphorus. In silicon carbide epitaxial layer 5, a region where neither body region 13 nor source region 14 is formed is drift region 12. Drift region 12 is an n-type region containing a donor impurity such as nitrogen. Source region 14 is formed to be separated from drift region 12 by body region 13.

  Next, an activation annealing step (S30: FIG. 5) is performed. Specifically, silicon carbide substrate 10 including body region 13 and source region 14 is heated for about 30 minutes at a temperature of 1600 ° C. or higher and 2000 ° C. or lower, for example. Thereby, the impurity introduced by ion implantation is activated. As described above, the drift region 12 having n-type, the body region 13 in contact with the drift region 12 and having a p-type different from the n-type, and the n-type and separated from the drift region 12 by the body region 13 Silicon carbide substrate 10 including source region 14 is prepared. At this time, the contact region 18 may or may not be formed.

  Next, a gate oxide film formation step (S40: FIG. 5) is performed. Specifically, silicon carbide substrate 10 having body region 13 and source region 14 formed on first main surface 10a side of silicon carbide substrate 10 is placed in a heating furnace. For example, the temperature of silicon carbide substrate 10 is heated from room temperature to 1300 ° C. while maintaining the state where nitrogen gas is introduced into the heating furnace. After silicon carbide substrate 10 reaches 1300 ° C., oxygen gas is introduced into the heating furnace. By holding silicon carbide substrate 10 at a temperature of about 1300 ° C. for about 1 hour in an oxygen atmosphere, gate oxide film 15 is formed on first main surface 10a of silicon carbide substrate 10. As described above, gate oxide film 15 made of silicon dioxide is formed so as to cover first main surface 10a of silicon carbide substrate 10 (see FIG. 8). Gate oxide film 15 is formed in contact with drift region 12, body region 13, and source region 14 on first main surface 10 a of silicon carbide substrate 10. The thickness of the gate oxide film 15 is, for example, about 50 nm.

  Next, a NO annealing step (S50: FIG. 5) is performed. Specifically, silicon carbide substrate 10 on which gate oxide film 15 is formed is heat-treated at a temperature of about 1300 ° C. in an atmosphere containing nitrogen. Examples of the gas containing nitrogen include nitrogen monoxide (NO), dinitrogen monoxide, nitrogen dioxide, and ammonia. Preferably, silicon carbide substrate 10 on which gate oxide film 15 is formed is held in a gas containing nitrogen at a temperature of 1300 ° C. or higher and 1500 ° C. or lower for about 1 hour, for example.

  Next, an Ar annealing step (S60: FIG. 5) is performed. Specifically, silicon carbide substrate 10 on which gate oxide film 15 is formed is heat-treated at a temperature of about 1300 ° C. in an inert gas atmosphere such as argon. Preferably, silicon carbide substrate 10 on which gate oxide film 15 is formed is held in argon gas at a temperature of 1100 ° C. or higher and 1500 ° C. or lower for about 1 hour, for example. More preferably, silicon carbide substrate 10 on which gate oxide film 15 is formed is maintained at a temperature of 1300 ° C. or higher and 1500 ° C. or lower.

  Next, a gate electrode formation step (S70: FIG. 5) is performed. For example, a gate electrode 27 made of polysilicon containing impurities is formed on the gate oxide film 15 by LPCVD (Low Pressure Chemical Vapor Deposition), for example. Gate electrode 27 is formed to face drift region 12, source region 14 and body region 13 with gate oxide film 15 interposed therebetween (see FIG. 9).

  Next, an interlayer insulating film forming step (S80: FIG. 5) is performed. For example, interlayer insulating film 21 made of silicon dioxide is formed to cover gate oxide film 15 and gate electrode 27. Specifically, for example, TEOS (Tetraethylorthosilicate) gas is supplied onto silicon carbide substrate 10 at a temperature of about 650 ° C. to 750 ° C. for about 6 hours. Thereby, interlayer insulating film 21 is formed so as to cover gate electrode 27 with gate oxide film 15 and interlayer insulating film 21. The gate oxide film 15 and the interlayer insulating film 21 constitute an insulating film 22 (see FIG. 10).

Next, an etching step (S85: FIG. 5) is performed. Referring to FIG. 11, the region of insulating film 22 formed of interlayer insulating film 21 and gate oxide film 15 on the region where source electrode 16 is to be formed is removed. Thereby, an opening 80 exposing at least a part of the source region 14 is formed. In other words, the insulating film 22 is etched so that the source region 14 is exposed from the insulating film 22 composed of the interlayer insulating film 21 and the gate oxide film 15. When etching the insulating film 22 made of silicon dioxide, CF ₄ can be used as an etching gas. As described above, insulating film 22 having opening 80 where source region 14 is exposed at first main surface 10a of silicon carbide substrate 10 is formed.

  Next, a buffer layer forming step (S90: FIG. 5) is performed. Referring to FIG. 12, buffer layer 17 is in contact with source region 14 on first main surface 10 a of silicon carbide substrate 10, in contact with the side of insulating film 22 in opening 80, and outside opening 80. It is formed in contact with the upper surface of the insulating film 22. Specifically, buffer layer 17 is formed in contact with interlayer insulating film 21 and gate oxide film 15 in opening 80. As described above, the buffer layer 17 is formed in contact with the source region 14 on the first main surface 10 a and in contact with the insulating film 22 in the opening 80. The buffer layer 17 is made of a material not containing aluminum, and preferably made of a material containing titanium and nitrogen. The buffer layer 17 may be made of a material containing, for example, TiN, TaN, TiW, WN, or the like.

Next, a recess forming step (S100: FIG. 5) is performed. Referring to FIG. 13, for example, anisotropic etching is performed in the direction of the arrow from the first main surface 10 a side of silicon carbide substrate 10. Specifically, the first portion of silicon carbide substrate 10 is removed by removing a portion of buffer layer 17 on source region 14 and a portion of source region 14 in an atmosphere containing at least one of aluminum and boron. A concave portion 8 formed by a side portion 8a connected to the main surface 10a and a bottom portion 8b connected to the side portion is formed. By the anisotropic etching, the buffer layer 17 on the upper surface of the interlayer insulating film 21 and the buffer layer 17 on the first main surface 10a are removed, and the buffer layer 17 on the side of the interlayer insulating film 21 is left. For example, by processing a silicon carbide substrate using a gas containing BCl ₃ and Cl ₂ , a part of source region 14 is etched, and side portion 8a connected to first main surface 10a of silicon carbide substrate 10 A concave portion 8 formed by the bottom portion 8b connected to the side portion is formed.

In the recess forming step, silicon carbide substrate 10 is processed using an aluminum-based gas containing aluminum or a boron-based gas containing boron. Examples of the aluminum-based gas containing aluminum include AlCl ₃ , AlF ₃ , AlBr _3, and AlI ₃ . Examples of the boron-based gas containing boron include BCl ₃ , BF ₃ , BBr _3, and BI ₃ . The silicon carbide substrate 10 is processed in an atmosphere in which aluminum radicals or boron radicals are present. Thereby, acceptor impurities such as aluminum or boron are introduced into the source region 14. As a result, a contact region 18 having a p-type, connecting bottom 8b of recess 8 and body region 13 and having a higher impurity concentration than body region 13 is formed. Preferably, the contact region 18 is performed using plasma. Specifically, plasma etching is performed on source region 14 of silicon carbide substrate 10 using a gas containing BCl ₃ and Cl ₂ to form recess 8 in first main surface 10a of silicon carbide substrate 10. The Next, after the supply of the Cl ₂ gas is stopped, the silicon carbide substrate 10 with the recesses 8 formed using a gas containing BCl ₃ is processed in plasma. Plasma treatment is performed on the source region 14 of the silicon carbide substrate 10 using BCl ₃ without supplying Cl ₂ gas, so that high-concentration boron is introduced into the source region 14 and the bottom of the recess 8 A contact region 18 in contact with 8b is formed. That is, the contact region 18 is formed by processing the silicon carbide substrate 10 using a gas containing BCl ₃ . In the step of forming the recess 8, the recess 8 is formed by plasma etching in at least a part of the step of etching the buffer layer 17 and the source region 14, and at the same time, the contact region 18 is selectively formed with respect to the bottom 8b of the recess 8. While forming, the source region 14 may be exposed to the side 8 a of the recess 8.

  Alternatively, after aluminum is formed on the interlayer insulating film 21 or a resist layer (not shown) formed on the interlayer insulating film 21, the source region 14 is plasma-etched with the aluminum exposed. The contact region 18 that connects the bottom 8 b of the recess 8 and the body region 13 may be formed by introducing aluminum into the bottom 8 b of the recess 8 while the recess 8 is formed in the source region 14.

Preferably, the maximum concentration of impurities such as boron included in the contact region 18 is 1 × 10 ¹⁹ cm ⁻³ or more and 4 × 10 ²⁰ cm ⁻³ or less. Referring to FIG. 3, after the step of forming contact region 18, the first impurity concentration maximum value a1 in contact region 18 in the direction perpendicular to first main surface 10a of silicon carbide substrate 10 is shown. The distance between the position x1 and the second position x2 having the impurity concentration a2 that is 1/10 of the maximum value a1 of the impurity concentration is less than 0.1 μm. Preferably, after the step of forming the recess, the height H of the side portion 8a of the recess 8 in the direction perpendicular to the first main surface 10a of the silicon carbide substrate 10 is not less than 0.1 μm and not more than 0.3 μm. is there. Referring to FIG. 4, preferably, after the step of forming the recess, the width of bottom portion 8b of recess 8 in the direction parallel to first main surface 10a of silicon carbide substrate 10 is W1 (μm), and the contact is made. When the width of the region 18 is W2 (μm), W2 (μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. That is, the contact region 18 may be formed such that the width W2 of the contact region 18 is smaller than the width W1 of the bottom 8b of the recess 8, and the width W2 of the contact region 18 is smaller than the width W1 of the bottom 8b of the recess 8. The contact region 18 may be formed so as to be larger.

  Next, a source electrode forming step (S110: FIG. 5) is performed. Referring to FIG. 14, source electrode 16 is formed which contacts source region 14 at side 8a of recess 8 and does not contact source region 14 at first main surface 10a. Source electrode 16 is formed in contact with contact region 18 at bottom 8 b of recess 8. The source electrode 16 is made of a material containing aluminum, and preferably made of a material containing TiAlSi. The source electrode 16 is formed by, for example, a sputtering method. The source electrode 16 is formed so as to extend from the bottom 8 b of the recess 8 along the side 8 a of the recess 8 in a direction parallel to the side 8 a of the recess 8. The source electrode 16 is formed to be in contact with the side portion of the buffer layer 17 on the surface extending along the side portion 8 a of the recess 8, and to be in contact with the upper surface of the buffer layer 17 and the upper surface of the interlayer insulating film 21. .

  Next, the source electrode 16 on the upper surface of the interlayer insulating film 21 is removed. For example, by performing dry etching from the first main surface 10a side of silicon carbide substrate 10 using a mask (not shown), source electrode 16 is formed from a part of the upper surface of interlayer insulating film 21 and the upper surface of buffer layer 17. Removed. The source electrode 16 is formed in contact with a part of the upper surface of the buffer layer 17 and not in contact with the upper surface of the interlayer insulating film 21. In other words, the end portion of the source electrode 16 provided in contact with the upper surface of the buffer layer 17 in the direction parallel to the first main surface 10 a is recessed more than the boundary surface between the interlayer insulating film 21 and the buffer layer 17. The source electrode 16 is formed so as to be positioned on the 8 side (see FIG. 2).

  Next, an alloying annealing step (S120: FIG. 5) is performed. Specifically, silicon carbide substrate 10 formed so that source electrode 16 is in contact with source region 14 at side 8a of recess 8 and is in contact with contact region 18 at bottom 8b of recess 8 is annealed. Specifically, heat treatment of, for example, 900 ° C. or higher and 1100 ° C. or lower is performed on silicon carbide substrate 10 for about 5 minutes. Thereby, at least a part of source electrode 16 reacts with silicon contained in the silicon carbide substrate to be silicided to form an alloyed layer. As a result, the source electrode 16 including the alloyed layer that is in ohmic contact with the source region 14 is formed. Preferably, the source electrode 16 is in ohmic contact with the source region 14 at the side 8 a of the recess 8 and is in ohmic contact with the contact region 18 at the bottom 8 b of the recess 8. In the alloying annealing step, impurities contained in the contact region 18 are activated.

  Next, the surface protection electrode 19 is formed so as to contact the source electrode 16 and cover the interlayer insulating film 21. The surface protective electrode 19 is preferably made of a material containing Al, for example, AlSiCu. After the surface protective electrode 19 is formed, a lamp annealing process may be performed. In the lamp annealing step, silicon carbide substrate 10 provided with surface protective electrode 19 is heated, for example, for about 30 seconds at a temperature of 700 ° C. or higher and 800 ° C. or lower.

  Next, drain electrode 20 made of, for example, NiSi is formed in contact with second main surface 10b of silicon carbide substrate 10. The drain electrode 20 may be TiAlSi, for example. The formation of the drain electrode 20 is preferably performed by a sputtering method, but may be performed by vapor deposition. After the drain electrode 20 is formed, the drain electrode 20 is heated by, for example, laser annealing. As a result, at least a part of the drain electrode 20 is silicided, and the drain electrode 20 that is in ohmic contact with the silicon carbide single crystal substrate 11 is formed. Next, the back surface protective electrode 23 is formed in contact with the drain electrode 20. The back surface protective electrode 23 is made of, for example, a material containing Al. As described above, MOSFET 1 shown in FIG. 1 is manufactured.

  Next, the effect of MOSFET 1 as a silicon carbide semiconductor device according to the present embodiment and the method for manufacturing the same will be described.

  According to the method for manufacturing MOSFET 1 according to the first embodiment, source electrode 16 is formed that contacts source region 14 at side 8a of recess 8 and does not contact source region 14 at first main surface 10a. In order to reduce the contact resistance between the source electrode 16 and the source region 14, the contact area between the source electrode 16 and the source region 14 needs to be increased to some extent. In the case where the source electrode 16 is in contact with the source region 14 on the first main surface 10a, the degree of integration of the semiconductor element is lowered when the contact area between the source electrode 16 and the source region 14 is increased. Therefore, by providing the source electrode 16 so as to be in contact with the source region 14 at the side 8a of the recess 8 and not to be in contact with the source region 14 at the first main surface 10a, without reducing the integration degree of the semiconductor element, The contact area between the source electrode 16 and the source region 14 can be increased. As a result, the contact resistance between the source region 14 and the source electrode 16 of the silicon carbide substrate 10 can be reduced while increasing the degree of integration of the semiconductor elements.

  In addition, according to the method for manufacturing MOSFET 1 according to the first embodiment, the portion of buffer layer 17 on source region 14 and part of source region 14 are removed in an atmosphere containing at least one of aluminum and boron. Thereby, the recessed part 8 formed of the side part 8a connected with the 1st main surface 10a and the bottom part 8b connected with the side part 8a is formed. The step of forming the recess 8 includes a step of forming a contact region 18 having a p-type, connecting the bottom 8b of the recess 8 and the body region 13 and having an impurity concentration higher than that of the body region 13. Thereby, the impurity concentration in the portion of the contact region 18 in direct contact with the source electrode 16 can be increased. Therefore, the contact resistance between the contact region 18 and the source electrode 16 can be effectively reduced.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming contact region 18 is performed using plasma. Thereby, since aluminum or boron can be effectively introduced into the bottom 8b of the recess 8, the contact region 18 having a high impurity concentration can be formed. As a result, the contact resistance between the source electrode 16 and the contact region 18 can be reduced.

  Furthermore, the method for manufacturing MOSFET 1 according to the first embodiment further includes an annealing step of alloying source electrode 16. Thereby, alloying of the source electrode 16 and activation of impurities contained in the contact region 18 can be performed simultaneously.

Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming recess 8 includes the step of processing silicon carbide substrate 10 using a gas containing BCl ₃ and Cl ₂ . Thereby, recess 8 can be formed by effectively etching first main surface 10a of silicon carbide substrate 10.

Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, the step of forming recess 8 includes a step of treating silicon carbide substrate 10 using a gas containing BCl ₃ and Cl ₂ and a gas containing BCl _3. The process of processing the silicon carbide substrate 10 using is included. In the step of processing silicon carbide substrate 10 using a gas containing BCl ₃ , fourth impurity region 18 is formed. Recess 8 is formed by processing silicon carbide substrate 10 using a gas containing BCl ₃ and Cl ₂ , and then silicon carbide substrate 10 is processed using a gas containing BCl ₃ , thereby forming bottom 8b of recess 8. Boron can be introduced. As a result, the boron concentration in the portion of the contact region 18 in contact with the bottom 8b of the recess 8 can be increased, so that the contact resistance between the contact region 18 and the electrode 16 can be effectively reduced.

Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, after the step of forming contact region 18, the maximum value of the impurity concentration of contact region 18 is 1 × 10 ¹⁹ cm ⁻³ or more and 4 × 10 ²⁰ cm ^{−. 3} or less. By setting the maximum impurity concentration of the contact region 18 to 1 × 10 ¹⁹ cm ⁻³ or more, the contact resistance between the contact region 18 and the electrode 16 can be effectively reduced. Further, the switching speed of the MOSFET 1 can be improved. By setting the maximum value of the impurity concentration of the contact region 18 to 4 × 10 ²⁰ cm ⁻³ or less, it is possible to suppress the deterioration of the crystallinity of the upper surface of the contact region 18.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, after the step of forming contact region 18, the maximum value a1 of the impurity concentration in contact region 18 in the direction perpendicular to first main surface 10a is obtained. The distance between the position x1 shown and the position x2 having the impurity concentration a2 that is 1/10 of the maximum value a1 is less than 0.1 μm. Thereby, the series resistance of the contact region 18 itself can be reduced until the source electrode 16 and the body region 13 are connected, and the switching speed can be improved.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, source electrode 16 includes TiAlSi. Thereby, both the contact resistance between the source region 14 having the first conductivity type and the source electrode 16 and the contact resistance between the contact region 18 having the second conductivity type and the source electrode 16 are reduced. Can do.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, buffer layer 17 includes TiN. Thereby, the adhesiveness of the buffer layer 17 and the insulating film 22 can be improved.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, after the step of forming recess 8, height H of side 8a of recess 8 in the direction perpendicular to first main surface 10a is 0. .1 μm or more and 0.3 μm or less. By setting the height H of the side portion 8a of the recess 8 to 0.1 μm or more, the contact area between the electrode 16 and the source region 14 can be increased. As a result, the contact resistance between the electrode 16 and the source region 14 can be reduced. By setting the height H of the side portion 8a of the recess 8 to 0.3 μm or less, the recess 8 can be prevented from penetrating the source region 14.

  Furthermore, according to the method for manufacturing MOSFET 1 according to the first embodiment, after the step of forming recess 8, the width of bottom 8b of recess 8 in the direction parallel to first main surface 10a is set to W1 (μm), When the width of the contact region 18 is W2 (μm), W2 (μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. By setting W2 ([mu] m) to be W1-0.2 ([mu] m) or more, a necessary minimum width for obtaining a desired contact resistance can be ensured. By setting W2 (μm) to W1 + 0.2 (μm) or less, excessive impurity erosion to the side wall is suppressed, and a contact height H necessary for a desired contact resistance between the source electrode 16 and the source region 14 is secured. Can do.

  According to MOSFET 1 described in the first embodiment, source electrode 16 is in contact with source region 14 at side 8a of recess 8 and is not in contact with source region 14 at first main surface 10a. In order to reduce the contact resistance between the source electrode 16 and the source region 14, the contact area between the source electrode 16 and the source region 14 needs to be increased to some extent. In the case where the source electrode 16 is in contact with the source region 14 on the first main surface 10a, the degree of integration of the semiconductor element is lowered when the contact area between the source electrode 16 and the source region 14 is increased. Therefore, by providing the source electrode 16 so as to be in contact with the source region 14 at the side 8a of the recess 8 and not to be in contact with the source region 14 at the first main surface 10a, without reducing the integration degree of the semiconductor element, The contact area between the electrode 16 and the source region 14 can be increased. As a result, the contact resistance between the source region 14 and the source electrode 16 of the silicon carbide substrate 10 can be reduced while increasing the degree of integration of the semiconductor elements.

Further, according to MOSFET 1 described in the first embodiment, the maximum value of the impurity concentration of contact region 18 is not less than 1 × 10 ¹⁹ cm ^{−3 and not} more than 4 × 10 ²⁰ cm ⁻³ . By setting the maximum impurity concentration of the contact region 18 to 1 × 10 ¹⁹ cm ⁻³ or more, the contact resistance between the contact region 18 and the source electrode 16 can be effectively reduced. Further, the switching speed of the MOSFET 1 can be improved. By setting the maximum value of the impurity concentration of the contact region 18 to 4 × 10 ²⁰ cm ⁻³ or less, it is possible to suppress deterioration of the crystallinity of the upper surface of the contact region 18.

  Furthermore, according to MOSFET 1 described in the first embodiment, position x1 indicating the maximum value a1 of the impurity concentration of contact region 18 in the direction perpendicular to first main surface 10a and one-tenth of the maximum value. The distance from the position x2 having the impurity concentration a2 is less than 0.1 μm. Thereby, the series resistance of the contact region 18 itself can be reduced until the source electrode 16 and the body region 13 are connected, and the switching speed can be improved.

  Furthermore, according to MOSFET 1 described in the first embodiment, source electrode 16 includes TiAlSi. This can reduce both the contact resistance between the source region 14 having the first conductivity type and the source electrode 16 and the contact resistance between the contact region 18 having the second conductivity type and the electrode 16. it can.

  Furthermore, according to MOSFET 1 described in the first embodiment, buffer layer 17 includes TiN. Thereby, the adhesiveness of the buffer layer 17 and the insulating film 22 can be improved.

  Furthermore, according to MOSFET 1 described in the first embodiment, the height H of the side portion 8a of the recess 8 in the direction perpendicular to the first main surface 10a is not less than 0.1 μm and not more than 0.3 μm. By setting the height H of the side portion 8a of the recess 8 to 0.1 μm or more, the contact area between the electrode 16 and the source region 14 can be increased. As a result, the contact resistance between the electrode 16 and the source region 14 can be reduced. By setting the height H of the side portion 8a of the recess 8 to 0.3 μm or less, the recess 8 can be prevented from penetrating the source region 14.

  Furthermore, according to MOSFET 1 described in the first embodiment, the width of bottom 8b of recess 8 in the direction parallel to first main surface 10a is W1 (μm), and the width of contact region 18 is W2 (μm). In this case, W2 (μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. By setting W2 ([mu] m) to be W1-0.2 ([mu] m) or more, a necessary minimum width for obtaining a desired contact resistance can be ensured. By setting W2 (μm) to W1 + 0.2 (μm) or less, excessive impurity erosion to the side wall is suppressed, and a contact height H necessary for a desired contact resistance between the source electrode 16 and the source region 14 is secured. Can do.

(Embodiment 2)
Next, the structure of the silicon carbide semiconductor device according to the second embodiment of the present invention will be described. The MOSFET according to the second embodiment is different from the MOSFET according to the first embodiment in that a trench is formed in the first main surface 10a of the silicon carbide substrate 10, and other configurations are the same as those in the first embodiment. This is almost the same as the MOSFET. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated. Hereinafter, the structure of the MOSFET according to the second embodiment will be described focusing on the different points.

  Referring to FIG. 15, trench TR is provided in first main surface 10 a of silicon carbide substrate 10. Trench TR has a side wall part SW connected to first main surface 10a and a bottom part BT connected to side wall part SW. Sidewall SW passes through source region 14 and body region 13 and reaches drift region 12. The portion of the body region 13 that faces the side wall portion SW becomes the channel region CH. Sidewall portion SW of trench TR is inclined with respect to first main surface 10a of silicon carbide substrate 10. Trench TR is provided such that side wall portion SW expands in a tapered shape toward the opening. Gate oxide film 15 is in contact with each of source region 14, body region 13, and drift region 12 at sidewall SW of trench TR, and is in contact with drift region 12 at bottom BT of trench TR. A part of gate oxide film 15 is in contact with source region 14 on first main surface 10a of silicon carbide substrate 10. The gate electrode 27 is provided on and in contact with the gate oxide film 15. Gate electrode 27 is provided in contact with each of sidewall portion SW and bottom portion BT of trench TR through gate oxide film 15. The interlayer insulating film 21 is formed in contact with the gate electrode 27 so as to fill the groove formed by the gate electrode 27.

  First main surface 10a of silicon carbide substrate 10 is, for example, a (000-1) plane or a plane that is off from the (000-1) plane by about 8 ° or less, and second main surface 10b is a (0001) plane. Alternatively, the surface is off by about 8 ° or less from the (0001) plane. The surface on which the side wall SW is formed is preferably inclined at 50 ° or more and 70 ° or less with respect to the (000-1) plane.

  Referring to FIG. 15, silicon carbide substrate 10 is provided with a recess 8 formed by a side portion 8a connected to first main surface 10a and a bottom portion 8b connected to side portion 8a. Preferably, height H of side portion 8a of recess 8 in a direction perpendicular to first main surface 10a of silicon carbide substrate 10 is not less than 0.1 μm and not more than 0.3 μm. The width W1 of the bottom 8b of the recess 8 in the direction parallel to the first main surface 10a is, for example, not less than 2 μm and not more than 3 μm. Source region 14 constitutes at least a part of side 8a of recess 8 and constitutes a part of side wall SW of trench TR. Side 8a of recess 8 is configured to face side wall SW of trench TR. A plane extending along the bottom 8b of the recess 8 is configured to intersect the side wall SW of the trench TR. That is, the height H of the side portion 8a of the recess 8 in the direction perpendicular to the first main surface 10a is smaller than the height of the side wall portion SW of the trench TR.

  The source electrode 16 is in contact with the source region 14 at the side 8 a of the recess 8 and is in contact with the contact region 18 at the bottom 8 b of the recess 8. Source electrode 16 does not contact source region 14 at first main surface 10a of silicon carbide substrate 10. The source region 14 is provided so as to be sandwiched between the sidewall portion SW of the trench TR and the side portion 8 a of the recess 8, and is disposed so as to be sandwiched between the sidewall portion SW of the trench TR and the contact region 18. .

  In each of the embodiments described above, the first conductivity type is n-type and the second conductivity type is p-type. However, the first conductivity type is p-type and the second conductivity type is n-type. Also good. In the above description, a MOSFET has been described as an example of a silicon carbide semiconductor device. However, the silicon carbide semiconductor device may be an IGBT (Insulated Gate Bipolar Transistor) or the like. When the silicon carbide semiconductor device is an IGBT, electrode 16 serves as an emitter electrode.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 Silicon carbide semiconductor device (MOSFET)
5 Silicon carbide epitaxial layer 8 Recess 8a Side 8b, BT Bottom 10 Silicon carbide substrate 10a Main surface (first main surface)
10b Second main surface 11 Silicon carbide single crystal substrate 12 Drift region (first impurity region)
13 Body region (second impurity region)
14 Source region (third impurity region)
15 Gate oxide film 16 Electrode (source electrode)
17 Buffer layer 18 Contact region (fourth impurity region)
19 Surface protective electrode 20 Drain electrode 21 Interlayer insulating film 22 Insulating film 23 Back surface protective electrode 27 Gate electrode 80 Opening portion CH Channel region SW Side wall portion TR Trench W1, W2 Width X direction a1 Maximum value a2 Impurity concentration x1 First position x2 First 2 position

Claims (18)

Comprising a step of forming a silicon carbide substrate having a main surface,
The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and the first impurity region A third impurity region having a conductivity type and separated from the first impurity region by the second impurity region, and
Forming an insulating film having an opening in which the third impurity region is exposed in the main surface of the silicon carbide substrate;
Forming a buffer layer in contact with the third impurity region on the main surface and in contact with the insulating film in the opening;
In an atmosphere containing at least one of aluminum and boron, a side portion connected to the main surface is removed by removing a portion of the buffer layer on the third impurity region and a portion of the third impurity region. And forming a recess formed by a bottom portion connected to the side portion,
The step of forming the recess includes a fourth impurity region having the second conductivity type, connecting the bottom portion of the recess and the second impurity region, and having an impurity concentration higher than that of the second impurity region. Forming, and further comprising:
Forming an electrode containing aluminum, in contact with the fourth impurity region at the bottom of the recess, in contact with the third impurity region at the side of the recess, and not in contact with the third impurity region at the main surface; A method for manufacturing a silicon carbide semiconductor device, comprising: a step.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the step of forming the fourth impurity region is performed using plasma.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising an annealing step of alloying the electrode. The step of forming the recess comprises the step of treating the silicon carbide substrate using a gas containing BCl ₃ and Cl _2, the silicon carbide semiconductor device according to any one of claims 1 to 3 Production method. The step of forming the recess includes a step of processing the silicon carbide substrate using a gas containing BCl ₃ after the step of processing the silicon carbide substrate using a gas containing BCl ₃ and Cl ₂ .
The method of manufacturing a silicon carbide semiconductor device according to claim 4, wherein the fourth impurity region is formed in the step of processing the silicon carbide substrate using the gas containing BCl ₃ . The maximum value of the impurity concentration of the fourth impurity region is 1 × 10 ¹⁹ cm ⁻³ or more and 4 × 10 ²⁰ cm ⁻³ or less after the step of forming the fourth impurity region. 6. A method for manufacturing a silicon carbide semiconductor device according to claim 5.   After the step of forming the fourth impurity region, a position indicating the maximum value of the impurity concentration of the fourth impurity region in a direction perpendicular to the main surface, and an impurity concentration of 1/10 of the maximum value The method for manufacturing a silicon carbide semiconductor device according to any one of claims 1 to 6, wherein a distance from the position having a thickness of less than 0.1 µm.   The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the electrode includes TiAlSi.   The said buffer layer is a manufacturing method of the silicon carbide semiconductor device of any one of Claims 1-8 containing TiN.   The height of the said side part of the said recessed part in the direction perpendicular | vertical with respect to the said main surface after the process of forming the said recessed part is 0.1 micrometer or more and 0.3 micrometer or less, Any of Claims 1-9 A method for manufacturing a silicon carbide semiconductor device according to claim 1.   After the step of forming the recess, when the width of the bottom of the recess in the direction parallel to the main surface is W1 (μm) and the width of the fourth impurity region is W2 (μm), W2 ( The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein μm) is W1−0.2 (μm) or more and W1 + 0.2 (μm) or less. A silicon carbide substrate provided with a recess formed by a side portion connected to the main surface and a bottom portion connected to the side portion,
The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region in contact with the first impurity region and having a second conductivity type different from the first conductivity type, and the first impurity region A third impurity region having a conductivity type and separated from the first impurity region by the second impurity region, and having the second conductivity type, and connecting the bottom portion of the recess and the second impurity region. And a fourth impurity region having an impurity concentration higher than that of the second impurity region, and
A buffer layer in contact with the third impurity region on the main surface;
An electrode in contact with the fourth impurity region at the bottom of the recess and containing aluminum;
The silicon carbide semiconductor device, wherein the electrode is in contact with the third impurity region at the side portion of the recess and is not in contact with the third impurity region at the main surface. The silicon carbide semiconductor device according to claim 12, wherein the maximum value of the impurity concentration of the fourth impurity region is not less than 1 × 10 ¹⁹ cm ^{−3 and not} more than 4 × 10 ²⁰ cm ⁻³ .   The distance between the position showing the maximum value of the impurity concentration of the fourth impurity region and the position having an impurity concentration of 1/10 of the maximum value in a direction perpendicular to the main surface is less than 0.1 μm The silicon carbide semiconductor device according to claim 12 or 13, wherein   The silicon carbide semiconductor device according to any one of claims 12 to 14, wherein the electrode includes TiAlSi.   The silicon carbide semiconductor device according to any one of claims 12 to 15, wherein the buffer layer includes TiN.   The height of the said side part of the said recessed part in the direction perpendicular | vertical with respect to the said main surface is a silicon carbide semiconductor of any one of Claims 12-16 which is 0.1 micrometer or more and 0.3 micrometer or less. apparatus.   When the width of the bottom of the recess in the direction parallel to the main surface is W1 (μm) and the width of the fourth impurity region is W2 (μm), W2 (μm) is W1-0.2. 18. The silicon carbide semiconductor device according to claim 12, wherein the silicon carbide semiconductor device is not less than (μm) and not more than W1 + 0.2 (μm).

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