JP2015171020A - Receiving device and receiving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiving device capable of seamlessly switching an IP stream including a plurality of encoded streams of different encoding system and formats.SOLUTION: A receiving device includes a decoding part 2, an interpolation part 3 and a synchronizing part 4. The decoding part 2 includes a plurality of decoding blocks which are provided in parallel with one another for each of a plurality of encoding systems, to which IP streams are simultaneously input and which decode the corresponding encoded streams in a predetermined unique format. The decoding part 2 outputs respective pieces of decoded data output from the respective decoding blocks, as decoded data by encoding systems for each encoding system. The interpolation part 3 interpolates the decoded data in accordance with a parameter for each format for each of the decoded data by encoding systems and outputs interpolated data by encoding systems for each encoding system. The synchronizing part 4 synchronizes each piece of the input interpolated data by encoding systems with a predetermined reference clock and executes thinning-out processing for thinning out data of a portion equivalent to a frequency difference between the reference clock and each format from the interpolated data by encoding systems during the synchronization.

Description

  The present invention relates to a receiving apparatus and a receiving method for receiving an IP (Internet Protocol) stream including a plurality of encoded streams having different encoding methods and formats.

  A band compression (also called “encoding”) technique is known as a technique for reducing the capacity of a network transmission path. The encoding method is not one type, and various methods (for example, MPEG2 method and H.264 method) are defined and used in practice depending on the application. In the above, MPEG is an abbreviation for Moving Picture Experts Group.

  On the other hand, the standard of video resolution (also referred to as “format”) is not single. For example, various standards such as VGA (Video Graphics Array) and full HD (High Definition) are defined and used practically. Yes.

  Therefore, at present, IP streams including a plurality of encoded streams having different encoding methods and formats are coming and going on the network.

  Patent Document 1 discloses a seamless switching between SD broadcasting and HD broadcasting when transmitting “mottled organization” in which SD (Standard Definition) broadcasting and HD broadcasting are mixed using IP multicast technology in real time. Techniques that enable this are described.

JP 2008-244781 A (Page No. 3-7)

  As a general configuration for processing the IP stream as described above, for example, a configuration in which a plurality of decoding devices that individually perform decoding corresponding to each encoding method as illustrated in FIG. Can do.

  However, in the case of the above configuration, a time lag may occur when switching between decoding apparatuses. Therefore, the above configuration cannot display video seamlessly.

  In addition, when there is a cost limitation in the above configuration, it is not an expensive device (that is, a device that can appropriately decode difficult video containing a lot of high-frequency components) that can process high-level algorithms in each decoding device at high speed. It is expected that only inexpensive devices can be installed. In this case, there is a possibility that the decoding of the single video itself is not normally performed before the seamless switching.

  On the other hand, adding a memory or the like around an inexpensive device of each decoding apparatus increases the possibility of avoiding an encoding error. However, new problems such as an increase in the size of the apparatus occur.

  Therefore, there is a demand for an apparatus (or method) capable of seamlessly switching an IP stream including a plurality of encoded streams having different encoding methods and formats even in an environment where an inexpensive decoding device is used. Yes.

  Patent Document 1 describes a technology that enables seamless switching between SD broadcasting and HD broadcasting, but with this technology, it is difficult to seamlessly display an IP stream as described above.

  The present invention has been made to solve the above-described problem, and an IP stream including a plurality of encoded streams having different encoding methods and formats can be obtained even in an environment where an inexpensive decoding device is used. An object of the present invention is to provide a receiving apparatus and a receiving method that can be switched seamlessly.

  The receiving apparatus of the present invention is a receiving apparatus that receives an IP stream in which a plurality of encoded streams having different encoding schemes and formats are mixed, and is provided in parallel for each of the plurality of encoding schemes. A plurality of decoding blocks for decoding the corresponding encoded stream in a predetermined unique format, wherein each of the decoded data output from each decoding block is encoded for each encoding method; A decoding unit that outputs as decoding data by method, and interpolates the decoding data according to the parameters for each format for each decoding data by coding method, and outputs interpolation data by coding method for each coding method And synchronizes each of the input interpolation data for each encoding method with a predetermined reference clock and the synchronization When, from the encoding system by the interpolation data, and a synchronization unit which performs thinning process for thinning out the partial data corresponding the the reference clock to the frequency difference of each format.

  The receiving method of the present invention is a receiving method for receiving an IP stream in which a plurality of encoded streams having different encoding schemes and formats are mixed, and is provided in parallel for each of the plurality of encoding schemes. A plurality of decoding blocks for decoding the corresponding encoded stream in a predetermined unique format, wherein each of the decoded data output from each decoding block is encoded for each encoding method; Output as decoded data by method, interpolate the decoded data according to the parameters for each format for each decoded data by the encoding method, and output interpolated data by the encoding method for each encoding method, and input Each of the interpolated interpolation data for each encoding method is synchronized with a predetermined reference clock, and at the time of the synchronization, the encoding method From the interpolation data, and executes a thinning process for thinning out the partial data corresponding the the reference clock to the frequency difference of each format.

  According to the present invention, an IP stream including a plurality of encoded streams having different encoding methods and formats can be switched seamlessly even in an environment where an inexpensive decoding device is used.

It is a block diagram which shows the structural example of the receiver which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structural example of the receiver which concerns on the 2nd Embodiment of this invention. It is a figure which shows the state from which the continuity of PTS has shifted | deviated to the minus direction. It is a figure which shows the state from which the continuity of PTS has shifted | deviated to the plus direction. It is a block diagram of the general receiver which connected with multiple decoding apparatuses which perform the decoding corresponding to each encoding system separately. It is a figure explaining the packet malfunction which generate | occur | produces by the influence of routing etc. in general IP network transmission.

[First Embodiment]
FIG. 1 is a block diagram illustrating a configuration example of a receiving device 1 according to the first embodiment of the present invention. The receiving apparatus 1 receives an IP stream in which a plurality of encoded streams having different encoding methods and formats are mixed. The receiving device 1 includes a decoding unit 2, an interpolation unit 3, and a synchronization unit 4.

  The decoding unit 2 is provided in parallel for each of a plurality of encoding schemes, and includes a plurality of decoding blocks that receive IP streams at the same time and decode the corresponding encoded streams in a predetermined unique format. Each decoded data output from each decoding block is output as decoding data for each encoding method.

  The interpolator 3 interpolates the decoded data according to the parameter for each format for each decoded data for each encoding method, and outputs the interpolated data for each encoding method.

  The synchronization unit 4 synchronizes each of the input interpolation data for each encoding method with a predetermined reference clock, and corresponds to the frequency difference between the reference clock and each format from the interpolation data for each encoding method at the time of synchronization. The thinning process is performed to thin out the data for the amount to be processed.

  As described above, in the first embodiment, the decoding unit 2 is provided with a plurality of decoding blocks for decoding the encoded stream in a predetermined unique format in parallel, and the interpolation unit 3 sets the parameters of the encoded stream. Based on this, the decoded data is interpolated, and the synchronizing unit 4 synchronizes each interpolation data with a predetermined reference clock.

Therefore, according to the first embodiment, an IP stream including a plurality of encoded streams with different encoding methods and formats can be switched seamlessly even in an environment where an inexpensive decoding device is used. .
[Second Embodiment]
FIG. 2 is a block diagram illustrating a configuration example of the receiving device 10 according to the second embodiment of the present invention.

  The receiving device 10 includes a decoding unit 12, an interpolation unit 14, and a synchronization unit 16.

  The decoding unit 12 includes an MPEG2 decoding block BL01, H.264, and H.264. H.264 decoding block BL02.

  The decoding unit 12 receives the IP stream S01 from an external device (not shown in FIG. 2) through a network such as the Internet. The IP stream S01 includes encoded streams of different encoding schemes (for example, MPEG2 stream S02 and H.264 stream S03). Furthermore, each encoded stream (S02, S03) includes encoded streams of different formats (for example, SD and HD).

  Regarding the resolution, there is a difference in the video format depending on the baseband region of the video parallel signal S31 and the video serial signal S41 to be finally output. The H.264 stream S03 is also defined by the encoding level and profile. Specifically, Seq_h as the MPEG2 system resolution signal Y1 is defined in the header part of the MPEG2 stream S02. On the other hand, H. SPS_NAL as the H.264 system resolution signal Y2 is H.264. It is defined in the header part of the H.264 stream S03.

  The IP stream S01 is composed of MPEG2 decoding block BL01 and H.264. It is simultaneously input to the H.264 decoding block BL02 and decoded.

  The MPEG2 system SD decoding block B01 decodes only the stream having the SD resolution or less in the MPEG2 stream S02 in the IP stream S01. The decoding here is uniquely performed with the maximum size within this range (for example, VGA to SD), that is, SD size = 720 (H) × 480 (V).

  The MPEG2 HD decoding block B02 decodes only a stream having a resolution higher than the SD resolution and lower than the full HD resolution in the MPEG2 stream S02 of the IP stream S01. The decoding here is uniquely performed with the maximum size within this range (for example, HD to full HD), that is, full HD size = 1920 (H) × 1080 (V).

  H. The H.264 SD decoding block B03 is an H.264 of the IP stream S01. Only the stream having the SD resolution or less of the H.264 stream S03 is decoded. The decoding here is performed uniquely with the SD size in the same way as the MPEG2 SD decoding block B01.

  H. The H.264 HD decoding block B04 is the H.264 of the IP stream S01. Only a stream having a resolution higher than the SD resolution and lower than the full HD resolution in the H.264 stream S03 is decoded. The decoding here is uniquely performed in the full HD size similarly to the MPEG2 system HD decoding block B02.

  That is, the MPEG2 SD decoding block B01, the MPEG2 HD decoding block B02, H.264 SD decoding block B03; The H.264 system HD decoding block B04 is provided in parallel.

  The MPEG2 system decoding block BL01 outputs MPEG2 system decoded data S11 including the decoded data decoded by the MPEG2 system SD decoding block B01 and the decoded data decoded by the MPEG2 system HD decoding block B02.

  H. The H.264 decoding block BL02 is an H.264 decoding block. H.264 SD decoding block B03 and the decoded data H.264 system HD decoding block B04 including the decoded data. H.264 system decoded data S12 is output.

  The MPEG2 decoding block BL01 and the H.264 decoding block. In the H.264 decoding block BL02, a matching operation described below is executed.

  Specifically, the IP stream S01 is simultaneously input to each decoding block (B01 to B04). Each decoding block (B01 to B04) executes the decoding process regardless of the content of the IP stream S01, and outputs a signal only when the decoding is successful.

  More specifically, the MPEG2 system decoding block BL01 is a stream that does not match its own system. Even if the H.264 stream S03 is input, it is not decoded (cannot be decoded). On the other hand, H.C. The H.264 decoding block BL02 does not decode (cannot be decoded) even if an MPEG2 stream S02 that is a stream that does not match its own method is input.

  On the other hand, a block for decoding a stream of SD resolution or lower does not decode even if a stream having a resolution higher than the SD resolution and not higher than the full HD resolution is input. Can't). Conversely, a block that decodes a stream having a resolution higher than the SD resolution and lower than or equal to the full HD resolution does not decode even if a stream having a resolution lower than the SD resolution, which is a stream that does not match its own method, is input (decoding Can not do it).

  In FIG. 2, only the MPEG2 stream S02 is input to the MPEG2 decoding block BL01. H.264 decoding block BL02 A state in which only H.264 stream S03 is input is shown. However, this is for clearly indicating the result of the above matching operation (that is, processing only the stream suitable for its own system). The H.264 decoding block BL02 is simultaneously input with the IP stream S01 as a common stream.

  Also, MPEG2 system and H.264 standard. The number of decoding blocks (B01 to B04) can be obtained by adopting a configuration in which the H.264 system is automatically discriminated by the cores in the decoding block, or by mounting a core that can be decoded regardless of the encoding profile and encoding level. Can be reduced. However, in this description, in order to clarify the function of the decoding unit 12, a case where the decoding unit 12 is configured by individual decoding blocks (B01 to B04) will be described as an example.

  The interpolation unit 14 includes an MPEG2 resolution information extraction block B05, H.264 system resolution information extraction block B08, MPEG2 system time information extraction block B06, H.264 system time information extraction block B09, MPEG2 system continuity confirmation block B07, H.264 system continuity confirmation block B10, MPEG2 system decoding interpolation block B11, H.264 decoding interpolation block B12.

  The IP stream S01 includes MPEG2 format resolution information extraction block B05, H.264 and H.264. H.264 system resolution information extraction block B08, MPEG2 system time information extraction block B06, It is simultaneously input to the H.264 system time information extraction block B09.

  The MPEG2 system resolution information extraction block B05 extracts the MPEG2 system resolution information signal D1 from the MPEG2 stream S02 of the IP stream S01.

  H. The H.264 system resolution information extraction block B08 is an H.264 of the IP stream S01. H.264 stream S03 to H.264 H.264 system resolution information signal D2 is extracted.

  The MPEG2 system resolution information signal D1 is input to the MPEG2 system decoding interpolation block B11 together with the above-described MPEG2 system decoding data S11.

  H. The H.264 system resolution information signal D2 is the above-described H.264 format. H.264 system decoded data S12 and H.264 It is input to the H.264 decoding interpolation block B12.

  The MPEG2 system time information extraction block B06 extracts the MPEG2 system time information signal Z1 from the MPEG2 stream S02 of the IP stream S01. The MPEG2 system time information signal Z1 corresponds to PTS (Presentation Time Stamp). The MPEG2 system time information signal Z1 is input to the MPEG2 system continuity confirmation block B07. The MPEG2 system continuity confirmation block B07 confirms the temporal continuity of the MPEG2 system time information signal Z1, and outputs the confirmation result as an MPEG2 system time information continuous flag Z3 to the MPEG2 system decoding interpolation block B11.

  H. H.264 system time information extraction block B09 is an H.264 of IP stream S01. H.264 stream S03 to H.264 H.264 system time information signal Z2 is extracted. H. The H.264 system time information signal Z2 corresponds to PTS. H. H.264 system time information signal Z2 is H.264. H.264 system continuity confirmation block B10. H. H.264 system continuity confirmation block B10 is H.264. The time continuity of the H.264 system time information signal Z2 is confirmed. As the H.264 system time information continuous flag Z4, H.264 is used. H.264 decoding interpolation block B12.

  Note that the interpolation unit 14 also uses MPEG2 decoding blocks BL01 and H.264. A matching operation similar to that of the H.264 decoding block BL02 is performed.

  More specifically, the IP stream S01 includes MPEG2 format resolution information extraction block B05, MPEG2 time information extraction block B06, and H.264. H.264 system resolution information extraction block B08; It is simultaneously input to the H.264 system time information extraction block B09.

  The MPEG2 system resolution information extraction block B05 is an H.264 format. Even if the H.264 stream S03 is input, the resolution information signal for the stream is not extracted (cannot be extracted). On the other hand, H.C. Even if the MPEG2 stream S02 is input, the H.264 resolution information extraction block B08 does not extract (cannot extract) the resolution information signal for the stream.

  The MPEG2 system time information extraction block B06 is an H.264 format. Even when the H.264 stream S03 is input, the time information signal for the stream is not extracted (cannot be extracted). On the other hand, H.C. Even if the MPEG2 stream S02 is input, the H.264 time information extraction block B09 does not extract (cannot extract) the time information signal for the stream.

  The MPEG2 system decoding interpolation block B11 performs an interpolation process described below on the MPEG2 system decoding data S11.

  In the MPEG2 SD decoding block B01, the stream having the SD resolution or lower is uniquely decoded with the SD size = 720 (H) × 480 (V) as described above. Lacks data.

  On the other hand, in the MPEG2 HD decoding block B02, a stream having a resolution higher than the SD resolution and lower than the full HD resolution is uniquely decoded with the full HD size = 1920 (H) × 1080 (V) as described above. In the case of a stream having a resolution lower than full HD, data is insufficient.

  Accordingly, the MPEG2 system decoding interpolation block B11 interpolates each of the shortages. The interpolation here includes “inner interpolation” and “outer interpolation”.

  When the interpolation process is completed within the frame, the inner interpolation is executed. The inner interpolation can be performed by using a well-known technique such as up-conversion or scaling. Further, the MPEG2 system decoding interpolation block B11 refers to the MPEG2 system resolution information signal D1, determines the resolution of the interpolation target stream, and executes appropriate internal interpolation. Note that when the resolution of the interpolation target stream is the maximum size of each range, interpolation is not necessary.

  On the other hand, as shown in FIG. 3, when the continuity of the MPEG2 system time information continuous flag Z3 is shifted in the minus direction, the outer interpolation is executed. FIG. 3 shows that the MPEG system time information signal Z1 expressed in units of frames is negative, that is, a state where frames are insufficient with respect to relative time. Therefore, it is necessary to interpolate the deficient frames. However, since this interpolation is performed between the frames, the interpolation is executed as outer interpolation instead of inner interpolation. Outer interpolation can be performed by using a well-known technique such as frame synchronization or multiple-frame super-resolution.

  The MPEG2 system decoding interpolation block B11 outputs the decoded data subjected to the above interpolation as MPEG2 system decoding interpolation data S21.

  H. The H.264 decoding interpolation block B12 is the H.264 decoding interpolation block B12. The interpolation processing described below is executed on the H.264 decoding data S12.

  H. In the H.264 SD decoding block B03, the stream having the SD resolution or lower is uniquely decoded with the SD size = 720 (H) × 480 (V) as described above. Lacks data.

  On the other hand, H. In the H.264 decoding block B04, a stream having a resolution higher than the SD resolution and lower than or equal to the full HD resolution is uniquely decoded with the size of full HD = 1920 (H) × 1080 (V) as described above. In the case of a stream having a resolution lower than full HD, data is insufficient.

  Therefore, H.I. The H.264 decoding interpolation block B12 interpolates each of the shortages. The interpolation here includes “inner interpolation” and “outer interpolation”.

  When the interpolation process is completed within the frame, the inner interpolation is executed. The method for realizing the inner interpolation is as described above. H. The H.264 decoding interpolation block B12 is the H.264 decoding interpolation block B12. The resolution of the interpolation target stream is determined with reference to the H.264 resolution information signal D2. Note that when the resolution of the interpolation target stream is the maximum size of each range, interpolation is not necessary.

  On the other hand, as shown in FIG. When the continuity of the H.264 time information continuous flag Z4 is shifted in the negative direction, outer interpolation is executed. FIG. 3 shows H.264 expressed in frame units. This indicates that the H.264 system time information signal Z2 is negative, that is, the frame is insufficient. Therefore, it is necessary to interpolate the deficient frames. However, since this interpolation is performed between the frames, the interpolation is executed as outer interpolation instead of inner interpolation. The method for realizing outer interpolation is as described above.

  H. The H.264 decoding interpolation block B12 converts the decoded data subjected to the above interpolation to H.264. It outputs as H.264 system decoding interpolation data S22.

  MPEG2 system continuity confirmation block B07 and H.264. By providing the H.264 continuity confirmation block B10, data can be interpolated even when the IP stream S01 has lost data in the stage before input due to the influence of the network environment or the like.

  The synchronization unit 16 includes a clock PLL block B13, a synchronization control block B14, an MPEG2 system synchronization block B15, H.264 system synchronization block B16 and video / serial conversion block B17.

  The MPEG2 system decoding interpolation data S21 output from the MPEG2 system decoding interpolation block B11 is input to the MPEG2 system synchronization block B15 and written in a video signal area having a self-running readout-side SYNC signal. A reference clock signal X01 is used as a read clock.

  On the other hand, the writing to the video signal area is a synchronization in which the reference clock signal X01 and the PCR (Program Clock Reference) value included in the IP stream S01 are synchronized by the clock PLL block B13 and data writing corresponding to the synchronization difference is stopped. This is executed based on the control write control flag E1.

  For example, the ratio of the frequency of a general HD video signal and the frequency of the reference clock signal X01 of this embodiment is 74.25 (MHz): 74.25 / 1.001 (MH). When this is expressed as a ratio of the number of video frames in 100 seconds, it is 6000 (sheets): 5994 (sheets). The difference between the six images is a data amount difference when synchronizing the PCR value included in the reference clock signal X01 and the IP stream S01 with the clock PLL block B13.

  The synchronized write control flag E1 is input to the synchronized control block B14. Based on the MPEG2 system resolution information signal D1, the synchronization control block B14 determines whether the input MPEG2 system decoding interpolation data S21 is data to be written to the SD resolution area in the MPEG2 system synchronization block B15 or to the HD resolution area. Determine whether the data is to be written. For example, the synchronization control block B14 is data to be written to the SD resolution area when the horizontal resolution is 720 or less, and is determined to be data to be written to the HD resolution area when the horizontal resolution is larger than 720. To do. The synchronization control block B14 controls writing of the MPEG2 system synchronization block B15 by the MPEG2 system synchronization area flag C1 based on the determination result and the synchronization write control flag E1.

  FIG. 4 shows a state where data is excessive as described above. FIG. 4 shows that the MPEG system time information signal Z1 expressed in units of frames is positive, that is, a state where the frame is excessive with respect to the relative time.

  In other words, the synchronization unit 16 realizes an operation that has to be relatively thinned out due to excessive data by periodically stopping writing in the synchronization block (B15, B16) composed of the memory. ing.

  Similarly, H.M. H.264 system decoding interpolation block B12. The H.264 decoding interpolation data S22 is H.264. It is input to the H.264 system synchronization block B16 and written into the video signal area having the read-side SYNC signal that is free-running. A reference clock signal X01 is used as a read clock.

  On the other hand, the writing to the video signal area is performed by synchronizing the PCR value included in the reference clock signal X01 and the IP stream S01 with the clock PLL block B13 and stopping the writing of data corresponding to the synchronization difference. It is executed based on.

  The difference in clock frequency of each signal and the data difference when synchronizing are the same as in MPEG2.

  The synchronized write control flag E1 is input to the synchronized control block B14. The synchronization control block B14 is H.264. The H.264 system resolution information signal D2 is input based on the input H.264 resolution information signal D2. H.264 decoding interpolation data S22 is H.264. It is determined whether the data is to be written to the SD resolution area or the HD resolution area in the H.264 synchronization block B16. The synchronization control block B14 is based on the determination result and the synchronization write control flag E1. H.264 system synchronization area flag C2 The writing of the H.264 system synchronization block B16 is controlled.

  MPEG2 synchronization block B15 and H.264. The reading side of the H.264 system synchronization block B16 is connected to the MPEG2 system synchronization area flag C1 or H.264. The path to the video parallel signal S31 to be output is switched in conjunction with the H.264 system synchronization area flag C2. After that, the video / serial conversion block B17 performs parallel / serial conversion on the video parallel signal S31 and outputs a video serial signal S41.

  As described above, in the second embodiment, the decoding unit 12 is provided with a plurality of decoding blocks for decoding the encoded stream in a predetermined unique format in parallel, and the interpolation unit 14 uses the encoded stream parameters ( The decoded data is interpolated based on the resolution and the time information continuous flag), and the synchronizing unit 16 synchronizes each interpolation data with a predetermined reference clock.

  Therefore, according to the second embodiment, an IP stream including a plurality of data streams with different encoding methods and formats can be switched seamlessly even in an environment where an inexpensive decoding device is used.

  Furthermore, according to the present embodiment, when the video to be processed is a difficult video containing a lot of high frequency components, or a problem (for example, frame dropping) that occurs during routing during general IP network transmission as shown in FIG. And frame skipping) can be avoided.

  Further, by configuring as in the present embodiment, the configuration as shown in FIG. 5 (configuration in which a plurality of decoding devices that individually execute decoding corresponding to each encoding method are connected) is realized by one device. be able to. Therefore, not only can the system configuration be simplified, but also the time lag and processing delay at the time of switching can be reduced to a negligible level.

  Note that the encoding method and format used in the above description are merely examples, and the receiving apparatus 10 of the present embodiment can cope with an encoding method and format different from the above and achieve the same effect as described above. be able to.

  The extraction of resolution information and time information included in the stream can also be executed by a decoding block.

  In the above description, the case where decoding of each decoding block is performed with the maximum size that can be decoded by each decoding block is described as an example. However, the present invention is not limited to this. In this case, the area of the subsequent interpolation block may be enlarged.

  Furthermore, if the resolution range of the decoding setting that does not require setting is widely covered, for example, a device that can decode from VGA size to full HD, one decoding block, that is, an SD decoding block and an HD decoding block is provided. It is also possible to make it.

  In addition, the MPEG2 system and the H.264 standard. If the device can decode both of the H.264 system, the MPEG2 system decoding block, It is also possible to combine two large decoding blocks called H.264 decoding blocks.

  Further, if a digital / analog conversion block is used in the final stage, an analog video can be output.

In many cases, the audio signal is inherent in the input IP stream. However, there are cases where the IP stream is composed only of audio signals, such as IP radio. In the above description, a video signal is taken as an example, but the present embodiment can be applied to only an audio IP stream.
[Industrial applicability]
As an example of use of the present invention, it is possible to provide viewing without switching shock when continuously observing in real time in a system that collects on-site images such as traffic conditions at multiple points and factory work. It can also be used to simplify large-scale facilities such as continuous display of advertising content such as digital signage and immediate interruption of emergency broadcasting.

1, 10 Receiving device 2, 12 Decoding unit 3, 14 Interpolation unit 4, 16 Synchronization unit BL01 MPEG2 decoding block BL02 H. H.264 decoding block B01 MPEG2 SD decoding block B02 MPEG2 HD decoding block B03 H.264 SD decoding block B04 H.264 system HD decoding block B05 MPEG2 system resolution information extraction block B06 MPEG2 system time information extraction block B07 MPEG2 system continuity confirmation block B08 H.264 H.264 system resolution information extraction block B09 H.264 system time information extraction block B10 H.264 system continuity confirmation block B11 MPEG2 system decoding interpolation block B12 H.264 system decoding interpolation block B13 Clock PLL block B14 Synchronization control block B15 MPEG2 system synchronization block B16 H.264 system synchronization block B17 Video parasite conversion block S01 IP stream S02 MPEG2 stream S03 H.264 stream S11 MPEG2 decoding data S12 H.264 H.264 decoding data S21 MPEG2 decoding interpolation data S22 H.264 system decoded interpolation data S31 Video parallel signal S41 Video serial signal C1 MPEG2 system synchronization area flag C2 H.264 H.264 system synchronization area flag D1 MPEG2 system resolution information signal D2 H.264 H.264 system resolution information signal E1 synchronized write control flag X01 reference clock signal Y1 MPEG2 system resolution signal Y2 H.264 H.264 system resolution signal Z1 MPEG2 system time information signal Z2 H.264 system time information signal Z3 MPEG2 system time information continuous flag Z4 H.264 H.264 system time information continuous flag

Claims (7)

A receiving device that receives an IP stream in which a plurality of encoded streams having different encoding methods and formats are mixed,
A plurality of decoding blocks provided in parallel for each of the plurality of encoding schemes, wherein the IP streams are simultaneously input, and the corresponding encoded streams are decoded in a predetermined unique format; A decoding unit that outputs each decoded data output from the block as decoded data for each encoding method;
An interpolation unit that interpolates the decoded data according to the parameters for each format for each decoded data for each encoding method, and outputs interpolated data for each encoding method for each encoding method;
Each of the inputted interpolation data for each encoding method is synchronized with a predetermined reference clock, and at the time of the synchronization, the interpolation data for each encoding method is equivalent to a frequency difference between the reference clock and each format. And a synchronizer that executes a thinning process for thinning out the data to be reduced.   The receiving apparatus according to claim 1, wherein the predetermined unique format is a format of a maximum size decoded by each of the decoding blocks.   3. The reception according to claim 1, wherein the interpolation performed by the interpolation unit is at least one of inner interpolation in which interpolation processing is completed within a frame and outer interpolation in which interpolation processing is performed between the frames. apparatus.   The receiving apparatus according to claim 3, wherein the parameter is resolution information indicating a resolution of the encoded stream, and the interpolation unit performs the inner interpolation based on the resolution information.   The said parameter is a time information continuation flag which shows the continuity of the time information of the said encoding stream, The said interpolation part performs the said outer interpolation based on the said time information continuation flag. Receiver device.   The synchronization unit obtains a difference between the frequency of the reference clock and the frequency of each format as a difference in the number of frames within a predetermined unit time, and periodically stops writing corresponding to the difference within the unit time. The receiving apparatus according to claim 1, wherein the receiving apparatus includes: A receiving method for receiving an IP stream in which a plurality of encoded streams having different encoding methods and formats are mixed,
A plurality of decoding blocks provided in parallel for each of the plurality of encoding schemes, wherein the IP streams are simultaneously input, and the corresponding encoded streams are decoded in a predetermined unique format; Each decoded data output from the block is output as decoded data by encoding method for each encoding method,
For each decoded data for each encoding method, interpolate the decoded data according to the parameters for each format, and output the interpolated data for each encoding method for each encoding method,
Each of the inputted interpolation data for each encoding method is synchronized with a predetermined reference clock, and at the time of the synchronization, the interpolation data for each encoding method is equivalent to a frequency difference between the reference clock and each format. A receiving method characterized by executing a thinning process for thinning out the data to be processed.

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