JP2015106695A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of preventing the occurrence of defects at a PN junction portion of an IGBT region side and the degradation of ohmic characteristics of a diode region side, and to provide a method of manufacturing the same.SOLUTION: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface; a first-conductivity-type first semiconductor region provided on the first surface side; a second-conductivity-type second semiconductor region formed on the first surface side and provided in a part of the first semiconductor region; a first-conductivity-type third semiconductor region provided on the first surface and having a lower first-conductivity-type impurity concentration than that of the first semiconductor region; a first-conductivity-type first semiconductor layer provided on the second surface side; a second-conductivity-type second semiconductor layer provided between the first semiconductor region and the third semiconductor region, and the second surface; a metal layer provided on the first semiconductor region and the second semiconductor region; and an aluminum layer provided on the metal layer and the third semiconductor region.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  Generally, a reverse conducting IGBT (Insulated Gate Bipolar Transistor) has an IGBT region and a diode region. A metal layer is provided on the surface side of both regions in contact with the silicon (Si) layer. For example, titanium (Ti), titanium tungsten (TiW), titanium sodium (TiN), or the like. It is desirable to connect a metal such as aluminum that suppresses contact resistance to the Si layer on the IGBT region side. However, when a metal such as aluminum is connected, a metal such as aluminum may enter the Si layer in the IGBT region. When a metal such as aluminum enters the body region, there is a problem that a part of the PN junction where the body region and the drift layer are joined becomes defective, and a desired rated voltage cannot be obtained. In order to avoid this problem, a metal layer such as Ti, TiW or TiN is used between the Si layer and the aluminum layer. However, this metal layer may be formed also on the diode region side in manufacturing. The metal layer on the diode region side has a different resistance value at each junction, and the ohmic characteristics are lowered as compared with the case where an aluminum layer is provided on the Si layer on the diode region side.

JP 2010-192597 A

  The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing the same that can suppress the generation of defects in the PN junction portion on the IGBT region side and the deterioration of the ohmic characteristics on the diode region side. It is.

  A semiconductor device according to an embodiment of the present invention includes a semiconductor substrate having a first surface and a second surface, a first semiconductor region of a first conductivity type provided on the first surface side, and on the first surface side. A second semiconductor region of a second conductivity type formed in a part of the first semiconductor region and a first conductivity type impurity concentration provided on the first surface and having a lower first conductivity type impurity concentration than the first semiconductor region. A third semiconductor region of one conductivity type, a first semiconductor layer of a first conductivity type provided on the second surface side, and between the first semiconductor region and the third semiconductor region and the second surface; A second semiconductor layer of a second conductivity type provided; a gate electrode provided via an insulating film from the first surface side toward the second surface side through the second semiconductor layer; and the first semiconductor A region, a metal layer provided on the second semiconductor region, and a metal layer provided on the metal layer and the third semiconductor region. Characterized in that it comprises the aluminum layer.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which impurity ions are implanted from a first surface side of a semiconductor substrate, and a first conductivity type first semiconductor region and a first conductive region that is more conductive than the first semiconductor region. Forming a first conductive type third semiconductor region having a low type impurity concentration; and implanting impurity ions into a part of the first semiconductor region to form a second conductive type second semiconductor region; Implanting impurity ions from the second surface side of the semiconductor substrate to form a first semiconductor layer of a first conductivity type; implanting impurity ions from the first surface side of the semiconductor substrate; Forming a second semiconductor layer of a second conductivity type between the region and the third semiconductor region and the second surface, and the second semiconductor layer from the first surface side toward the second surface side Forming a gate electrode through an insulating film until the first half Forming an aluminum layer on the body region and the third semiconductor region, removing the aluminum layer on the first semiconductor region, and forming a metal layer on the first semiconductor region from which the aluminum layer has been removed. And the step of performing.

1 is a schematic cross-sectional view of a semiconductor device showing an embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention. The typical sectional view of the semiconductor device shown for every manufacturing process in one embodiment of the present invention.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the description, common parts are denoted by common reference symbols throughout the drawings.

  FIG. 1 is a schematic cross-sectional view of a semiconductor device 1 according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 26 mainly made of silicon (Si). The semiconductor substrate 26 has an IGBT region 3 and a diode region 2.

  In the IGBT region 3, the plurality of trenches 11 are provided on the upper surface 25 a side of the semiconductor substrate 26. The insulating film 16 is provided on the inner wall surface of the trench 11. The gate electrode 15 is provided in the trench 11 via the insulating film 16. Another insulating film 18 is provided on the gate electrode 15.

  The P-type body region 13 as the first semiconductor region of the first conductivity type is provided on the upper surface 25 a side of the semiconductor substrate 26. The N-type emitter region 14 as the second conductivity type second semiconductor region is also formed on the upper surface 25 a side and is selectively provided in the P-type body region 13. The N-type emitter region 14 is provided in contact with the insulating film 16. The N type drift layer 10 as the second conductivity type second semiconductor layer is provided below the P type body region 13. The N-type buffer layer 19 as the second conductivity type fourth semiconductor layer is provided below the N-type drift layer 10. The N-type impurity concentration of the N-type contact layer 19 is higher than the N-type impurity concentration of the N-type drift layer 10. The P-type collector layer 21 as the first conductive type first semiconductor layer is provided on the lower surface 25 b side of the semiconductor substrate 26. The P-type impurity concentration of the P-type collector layer 21 is higher than the P-type impurity concentration of the P-type body region 13.

  In the diode region 2, the plurality of trenches 27 are provided on the upper surface 25 a side of the semiconductor substrate 26. The trench 27 extends to substantially the same depth as the trench 11. The insulating film 16 is provided on the inner wall surface of the trench 27. The trench electrode 17 is formed in the trench 27. The insulating film 18 is provided on the trench electrode 17.

  The P-type anode region 12 as the first conductivity type third semiconductor region is provided on the upper surface 25a side. The P-type impurity concentration of the P-type anode region 12 is lower than the P-type impurity concentration of the P-type body region 13.

  The N-type cathode layer 28 as the second conductive type second semiconductor layer is provided below the P-type anode region 12. The N-type cathode layer 28 is the same layer as the N-type drift layer 10 in the IGBT region 3. The N-type impurity concentration of the N-type cathode layer 28 is substantially equal to the N-type impurity concentration of the N-type drift layer 10 and is lower than the N-type impurity concentration of the N-type contact layer 19. By doing so, the breakdown voltage of the semiconductor device due to the punch-through phenomenon can be ensured.

  The N-type contact layer 20 as the second conductivity type third semiconductor layer is provided on the lower surface 25b side. The lower electrode 23 is provided over the entire lower surface 25 b of the semiconductor substrate 26. The lower electrode 23 is in ohmic contact with the P-type collector layer 21 and the N-type contact layer 20. Further, the N-type impurity concentration of the N-type contact layer 20 is higher than the N-type impurity concentration of the N-type buffer layer 19. By doing so, the contact resistance between the N-type contact layer 20 and the lower electrode 23 can be suppressed.

  The metal layer 22 is provided on the P-type body region 13 and the N-type emitter region 14 on the upper surface 25 a of the IGBT region 3. The aluminum layer 24 is provided on the metal layer 22. The aluminum layer 24 is provided on the P-type anode region 12 on the upper surface 25 a of the diode region 2. The aluminum layer 24 provided on the metal layer 22 in the IGBT region 3 is desirably thinner than the aluminum layer 24 provided on the P-type anode region 12 in the diode region 2. By doing so, the amount of aluminum is reduced, and entry into the P-type body region 13 can be suppressed. Further, the metal layer 22 is provided on the insulating film 18 and the aluminum layer 24 in the diode region 2. The metal layer 22 in the IGBT region 3 is preferably thicker than the metal layer 22 provided on the insulating film 18 and the aluminum layer 24 in the diode region 2. By doing so, the metal layer can suppress the aluminum layer from entering the P-type body region 13. The material for the metal layer 22 includes Ti, TiW, TiN, and the like.

  As described above, the metal layer 22 is on the P-type body region 13 and the N-type emitter region 14 on the upper surface 25a in the IGBT region 3, and the aluminum layer 24 is on the P-type anode region 12 on the upper surface 25a in the diode region 2. Is provided. Thereby, in the IGBT region 3, since the aluminum layer 24 is provided on the metal layer 22, aluminum can be prevented from entering the P-type body region 13. Therefore, a desired rated voltage can be obtained without causing a defect in the PN junction portion where the P-type body region 13 and the N-type drift layer 10 are joined. In addition, in the diode region 2, since the number of junctions due to different metals is small compared to the case where the metal layer 22 is provided between the P-type anode region 12 on the diode region 2 side and the aluminum layer 24, a reduction in ohmic characteristics is suppressed. be able to. In the above embodiment, by providing a metal that matches the characteristics of the P-type body region 13 that is the Si layer of the IGBT region 3 and the P-type anode region 12 that is the Si layer of the diode region 2, The semiconductor device 26 that suppresses the generation of defects in the PN junction and the deterioration of the ohmic characteristics on the diode region 2 side can be formed.

  Next, the operation of the semiconductor device 1 will be described.

  Consider a case where a high potential is applied to the upper electrode (not shown) and a low potential is applied to the lower electrode 23. In this case, the diode region 2 has a high potential on the anode side (upper electrode) and a low potential on the cathode side (lower electrode 23). That is, the forward voltage is applied. For this reason, the diode region 2 is turned on.

  On the other hand, in the IGBT region 3, the emitter side (upper electrode) has a high potential and the collector side (lower electrode 23) has a low potential. For this reason, the IGBT region 3 is not turned on.

  When the diode region 2 is caused to function as a freewheel diode, the state is switched from a state in which a forward voltage is applied to the diode region 2 to a state in which a reverse voltage is applied to the diode region 2. That is, the state is switched to a state in which a high potential is applied to the lower electrode 23 and a low potential is applied to the upper electrode. Then, the diode region 2 is turned off, and a reverse current (current from the lower electrode 23 toward the upper electrode) flows in the diode region 2.

  That is, in a state where the forward voltage is applied and the diode region 2 is turned on, electrons and holes flow through the N-type cathode layer 28. From this state, when a reverse voltage is applied to the diode region 2, electrons present in the N-type cathode layer 28 are discharged to the cathode side (lower electrode 23), and holes present in the N-type cathode layer 28. Is discharged to the anode side (upper electrode). For this reason, a reverse current flows through the diode region 2.

  When a high potential is applied to the lower electrode 23 and a low potential is applied to the upper electrode, the IGBT region 3 has a high potential on the collector side (lower electrode 23) and a lower potential on the emitter side (upper electrode). When a positive potential is applied to the gate electrode 15 in this state, the P-type body region 13 in contact with the insulating film 16 is inverted from P-type to N-type. As a result, a channel is formed in the P-type body region 13 in a range in contact with the insulating film 16.

  When the channel is formed, the potential difference between the lower electrode 23 and the upper electrode (that is, the collector-emitter voltage) causes electrons to flow from the upper electrode to the channels in the N-type emitter region 14 and the P-type body region 13. It flows to the lower electrode 23 via the N-type drift layer 10 and the P-type collector layer 21. In addition, holes flow from the P-type body region 13 to the upper electrode via the P-type collector layer 21, the N-type drift layer 10, and the P-type body region 13 (parts other than the channel) from the lower electrode 23. That is, the IGBT region 3 is turned on.

  As described above, the metal layer 22 is provided on the P-type body region 13 and the N-type emitter region 14 on the upper surface 25 a in the IGBT region 3, so that the aluminum provided on the metal layer 22 is converted into the P-type body region 13. Intrusion can be suppressed, and a desired rated voltage can be obtained during operation without causing defects in the PN junction portion. Further, in the diode region 2, it is not necessary to increase the impurity concentration of the P-type anode region 12 in order to suppress the ohmic degradation, and the amount of holes existing in the N-type cathode layer 28 is suppressed and the holes are discharged. Can be shortened.

  Next, a method for manufacturing the semiconductor device 1 will be described with reference to the drawings. 2 to 10 are schematic cross-sectional views of a semiconductor device shown for each manufacturing process in an embodiment of the present invention.

  As shown in FIG. 2, the semiconductor substrate 26 is manufactured from a silicon wafer containing N-type impurities having substantially the same concentration as the N-type drift layer 10 and the N-type cathode layer 28.

  First, the P-type body layer 13 and the P-type anode layer 12 are formed on the upper surface 25a side of the silicon wafer by impurity ion implantation, thermal diffusion, or the like. At this time, the P-type impurity concentration of the P-type anode region 12 is set lower than the P-type impurity concentration of the P-type body region 13.

  Next, as shown in FIG. 3, a mask having a pattern corresponding to the trench 11 and the trench 27 is formed on the silicon wafer by a CVD method or the like. Then, the upper surface of the silicon wafer is etched by RIE to form a trench 11 on the IGBT region 3 side and a trench 27 on the diode region 2 side. When the trench 11 and the trench 27 are formed, first, a thermal oxide film is formed on the inner surface of the trench 11, and the thermal oxide film is removed by wet etching, whereby the inner surface of the trench 11 is surface-treated. During this wet etching, the mask is also removed.

  Next, a thermal oxide film is grown on the inner surface of the trench 11 to form an insulating film 16. Then, polysilicon is filled into the trench 11 by the CVD method. Thereafter, the polysilicon is etched back to leave the polysilicon only in the trenches 11, thereby forming the gate electrode 15 as shown in FIG.

  Next, a thin thermal oxide film is formed on the inner surface of the trench 27, and the trench 27 is filled with polysilicon by a CVD method. Thereafter, the polysilicon is etched back to leave the polysilicon only in the trench 27, thereby forming the trench electrode 17 as shown in FIG. After the formation of the gate electrode 17, as shown in FIG. 5, an N-type emitter region 14 is formed by impurity ion implantation, thermal diffusion, or the like.

  Next, as shown in FIG. 6, an N-type buffer layer 19, a P-type collector layer 21, an N-type contact layer 20, an upper electrode 64, and a lower electrode 23 are formed by a conventionally known method. At this time, the N-type impurity concentration of the N-type buffer layer 19 is set lower than the N-type impurity concentration of the N-type contact layer 20, and the N-type impurity concentration of the N-type cathode layer 28 is set to be N-type of the N-type contact layer 19. Set lower than impurity concentration. The P-type impurity concentration of the P-type collector layer 21 is set higher than the P-type impurity concentration of the P-type body region 13. Then, as shown in FIG. 7, an insulating film 18 is formed on the gate electrode 15 and the trench electrode 17 by a thermal oxide film.

  Thereafter, as shown in FIG. 8, an aluminum layer 24 is formed on the P-type anode region 12 on the upper surface 25 a of the diode region 2. Then, as shown in FIG. 9, a metal layer 22 is formed on the P-type body region 13, the N-type emitter region 14, and the aluminum layer on the diode region side of the upper surface 25 a of the IGBT region 3. Finally, as shown in FIG. 10, an aluminum layer 24 is formed on the metal layer 22 in the IGBT region 3, thereby completing the semiconductor device 1 shown in FIG. At this time, the aluminum layer 24 provided on the metal layer 22 in the IGBT region 3 is formed thinner than the aluminum layer 24 provided on the P-type anode region 12 in the diode region 2. The metal layer 22 in the IGBT region 3 is formed thicker than the metal layer 22 provided on the insulating film 18 and the aluminum layer 24 in the diode region 2.

  As described above, the metal layer 22 is on the P-type body region 13 and the N-type emitter region 14 on the upper surface 25a in the IGBT region 3, and the aluminum layer 24 is on the P-type anode region 12 on the upper surface 25a in the diode region 2. Can be formed.

  As described above, according to the method of manufacturing a semiconductor device according to the above embodiment, each of the P-type body region 13 that is the Si layer of the IGBT region 3 and the P-type anode region 12 that is the Si layer of the diode region 2. By providing the metal suitable for the characteristics, it is possible to form the semiconductor device 1 that suppresses the generation of defects in the PN junction portion on the IGBT region 3 side and the deterioration of the ohmic characteristics on the diode region 2 side.

  The above embodiment is not the only embodiment, and various modifications are possible. That is, the above-described one embodiment includes a plurality of aspects, and only a part thereof may be implemented.

  Although the embodiments of the present invention have been described, these embodiments are presented as examples, and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 2 ... Diode region, 3 ... IGBT region, 10 ... N type drift layer, 11 ... Trench, 12 ... P type anode region, 13 ... P type body region, 14 ... N type emitter region, 15 ... Gate Electrode, 16 ... insulating film, 17 ... trench electrode, 18 ... insulating film, 19 ... N-type buffer layer, 20 ... N-type contact layer, 21 ... N-type collector layer, 22 ... metal layer, 23 ... lower electrode, 24 ... Aluminum layer, 25a ... upper surface, 25b ... lower surface, 26 ... semiconductor substrate, 27 ... trench, 28 ... N-type cathode layer

Claims (6)

A semiconductor substrate having a first surface and a second surface;
A first semiconductor region of a first conductivity type provided on the first surface side;
A second semiconductor region of a second conductivity type formed on the first surface side and provided in a part of the first semiconductor region;
A third semiconductor region of a first conductivity type provided on the first surface and having a first conductivity type impurity concentration lower than that of the first semiconductor region;
A first semiconductor layer of a first conductivity type provided on the second surface side;
A second conductivity type second semiconductor layer provided between the first semiconductor region and the third semiconductor region and the second surface;
A gate electrode provided through an insulating film from the first surface side toward the second surface side to the second semiconductor layer;
A metal layer provided on the first semiconductor region and the second semiconductor region;
An aluminum layer provided on the metal layer and the third semiconductor region;
A semiconductor device comprising: A third semiconductor layer of a second conductivity type provided between the second surface and the second semiconductor layer;
2. The fourth semiconductor layer according to claim 1, further comprising a fourth semiconductor layer of a second conductivity type provided between the first semiconductor layer, the third semiconductor layer, and the second semiconductor layer. Semiconductor device. A second conductivity type impurity concentration of the second semiconductor layer is lower than an impurity concentration of the fourth semiconductor layer;
The semiconductor device according to claim 2, wherein a second conductivity type impurity concentration of the fourth semiconductor layer is lower than an impurity concentration of the third semiconductor layer.   2. The semiconductor device according to claim 1, wherein the aluminum layer provided on the metal layer is thicker than the aluminum layer provided on the third semiconductor region.   The semiconductor device according to claim 1, wherein the metal layer is also provided on the aluminum layer on the third semiconductor layer region side. Impurity ions are implanted from the first surface side of the semiconductor substrate to form a first conductivity type first semiconductor region and a first conductivity type third semiconductor region having a first conductivity type impurity concentration lower than that of the first semiconductor region. Forming, and
Implanting impurity ions into a part of the first semiconductor region to form a second semiconductor region of a second conductivity type;
Implanting impurity ions from the second surface side of the semiconductor substrate to form a first semiconductor layer of a first conductivity type;
Implanting impurity ions from the first surface side of the semiconductor substrate to form a second semiconductor layer of a second conductivity type between the first semiconductor region and the third semiconductor region and the second surface;
Forming a gate electrode through an insulating film from the first surface side toward the second surface side to the second semiconductor layer;
Forming an aluminum layer on the first semiconductor region and the third semiconductor region;
Removing the aluminum layer on the first semiconductor region;
And a step of forming a metal layer on the first semiconductor region from which the aluminum layer has been removed.

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