JP2015103551A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of further reducing β variation of a bipolar transistor, and to provide a method of manufacturing the same.SOLUTION: Provided is a semiconductor device comprising a bipolar transistor using a polysilicon film as an emitter electrode. The bipolar transistor 100 comprises: a collector region 10 formed on an Si substrate 1; a base layer 30 formed on the collector region 10; an emitter region 39 formed at an upper portion away from the collector region 10, of the base layer 30; and an insulating film 40 formed on the base layer 30, and covering a junction part between the base layer 30 and the emitter region 39. The insulating film 40 at least includes a silicon thermal oxide film 41 formed on the base layer 30.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device and a method for manufacturing the same that can further reduce variations in the current amplification factor β of bipolar transistors.

In recent years, bipolar transistors using a polysilicon film as an emitter electrode are widely used in communication devices that require high speed and high integration. A structure of a bipolar transistor and a manufacturing method thereof are disclosed in, for example, Patent Document 1.
A typical characteristic of a bipolar transistor is a current amplification factor β (or called hFE). In general, β is said to be a parameter that is very likely to vary, and various studies have been made to reduce variation in β (that is, β variation). For example, Patent Document 2 breaks up a natural oxide film existing at the boundary between a polysilicon film and a base layer by implanting fluorine (F) into a polysilicon film to be an emitter electrode and further performing a heat treatment. In addition, there is described a method for reducing β variation due to variation in the natural oxide film thickness by reducing the hole reverse injection barrier.

Japanese Patent Laid-Open No. 2004-311971 Japanese Patent Laid-Open No. 11-40572

By the way, the method described in Patent Document 2 can suppress only β variation caused by variation in film thickness of a natural oxide film present at a boundary portion between a polysilicon film serving as an emitter electrode and a base layer.
As shown in FIG. 16, when an actual device is manufactured, the interface state (marked by x in FIG. 16) existing at the junction between the emitter region 239 and the base region 235 and at the interface with the insulating film 241 has β variation. It is often the cause. This is because the variation in the base current increases due to this interface state, and as a result, the variation in β increases.

That is, even if fluorine is ion-implanted into the polysilicon film 250 to be the emitter electrode by the method described in Patent Document 2, β variation cannot be sufficiently reduced unless the interface state indicated by the x mark can be reduced. There is. Fluorine is an effective element for terminating dangling bonds (dangling bonds) and is effective in reducing the interface state. However, the ion implantation method described in Patent Document 2 is a breakup of a natural oxide film. Therefore, high-concentration fluorine cannot reach the region where the interface state indicated by the x mark exists. For this reason, the method described in Patent Document 2 has a problem that a β variation reduction effect due to interface state reduction cannot be sufficiently obtained.
Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can further reduce the β variation of the bipolar transistor.

  In order to solve the above problems, a semiconductor device according to one embodiment of the present invention is a semiconductor device including a bipolar transistor using a polysilicon film as an emitter electrode, and the bipolar transistor includes a collector region formed in a substrate. A base layer formed on the collector region, an emitter region formed in an upper part of the base layer away from the collector region, and formed on the base layer, the base layer and the emitter And an insulating film covering a junction with the region, wherein the insulating film includes at least a silicon thermal oxide film formed on the base layer.

In the above semiconductor device, the insulating film may further include a silicon oxide film formed on the silicon thermal oxide film.
In the above semiconductor device, the silicon oxide film may be a CVD silicon oxide film formed by a CVD method.
In the semiconductor device, the density of the silicon thermal oxide film may be higher than the density of the silicon oxide film.

  A method for manufacturing a semiconductor device according to another aspect of the present invention is a method for manufacturing a semiconductor device including a bipolar transistor using a polysilicon film as an emitter electrode, the step of forming a collector region on a substrate, and the collector region A step of forming a base layer thereon, a step of forming a silicon thermal oxide film on the base layer, a step of forming a silicon oxide film on the silicon thermal oxide film, and a polysilicon film on the silicon oxide film A step of partially etching the polysilicon film, the silicon oxide film, and the silicon thermal oxide film to form an opening having the base layer as a bottom surface, and the opening through the opening. And introducing an impurity into the base layer to form an emitter region in an upper part of the base layer away from the collector region. And wherein the door.

In the method for manufacturing a semiconductor device, the silicon oxide film may be a CVD silicon oxide film formed by a CVD method.
In the method for manufacturing a semiconductor device, the density of the silicon thermal oxide film may be higher than the density of the silicon oxide film.

  According to one aspect of the present invention, the insulating film formed on the base layer and covering the junction between the base layer and the emitter region includes at least a silicon thermal oxide film formed on the base layer. Since the silicon thermal oxide film is formed by thermal oxidation of silicon, unnecessary impurities remain less than a silicon oxide film formed by, for example, the CVD method. For this reason, it is possible to suppress the generation of interface states at the interface between the base layer and the emitter region and at the interface with the insulating film. Therefore, in the bipolar transistor, it is possible to sufficiently obtain the effect of reducing β variation by reducing the interface state (that is, further reducing β variation by reducing the interface state).

It is sectional drawing which shows the structural example of the semiconductor device which concerns on embodiment. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing which showed the manufacturing method of the semiconductor device which concerns on embodiment to process order. It is sectional drawing for demonstrating a subject.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration and the same function are denoted by the same reference numerals, and repeated description thereof is omitted.
(Constitution)
FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to an embodiment of the present invention.
The semiconductor device shown in FIG. 1 includes an NPN bipolar transistor 100 having a heterojunction structure using a polysilicon film as the emitter electrode 50.
The NPN bipolar transistor 100 includes an N type collector region (high concentration collector region 11 and low concentration collector region 13) 10 formed on a silicon (Si) substrate 1, and a P type base layer formed on the collector region 10. 30, an N-type emitter region 39 formed in an upper part of the base layer 30 away from the collector region 10, and an insulating film 40 formed on the base layer 30. In the NPN bipolar transistor 100, the insulating film 40 covers the junction between the base layer 30 and the emitter region 39. Here, the “upper part” refers to a region of the base layer 30 that is not in contact with the collector region 10.

The insulating film 40 includes a silicon thermal oxide film 41 formed on the base layer 30 and a CVD silicon oxide film 42 formed on the silicon thermal oxide film 41. A polysilicon film 43 is formed on the CVD silicon oxide film 42.
The density of the silicon thermal oxide film 41 is higher than the density of the CVD silicon oxide film 42. The silicon thermal oxide film 41 according to the present embodiment is a silicon oxide film (SiO ₂ film) formed by thermally oxidizing Si using, for example, oxygen gas or a mixed gas of oxygen and water. In addition, the CVD silicon oxide film 42 according to the present embodiment is a silicon oxide film formed using a CVD (Chemical Vapor Deposition) method. Further, “the density of the silicon thermal oxide film 41 is higher than the density of the CVD silicon oxide film 42” means “the silicon thermal oxide film 41 is denser than the CVD silicon oxide film 42. "Means.

The structure of the NPN bipolar transistor 100 will be described in more detail below.
As shown in FIG. 1, the NPN bipolar transistor 100 includes a P-type Si substrate 1. A collector region 10 and an element isolation layer 20 are formed in the P-type Si substrate 1. The collector region 10 includes a high concentration collector region 11 which is a high concentration N type Si region formed in the P type Si substrate 1 and a low concentration collector which is a low concentration N type Si region formed thereon. It consists of a region 13. The element isolation layer 20 that electrically isolates the collector region 10 includes a deep trench 22 and a shallow trench 21 formed on the deep trench 22. The deep trench 22 is made of polysilicon, and the shallow trench 21 is made of a silicon oxide film.

  A base layer 30 is formed on the low concentration collector region 13 and the shallow trench 21 described above. As shown in FIG. 7 described later, the base layer 30 includes a Si layer 31, a silicon germanium (SiGe) layer 32 stacked on the Si layer 31, and a Si layer 33 stacked on the SiGe layer 32. A semiconductor layer having a heterojunction structure. The emitter region 39 is formed in the Si layer 33 that is the upper portion of the base layer 30. In this base layer 30, a region sandwiched between the emitter region 39 and the collector region 10 (specifically, the low concentration collector region 13) is an effective base region 35 that effectively functions as a base.

  Here, portions (regions) formed on the shallow trench 21 in the base layer 30 are polycrystalline Si layers and SiGe layers (hereinafter also referred to as “polycrystalline Si / SiGe / Si layer regions”). It has become. On the other hand, a portion of the base layer 30 formed on the single crystal region excluding the shallow trench 21 (that is, on the low-concentration collector region 13) is composed of a single crystal Si layer and a SiGe layer (hereinafter referred to as “single crystal Si / It is also expressed as “SiGe / Si layer region”.

  Further, the NPN bipolar transistor 100 has an insulating film 40 above the single crystal Si / SiGe / Si layer region. This insulating film 40 has a structure in which a silicon thermal oxide film 41 formed on a single crystal Si / SiGe / Si layer region and a CVD silicon oxide film 42 formed on the silicon thermal oxide film 41 are laminated. Yes. A polysilicon film 43 is formed on the CVD silicon oxide film 42. The silicon thermal oxide film 41 is a silicon oxide film having an emitter opening and formed by thermal oxidation. The CVD silicon oxide film 42 is a silicon oxide film having an emitter opening and formed by a CVD method. The polysilicon film 43 is a polysilicon film having an emitter opening. Here, the density of the silicon thermal oxide film 41 is higher than the density of the CVD silicon oxide film 42.

  The NPN bipolar transistor 100 is formed on the polysilicon film 43 and fills the emitter opening and contacts the base layer 30 (specifically, the single crystal Si / SiGe / Si layer region). It has. Further, sidewalls 59 made of a silicon oxide film are formed on the side surfaces of the silicon thermal oxide film 41, the CVD silicon oxide film 42, the polysilicon film 43, and the emitter electrode 50, respectively. A cobalt silicide (CoSi) layer 61 is formed on the emitter electrode 50, on the polycrystalline Si / SiGe / Si layer region of the base layer 30, and on the single crystal Si region of the collector contact region 14, respectively. .

  Further, an interlayer insulating film 65 made of a silicon oxide film covering the CoSi layer 61 and the shallow trench 21 is formed above the Si substrate 1. In the interlayer insulating film 65, tungsten (W) plugs that penetrate the interlayer insulating film 65 and are electrically connected to the respective CoSi layers 61 are formed. A metal wiring made of an aluminum (Al) alloy film that is electrically connected to each W plug is formed on the interlayer insulating film 65 having the W plug. More specifically, an emitter contact portion 71 is connected to the CoSi layer 61 formed on the emitter electrode 50 as the W plug. A base contact portion 73 is connected to the CoSi layer 61 formed on the polycrystalline Si / SiGe / Si layer region of the base layer 30. Further, a collect contact portion 75 is connected to the CoSi layer 61 formed on the single crystal Si region of the collector contact region 14. A metal wiring 81 is connected to the emitter contact portion 71. A metal wiring 83 is connected to the base contact portion 73. A metal wiring 85 is connected to the collect contact portion 75.

(Production method)
Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described.
2 to 15 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. FIG. 14 is an enlarged cross-sectional view of the main part. In this embodiment, an NPN bipolar transistor (HBT) having a heterojunction structure using Si / SiGe / Si as the base layer 30 will be described as an example. However, the present invention is not limited to this structure.

As shown in FIG. 2, first, a P-type silicon (Si) substrate 1 is prepared. Next, a thermal oxide film 3 having a thickness of about 100 mm is formed on the surface of the Si substrate 1. Next, a photoresist 5 is formed on the thermal oxide film 3 by lithography so as to open above the HBT formation region and cover other regions. Then, using this photoresist 5 as a mask, N-type impurities are ion-implanted into the Si substrate 1 at a high concentration. In this ion implantation process, arsenic or phosphorus is used as the N-type impurity. The dose amount for ion implantation is about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . After this ion implantation, the photoresist 5 is removed. Subsequently, the thermal oxide film 3 is removed by wet etching, and a single crystal Si layer is epitaxially grown on the surface of the Si substrate 1 by about 1 μm.

Next, as shown in FIG. 3, a thermal oxide film 7 having a thickness of about 100 mm is formed on the surface of the Si substrate 1. Then, a photoresist 9 is formed by lithography so as to open above the HBT formation region and cover other regions. Subsequently, N-type impurities are ion-implanted at a low concentration into the Si substrate 1 using the photoresist 9 as a mask. In this ion implantation process, arsenic or phosphorus is used as the N-type impurity. The dose amount for ion implantation is about 1 × 10 ¹² to 1 × 10 ¹³ cm ⁻² . After this ion implantation, the photoresist 9 is removed.

  Next, the entire Si substrate 1 is subjected to heat treatment at about 1200 ° C./60 min to activate and diffuse the N-type impurities implanted into the Si substrate 1. As a result, as shown in FIG. 4, a high concentration collector region (N + layer) 11 and a low concentration collector region (N− layer) 13 located on the high concentration collector region 11 are formed on the Si substrate 1. Thus, the collector region 10 composed of the high concentration collector region 11 and the low concentration collector region 13 is formed.

Next, as shown in FIG. 4, the element isolation layer 20 is constituted by a shallow trench 21 having a depth of about 0.3 μm constituted by a silicon oxide film, a non-doped polysilicon film and a silicon oxide film surrounding the non-doped polysilicon film. A deep trench 22 having a depth of about 6 μm is formed.
Next, as shown in FIG. 5, a silicon oxide film 23 having a film thickness of about 1000 mm and a polysilicon film 25 having a film thickness of about 1000 mm are deposited on the entire upper surface of the Si substrate 1 by CVD or the like. The polysilicon film 25 and the silicon oxide film 23 are partially removed from the HBT formation region by etching. Thereby, the surface of the low concentration collector region 13 is partially exposed.

  Next, as shown in FIG. 6, a base layer 30 is formed on the Si substrate 1. In the step of forming the base layer 30, for example, as shown in FIG. 7, a Si layer 31 having a thickness of about 300 mm, a silicon germanium (SiGe) layer 32 having a thickness of about 700 mm, and a Si layer 33 having a thickness of about 100 mm are formed in this order. Epitaxially grow. At this time, single crystal Si and SiGe grow on the single crystal Si substrate 1, and polycrystalline or amorphous Si and SiGe grow on the polysilicon film 25 shown in FIG. 6 and a silicon oxide film (not shown). In other words, single crystal Si and SiGe grow on the low concentration collector region 13 made of single crystal, and polycrystalline or amorphous Si and SiGe grow on the polysilicon film 25 and the shallow trench 21.

In the formation process of the base layer 30, boron is introduced into the SiGe layer 32 by, for example, in-situ doping. Thereby, the conductivity type of the SiGe layer 32 is changed to the P type.
Next, as shown in FIG. 8, a silicon oxide film (silicon thermal oxide film) 41 is formed on the base layer 30 using a thermal oxidation method, and subsequently, a CVD method is used on the silicon thermal oxide film 41. A silicon oxide film (CVD silicon oxide film) 42 is formed. The thickness of the silicon thermal oxide film 41 is preferably about 10 to 100 mm. The thickness of the CVD silicon oxide film 42 is preferably about 200 to 350 mm. Thus, the insulating film 40 formed by laminating the silicon thermal oxide film 41 and the CVD silicon oxide film 42 is formed. Thereafter, a polysilicon film 43 having a thickness of about 500 mm is deposited on the CVD silicon oxide film 42.

Hereinafter, a method for forming the silicon thermal oxide film 41 and the CVD silicon oxide film 42 will be briefly described.
In the present embodiment, the silicon thermal oxide film 41 is formed in a high temperature environment by, for example, a mixed gas or O ₂ gas containing oxygen (O ₂ ) and water (H ₂ O), and Si existing in the vicinity of the surface of the base layer 30. To form (i.e., thermally oxidized). More specifically, for example, dry oxidation that oxidizes the surface of the base layer 30 only with O ₂ gas, wet oxidation that oxidizes with a mixed gas containing oxygen (O ₂ ) and hydrogen (H ₂ ) (for example, pyrogenic oxidation). As a result, the above-described silicon thermal oxide film 41 is formed.

  In the present embodiment, the CVD silicon oxide film 42 is formed by using, for example, a low pressure CVD method. More specifically, the silicon oxide film is formed by using, for example, a high temperature low pressure deposition (HLD) method. When the CVD silicon oxide film 42 is formed, for example, TEOS (Tetra Ethyl Ortho Silicate) is used as the material.

  Next, as shown in FIG. 9, an opening pattern is formed in the polysilicon film 43 by lithography and dry etching. After the opening pattern is formed, the photoresist (not shown) is removed by ashing. Thereafter, the CVD silicon oxide film 42 and the silicon thermal oxide film 41 are sequentially opened by wet etching using the polysilicon film 43 having an opening pattern as a mask. As a result, an opening 45 having the base layer 30 as the bottom is formed in the HBT formation region through the polysilicon film 43, the CVD silicon oxide film 42, and the silicon thermal oxide film 41.

Next, as shown in FIG. 10, a non-doped polysilicon film 50 'serving as an emitter electrode is deposited on the Si substrate 1 to a thickness of about 2500 mm to fill the opening 45 by, eg, CVD. Then, N-type impurities are ion-implanted into the deposited polysilicon film 50 '. The dose of this ion implantation is about 5 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . Instead of depositing the non-doped polysilicon film 50 'and performing ion implantation, a so-called doped polysilicon film doped with phosphorus in-situ may be deposited.

Next, the polysilicon film 50 'is patterned by lithography and dry etching. Thereby, as shown in FIG. 11, the emitter electrode 50 made of the polysilicon film 50 'is formed. Subsequently, in order to reduce the resistance of the external base region (that is, the region for drawing out the effective base region to the outside) while leaving the photoresist 53 on the emitter electrode 50, the base layer 30 is exposed from under the emitter electrode 50. Boron or BF ₂ is ion-implanted into the exposed region at a dose of about 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² . Thereafter, the photoresist 53 is removed from the emitter electrode 50.

Next, as shown in FIG. 12, the insulating film 40 and the base layer 30 are patterned by lithography and dry etching to form an external base region 37 in the base layer 30. Thereafter, the photoresist (not shown) used for patterning the insulating film 40 and the base layer 30 is removed.
Next, as shown in FIG. 13, a silicon oxide film 55 having a thickness of about 100 mm is formed above the Si substrate 1. Then, a photoresist 57 is formed by lithography so as to open above the contact region (that is, collector contact region) 14 of the low concentration collector region 13 and cover the other regions. Next, arsenic is ion-implanted with a dose of about 1 × 10 ^{15 to} 5 × 10 ¹⁵ cm ⁻² using the photoresist 57 as a mask. Thereafter, the photoresist 57 is removed.

  Next, annealing is performed on the entire Si substrate 1 at a temperature of about 950 ° C./hour for about 10 seconds. As a result, as shown in FIG. 14, the N-type impurity contained in the emitter electrode 50 made of the polysilicon film 50 ′ is diffused from the emitter electrode 50 to the base layer 30, so that the low concentration collector region of the base layer 30. An emitter region 39 is formed in an upper portion (for example, the Si layer 33 shown in FIG. 7) away from the region.

During this annealing, hydrogen (H) atoms taken into the silicon thermal oxide film 41 when the silicon thermal oxide film 41 is formed also diffuse from the silicon thermal oxide film 41 to the base layer 30. The dangling bonds existing in the vicinity of the interface between the silicon thermal oxide film 41 and the base layer 30 can be terminated by the diffusing H atoms.
Next, a silicon oxide film is deposited on the upper side of the Si substrate 1 by about 300 mm, and then an anisotropic etch back is performed on the silicon oxide film. Thereby, as shown in FIG. 15, sidewalls 59 that cover the respective sidewalls of the emitter electrode 50, the polysilicon film 43, the CVD silicon oxide film 42, the silicon thermal oxide film 41, and the base layer 30 are formed. Note that the CVD silicon oxide film 42 and the silicon thermal oxide film 41 are also removed during the formation of the sidewalls.

  Next, due to self-aligned silicide, the exposed surface of the emitter electrode 50, the exposed surface of the external base region 37, and the exposed surface of the low-concentration collector region 13 (that is, the collector contact region 14). The CoSi layer 61 is formed on each of the surfaces. In the subsequent steps, a standard multilayer wiring process is used to make electrical connection between the elements. That is, as shown in FIG. 1, an interlayer insulating film 65 is formed, contact holes are formed through the interlayer insulating film 65 and each CoSi layer 61 is a bottom surface, and an electrode material is embedded in each of these contact holes. Thereby, the emitter contact portion 71 electrically connected to the emitter electrode 50, the base contact portion 73 electrically connected to the external base region 37, and the low concentration collector region 13 (collector contact region 14) are electrically connected. And a collector contact portion 75 to be formed.

  Finally, a metal wiring film (not shown) is formed on the interlayer insulating film 65 on which the emitter contact portion 71, the base contact portion 73, and the collector contact portion 75 are formed, and the metal wiring film is patterned. In this way, as shown in FIG. 1, metal wirings 81, 83, and 85 that are electrically connected to the emitter contact portion 71, the base contact portion 73, and the collector contact portion 75 are formed.

Through the above steps, a semiconductor device including the NPN bipolar transistor 100 having a heterojunction structure with reduced β variation is completed.
In this embodiment, the high concentration collector region 11 and the low concentration collector region 13 correspond to the collector region of the present invention. The silicon thermal oxide film 41 and the CVD silicon oxide film 42 correspond to the insulating film of the present invention. Further, the NPN bipolar transistor 100 having a heterojunction structure corresponds to the bipolar transistor of the present invention.

(Effect of embodiment)
The embodiment of the present invention has the following effects.
(1) The insulating film 40 formed on the base layer 30 and covering the junction between the base layer 30 and the emitter region 39 includes at least a silicon thermal oxide film 41 formed on the base layer 30. Since this silicon thermal oxide film 41 is formed by thermal oxidation of Si, unnecessary impurities remain less as compared with a silicon oxide film formed by, for example, the CVD method. For this reason, it is possible to suppress the generation of interface states at the interface between the base layer 30 and the emitter region 39 and at the interface with the insulating film 40. Therefore, in the semiconductor device including the bipolar transistor 100, it is possible to sufficiently obtain the effect of reducing the β variation due to the reduction of the interface state (that is, to further reduce the β variation by reducing the interface state).

Further, when the N-type impurities are annealed and diffused from the emitter electrode 50 to the base layer 30 side, H atoms taken into the silicon thermal oxide film 41 when the silicon thermal oxide film 41 is formed are SiGe layers 32 of the base layer 30. It reaches the vicinity of the interface (Si / SiO ₂ interface) between the Si layer 33 formed above and the silicon thermal oxide film 41 (SiO ₂ layer). Thereby, dangling bonds existing at the interface can be effectively terminated with H atoms. Therefore, according to the present embodiment, for example, an insulating film having fewer interface states can be formed as compared with a case where a silicon oxide film is formed by using the CVD method. Therefore, the interface state existing at the interface can be sufficiently and stably reduced. Therefore, in the semiconductor device including the bipolar transistor 100, it is possible to sufficiently obtain the β variation reduction effect due to the reduction of the interface state.

  Furthermore, the silicon thermal oxide film 41 is formed at normal pressure (atmospheric pressure) without using plasma. Thereby, since surface defects of the base layer 30 caused by plasma can be reduced, it is possible to suppress the generation of interface states at the interface between the base layer 30 and the emitter region 39 and at the interface with the insulating film 40. it can. Therefore, in the semiconductor device including the bipolar transistor 100, it is possible to sufficiently obtain the β variation reduction effect due to the reduction of the interface state.

(2) The insulating film 40 further includes a silicon oxide film formed on the silicon thermal oxide film 41. That is, the insulating film 40 is a silicon oxide film having a laminated structure. Thereby, compared with the case where a silicon oxide film is not laminated | stacked, insulation can be improved more. Therefore, the emitter region 39 provided in the base layer 30 can be formed in a predetermined region.

(3) The silicon oxide film formed on the silicon thermal oxide film 41 is a CVD silicon oxide film 42. For this reason, the laminated silicon oxide film can be formed by using a known CVD method. Therefore, the silicon oxide film can be formed with increased reliability. Further, by using a known technique (general-purpose technique), it is possible to suppress an increase in the manufacturing cost of the semiconductor device including the bipolar transistor 100.

(4) The density of the silicon thermal oxide film 41 is higher than the density of the CVD silicon oxide film 42. Therefore, unnecessary impurities contained in the CVD silicon oxide film 42 reach the junction between the base layer 30 and the emitter region 39 and the vicinity of the interface with the insulating film 40 through the silicon thermal oxide film 41. Can be reduced. Therefore, generation of interface states due to impurities in the vicinity of the interface can be suppressed. Therefore, in the semiconductor device including the bipolar transistor 100, it is possible to sufficiently obtain the β variation reduction effect due to the reduction of the interface state.

(Modification)
(1) In the above embodiment, the case where the CVD silicon oxide film 42 is formed on the silicon thermal oxide film 41 has been described. However, in the present invention, the silicon oxide film formed on the silicon thermal oxide film 41 is not limited to the CVD silicon oxide film 42. The silicon oxide film on the silicon thermal oxide film 41 may be, for example, a silicon oxide film formed using a solution. Even in such a case, the same effects as the effects (1) to (4) of the embodiment are obtained.

(2) In the above embodiment, the case where the bipolar transistor of the present invention is an NPN bipolar transistor having a heterojunction structure has been described. However, the bipolar transistor is not limited to this in the present invention.
For example, the bipolar transistor of the present invention may be a PNP bipolar transistor having a heterojunction structure. In that case, in the above-described embodiment, the conductivity type of the impurity contained in each semiconductor layer may be replaced with P-type for N-type and N-type for P-type. Even in such a case, the same effects as the effects (1) to (4) of the embodiment are obtained.

<Others>
The present invention is not limited to the embodiment described above. Based on the knowledge of those skilled in the art, design changes and the like can be made to the embodiments, and such a modified embodiment is also included in the scope of the present invention. In other words, the present invention can be implemented with various modifications within the scope of the gist. In the drawings, positional relationships such as up, down, left and right are based on the positional relationships shown in the drawings unless otherwise specified. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios.

DESCRIPTION OF SYMBOLS 1 Substrate 3, 7 Thermal oxide film 5, 9, 53, 57 Photoresist 10 Collector region 11 High concentration collector region 13 Low concentration collector region 14 Collector contact region 20 Element isolation layer 21 Shallow trench 22 Deep trench 23, 55 Silicon oxide ( SiO ₂ ) film 25, 43 polysilicon film 30 base layer 31 Si layer 32 SiGe layer 33 Si layer 35 effective base region 37 external base region 39 emitter region 40 insulating film 41 silicon thermal oxide film 42 CVD silicon oxide film 45 opening 50 Emitter electrode 50 ′ Polysilicon film 59 Side wall 61 CoSi layer 65 Interlayer insulating film 71 Emitter contact part 73 Base contact part 75 Collector contact parts 81, 83, 85 Metal wiring 100 NPN bipolar transistor having a heterojunction structure

Claims (7)

A semiconductor device comprising a bipolar transistor using a polysilicon film as an emitter electrode,
The bipolar transistor is:
A collector region formed in the substrate;
A base layer formed on the collector region;
An emitter region formed in an upper portion of the base layer away from the collector region;
An insulating film formed on the base layer and covering a junction between the base layer and the emitter region;
The semiconductor device, wherein the insulating film includes at least a silicon thermal oxide film formed on the base layer.   The semiconductor device according to claim 1, wherein the insulating film further includes a silicon oxide film formed on the silicon thermal oxide film.   3. The semiconductor device according to claim 2, wherein the silicon oxide film is a CVD silicon oxide film formed using a CVD method.   4. The semiconductor device according to claim 2, wherein a density of the silicon thermal oxide film is higher than a density of the silicon oxide film. A method of manufacturing a semiconductor device comprising a bipolar transistor using a polysilicon film as an emitter electrode,
Forming a collector region on the substrate;
Forming a base layer on the collector region;
Forming a silicon thermal oxide film on the base layer;
Forming a silicon oxide film on the silicon thermal oxide film;
Forming a polysilicon film on the silicon oxide film;
Partially etching the polysilicon film, the silicon oxide film, and the silicon thermal oxide film to form an opening having the base layer as a bottom surface;
And a step of introducing an impurity into the base layer through the opening to form an emitter region in an upper portion of the base layer away from the collector region.   6. The method of manufacturing a semiconductor device according to claim 5, wherein the silicon oxide film is a CVD silicon oxide film formed using a CVD method.   7. The method of manufacturing a semiconductor device according to claim 5, wherein the density of the silicon thermal oxide film is higher than the density of the silicon oxide film.

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