JP2015095979A - Power supply voltage interruption circuit for adjusting supply voltage to mixed circuit with linear ic and logic ic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress a malfunction in a circuit having a linear IC and a logic IC mixed.SOLUTION: The power supply voltage interruption circuit 1200, adjusting an input voltage into a mixed circuit 1000 having a linear IC and a logic IC, is made to serve as a power supply voltage interruption circuit that inhibits transmission of the input voltage into the mixed circuit when the input voltage is smaller than a predetermined voltage (V). Preferably, at a pre-stage of the mixed circuit, there is provided a Zener diode that inhibits transmission of the input voltage into the mixed circuit when the input voltage is smaller than the predetermined voltage (V).

Description

  The present invention relates to a power supply voltage cutoff circuit that adjusts a supply voltage to a mixed circuit including a linear IC and a logic IC, and a mixed circuit including the same.

  Light and miniaturized light by integrating analog ICs such as light-emitting element drive circuits and received signal amplifiers and logic circuit ICs that perform digital processing into a single chip, together with a light-emitting element and a light-receiving element. The invention aims to provide an optical communication device that constitutes a transmission / reception unit of a communication system, wherein a light emitting element for transmitting a signal, a drive circuit for driving the light emitting element, and a signal from the outside are received. A light receiving element; an amplifier circuit that amplifies a signal received by the light receiving element; and a logic circuit that modulates a signal to the drive circuit and demodulates a signal from the amplifier circuit, the drive circuit, the amplifier circuit, and An optical communication device in which a logic circuit is formed by a one-chip IC, and the IC, the light emitting element, and the light receiving element are incorporated in one package. The following Patent Document 1 describes that the wiring connecting each circuit does not extend or exposed long, so that it is possible to obtain a high-quality transmitting / receiving unit without being picked up noise and to be downsized. ing.

  According to Patent Document 1, each circuit necessary as a transmission / reception unit of an optical communication system is integrated into one chip together with a light emitting element and a light receiving element, so that connection wiring between the circuits is not exposed and the influence of noise is exerted. An optical communication device with excellent performance that is difficult to receive is obtained, and the lens part is integrally formed, so that the directivity of the light emitting / receiving element can be stably obtained, and an optical communication device that satisfies the standard can be easily obtained. Furthermore, since all the parts are packaged in one package, the size can be reduced. For example, the size is 1/4 to 1/5 of the conventional size, 12 mm × 5.5 mm × 4.5 mm ( It is described that it can be as large as (thickness).

JP 09-284217 A

  It is known that malfunctions occur when a voltage is applied in a circuit in which a linear IC and a logic IC are mixedly mounted. For example, in the system organizer IC of the block diagram illustrated in FIG. 6 equipped with the microcomputer reset function and the reference voltage output, the output waveform (VOUT) at power-on and the output waveform (VOUT) at power-off are shown in FIG. As shown, an unexpected waveform due to malfunction is observed.

  FIG. 6 shows a delay time of 50, 100 ms (adjustable by resistance), a reset detection voltage of 2.745 V ± 1%, a high-precision reference voltage of 3.050 V ± 0.8%, and a manual It is a block diagram explaining an example of the mixed circuit of linear IC and logic IC equipped with the reset function and sleep mode.

  FIG. 7 shows the power supply monitoring and reset circuit for the microprocessor, AD-DA conversion circuit, personal computer and its peripheral devices, digital camera, digital video camera, various PDAs, and other various industrial devices. 6 is a timing chart illustrating waveforms of a mixed circuit of a linear IC and a logic IC shown.

  The malfunction in the mixed circuit of the linear IC and the logic IC described above is caused by erroneous reaction at the voltage rising stage before the linear IC is within the original operating voltage range, etc., and is connected to the subsequent stage. It is considered that the logic IC that receives the erroneous response output of the linear IC outputs an incorrect output.

  Such malfunction at the initial stage of voltage application, for example, transmits an erroneous electrical signal to various electronic devices connected to the subsequent stage of the logic IC, and hinders an accurate desired operation of the entire circuit. Since it is obtained, it is not preferable.

  The present invention has been made in view of the above-described problems, and an object thereof is to reduce malfunctions in a circuit in which a linear IC and a logic IC are mixedly mounted.

The power supply voltage cut-off circuit of the present invention is a power supply voltage cut-off circuit that adjusts the supply voltage to a mixed circuit including a linear IC and a logic IC, and when the supply voltage is smaller than a predetermined voltage (V _z ) It is characterized in that transmission of supply voltage to the circuit is prevented.

Further, the mixed circuit including the linear IC and the logic IC according to the present invention is more preferably characterized in that the supply voltage is a DC voltage.
In the hybrid circuit including the linear IC and the logic IC according to the present invention, the predetermined voltage (V _z ) is more preferably larger than the lower limit voltage of the linear IC operable range and smaller than the operation start voltage of the linear IC. It is characterized by that.

  It is possible to reduce malfunctions in a circuit in which a linear IC and a logic IC are mixedly mounted.

It is a block diagram explaining the structure outline | summary of the hybrid circuit provided with the linear IC and logic IC concerning 1st embodiment of this invention. A chart for explaining an outline of a relative relationship at the time of voltage rise between an input voltage (V _in ) to a power supply voltage cutoff circuit of a mixed circuit including a linear IC and a logic IC and a supply voltage (V _cc ) to the IC unit FIG. 4A is a diagram showing an input voltage (V _in ) to a power supply voltage cutoff circuit, and FIG. 4B is a diagram showing a supply voltage (V _cc ) to an IC unit. A linear IC supply voltage to the IC unit of the hybrid circuit and a logic IC _{(V cc),} an analog power monitoring section of the linear IC output voltage _{(V o} (linear)), a logic IC in the output voltage _{(V o} (Logic)), that is, a chart for explaining an outline of the relative relationship between the output voltage (V _o (logic)) of the IC unit and (a) an IC unit of a mixed circuit including a linear IC and a logic IC shows the supply voltage _{(V cc)} to, (b) is an analog power supply monitoring unit of the linear IC output voltage _{(V o} (linear)) indicates, (c) the output voltage of the logic IC _{(V o} (logic) ) That is, the output voltage (V _o (logic)) of the IC section. It is a block diagram explaining the structure of the conventional mixed circuit for comparing with the mixed circuit provided with the linear IC and logic IC concerning 1st embodiment of this invention. The input voltage (V _in ) to the IC unit of the conventional mixed circuit including the linear IC and the logic IC, the output voltage (V _o (linear)) of the linear IC of the analog power supply monitoring unit, and the output voltage of the logic IC ( V _o (logic)), that is, a chart for explaining an outline of the relative relationship between the output voltage of the IC section (V _o (logic)) and (a) a conventional mixed mounting including a linear IC and a logic IC. The input voltage (V _in ) to the IC part of the circuit is shown, (b) shows the output voltage (V _o (linear)) of the linear IC of the analog power supply monitoring part, and (c) shows the output voltage (V) of the logic IC. _o (logic)), that is, the output voltage (V _o (logic)) of the IC section. Delay time is 50,100ms (adjustable by resistance), reset detection voltage is 2.745V ± 1%, high precision reference voltage is 3.050V ± 0.8%, manual reset function and sleep It is a block diagram explaining an example of a mixed circuit of a linear IC and a logic IC mounted with a mode. Microprocessor power supply monitoring and reset circuit, AD-DA conversion circuit, personal computer and its peripherals, digital cameras and digital video cameras, various PDAs, other various industrial devices, etc. 5 is a timing chart for explaining the waveform of the embedded circuit.

  The mixed circuit including the linear IC and the logic IC described in the present embodiment includes a power supply voltage cutoff circuit that cuts off the input voltage when the input voltage is smaller than a predetermined value in the preceding stage.

  The power supply voltage cut-off circuit transmits the input voltage to the mixed circuit only when the input voltage is equal to or higher than a predetermined voltage value. In this case, the predetermined voltage value is set to a value lower than the threshold voltage of the IC and a value equal to or higher than a voltage causing malfunction. By setting the voltage of the Zener diode 1260 that cuts off the input voltage to a value lower than the threshold voltage of the IC, it is possible to prevent malfunction and to operate the IC normally.

  Thus, for example, when the power is turned on, the operation of the embedded circuit starts normally without delay after the input voltage is transmitted to the embedded circuit, and when the power is shut down, the operation of the embedded circuit is normally stopped. After that, the input voltage is cut off without delay.

  Therefore, when the power is turned on or when the power is shut down, it is possible to reduce the state in which an input voltage that is lower than the lower limit of the operation range of the embedded circuit is input to the embedded circuit, It is possible to avoid malfunction of the linear IC and / or logic IC that occurs in a state of being input to the mixed circuit.

  In other words, in a conventional circuit in which a linear IC and a logic IC are mixed, the linear IC malfunctions at a value lower than the voltage driven when the input voltage is applied, and the logic IC reacts to it at an incorrect timing. Will cause on-off. Therefore, a circuit that does not cause malfunction immediately after the input voltage is applied is required.

  For example, the circuit of FIG. 4 malfunctions when an input voltage is applied as shown in FIG. In order to prevent malfunction, in this embodiment, a power supply voltage cutoff circuit using a Zener diode, a PNP transistor, and an NPN transistor is inserted before the linear IC and logic IC as shown in FIG.

  As a result, the PNP and NPN transistors are driven only when the input voltage becomes higher than the Zener voltage of the Zener diode. That is, as shown in FIG. 2 and FIG. 3, a voltage smaller than the breakdown voltage (zener voltage) of the Zener diode is such that no voltage is applied to the linear IC and logic IC.

  Further, when an input voltage lower than the Zener voltage of the Zener diode is applied, the PNP transistor and the NPN transistor are not driven, so that no voltage is applied to the linear IC and the logic IC.

  However, when an input voltage equal to or higher than the Zener voltage of the Zener diode is applied, the PNP transistor is driven because the base current of the PNP transistor flows. Further, when the PNP transistor is driven, the base current of the NPN transistor flows, so that a voltage is applied to the linear IC and the logic IC. This eliminates IC malfunctions at low input voltages. Accordingly, the embodiments will be sequentially described below with reference to the drawings as appropriate.

(First embodiment)
FIG. 1 is a block diagram illustrating an outline of a configuration of a mixed circuit 1000 including a linear IC and a logic IC according to the first embodiment of the present invention. As shown in FIG. 1, a mixed circuit 1000 including a linear IC and a logic IC includes a power supply unit 1300, a power supply voltage cutoff circuit 1200, and an IC unit 1100 in this order.

  The power supply unit 1300 includes a DC voltage source 1310 such as a secondary battery or a DC-DC converter, a smoothing capacitor 1320 arranged in parallel with the DC voltage source 1310, and a power supply resistor 1330 arranged in series with the DC voltage source 1310. Is provided.

  Further, the IC unit 1100 includes an analog power supply monitoring unit 1110 that monitors input power and a logic IC unit 1120 in order. The analog power supply monitoring unit 1110 includes, for example, a linear IC 1111 such as a comparator, three analog power supply monitoring resistors 1113, 1114, and 1115, and an analog power supply monitoring zener diode 1112.

  The analog power supply monitoring unit 1110 that monitors the input power supplies the voltage to the linear IC 1111 only when the input voltage is larger than an arbitrary voltage value determined by the Zener voltage of the analog power supply monitoring Zener diode 1112, and the linear IC 1111 is supplied. Can be driven.

The output voltage V _o (linear) from the linear IC 1111 that is driven by the input voltage is input to the logic IC 1121 and the logic IC 1121 is driven based on this input.

  As is apparent from FIG. 1, the analog power supply monitoring resistor 1114 and the analog power supply monitoring resistor 1115 are connected in series with each other, and the serially connected ones are arranged in parallel with the input. Similarly, the analog power supply monitoring resistor 1113 and the cathode of the analog power supply monitoring zener diode 1112 are connected in series, and the serially connected ones are arranged in parallel to the input.

  A connection node between the analog power supply monitoring resistor 1114 and the analog power supply monitoring resistor 1115 and a connection node between the analog power supply monitoring resistor 1113 and the cathode of the analog power supply monitoring Zener diode 1112 are both input to the linear IC 1111. Is done.

  As shown in FIG. 1, the power supply voltage cutoff circuit 1200 includes a Zener diode 1260 having an anode connected to the ground, a first resistor 1250 having one end connected to the cathode of the Zener diode 1260, and a first resistor 1250. And a PNP transistor 1210 having a base connected to the other end.

  As shown in FIG. 1, the collector of the PNP transistor 1210 is connected to the base of the NPN transistor 1220 via the second resistor 1230, and the collector of the NPN transistor 1220 and the emitter of the PNP transistor 1210 are connected. To do. As shown in FIG. 1, a third resistor 1240 is connected between the emitter and base of the PNP transistor 1210.

Further, in FIG. 1, the input voltage (V _in ) from the power supply unit 1300 is input between the ground of the power supply voltage cutoff circuit 1200, that is, the anode of the Zener diode 1260 and the emitter of the PNP transistor 1210.

Further, when the input voltage (V _in ) is smaller than the Zener voltage of the Zener diode 1260, the power supply voltage cutoff circuit 1200 is not driven because both the PNP transistor 1210 and the NPN transistor 1220 are turned off. An input voltage (V _in ) smaller than the zener voltage of 1260 is not output to the IC unit 1100.

On the other hand, if the input voltage (V _in ) is not smaller than the Zener voltage (V _z ) of the Zener diode 1260, the PNP transistor 1210 and the NPN transistor 1220 are both turned on and driven. 1200 outputs to the IC unit 1100 an input voltage (V _in ) that is not smaller than the Zener voltage of the Zener diode 1260.

As a result, only the input voltage (V _in ) that is not smaller than the Zener voltage of the Zener diode 1260 is applied to the linear IC 1111 and the logic IC 1121 of the IC unit 1100. It is possible to reduce a concern that a voltage that is lower than the operable lower limit of the IC unit 1100 is applied to the IC unit 1100.

FIG. 2 shows the relative relationship between the input voltage (V _in ) to the power supply voltage cutoff circuit 1200 of the hybrid circuit 1000 including the linear IC and the logic IC and the supply voltage (V _cc ) to the IC unit 1100 at the time of voltage rise. FIG. 6 is a chart for explaining a general relationship outline, in which (a) shows the input voltage (V _in ) to the power supply voltage cutoff circuit 1200 and (b) shows the supply voltage (V _cc ) to the IC unit 1100. is there.

As can be understood from FIG. 2, when a power switch (not shown) of the power supply unit 1300 is turned on and the power is turned on, the input voltage (V _in ) to the power supply voltage cutoff circuit 1200 starts to gradually increase from zero. However, the supply voltage (V _cc ) to the IC unit 1100 remains zero for a while after the input voltage (V _in ) to the power supply voltage cutoff circuit 1200 starts to gradually increase from zero.

Then, the time in _{(T a),} the input voltage to the power supply voltage blocking circuit 1200 _{(V in)} is equal to or Zener voltage of the Zener diode 1260 _{(V z),} the Zener voltage _{(V z)} of the IC unit 1100 is applied as a supply voltage _{(V cc),} then the supply voltage _{(V cc)} to the IC unit 1100 in response to the rise of the input voltage to the power supply voltage blocking circuit 1200 _{(V in)} to the power supply voltage (V) To rise.

Further, FIG. 3 shows a supply voltage (V _cc ) to the IC unit 1100 of the embedded circuit 1000 including a linear IC and a logic IC, and an output voltage (V _o (linear)) of the linear IC 1111 of the analog power supply monitoring unit 1110. FIG. 4 is a chart for explaining an outline of a relative relationship between the output voltage (V _o (logic)) of the logic IC 1121, that is, the output voltage (V _o (logic)) of the IC unit 1100, and FIG. The supply voltage (V _cc ) to the IC unit 1100 of the embedded circuit 1000 including the logic IC is shown, (b) shows the output voltage (V _o (linear)) of the linear IC 1111 of the analog power supply monitoring unit 1110, (c ) is a diagram showing the output voltage of the logic IC1121 _{(V o} (logic)) or output voltage of the IC unit 1100 _{(V o} (logic)).

As shown in FIG. 3, the supply voltage (V _cc ) to the IC unit 1100 rises to the Zener voltage (V _z ) of the Zener diode 1260 at time (T _a ), but the Zener diode 1112 for analog power supply monitoring The IC unit 1100 is not driven until a predetermined threshold voltage value (V _th ) determined by the voltage is reached (between T _{a and} T _b ).

For this reason, the output of the linear IC 1111 of the analog power supply monitoring unit 1110 is until the predetermined threshold voltage value (V _th ) determined by the Zener voltage of the analog power supply monitoring Zener diode 1112 (between T _{a and} T _b ). a voltage _{(V o} (linear)), and the output voltage of the logic IC1121 _{(V o} (logic)) or output voltage of the IC unit 1100 _{(V o} (logic)), both remain zero.

Further, as shown in FIG. 3, at time (T _b ), the supply voltage (V _cc ) to the IC unit 1100 is set to a predetermined threshold voltage value (V) determined by the Zener voltage of the analog power supply monitoring Zener diode 1112 or the like. _th ) or more, voltage is applied to the linear IC 1111 and its driving is started, and the output voltage (V _o (linear)) of the linear IC 1111 of the analog power supply monitoring unit 1110 and the output voltage (V _o (logic) of the logic IC 1121. In other words, the output voltage (V _o (logic)) of the IC unit 1100 is output.

  That is, in the present invention, a two-stage configuration is provided by two Zener diodes, namely, an analog power supply monitoring Zener diode 1112 of the analog power supply monitoring unit 1110 and a Zener diode 1260 of the power supply voltage cutoff circuit 1200 provided in the preceding stage. Therefore, a circuit configuration that restricts voltage input to the linear IC 1111 is employed.

  In other words, the Zener diode 1260 of the power supply voltage cutoff circuit 1200 determines the voltage applied to the analog power supply monitoring unit 1110, and the analog power supply monitoring Zener diode 1112 and the like of the analog power supply monitoring unit 1110 are included in the IC unit 1100. It determines the operating lower limit voltage.

Therefore, as illustrated in FIG. 3, the Zener voltage (V _z ) of the Zener diode 1260 of the power supply voltage cutoff circuit 1200 that determines the voltage applied to the analog power supply monitoring unit 1110 determines the operating voltage of the IC unit 1100. The voltage value is preferably smaller than a predetermined threshold voltage value (V _th ) determined by the analog power supply monitoring Zener diode 1112 of the analog power supply monitoring unit 1110 or the like.

  FIG. 4 is a block diagram illustrating a configuration of a conventional embedded circuit 4000 for comparison with the embedded circuit 1000 including the linear IC and the logic IC according to the first embodiment of the present invention. As shown in FIG. 4, a mixed circuit 4000 including a linear IC and a logic IC includes a power supply unit 4300 and an IC unit 4100 in order.

  The power supply unit 4300 includes a DC voltage source 4310 such as a secondary battery or a DC-DC converter, a smoothing capacitor 4320 arranged in parallel with the DC voltage source 4310, and a power supply resistor 4330 arranged in series with the DC voltage source 4310. Is provided.

  The IC unit 4100 includes an analog power supply monitoring unit 4110 that monitors input power and a logic IC unit 4120 in order. The analog power supply monitoring unit 4110 includes, for example, a linear IC 4111 such as a comparator, three analog power supply monitoring resistors 4113, 4114, and 4115, and an analog power supply monitoring zener diode 4112.

  The analog power supply monitoring unit 4110 that monitors the input power supplies the voltage to the linear IC 4111 only when the input voltage is larger than an arbitrary voltage value determined by the Zener voltage of the analog power supply monitoring Zener diode 4112. Can be driven.

The output voltage V _o (linear) from the linear IC 4111 driven by the input voltage is input to the logic IC 4121, and the logic IC 4121 is driven based on this input.

  As is apparent from FIG. 4, the analog power supply monitoring resistor 4114 and the analog power supply monitoring resistor 4115 are connected in series with each other, and the serially connected ones are arranged in parallel with the input. Similarly, the analog power supply monitoring resistor 4113 and the cathode of the analog power supply monitoring Zener diode 4112 are connected in series, and the serially connected ones are arranged in parallel with the input.

  A connection node between the analog power supply monitoring resistor 4114 and the analog power supply monitoring resistor 4115 and a connection node between the analog power supply monitoring resistor 4113 and the cathode of the analog power supply monitoring Zener diode 4112 are both input to the linear IC 4111. Is done.

FIG. 5 shows an input voltage (V _in ) to an IC unit 4100 of a conventional mixed circuit 4000 including a linear IC and a logic IC, and an output voltage (V _o (linear)) of a linear IC 4111 of an analog power supply monitoring unit 4110. FIG. 4 is a chart for explaining an outline of a relative relationship between the output voltage (V _o (logic)) of the logic IC 4121, that is, the output voltage (V _o (logic)) of the IC unit 4100, and FIG. The input voltage (V _in ) to the IC unit 4100 of the conventional mixed circuit 4000 having a logic IC is shown, (b) shows the output voltage (V _o (linear)) of the linear IC 4111 of the analog power supply monitoring unit 4110, is a diagram showing a (c) is the output voltage of the logic IC4121 _{(V o} (logic)) or output voltage _{(V o} (logic)) of the IC 4100

As can be understood from FIG. 5, the input voltage (V _in ) to the IC unit 4100 is considerably smaller than the voltage in the normal operating range of the IC unit 4100 (determined by the analog power supply monitoring Zener diode 4112). The voltage is supplied to the IC unit 4100 from the initial stage of voltage rise.

For this reason, the output voltage (V _o (linear)) of the linear IC 4111 of the analog power supply monitoring unit 4110 when a voltage smaller than the lower limit voltage at which the IC unit 4100 determined by the analog power supply monitoring Zener diode 4112 can operate normally is applied. the voltage waveform manifested by malfunction in, correspondingly, the voltage waveform due to even malfunction in the output voltage of the logic IC4121 _{(V o} (logic)) or output voltage of the IC unit 4100 _{(V o} (logic)) It will be manifested.

  Such a malfunction is known to occur both when the voltage rises and when it falls, increasing the concern that an unexpected malfunction of the circuit will occur when the power is turned on or when the power is shut down. It has become.

  In addition, the IC unit 4100 operates normally when a voltage within the normal operable range shown as “linear IC operation range” in FIG. 5 is input, but is smaller than the lower limit of the normal operable range. When voltage is input, malfunction may occur.

  Therefore, in the mixed circuit 1000 of the present embodiment, the power supply voltage cutoff circuit 1200 determines whether or not the input voltage value is smaller than the lower limit voltage of the normal operable range of the IC unit 1100, and the voltage value higher than that. The voltage is input to the IC unit 1100 only when

  For example, the operation range of the linear IC is 0 V to 6.5 V, the analog power supply reference Zener voltage is 3 V, the threshold voltage value (Vth) is 2.72 V to 2.78 V, and the Zener voltage (Vz) is 2 Assuming that the voltage is .4V, if there is no limiting circuit including the Zener diode 1260 and the transistors 1220 and 1230, the linear IC malfunctions at the timing when the input voltage is applied. However, by incorporating the circuit of this embodiment, a voltage lower than the zener voltage is not applied to the IC, and malfunction can be prevented. Here, it is assumed that the minimum value of the operation range of the linear IC <= Zener voltage (1260) <= IC threshold voltage.

The power supply voltage cutoff circuit of the present invention is a power supply voltage cutoff circuit that adjusts an input voltage to a mixed circuit including a linear IC and a logic IC, and when the input voltage is smaller than a predetermined voltage (V _z ) It is characterized by preventing the transmission of the input voltage to the circuit.

In addition, the power supply voltage cutoff circuit of the present invention preferably includes a Zener diode that prevents transmission of the input voltage to the embedded circuit before the embedded circuit when the input voltage is smaller than a predetermined voltage (V _z ). Features.

  In the power supply voltage cutoff circuit of the present invention, more preferably, the base of the PNP transistor is connected to the cathode of the Zener diode via the first resistor, and the base is connected to the collector of the PNP transistor via the second resistor. And an NPN transistor.

  The power supply voltage cutoff circuit of the present invention is more preferably characterized in that the emitter of the PNP transistor and the collector of the NPN transistor are connected.

  The power supply voltage cutoff circuit according to the present invention further includes a third resistor connected between the emitter and base of the PNP transistor.

In the power supply voltage cutoff circuit according to the present invention, more preferably, when the input voltage is smaller than the predetermined voltage (V _z ), neither the PNP transistor nor the NPN transistor is driven, and the input voltage is the predetermined voltage (V _z). If not smaller, the PNP transistor and the NPN transistor are both driven.

The power supply voltage cutoff circuit of the present invention is more preferably characterized in that the predetermined voltage (V _z ) is a Zener voltage.

  In addition, a mixed circuit including the linear IC and the logic IC according to the present invention includes the power supply voltage cutoff circuit according to any one of the above-described items in the preceding stage.

  In the hybrid circuit including the linear IC and the logic IC according to the present invention, the linear IC preferably forms an analog power supply monitoring unit.

  The mixed circuit including the linear IC and the logic IC according to the present invention is more preferably characterized in that the linear IC is a comparator.

  Further, the mixed circuit including the linear IC and the logic IC according to the present invention is more preferably characterized in that the linear IC is arranged in the preceding stage of the logic IC.

Further, the mixed circuit including the linear IC and the logic IC according to the present invention is more preferably characterized in that the input voltage is a DC voltage.
In the hybrid circuit including the linear IC and the logic IC according to the present invention, the predetermined voltage (V _z ) is more preferably larger than the lower limit voltage of the linear IC operable range and smaller than the operation start voltage of the linear IC. It is characterized by that.

  The embedded circuit 1000 including the linear IC and the logic IC exemplified in the above-described embodiment is not limited to the description in the embodiment, but within the scope of the technical idea described in the embodiment and within the obvious range. The configuration, operation, operation method, and the like can be changed as appropriate. For convenience of explanation, the embodiments are individually described. However, the configurations of the embodiments may be applied in an appropriate combination, and the operations may be arranged in an appropriate combination.

  The hybrid circuit including the linear IC and the logic IC of the present invention includes various power supply systems, microprocessor power supply monitoring and reset circuits, AD-DA conversion circuits, personal computers and peripheral devices, digital cameras and digital video cameras, It can be widely applied as a configuration of various PDAs and other various industrial equipment.

  1000... Mixed circuit including linear IC and logic IC, 1100... IC section, 1200... Power supply voltage cutoff circuit, 1300.

Claims (7)

A power supply voltage cutoff circuit for adjusting an input voltage to a mixed circuit including a linear IC and a logic IC,
When the input voltage is smaller than a predetermined voltage (V _z ), transmission of the input voltage to the mixed circuit is blocked. The power supply voltage cutoff circuit according to claim 1,
A power supply voltage cutoff circuit, comprising: a Zener diode that prevents transmission of the input voltage to the mixed circuit when the input voltage is smaller than the predetermined voltage (V _z ). The power supply voltage cutoff circuit according to claim 2,
A PNP transistor whose base is connected to the cathode of the Zener diode via a first resistor; an NPN transistor whose base is connected to the collector of the PNP transistor via a second resistor; and an emitter of the PNP transistor; A third resistor connected between the base and
A power supply voltage cutoff circuit, wherein an emitter of the PNP transistor and a collector of the NPN transistor are connected. In the power supply voltage cutoff circuit according to any one of claims 1 to 3,
When the input voltage is smaller than the predetermined voltage (V _z ), the PNP transistor and the NPN transistor are not driven,
If the input voltage is not smaller than the predetermined voltage (V _z ), the PNP transistor and the NPN transistor are driven together. In the power supply voltage cutoff circuit according to any one of claims 1 to 4,
The predetermined voltage (V _z ) is a Zener voltage. The power supply voltage cutoff circuit according to any one of claims 1 to 5 is provided in the preceding stage,
The linear IC forms an analog power supply monitoring unit, is a comparator, and the logic input voltage is arranged in front of the clock IC that is a DC voltage,
A mixed circuit comprising a linear IC and a logic IC. In a mixed circuit comprising the linear IC and the logic IC according to claim 6,
The mixed circuit including a linear IC and a logic IC, wherein the predetermined voltage is lower than a lower threshold voltage at which the linear IC can operate.

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