JP2015090884A - Power semiconductor device, power semiconductor module, and manufacturing method of power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a small power semiconductor device which deals with high-temperature operation and achieves high reliability.SOLUTION: A power semiconductor device 1 includes: a ceramic base material 2i; a conductor layer 2a provided on an upper surface of the ceramic base material; power semiconductor elements 3a, 3b which are joined to an upper surface of the conductor layer; a main terminal 6a joined to a region which is located on upper surfaces of the power semiconductor elements and exclude an end edge part; a frame member 10 which is bonded to the upper surface of the conductor layer so as to enclose the semiconductor elements; and a sealing resin 12 which fills the inner side of the frame member and seals at least a joint region between the semiconductor elements and the main terminal. A low thermal expansion material 15 having a linear expansion coefficient smaller than the sealing resin is joined to a portion of the upper surface of the conductor surface which is located between the frame member and the semiconductor elements.

Description

  The present invention relates to a power semiconductor device using a circuit board having a ceramic base.

  In recent years, power semiconductor devices have been widely used not only for general industrial and electric railways but also for in-vehicle use. Especially in in-vehicle devices, reducing the size and weight of each component within a limited size range directly leads to a reduction in the weight and performance of the vehicle. This is an important issue. Thus, development of a wide band gap semiconductor material such as silicon carbide (SiC) capable of flowing a large current and capable of high-temperature operation as a semiconductor material replacing silicon (Si) is underway. In addition, as a circuit board having heat resistance and thermal conductivity corresponding to the above-described high performance, a circuit board having a ceramic base material and a metal conductor layer bonded on both sides thereof is used.

  The main surface (circuit surface) of a circuit board on which such a power semiconductor element is mounted is generally sealed with a silicone gel together with a wiring member or the like. However, when the operating temperature range becomes high, a flexible (low elastic modulus) material such as silicone gel cannot sufficiently suppress the stress applied to the joint portion of the semiconductor element and the stress applied to the wiring member such as a wire. The desired product life may not be satisfied.

  Therefore, by sealing the power semiconductor device with a sealing resin having a high elastic modulus such as an epoxy resin instead of the silicone gel, a configuration in which the stress applied to the joint portion and the wiring member near the power semiconductor element is reduced. It has come to be used.

  At this time, since the linear expansion coefficients of the metal constituting the wiring member and the ceramic base material are greatly different, when a sealing resin having a high elastic modulus is used, the linear expansion between the sealing resin and another circuit member is performed. It is difficult to match the coefficients, which is not preferable from the viewpoint of improving the reliability of the power semiconductor device.

  Here, for example, in Patent Document 1, in order to reduce the stress of the aluminum wire bonding portion of the wiring member, a silicon sealing region is provided separately from the epoxy sealing region, and a semiconductor element is arranged in the silicon sealing region. A power module is disclosed.

  On the other hand, in the power module disclosed in Patent Document 2, the entire module is sealed with an epoxy resin adjusted to the linear expansion coefficient of the solder bonding material of the semiconductor element. In addition, an inexpensive metal substrate is used as the substrate, and a thermal diffusion plate having a thermal diffusion function and a linear expansion mismatch relaxation function is inserted between the semiconductor element and the metal substrate.

JP 2011-199207 A (paragraphs [0022] to [0040], FIGS. 1 to 3) JP 2005-56873 A (paragraphs [0010] to [0021], FIG. 1)

  However, in the technique described in Patent Document 1, the semiconductor element is provided in the silicon sealing region, and the stress applied to the joint portion cannot be sufficiently reduced. Moreover, in the technique described in Patent Document 2, since the heat dissipation of the metal substrate is inferior to that of the ceramic substrate, an increase in the size in the planar direction cannot be avoided, such as the need to insert a heat diffusion plate.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a small and reliable power semiconductor device that can cope with high-temperature operation.

  In order to achieve the above object, a power semiconductor device according to the present invention includes a ceramic substrate, a conductor layer provided on the upper surface of the ceramic substrate, a power semiconductor element bonded to the upper surface of the conductor layer, A main terminal joined to the upper surface of the power semiconductor element and excluding the terminal portion; a frame member bonded to the upper surface of the conductor layer so as to surround the power semiconductor element; and an inner side of the frame member A sealing resin that is filled and seals at least a joining region between the power semiconductor element and the main terminal. A low thermal expansion material having a smaller linear expansion coefficient than that of the sealing resin is bonded to the upper surface of the conductor layer between the frame member and the power semiconductor element.

  The method for manufacturing a power semiconductor device according to the present invention includes a step of providing a conductor layer on the upper surface of the ceramic substrate, a step of bonding the power semiconductor element to the upper surface of the conductor layer, and an upper surface of the power semiconductor element. A step of bonding the main terminal to the region excluding the terminal portion, a step of adhering a frame member to the upper surface of the conductor layer so as to surround the power semiconductor element, and a sealing resin inside the frame member Filling and sealing at least the junction region between the power semiconductor element and the main terminal, and a linear expansion coefficient smaller than the sealing resin on the upper surface of the conductor layer between the frame member and the power semiconductor element. Joining the low thermal expansion material. The step of bonding the low thermal expansion material is performed simultaneously with the step of bonding the power semiconductor element or the step of bonding the main terminal.

  According to the present invention, a small and reliable power semiconductor device that can cope with a high-temperature operation is realized by suppressing the progress of peeling occurring at the interface between the frame member and the sealing resin. The In addition, the power semiconductor device can be manufactured without increasing the number of steps.

2A is a plan view of the power semiconductor device according to the first embodiment of the present invention, and FIG. It is sectional drawing corresponding to FIG.1 (b) of the semiconductor device for electric power which concerns on Embodiment 2 of this invention. It is sectional drawing corresponding to FIG.1 (b) of the semiconductor device for electric power which concerns on Embodiment 3 of this invention. It is the top view (a) of the power semiconductor device which concerns on Embodiment 4 of this invention, and the AA sectional view (b). It is the top view (a) of the power semiconductor device which concerns on Embodiment 5 of this invention, and its AA sectional view (b). It is the top view (a) of the power semiconductor device which concerns on Embodiment 6 of this invention, and its AA sectional view (b). It is a figure which shows the flow direction of resin at the time of manufacturing the semiconductor device for electric power.

  A power semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. In each figure, the same or similar components are denoted by the same reference numerals. In addition, the terms “upper”, “lower”, “upper surface”, “lower surface”, etc. indicating the direction are for convenience to specify the direction in the drawing, and limit the installation direction of the device in use. Not what you want.

Embodiment 1 FIG.
FIG. 1A is a plan view of the power semiconductor device according to the first embodiment of the present invention. FIG.1 (b) is the sectional view on the AA line of Fig.1 (a).
As shown in FIG. 1, the power semiconductor device 1 includes a circuit board 2, power semiconductor elements (hereinafter simply referred to as semiconductor elements) 3a and 3b, electrode terminals 6a, 6b and 7, a wiring member 9, The frame member 10, the sealing resin 12, and the low thermal expansion material 15 are provided. Hereinafter, these configurations will be specifically described.

  The circuit board 2 is composed of a ceramic base 2i having excellent thermal conductivity and conductor layers 2a and 2b provided on both sides of the ceramic base 2i. The conductor layer provided on the main surface (circuit surface) of the circuit board 2 on which the semiconductor elements 3a and 3b are mounted is denoted by reference numeral 2a, and the conductor layer provided on the main surface (heat radiation surface) opposite to the circuit surface. 2b is attached | subjected. As shown in FIG. 1 (b), the size of the conductor layers 2a and 2b may be a size covering a certain region, not a size bonded to the entire surface of the ceramic substrate 2i.

As the ceramic substrate 2i, an insulating and excellent heat conductive material such as aluminum nitride (AlN), silicon nitride (Si ₃ N ₄ ), aluminum oxide (Al ₂ O ₃ ) is preferable. Industrially, the thickness of the base material 2i is, for example, about 0.3 mm to 1 mm. As the conductor layers 2a and 2b, for example, a material excellent in thermal conductivity and conductivity such as copper, aluminum, or a laminate of copper and aluminum can be used. The conductor layers 2a and 2b are fixed to the base material 2i by brazing, diffusion bonding or the like. Industrially, the thickness of the conductor layer 2a and the conductor layer 2b is, for example, about 0.2 mm to 1 mm. As the thickness increases, the heat dissipation from the semiconductor elements 3a and 3b increases, while the thermal stress on the substrate 2i also increases. In order to prevent destruction of the apparatus, it is necessary to ensure a large margin, and a thickness of about 0.3 mm is used in practice.

  The semiconductor elements 3a and 3b are bonded to the upper surface of the conductor layer 2a via bonding layers 8b and 8d. The semiconductor elements 3 a and 3 b are appropriately selected according to the application of the power semiconductor device 1. As an example, the semiconductor element 3a is an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or the like, and the semiconductor element 3b is an FWD (Free Wheel Diode) or the like. For example, in the case of an IGBT, the gate electrode of the control electrode and the emitter electrode of the main electrode are formed on the upper surface (front surface), and the collector electrode of the main electrode is formed on the lower surface (back surface). Hereinafter, the electrode formed on the surface (the upper surface in FIG. 1) of the semiconductor element that is not bonded to the circuit board is referred to as a surface electrode.

  Silicon is generally used as the semiconductor element 3, but a wide band gap semiconductor material such as silicon carbide (SiC), gallium nitride (GaN) -based material, gallium arsenide (GaAs), diamond, or the like is a main component. A material to be used may be used. By using a wide band gap semiconductor material, it is possible to operate at high temperature, and it is also possible to reduce the size of the entire device 1 by increasing the switching frequency, for example.

  As the bonding layers 8b and 8d, for example, a metal material having excellent conductivity and capable of mechanically fixing the semiconductor elements 3a and 3b, such as solder, silver (Ag) conductor, or copper (Cu) conductor is used. . Here, when a metal is used under a temperature condition higher than the recrystallization temperature, there is a property that the crystal grain boundary moves due to diffusion and the crystal grains become coarse and weak against metal fatigue. Therefore, as the bonding layers 8b and 8d arranged at the positions in direct contact with the semiconductor elements 3a and 3b, a high level such as silver is particularly used from the viewpoint of increasing the reliability of the bonding layer when the operating temperature of the elements increases. It is preferable to use a melting point material.

  The electrode terminals 6a and 6b are main terminals connected to main electrodes (not shown) of the semiconductor elements 3a and 3b, and are hereinafter referred to as main terminals 6a and 6b. The main terminal 6a is electrically connected to the main electrodes on the upper surfaces of the semiconductor elements 3a and 3b via the bonding layers 8a and 8c. As will be described later, the main terminal 6a is joined to a region excluding the terminal portions of the semiconductor elements 3a and 3b. The other end of the main terminal 6 a extends from the sealing resin 12 to the outside of the device 1. One end of the main terminal 6b is bonded to the conductor layer 2a via the bonding layer 8e, and is electrically connected to the main electrodes on the lower surfaces of the semiconductor elements 3a and 3b.

  As the bonding layers 8a and 8c, a low melting point material such as solder is preferable from the industrial viewpoint in that the heating temperature at the time of bonding is low. However, as described above, from the viewpoint of extending the period during which reliability can be guaranteed, it is preferable that the melting point during bonding is sufficiently high. In order to satisfy these requirements, materials that have a low melting point at the time of bonding and a melting point that increases during bonding, such as a silver sintered (Ag sintering) material, a copper sintered material, a copper-tin (CuSn) intermetallic compound material, etc. It is preferable to use a material.

  The electrode terminal 7 is a control terminal that transmits a control signal to the semiconductor element 3a, and is hereinafter referred to as a control terminal 7. As shown in FIG. 1A, there are a plurality of control terminals 7, and one end of each control terminal 7 is electrically connected to a control electrode (not shown) on the upper surface of the semiconductor element 3a via a wiring member 9. It is connected to the.

  As shown in FIG. 1B, the main terminal 6b and the control terminal 7 are integrated with the frame member 10 by insert molding. One end of the main terminal 6 b is bent so as to be parallel to the circuit surface of the circuit board 2 and is exposed from the frame member 10. Of the exposed portion, the surface facing the circuit surface is bonded to the conductor layer 2a via the bonding layer 8e. Similarly, one end of the control terminal 7 is bent so as to be parallel to the circuit surface of the circuit board 2, but the surface facing the circuit surface is covered with the frame member 10, and the frame member on the opposite side is covered. The wiring member 9 is joined to the surface exposed from 10.

  As the main terminals 6a and 6b and the control terminal 7, for example, a material excellent in conductivity and industrially easy to use such as copper or copper alloy is preferable. In particular, the main terminal 6a has a function of diffusing heat generated in the semiconductor element 3 to the surrounding sealing resin 12 or transmitting the heat to the outside of the device 1, so that the material has a high thermal conductivity such as copper. Material is preferred. When the thickness of the main terminal 6a is increased, the thermal stress on the semiconductor element 3 is increased. Conversely, when the thickness is decreased, resistance heat generation due to electric resistance during energization increases. Therefore, although it is necessary to select an appropriate thickness for the main terminal 6a, for example, it is about 0.2 mm to 1 mm. In addition, it is effective to reduce the thermal stress by reducing the apparent rigidity by making a hole in the main terminal 6a as necessary. Moreover, as the bonding material 8e, the same material as the bonding materials 8b and 8d can be used.

  Note that the circuit structure including the wiring of the main terminals 6a and 6b and the control terminal 7 described above is appropriately changed according to the mode in which the semiconductor elements 3a and 3b are used.

  The wiring member 9 electrically connects the control electrode of the semiconductor element 3 a and the control terminal 7. The wiring member 9 does not have to be a bonding wire, and may be a bonding ribbon or another configuration. As the wiring member 9, a material having excellent conductivity such as aluminum, copper, or gold can be used.

  As shown in FIG. 1A, the frame member 10 is provided so as to surround the semiconductor elements 3a and 3b, and covers the outer periphery of the conductor layer 2a. The frame member 10 is preferably a resin material that can be injection-molded, has good moldability, and is excellent in heat resistance. As the resin material, for example, polyphenylene sulfide (hereinafter referred to as PPS), liquid crystal polymer resin, fluorine resin, and the like are preferable. Like the sealing resin 12, the frame member 10 preferably has a linear expansion coefficient closer to the conductor layer 2a than to the ceramic substrate 2i. And the frame member 10 is adhere | attached using the adhesive agent 11 on the outer peripheral part of the conductor layer 2a which has a linear expansion coefficient closer to the frame member 10 than the ceramic base material 2i among the circuit surfaces of the circuit board 2. FIG.

  In this manner, the space of the portion where the circuit member is mounted (region of the conductor layer 2a) on the circuit surface of the circuit board 2 is surrounded by the frame member 10. The enclosed space is filled to a predetermined height using the sealing resin 12. As a result, the circuit members on the circuit surface including the semiconductor elements 3a and 3b are sealed by the sealing resin 12 except for the portions of the main terminals 6a and 6b and the control terminal 7 that extend from the device 1 to the outside. Will be. Of the main terminals 6a and 6b and the control terminal 7, portions extending from the device 1 to the outside are connected to an external switching power supply (not shown), other power semiconductor elements, and the like.

  The sealing resin 12 is filled inside the frame member 10, that is, in a region surrounded by the conductor layer 2a and the frame member 10, and seals circuit members such as the semiconductor elements 3a and 3b. The sealing resin 12 has a high elastic modulus of, for example, 10 GPa or more and a linear expansion coefficient that is closer to the conductor layer 2a than the ceramic substrate 2i. As the sealing resin 12, for example, a resin having a high elastic modulus and an effect of suppressing thermal expansion and thermal contraction can be used, such as an epoxy resin.

  As the sealing resin 12, ceramic particles such as fused silica are mixed as fillers in urethane resin, polyimide resin, polyamide resin, polyamideimide resin, acrylic resin, etc. in addition to epoxy resin, and the linear expansion coefficient and elastic modulus are increased. Adjusted materials can also be used. In this way, the linear expansion coefficient of the frame member 10 and the like can be similarly controlled.

  The low thermal expansion material 15 is bonded between the frame member 10 and the semiconductor element 3 a and on the upper surface of the conductor layer 2 a via the bonding layer 16, and suppresses the movement of the sealing resin 12 and the frame member 10. It is like that. As shown to Fig.1 (a), it is preferable that the low thermal expansion material 15 is opposingly arranged by the edge | side in which the wiring member 9 was given between the frame member 10 and the semiconductor element 3a. Referring to FIG. 1B, it is preferable that the low thermal expansion material 15 and the plurality of wiring members 9 intersect and overlap each other in plan view.

  As the low thermal expansion material 15, a material having a smaller linear expansion coefficient than the sealing resin 12 is used. Specifically, an Invar material that is an alloy of Fe and Ni, a CIC (Copper-Invar-Copper) material that is a composite material of Cu and Invar material, a CuMo material that is a composite material of Cu and Mo, A material that can realize a linear expansion coefficient of 0.1 ppm / K to 10.0 ppm / K, such as an AlSiC material that is a composite material of Al and SiC, is preferable. By providing the low thermal expansion material 15, it is possible to suppress the occurrence of thermal stress due to the difference in linear expansion coefficient between the frame member 10 and the sealing resin 12 at a high temperature, thereby causing peeling. Details will be described later.

  In addition to the configuration described above, the cooling member 4 is bonded to the lower surface of the conductor layer 2b on the heat absorbing surface side of the circuit board 2. Thus, the power semiconductor device is often used as a set with the cooling member. Radiating fins 4 a are attached to the lower surface of the cooling member 4. Instead of such a structure, a cooling jacket or the like through which a refrigerant flows may be used as the cooling member 4.

  As the cooling member 4, for example, a material having high thermal conductivity such as aluminum, copper, copper molybdenum (CuMo) alloy, SiC / Al (SiC fiber reinforced aluminum) is used. However, if the difference in the coefficient of linear expansion between the portion on which the semiconductor elements 3a and 3b such as the circuit board 2 including the ceramic substrate 2i are mounted and the cooling member 4 is large, the stress applied to the bonding layer 5 increases. Therefore, when the required reliability is high, it is preferable to use a material having a small coefficient of linear expansion such as CuMo or SiC / Al as the cooling member 4.

  The bonding layer 5 is preferably made of a material having high heat dissipation and little long-term deterioration. However, since the circuit board 2 is interposed between the bonding layer 5 and the semiconductor elements 3 a and 3 b, the maximum temperature reached by the bonding layer 5 is at least lower than that of the semiconductor element 3. Therefore, even when solder or the like is used as the bonding layer 5, the power semiconductor device 1 can sufficiently withstand practical use. As the bonding layer 5, other materials that can achieve durability at a higher temperature operation, for example, a silver sintered material, a copper sintered material, and a copper tin (intermetallic compound) material may be used.

  A second frame member 13 is bonded to the upper surface (heat absorption surface) of the cooling member 4 as a frame surrounding the circuit board 2 using an adhesive (not shown). The space surrounded by the second frame member 13 and the cooling member 4 is sealed with the second sealing resin 14 to a height that reaches the conductor layer 2a of the circuit board 2. Thereby, the edge part of the joining interface of the ceramic base material 2i and the conductor layers 2a and 2b is covered with the insulating second sealing resin 14, and is appropriate for the electric field concentration portion generated at the edge part of the joining interface. Insulating properties are maintained.

  The second frame member 13 may be made of the same material as that of the frame member 10, for example. The second sealing resin 14 may be made of, for example, the same material as that of the sealing resin 12. However, the second sealing resin 14 only needs to have insulating properties and adhesiveness, and is preferably a highly fluid resin such as silicone gel. . When a resin with high fluidity is used as the second sealing resin 14, it is preferable to provide the second frame member 13, but when a resin with low fluidity is used, the second frame member 13 is provided. The member 13 may be omitted.

  Next, an exemplary method for manufacturing the power semiconductor device 1 will be described.

  First, the semiconductor elements 3a and 3b are bonded to the upper surface of the conductor layer 2a using the bonding layers 8b and 8d (step S1). Next, a solder material is placed on the position where the bonding layers 8a and 8c are provided on the surface electrodes of the semiconductor elements 3a and 3b and the position where the bonding layer 8e is provided on the conductor layer 2a (step S2). Next, the frame member 10 incorporating the main terminal 6b and the control terminal 7 is bonded to the upper surface of the conductor layer 2a by insert molding (step S3). Next, the main terminals 6a and 6b are placed on the solder material and heated (step S4). By heating in step S4, bonding layers 8a and 8c interposed between the main terminal 6a and the semiconductor elements 3a and 3b, and a bonding layer 8e interposed between the main terminal 6b and the conductor layer 2a are formed (step). S5).

  Next, the wiring member 9 is electrically connected, for example, by ultrasonic bonding to the control electrode and the control terminal 7 of the semiconductor element 3a (step S6). In this way, necessary circuit members are mounted on the circuit board 2.

  Finally, the region surrounded by the conductor layer 2a and the frame member 10 is filled with, for example, an epoxy-based adhesive or potting material and cured to provide the sealing resin 12 (step S7). In this way, the semiconductor elements 3a and 3b and their surface electrodes are reliably covered with the sealing resin 12 and mechanically restrained.

  In the step S1 for bonding the semiconductor elements 3a and 3b, the low thermal expansion material 15 can be provided without increasing the number of steps by simultaneously bonding the low thermal expansion material 15 using the bonding layer 16. Alternatively, the low thermal expansion material 15 and the bonding layer 16 may be placed on the upper surface of the conductor layer 2a in accordance with the step S2, and then the steps S3 and S4 may be performed without increasing the number of steps. Can be provided. In the latter case, the bonding layer 16 is formed simultaneously with the end of step S4.

  Before the step S1, the circuit board 2 is bonded onto the cooling member 4 in advance, the second frame member 13 is bonded, and the second sealing resin 14 is filled, so that the entire configuration of FIG. It can be manufactured. When the sealing resin 12 is used as the second sealing resin 14, one step can be omitted by performing the filling of the second sealing resin 14 simultaneously with the step S <b> 7.

  Next, the operation of the power semiconductor device 1 and the effects obtained will be described in comparison with the operation of a general power semiconductor device. In order to distinguish from the power semiconductor device 1 according to the first embodiment, a general power semiconductor device is referred to as a power module. The power semiconductor element provided in the power module is called a power chip.

  The power module is used, for example, in an inverter that drives a motor or the like. When the motor is driven, a loss occurs in the power chip. When the temperature rise due to this loss exceeds the melting point of the bonding material such as solder, the bonding is not sufficiently maintained and the power module fails. Further, when the power chip reaches a high temperature, for example, about 370 ° C., there is a possibility that the insulation is lost and the power chip itself is destroyed. Furthermore, when a temperature change occurs due to an increase or decrease of a load such as a motor, a thermal stress is generated at a joint (adhesion) inside the power module. When the temperature change is repeated, the joint (bonded portion) may deteriorate and break down. Thus, the power module inevitably has a lifetime for long-term use. Therefore, in order to guarantee to the user a period during which the power module can be used safely, it is necessary to design the lifetime of the module.

  As described above, in the power module, the power chip itself becomes a heat source, and the periphery thereof reaches the highest temperature. Therefore, it is necessary to strictly manage the lifetime of the power chip, particularly the joint. An electrode terminal (corresponding to the main terminal 6a in the first embodiment) for securing a current-carrying path is bonded to the surface electrode of the power chip, and a bonding wire used for wiring (corresponding to the wiring member 9 in the first embodiment). ) Are joined.

First, the joint between the power chip and the electrode terminal will be considered.
A structure called a guard ring that relaxes the electric field generated at the terminal end of the power chip is formed at the terminal end of the main surface of the power chip so that insulation is maintained when the switch is turned off. Due to the presence of the guard ring, the electrode terminal cannot be bonded over the entire surface of the power chip, and is bonded to a portion other than the terminal portion via a bonding material. Therefore, the surface electrode of the power chip has a region where the electrode terminal is bonded and a region (terminal region) where the electrode terminal is not bonded, and the electrode terminal and the bonding material are at a certain angle with respect to the surface electrode of the power chip. It will be in the state which adhered by.

  It is known that stress concentration is generally likely to occur in a portion where such an angle change has occurred. On the contrary, when the electrode terminal is uniformly bonded to the entire surface of the surface electrode, stress concentration hardly occurs. Therefore, on the surface electrode of the power chip, there exists a “boundary portion” at the junction with the electrode terminal, and stress concentration occurs at the boundary portion. As a result of such stress concentration, when the stress enters the plastic region, the deterioration proceeds in a so-called low cycle fatigue mode.

  When the stress enters the plastic region, as a typical phenomenon, cracks occur at the stress concentration portion. Specifically, when plastic deformation first occurs in the stress concentration portion, a dent is formed on the surface of the stress concentration portion. When the dent is formed, the stress concentration further increases, and a minute tear is generated starting from the dent, leading to a crack. Once a crack occurs in the stress concentration part, the crack gradually develops due to plastic deformation caused by the stress cycle, and eventually the surface electrode may fall off. In general, metal fatigue progresses by such a mechanism. As described above, stress concentration that causes metal fatigue is an unavoidable phenomenon in power semiconductor elements such as switching elements.

  However, it is known that this stress concentration is alleviated to some extent when the power module is sealed with a resin having a high elastic modulus such as an epoxy resin.

Next, a joint portion between the power chip and a bonding wire (hereinafter referred to as a wire) will be considered.
When a cylindrical wire is bonded to the surface of the power chip, an unbonded portion is formed at the bonding interface end in the wire extension direction, and a wedge-shaped notch is generated in the cross-sectional shape of the unbonded portion. Stress concentration easily occurs at a position where such a wedge-shaped notch is generated. Such stress concentration at the notch is an unavoidable phenomenon when a wiring member such as a bonding ribbon is bent and joined to a flat surface, not limited to a cylindrical wire.

  However, it has been found that when the power module is sealed with a resin having a high elastic modulus such as an epoxy resin, the stress concentration at the wedge-shaped notch is suppressed. For example, there is an example in which the life of the power module with respect to a temperature cycle generated by an energization test called a power cycle test is three times or more.

  In the case of sealing with silicone gel or the like, the joint portion (joint interface) between the power chip and the wire becomes a fractured portion by a long-term reliability test. As described above, by using a sealing resin having a high elastic modulus, stress concentration caused by pressing a cylindrical wire against a flat surface is suppressed. At this time, due to the difference in the coefficient of linear expansion between the sealing resin and the wire, a thermal stress that prevents the sealing resin from expanding and contracting the entire length of the wire is generated according to the heat generation of the wire. In the middle or the neck portion becomes a stress concentration portion. Nevertheless, the period during which the reliability can be guaranteed for the user can be sufficiently prolonged as compared with the case of sealing with silicone gel or the like. When sealing with a sealing resin having a high elastic modulus, crack propagation of the solder layer can be suppressed even when the copper electrode is soldered to the surface electrode of the power chip instead of wire bonding using an aluminum wire. In this case, there is an example in which the life of the power chip is improved to about 10 times that of an aluminum wire.

  As described above, by sealing the power module with a resin having a high elastic modulus such as an epoxy resin, stress concentration generated at the joint between the power chip and the wire, and stress generated at the joint between the power chip and the electrode terminal It has been found that concentration can be eased to some extent. At this time, when the power module is sealed with a resin having a low elastic modulus such as silicone gel, the insulation is maintained and the adhesion of foreign matter to the power chip can be prevented, but the effect of relieving thermal stress. Can hardly be obtained. In addition, in order to fully exhibit the effect which suppresses a thermal expansion and a thermal contraction, it is preferable that the elasticity modulus of sealing resin is about 1/10 of a metal. In the first embodiment, the elastic modulus of the sealing resin 12 is set to 10 Gpa or more, and a sufficient effect can be expected.

Next, a new problem that occurs when a resin having a high elastic modulus is used will be described in detail.
On the circuit surface of the circuit board, there are members having greatly different linear expansion coefficients, such as a ceramic material constituting the base material of the circuit board and a metal material constituting the electrode terminal. When attempting to downsize the power module in such a configuration, the thickness of the resin is inevitably reduced. When the thickness of the resin is thin, the sealing members such as the frame member, the electrode terminal, and the power chip dominate the thermal stress in each (near) region. At this time, when a sealing resin having a high elastic modulus that restrains the electrode terminal or the like is used, it is difficult to adjust the linear expansion coefficient of the sealing resin so as to be able to deal with all the regions.

  As described above, when the circuit surface is sealed with a resin having a high elastic modulus, the sealing resin straddles materials having greatly different linear expansion coefficients. At this time, a new thermal stress is generated due to the difference in linear expansion coefficient, and the boundary between the frame member and the sealing resin, the boundary between the electrode terminal and the sealing resin, the boundary between the wire and the sealing resin, or the sealing There is a possibility that deterioration such as cracks may occur in the resin itself.

  In order to suppress the thermal stress caused by the difference in the linear expansion coefficient, in the power semiconductor device 1, only the region inside the conductor layer 2 a surrounded by the frame member 10 is included in the circuit surface of the circuit board 2. Covered with a sealing resin 12. Therefore, the sealing resin 12 does not have a contact surface with the ceramic base 2 i having a significantly different linear expansion coefficient with respect to the main terminal 6 a and the conductor layer 2 a. Thereby, the linear expansion coefficient of the sealing resin 12 can give priority to the compatibility with the main terminal 6a and the conductor layer 2a. More specifically, the metal (Cu: 18 ppm / K, which constitutes the conductor layer 2a and the main terminal 6a than the ceramic base material 2i having a linear expansion coefficient of the sealing resin 12 of generally about 5 ppm / K. Al: It can be set to a value close to 23 ppm / K).

  Further, the sealing resin 12 is filled inside the frame member 10, and expansion is limited by the frame member 10. Thereby, the sealing resin 12 can be filled with no gap within the height defined by the frame member 10, and the thermal stress applied to the main terminal 6a and the wiring member 9 joined to the semiconductor elements 3a and 3b can be sufficiently suppressed. Furthermore, on the surface electrodes of the semiconductor elements 3a and 3b, the linear expansion coefficient can be made substantially the same at the boundary between the main terminal 6a and the sealing resin 12, and the elastic modulus is not less than a predetermined value. Thus, the members having the effect of suppressing thermal expansion and contraction are connected, and the stress concentration described above can be reliably reduced.

  Here, since the resin frame member 10 itself does not have adhesiveness, the frame member 10 is bonded to the conductor layer 2a using the adhesive 11, and as described above, the resin wire constituting the frame member 10 is used. The expansion coefficient is preferably adjusted to a value close to that of the metal together with the sealing resin 12. However, at this time, the difference in linear expansion coefficient between the sealing resin 12 and the ceramic base material 2i becomes large, and the bonded frame member 10 and the ceramic base material 2i may be peeled off. In general, a creeping insulation distance is secured on the surface of the ceramic substrate 2i, and when the above-described peeling occurs, partial discharge occurs due to an electric field, resulting in a decrease in insulation. In other words, when interfacial peeling occurs, creeping discharge is likely to occur on the newly generated peeling surface, resulting in a problem that the withstand voltage characteristics are significantly reduced as compared with the previous non-peeling. In this case, the period during which the reliability can be guaranteed to the user becomes extremely short.

  On the other hand, in the power semiconductor device 1, the frame member 10 is directly bonded to the upper surface of the conductor layer 2a, and does not contact the ceramic substrate 2i. Thereby, since the linear expansion coefficient of the frame member 10 and the conductor layer 2a can be made substantially the same, generation | occurrence | production of stress can be suppressed and possibility of producing peeling can be reduced.

  Even in this case, when the frame member 10 is peeled from the upper surface of the conductor layer 2a, the sealing resin 12 is also peeled from the conductor layer 2a. When this peeling crosses the surfaces of the semiconductor elements 3a and 3b, the semiconductor elements 3a and 3b may be destroyed. However, according to the configuration of the first embodiment, the frame member 10 is removed from the upper surface of the conductor layer 2a. It has been found through various energization tests that peeling is sufficiently suppressed.

Next, the thermal stress resulting from the anisotropy of the linear expansion coefficient of the sealing resin 12 will be described.
It is preferable to use a resin such as PPS for the frame member 10. However, it is known that a resin such as PPS has anisotropy in linear expansion coefficient between a flow direction at the time of molding and a direction perpendicular to the flow direction. Particularly in the case of PPS, in the direction perpendicular to the flow direction, the linear expansion coefficient at a high temperature (about 150 degrees) is about 50 ppm / K to 100 ppm / K. In this case, the linear expansion coefficient of the conductor layer 2a is A large difference is generated between the sealing resin and the sealing resin (in the case of epoxy resin, about 18 ppm / K to 25 ppm / K).

  FIG. 7 shows the flow direction of the molding resin when the molding resin of the frame member 10 is injected from the side surface. Basically, the linear expansion coefficient of the molding resin tends to increase in a direction (in the drawing, a chain line arrow) perpendicular to the semiconductor elements 3a and 3b (in plan view). On the other hand, the linear expansion coefficient of the sealing resin 12 is preferably set to a value close to the conductor layer 2a and the main terminal 6a from the viewpoint of suppressing separation between the sealing resin 12 and these. Therefore, in consideration of anisotropy, it is not preferable to set the linear expansion coefficient of the sealing resin 12 to a large value exceeding 50 ppm / K, for example.

  However, when an energization test according to the actual inverter operating temperature is performed in a configuration in which the difference in linear expansion coefficient occurs in this way (for example, the maximum temperature reached is 40 ° C. to 150 ° C.), There is also an example in which peeling of the adhesive interface occurs during the period. Therefore, it is necessary to suppress the thermal stress generated between the frame member 10 and the sealing resin 12.

  In the power semiconductor device 1, the low thermal expansion material 15 is joined between the frame member 10 and the semiconductor element 3a. Therefore, there is a function that prevents thermal expansion in the direction in which the frame member 10 tends to expand greatly during high-temperature operation. Thereby, the thermal stress generated between the frame member 10 and the sealing resin 12 can be sufficiently suppressed.

  Here, the flow direction at the time of molding the frame member 10 is a direction that goes around the outer periphery in plan view. On the other hand, as described above, the direction in which the thermal expansion increases at a high temperature is a direction perpendicular to the flow direction. In the power semiconductor device 1, the semiconductor elements 3a and 3b are mounted as viewed from the frame member 10. Point in direction. That is, by disposing the low thermal expansion material 15 between the frame member 10 and the semiconductor element 3a, thermal expansion at a high temperature is suppressed, and peeling progress between the frame member 10 and the sealing resin 12 can be suppressed.

  It is the loss of the operation function due to the disconnection of the wiring member 9 that the separation of the adhesive interface between the frame member 10 and the sealing resin 12 progresses and is most likely to be a problem. As described above, as the wiring member 9, wire bonding using aluminum, copper, gold or the like as a main material may be used. Since the wiring member 9 is connected to the connection terminal 7 and generally only a small control current of about several mA flows, the required wire diameter is small. For example, in the case of an aluminum wire, a wire diameter of about 100 μm to 400 μm is sufficient. On the other hand, it is necessary to provide a certain bonding region in order to properly wire bond the semiconductor element. However, since this bonding region does not become an effective energization region of the semiconductor element 3a, a wire having the smallest possible wire diameter is used. There is a reason to want to earn an effective energizing area.

  Therefore, among the members constituting the power semiconductor device 1 and sealed with the sealing resin 12, the wiring member 9 becomes a particularly weak member and peels off due to propagation from the wire bond peripheral member. It is necessary to pay sufficient attention to this. That is, even if the control terminal 7, the wiring member 9 and the sealing resin 12 are completely in contact immediately after sealing, when the temperature stress is repeatedly applied, the frame member 10 is There is a possibility that peeling of the sealing resin 12 may occur.

  When the peeling gradually progresses and reaches the root of the wiring member 9, a great thermal stress is applied to the joint interface between the control terminal 7 and the wiring member 9. As a result, the sealing resin may be lifted together with the wiring member 9 and disconnected.

  On the other hand, in the first embodiment, the low thermal expansion material 15 is disposed between the frame member 10 and the semiconductor elements 3a and 3b with respect to the side where the signal wiring is provided, so that the control terminal 7 and the wiring member are arranged. 9 can sufficiently suppress the thermal stress generated at the bonding interface.

  As described above, in the power semiconductor device 1, it is possible to cope with a high temperature operation and improve reliability by suppressing the progress of separation occurring at the interface between the frame member 10 and the sealing resin 12. Is possible. Furthermore, the apparatus 1 can be downsized by reducing the thickness of the resin. Furthermore, the power semiconductor device 1 can be manufactured without increasing the number of steps.

  Hereinafter, modifications of the first embodiment will be described.

  In the above description, the configuration in which the control terminal 7 and the main terminal 6b are integrated with the frame member 10 by insert molding has been described. From the viewpoint of obtaining the effect that the region of the sealing resin 12 is secured by the frame member 10, the control terminal 7 and the main terminal 6 b are not necessarily integrated with the frame member 10. However, when the wiring member 9 is connected to the semiconductor element 3 and the control terminal 7 by using the wire bonding technique, the wire bonding can be performed with high stability by integrating them. In general, in the wire bonding process, it is necessary to stabilize the semiconductor element by using a technique such as complicated electrode pressing. However, since this can be omitted, an effect of improving productivity can be obtained.

  In particular, by joining the main terminal 6b embedded in the frame member 10 and the conductor layer 2a, the integrity of the frame member 10 and the circuit board 2 is improved. However, at least in the region within the frame member 10, the circuit member can be constrained closer to the linear expansion coefficient of the circuit member such as the conductor layer 2 a and the main terminals 6 a and 6 b, the control terminal 7, and the wiring member 9 than the ceramic substrate 2 i. By sealing with the sealing resin 12, a more reliable power semiconductor device 1 can be obtained.

  That is, the main terminal 6b or the like does not necessarily have to be embedded in the frame member 10, and the frame member 10 may be made of only resin. In this case, since the frame member 10 does not contact the circuit member, an elastic modulus that restrains the circuit member is not necessarily required.

  In the above description and drawings, the configuration in which one circuit board 2 is bonded onto one cooling member 4 has been described. However, the present invention is not limited to this, and a plurality of components are formed on one cooling member 4. The circuit board 2 may be bonded. In the claims, a configuration in which a plurality of circuit boards 2 are bonded on one cooling member is referred to as a “power semiconductor module”.

  For example, in a power module that constitutes an inverter, a ceramic substrate (corresponding to the circuit board 2 in the first embodiment) on which a plurality of power chips and electrode terminals according to the amount of energy to be supplied to the inverter or the like is mounted is used as a cooling member. A configuration in which a plurality are arranged on top is preferable. In order to drive the inverter in three phases, at least six ceramic substrates on which a pair of power chips composed of IGBTs and diodes are mounted are required. When the parallel number is increased according to the amount of energy necessary for energization, the number of ceramic substrates on the cooling member further increases.

  However, if sealing is performed across a plurality of ceramic substrates with a sealing resin with a binding force, due to the high hardness after curing the resin, even if it is within the operating temperature range required for the power module, the temperature swing May cause shrinkage of the resin. This shrinkage increases as the number of ceramic substrates increases, and the resin tends to break easily. If cracking occurs in the resin, as described above, the effect of reducing the stress on the surface of the power chip against the solder layer cannot be obtained sufficiently, and therefore the expected improvement in reliability may not be obtained sufficiently. is there.

  As in the first embodiment, a frame member 10 is provided for each circuit board 2 and the inside thereof is sealed with a sealing resin 12, and a portion between the circuit boards 2 on the cooling member 4 (outside of the frame member 10). The above problem is solved by filling the portion) with the second sealing resin 14 that has insulating properties and no binding force.

  Moreover, in the above description and drawings, the low thermal expansion material 15 is shown in a rectangular parallelepiped shape (plate shape), but it is not always necessary to have a rectangular parallelepiped shape. Further, the low thermal expansion material 15 may have a shape having a semicircular cross section. In this case, since the risk of contact with the wiring member 9 can be reduced, the loop height of the wiring member 9 is reduced to reduce the sealing resin 12 The thickness can be reduced, leading to a reduction in size and weight of the entire apparatus 1.

Embodiment 2. FIG.
FIG. 2 is a cross-sectional view corresponding to FIG. 1B of the power semiconductor device according to the second embodiment of the present invention. In FIG. 2, the same or similar components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  In FIG. 1B, if the thickness of the sealing resin 12 between the low thermal expansion material 15 and the wiring member 9 is large, the difference in linear expansion coefficient between the frame member 10 and the sealing resin 12 still remains large. . At this time, in the case where the low thermal expansion material 15 is arranged in the direction in which the frame member 10 is thermally expanded, in order to sufficiently suppress the thermal expansion of the frame member 10, the wiring member 9 integrated with the frame member 10 has a high height. It is preferable to make the height of the low thermal expansion material 15 higher than the height. That is, it is preferable to arrange the low thermal expansion material 15 as high as possible in the vicinity of the frame member 10 around the frame member 10, and in particular, by disposing it higher than the height of the frame member 10, the sealing resin 12 It is possible to drastically reduce the thermal stress generated between the frame member 10 and the frame member 10 and enhance the delamination suppressing effect.

  Therefore, in the second embodiment, the low thermal expansion material denoted by reference numeral 25 is the connection position between the wiring member 9 and the control terminal 7 indicated by reference numeral X in FIG. It extends to the upper side of the connection position between the member 9 and the semiconductor element 3a. Thereby, the thermal expansion suppression effect of the frame member 10 can further be exhibited.

Embodiment 3 FIG.
FIG. 3 is a cross-sectional view corresponding to FIG. 1B of the power semiconductor device according to the third embodiment of the present invention. In FIG. 3, the same or similar components as those in the second embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As described in the second embodiment, in terms of reducing the thermal stress generated between the sealing resin 12 and the frame member 10, the low thermal expansion material 25 is preferably disposed higher than the height of the frame member 10. However, when the wiring member 9 is disposed on the low thermal expansion material 25, the material constituting the low thermal expansion material 25 does not necessarily have electrical insulation, and therefore, between the low thermal expansion material 25 and the conductor layer 2 a. If the bonding material does not have electrical insulation, it is necessary to electrically insulate the wiring member 9 and the low thermal expansion material 25 from each other. Further, although the sealing material 12 is insulative, it is known that when the threshold value of the electric field strength is exceeded, the electric discharge breakdown is caused from an inherent minute defect, and the wiring member 9, the conductive member 25, It is necessary to secure a certain distance between them.

  That is, when the low thermal expansion material 25 and the conductor layer 2a immediately below the loop of the wiring member 9 are close to equipotential, it is necessary to ensure a certain distance between the wiring member 9 and the low thermal expansion material 15. Therefore, when trying to increase the height of the low thermal expansion material 15, the height of the top of the loop is determined after adding the necessary insulation distance, and the resin from the top of the loop to the surface of the sealing resin 12 is further removed. The size in the height direction of the power semiconductor device 1 is determined by the addition, which prevents the device 1 from being downsized.

  Therefore, in the third embodiment, the low thermal expansion material 25 is fixed to the upper surface of the conductor layer 2a through the bonding layer 26 having electrical insulation. Thereby, it is not necessary to take into consideration the insulation distance between the wiring member 9 and the low thermal expansion material 15, and the size of the device 1 in the height direction can be reduced to the minimum necessary. That is, according to the third embodiment, the apparatus 1 can be downsized while sufficiently exhibiting the thermal expansion suppressing effect of the frame member 10.

Embodiment 4 FIG.
FIG. 4A is a plan view of a power semiconductor device according to the fourth embodiment of the present invention, and FIG. In FIG. 4, the same or similar components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  1 to 3, the shape of the low thermal expansion material is illustrated as a rectangular parallelepiped shape. In addition, a low thermal expansion material is disposed in the vicinity of the control terminal 7 so that the effect described above is most exhibited. On the other hand, since the frame member 10 is formed so as to cover the outer periphery of the conductor layer 2 a and the sealing resin 12 is filled in the entire inside of the frame member 10, the entire area between the frame member 10 and the sealing resin 12 is covered. It is conceivable to provide a low thermal expansion material.

  Therefore, in the fourth embodiment, as shown in FIG. 4A, a low thermal expansion material denoted by reference numeral 45 is provided so as to surround the semiconductor elements 3a and 3b in a plan view.

  According to the fourth embodiment, even when peeling occurs between the frame member 10 and the sealing resin 12, progress of the peeling is suppressed. Thereby, it is suppressed that the said peeling progresses to the semiconductor element 3a, 3b side and a malfunctioning occurs. Further, it is possible to prevent the peeling from progressing to the bonding layers 8a to 8d on the upper surface and the lower surface of the semiconductor elements 3a and 3b, thereby eliminating the restraining effect by the sealing resin 12 and significantly reducing the reliability of the bonded portion. . As a result, the period during which reliability can be guaranteed for the user can be extended.

  In FIG. 4A, the low thermal expansion material 45 is illustrated in a ring shape (square ring shape) in plan view, but it is not necessarily a closed ring.

Embodiment 5 FIG.
FIG. 5A is a plan view of a power semiconductor device according to the fifth embodiment of the present invention, and FIG. In FIG. 5, the same reference numerals are given to the same or similar components as those in the first embodiment, and detailed description thereof is omitted.

  From the viewpoint of maintaining the thermal expansion suppressing effect of the frame member 10 by the low thermal expansion material, it is preferable that the adhesion between the upper surface of the low thermal expansion material and the sealing resin 12 is high. In order to improve adhesion, it is also conceivable to perform a coating treatment such as a primer treatment using, for example, a silane coupling agent or polyimide. However, in this case, the number of processes increases, and the processing cost increases accordingly.

  Therefore, in the fifth embodiment, a discontinuous recess 55a that does not penetrate is provided from the upper surface to the lower surface of the low thermal expansion material denoted by reference numeral 55. The recess 55a corresponds to an example of a “concave portion” in the claims. Further, as shown in FIG. 5 (b), the recess 55a has a shape in which the area of the entrance (upper surface side) is smaller than the area of the bottom surface (lower surface side), such as a dovetail shape and a bowl shape. It is preferable.

  According to the fifth embodiment, the sealing resin 12 enters the recess 55a of the low thermal expansion material 55, the anchor effect is exhibited, and the adhesion between the low thermal expansion material and the sealing resin is dramatically improved. That is, the stress in the shear direction generated between the upper surface of the low thermal expansion material 55 and the sealing resin 12 is reduced, and the effect of suppressing the thermal expansion of the frame member 10 by the low thermal expansion material 55 can be maintained.

  In the method for manufacturing the device 1 described in the first embodiment, the low thermal expansion material can be prepared in advance using press molding using a predetermined mold. In the fifth embodiment, the step of providing the depression 55a in the low thermal expansion material 55 is the addition of the press process using the mold for the depression 55a to the step of press molding the low thermal expansion material 55 by 1 to 3 steps. Can be implemented. Therefore, it is possible to dramatically improve the adhesion without greatly impairing the productivity.

  In addition, as shown to Fig.5 (a), although the shape of the hollow 55a is circular by planar view, it can change suitably according to the shape of a metal mold | die.

Embodiment 6 FIG.
FIG. 6A is a plan view of a power semiconductor device according to the sixth embodiment of the present invention, and FIG. In FIG. 6, the same or similar components as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  As described in the fifth embodiment, it is preferable to improve the adhesion between the low thermal expansion material and the sealing resin 12 from the viewpoint of maintaining the thermal expansion suppression effect of the frame member 10 by the low thermal expansion material.

  Therefore, in the sixth embodiment, a straight groove 65a that does not penetrate is provided from the upper surface to the lower surface of the low thermal expansion material denoted by reference numeral 65. The number of grooves 65a is arbitrary. The groove 65a corresponds to an example of a “concave portion” in the claims. Thereby, the sealing resin 12 enters the groove 65a of the low thermal expansion material 65, the anchor effect can be exhibited, and the adhesiveness can be dramatically improved. As in the fifth embodiment, the anchor effect is further enhanced by making the width of the entrance (upper surface side) of the groove 65a smaller than the width of the bottom surface (lower surface side).

  In particular, in the sixth embodiment, the low thermal expansion material 65 can be formed by a highly productive method in which a thick portion and a thin portion formed in advance by extrusion or the like are separated into a predetermined length.

  The configuration of each embodiment described above may be freely combined, modified, or omitted depending on the reliability required for the power semiconductor device 1.

  DESCRIPTION OF SYMBOLS 1 Power semiconductor device, 2 Circuit board, 2i Ceramic base material, 2a, 2b Conductor layer, 3a, 3b Power semiconductor element, 4 Cooling member, 4a Radiation fin, 5 Junction layer, 6a, 6b Main terminal, 7 Control terminal 8a to 8e bonding layer, 9 wiring member, 10 frame member, 11 adhesive, 12 sealing resin, 13 second frame member, 14 second sealing resin, 15, 25, 45, 55, 65 low thermal expansion Material, 55a depression, 65a groove, 16, 26 bonding layer.

Claims (10)

A ceramic substrate;
A conductor layer provided on the upper surface of the ceramic substrate;
A power semiconductor element bonded to the upper surface of the conductor layer;
A main terminal joined to a region on the upper surface of the power semiconductor element excluding a termination portion;
A frame member bonded to the upper surface of the conductor layer so as to surround the power semiconductor element;
A sealing resin that is filled inside the frame member and seals at least a junction region between the power semiconductor element and the main terminal;
A power semiconductor device, characterized in that a low thermal expansion material having a smaller linear expansion coefficient than that of the sealing resin is bonded between the frame member and the power semiconductor element and on the upper surface of the conductor layer. A control terminal for transmitting a control signal to the power semiconductor element;
A wiring member that electrically connects the control terminal and the power semiconductor element;
2. The power semiconductor device according to claim 1, wherein the low thermal expansion material is provided at a position overlapping the wiring member as viewed from above the conductor layer.   The power semiconductor device according to claim 2, wherein the low thermal expansion material extends to a position above a connection position between the wiring member and the control terminal and a connection position between the wiring member and the power semiconductor element. .   4. The power semiconductor device according to claim 1, wherein the low thermal expansion material is bonded to the conductor layer via an electrically insulating bonding material. 5.   5. The electric power supply according to claim 1, wherein the low thermal expansion material is provided so as to surround the electric power semiconductor element when viewed from the upper side of the conductor layer. 6. Semiconductor device. The low thermal expansion material is plate-shaped, and has a first surface joined to the conductor layer, and a second surface that faces the first surface and contacts the sealing resin,
6. The power semiconductor device according to claim 1, wherein a concave portion that does not penetrate is provided from the second surface of the low thermal expansion material toward the first surface. 6.   7. The power semiconductor device according to claim 1, wherein the power semiconductor element is formed of a wide band gap semiconductor material. 8.   8. The power semiconductor device according to claim 7, wherein the wide band gap semiconductor material is mainly composed of a material selected from the group consisting of silicon carbide, gallium nitride, gallium arsenide, and diamond. A power semiconductor module comprising a plurality of power semiconductor devices according to any one of claims 1 to 8,
A second conductor layer provided on the lower surface of each ceramic substrate;
One cooling member joined to the lower surface of each second conductor layer;
A second frame member bonded on the cooling member so as to surround the plurality of power semiconductor elements;
A power semiconductor module comprising a second sealing resin filled inside the second frame member. Providing a conductor layer on the upper surface of the ceramic substrate;
Bonding a power semiconductor element to the upper surface of the conductor layer;
Bonding the main terminal to the upper surface of the power semiconductor element and excluding the terminal portion;
Adhering a frame member to the upper surface of the conductor layer so as to surround the power semiconductor element;
Filling a sealing resin inside the frame member, sealing at least a junction region between the power semiconductor element and the main terminal;
Bonding a low thermal expansion material having a linear expansion coefficient smaller than that of the sealing resin to the upper surface of the conductor layer between the frame member and the power semiconductor element,
The method of manufacturing a power semiconductor device, wherein the step of bonding the low thermal expansion material is performed simultaneously with the step of bonding the power semiconductor element or the step of bonding the main terminal.

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