JP2015090588A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of improving robustness by taking measures for bit error tendency.SOLUTION: As redundant data, polarity-inverted data for input data is written (for example, "1" is written for input data "0"). Therefore, as compared with a case of writing data with the same polarity as that of input data, an overall probability of bit errors can be reduced. This can improve reliability of output data.

Description

  The present invention relates to a semiconductor memory device having a nonvolatile memory.

  In a semiconductor memory device using a non-volatile memory such as a flash memory, a data corruption detection / correction circuit is usually mounted in order to improve the reliability of data stored in the non-volatile memory. In order to detect / correct data corruption by the data corruption detection / correction circuit, redundant data is added to the data (input data) to be written. The main method is a method called mirroring. Examples of the technology include those disclosed in Patent Document 1.

JP 2010-134993 A

In Patent Document 1, when error correction using data majority is performed with, for example, 3 redundancy, if the input data is “0”, the initial state is 1-bit input data, 2-bit redundant data, As a result, 3 redundant "000" is obtained. For example, if it becomes “001” due to garbled 1 bit, “1” is corrected to “0” by 3 redundant majority, and output data becomes “0”.
On the other hand, when performing error detection using data mismatch, if “001” is generated due to 1-bit conversion and “011” is generated due to 2-bit conversion, data corruption is detected due to data mismatch and output data is used. Processing such as prohibition can be performed.

By the way, the actual data corruption in the nonvolatile memory generally occurs in one direction (for example, “0” can be changed to “1”) with a higher probability than the other (for example, “1” can be changed to “0”). It is. For example, in the case of a flash memory, if the probability that the charge of the floating gate is released due to some factor is p, and the probability that the charge enters the floating gate is q, in general, there is a tendency that p >> q (≈0). The probability of data corruption is also higher in one direction than in the other.
However, the current technology does not consider the tendency of bit corruption, and it is desired to further improve the robustness in consideration of the tendency of bit corruption.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory device that can improve robustness in consideration of the tendency of bit corruption.

  According to the first aspect of the present invention, when either the input data written in the first memory cell or the redundant data written in the second memory cell is garbled, the majority is corrected by the majority means. Can be output. In this case, when the input data “0” is written to the first memory cell, the redundant data “1” is written to the second memory cell, and the input data “1” is written to the first memory cell. When data is written, redundant data “0” is written in the second memory cell. Here, for example, when the nonvolatile memory is a flash memory, the charge enters the floating gate when the charge of the floating gate is released for some reason (the data is changed from “0” to “1”). Probability is higher than 1) to “0”. As a result, the overall probability of bit corruption is lower when different polarities are written in the first memory cell and the second memory cell than when the same polarity is written in both the first memory cell and the second memory cell. , The reliability of the output data can be increased.

1 is a block diagram showing a nonvolatile memory, an input stage, and an output stage according to a first embodiment of the present invention. FIG. 1 equivalent diagram showing the application state of the write voltage 1 equivalent diagram showing output data Block diagram showing the overall configuration of the flash memory device Logic diagram showing majority match circuit Logic diagram showing mismatch detection circuit Diagram showing the probability of bit corruption when input data is not inverted Fig. 7 equivalent diagram when inverting input data The block diagram which shows the structure of the non-volatile memory in 2nd Embodiment of this invention. FIG. 9 equivalent diagram showing a case where normal writing is impossible The block diagram which shows the structure of the non-volatile memory in 3rd Embodiment of this invention. FIG. 10 equivalent diagram showing a case where normal writing is impossible The block diagram which shows the output stage in 4th Embodiment of this invention The flowchart which shows the majority process by a processing circuit Flowchart showing mismatch detection circuit by processing circuit FIG. 1 equivalent view showing a fifth embodiment of the present invention FIG. 7 equivalent diagram showing a case where a part of input data is inverted The figure which shows the all bit write flow in 6th Embodiment of this invention. Diagram showing all bit write flow Block diagram showing the input stage Diagram showing operation corresponding to mode Diagram showing output stage Diagram showing operation corresponding to mode

(First embodiment)
Hereinafter, a first embodiment in which the present invention is applied to a flash memory device will be described with reference to FIGS. As shown in FIG. 4, the flash memory device 100 (corresponding to a semiconductor memory device) of the present embodiment includes a nonvolatile memory 1 composed of a NAND type flash memory, a decoder 3, an input stage 4, a booster circuit 5, and an output stage 6. The control circuit 7 and the input / output buffer 8 are provided.
The nonvolatile memory 1 is an array of flash memory cells and is composed of a plurality of sectors 2. Sector 2 is a unit of memory cells to be erased at once, and the size of one sector 2 is usually about several tens of Kbits to several Mbits, for example.

The decoder 3 decodes the applied address information and determines selection / non-selection of a memory cell in the nonvolatile memory 1.
The input stage 4 applies a predetermined voltage to the gate, source, and drain of the selected memory cell based on the information given from the decoder 3 and the control circuit 7.
The booster circuit 5 generates a high voltage or a negative voltage for performing a writing, reading, or erasing operation in accordance with a command from the control circuit 7.
The output stage 6 takes the majority of the data input from the nonvolatile memory 1 during the read operation and outputs it to the control circuit 7.

  The control circuit 7 includes a CPU 9, a ROM 10 and a RAM 11, and is configured to input / output address information, commands (control) and data via the input / output buffer 8. The control circuit 7 interprets commands received from the outside to execute operations such as writing, reading, or erasing, enabling / disabling the booster circuit 5, and controlling writing, reading, and erasing pulses. . Further, the control circuit 7 has a function of controlling validation / invalidation when outputting output data to the outside in a read operation or the like, and a function of controlling the state of the nonvolatile memory 1 and the operation to the memory cell.

As shown in FIG. 1, the sector 2 of the nonvolatile memory 1 is configured by combining words 12 composed of memory cells a0, a1, a2 (b0, b1, b2,...) Having 3 bits as a basic unit. A memory cell a0 (b0...) Is a first memory cell in which input data is written as it is, and memory cells a1, a2 (b1, b2...) Are second memory cells in which redundant data is written. Three redundancy is configured by the cells a0 to a2 (b0 to b2...). In other words, in the present embodiment, the input data and the redundant data exist in the same word 12.
In the following description, the memory cells a0 to a2 among the three redundant memory cells will be described as a representative, and description of the other memory cells b0 to b2.

  The memory cells a0, a1, and a2 are adapted to input input data via the input stage 4 (corresponding to input means). That is, the word line of the memory cell a0 is connected to the decoder 3 via the driver 0, and the word lines of the memory cells a1 and a2 are connected to the decoder 3 via the drivers 1 and 2 and the inverters 13a and 13b, respectively. . The decoder 3 outputs the input data to a predetermined output line selected by the address information.

  On the other hand, the memory cells a0, a1 and a2 are adapted to output output data via an output stage 6 (corresponding to output means). That is, the word line of the memory cell a0 is connected with the sense amplifier SA0. The word lines of the memory cells a1 and a2 are connected to the sense amplifiers SA1 and SA2 and inverters 16a and 16b, respectively. The sense amplifiers SA0 to SA2 determine whether the data is “1” or “0” based on the current flowing through the connected memory cells a0 to a2, and output the determination result.

  The majority circuit 15 takes the majority of the signal level of the input line and outputs the result. As shown in FIG. 5, the majority circuit 15 is configured by combining, for example, a plurality of Not-OR circuits 15a. When three or two of the three pieces of input data are “0”, the output level is “ When there are three or two of “0” and “1”, “1” is output as the output level.

  As shown in FIG. 2, when a write signal is applied to the decoder 3 when the input data is “0”, a voltage of “0” write is applied from the driver 0 to the memory cell a0, and from the drivers 1 and 2, A voltage for writing “1” is applied to the memory cells a1 and a2. Therefore, “011” is written in the memory cells a0 to a2 constituting three redundancy.

  On the other hand, when a read signal is applied, as shown in FIG. 3, input data “0” written in memory cell a0 is output as it is through sense amplifier SA0, and redundant data written in memory cells a1 and a2 is output. The data “1” is inverted and output to “0” by the inverters 14a and 14b. In this case, since all input data is “0” and the same, “0” is output from the majority circuit 15 as output data and processed.

  The input data or redundant data written in the memory cells a0 to a2 constituting 3 redundancy may be garbled for some reason. For example, if one redundant data is garbled from “0” to “1” and “000” becomes “001”, the majority circuit 15 outputs “0” as output data, and “1” becomes “1”. The output data corrected to 0 ″ can be output.

  Here, the probability of bit corruption is compared between the conventional case where the polarity of the input data is not inverted as redundant data and the case of the present invention where the polarity of the input data is inverted. If the probability that “0” is bitified to “1” is p and the probability that “1” is bitwise to “0” is q, the probability that “0” is not bitwise to “1” is 1-p, “ The probability that 1 ”is not garbled to“ 0 ”is 1-q.

As shown in FIG. 7, when the initial state is “000”, the probability of 1-bit corruption is approximately 3p, the probability of 2-bit corruption is approximately 3p ² , and the probability of 3-bit corruption is approximately p ³ . When the initial state is “111”, the probability of bit corruption is almost zero. Incidentally, the digit of p ³ when if 7 the final probability digit q = 0, p and p ² be mixed to omit the digit p ^2, digits p ² and p ³ are mixed Omitted.

On the other hand, as shown in FIG. 8, when the initial state is “011”, the probability of 1-bit corruption is almost p, the probability of 2-bit corruption is almost 0, and the probability of 3-bit corruption is almost 0. When the initial state is “100”, the probability of 1-bit corruption is approximately 2p, the probability of 2-bit corruption is approximately p ² , and the probability of 3-bit corruption is approximately 0.
From these FIG. 7 and FIG. 8, there is no change in the probability of 1-bit conversion, but the probability of 2-bit conversion that cannot be corrected can be reduced to 1/3, and further, the probability of 3-bit conversion that cannot be detected in addition to correction can be increased. You can see that it can be zero.

  According to such an embodiment, since the data with the polarity of the input data inverted is written as the redundant data, compared to the case where the data having the same polarity as the input data is written as the redundant data, the bit garbled data is obtained. Can reduce the overall probability. Thereby, the reliability of output data can be improved.

Instead of the majority circuit 15, a mismatch detection circuit may be provided, or both circuits may be provided. As shown in FIG. 6, the mismatch detection circuit 16 is configured by combining, for example, an exclusive-OR circuit 16a and an OR circuit 16b, and “0” and “1” are mixed in three input data. “1” is output as an error flag. That is, when “000” is input to the mismatch detection circuit 16, all the input data is the same, so the mismatch detection circuit 16 outputs “0” as an error flag. In this case, since the reliability of the output data is high, use of the output data is permitted. On the other hand, when one or two of the data written in the memory cells a1 and a2 are garbled, the mismatch detection circuit 16 outputs “1” as an error flag. In such a case, since the reliability of the output data is lost, the use of the output data is prohibited.
In the following embodiment, a configuration in which the majority circuit 15 is provided as in the first embodiment will be described. However, the mismatch detection circuit 16 may be provided instead of the majority circuit 15, or both circuits may be provided. Good.

(Second Embodiment)
A second embodiment of the present invention will be described with reference to FIGS. The second embodiment is characterized in that the memory cells a0, a1, and a2 are provided in different words, respectively.
As shown in FIG. 9, the first word 12a constituting the sector 2 of the nonvolatile memory 1 has a memory cell a0, the second word 12b has a memory cell a1, and the third word 12c has a memory cell a2. Is provided. In this embodiment, the majority circuit 15 of the output stage 6 inputs input data and redundant data from the memory cells a0, a1 and a2 of the first to third words 12a to 12c.

According to such an embodiment, data can be saved by the majority circuit 15 even when all of one word cannot be normally written due to some trouble as shown in FIG.
If only one word for redundant data is provided, the data cannot be saved, but the mismatch detection circuit 16 can detect that the data does not match.

(Third embodiment)
A third embodiment of the present invention will be described with reference to FIGS. The second embodiment is characterized in that the memory cells a0, a1, and a2 are provided in different sectors, respectively.
As shown in FIG. 11, a memory cell a0 is provided in the first sector 2a of the nonvolatile memory 1, a memory cell a1 is provided in the second sector 2b, and a memory cell a2 is provided in the third sector 2c. In this embodiment, the majority circuit 15 of the output stage 6 inputs input data and redundant data from the memory cells a0, a1 and a2 of the first to third sectors 2a to 2c.

According to such an embodiment, as shown in FIG. 12, for example, even when all of the data in one sector cannot be normally written due to a short circuit of word lines that connect memory cells a0, c0, e0. Data can be saved by the majority circuit 15.
If only one sector for redundant data is provided, the data cannot be saved, but the mismatch detection circuit 16 can detect that the data does not match.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIGS. The fourth embodiment is characterized in that it includes a processing circuit for executing the operations of the inverters 14a and 14b, the majority circuit 15 and the mismatch detection circuit 16 of the output stage 6 in the above embodiment by software.
As shown in FIG. 13, the word lines of the memory cells a0 to a2 are directly connected to the processing circuit 17 (corresponding to processing means) via sense amplifiers SA0 to SA2.
FIG. 14 shows a majority process for executing the operation of the majority circuit 15 by the processing circuit 17. The input data of the memory cell a0 is Q0, the redundant data of a1 is Q1, the redundant data of a2 is Q2, and the data whose polarity is inverted by software for executing the function of the inverter is preceded by “˜”. Added. The processing circuit 17 determines whether Q0 = ˜Q1 = ˜Q2, and if they match (YES), sets the output data to Q0. If they do not match (NO), it is determined whether “0” is more when Q0,..., Q1, and Q2 are compared. If “0” is more (YES), output data = 0. If “0” is smaller (NO), output data = 1.

With the operation as described above, the operation of the majority circuit 15 can be implemented by software by the majority process of the processing circuit 17.
FIG. 15 shows a mismatch detection process for executing the operation of the mismatch detection circuit 16 by the processing circuit 17. The processing circuit 17 determines whether Q0 = ˜Q1 = ˜Q2, and if they match (YES), sets the error flag to “0”. If they do not match (NO), the error flag is set to “1”.

By the operation as described above, the operation of the mismatch detection circuit 16 can be implemented by software by the mismatch detection processing of the processing circuit 17.
According to such an embodiment, the output data in which the bit corruption is corrected by the majority processing by the processing circuit 17 is output, or the error flag is set to 1 when a mismatch is detected by the mismatch detection process. The majority circuit 15 and the mismatch detection circuit 16 can be selectively operated according to the application application, or both can be operated at the same time, so that the requirements of the application can be flexibly handled.
In the present embodiment, the processing circuit 17 also serves as an input unit and an output unit. However, an inverter circuit may be provided and only the operation as the processing unit may be executed. Further, the processing circuit 17 may execute at least one of majority processing and mismatch detection processing.

(Fifth embodiment)
A fifth embodiment of the present invention will be described with reference to FIGS. The fifth embodiment is characterized in that the polarity of only one part of the input data is inverted instead of inverting all the polarities of the input data as redundant data.
As shown in FIG. 16, the input data is input to the memory cells a0 and a1 through the drivers 0 and 1, and the input data is input to the memory cell a2 through the driver 2 with the polarity inverted by the inverter 13b. Has been. On the other hand, the outputs of the memory cells a0 and a1 are output to the majority circuit 15 via the sense amplifiers SA0 and SA1, and the output of the memory cell a2 is output to the majority circuit 15 with the polarity inverted by the inverter 14b from the sense amplifier S2. It is configured to be.

  As shown in FIG. 17, by reversing the polarity of only part of the input data as redundant data, the overall probability of bit corruption when the initial state is “001” is when the initial state shown in FIG. 8 is “001”. Is equal to the overall probability of bit corruption. Further, the overall probability when the initial state is “110” is equal to the overall probability of bit corruption when the initial state shown in FIG. 8 is “011”. Accordingly, it can be seen that the overall probability of bit corruption when the polarity of only a part of the input data is inverted as redundant data is lower than the overall probability when the polarity of the input data is not inverted as redundant data. .

  According to such an embodiment, since the polarity of only a part of the input data is inverted as redundant data, an inverter for inverting the polarity of the data can be omitted, and the overall configuration is simplified. Can be achieved.

(Sixth embodiment)
A sixth embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 18, when all bits are written by inspection in a configuration in which the polarity of input data is not inverted as redundant data, the all-bit writing flow may be “0” writing. On the other hand, as shown in FIG. 19, when all bits are written by inspection in the configuration in which the polarity of the input data is inverted, a process of writing data in which the polarity of the input data is inverted as redundant data is required. Therefore, it becomes impossible to write all bits at once. For this reason, an extra flow for writing redundant data occurs, leading to an increase in inspection time. Further, when the output data is read from the majority circuit 15, the state of the redundant bit cannot be grasped, so that it may be an inconvenient configuration for inspection.
In consideration of these circumstances, we propose a circuit configuration that allows all-bit writing and all-bit reading. In addition to writing and reading signals, a test signal is prepared for user writing / reading and inspection. The circuit configuration distinguishes between writing and reading.

  First, the input stage 4 will be described. As shown in FIG. 20, the driver 0 inputs the input data to the memory cell a0 as it is, and the drivers 1 and 2 input the input data to the memory cells a1 and a2 via the switch SW1 (corresponding to the first switching means). The outputs from the inverters 13a and 13b are connected to the memory cells a1 and a2 via the switch SW2 (corresponding to the first switching means).

  A mode control circuit 18 (corresponding to the first mode control means) is provided to receive a write signal and a test signal, and executes a user mode and a test mode according to the input level of the write signal and the test signal. It is possible. That is, as shown in FIG. 21, when the write signal is “H” and the test signal is “L”, the mode control circuit 18 determines that the user mode is selected and turns off the switch SW1 and turns on the switch SW2. To do. Thereby, redundant data in which the polarity of the input data is inverted is written in the user mode. On the other hand, when the write signal is “H” and the test signal is “H”, the mode control circuit 18 determines that the test mode is set, and turns on the switch SW1 and turns off the switch SW2. Thus, in the inspection mode, the input data is written as redundant data as it is without inverting the polarity of the input data.

  Next, the output stage 6 will be described. As shown in FIG. 22, the sense amplifiers SA0 to SA2 output the data of the memory cells a0 to a2 via the switch SW1 (corresponding to the second switching means) and the majority circuit via SW2 (corresponding to the second switching means). 15 is output.

  The mode control circuit 18 (corresponding to the second mode control means) is provided so as to receive a read signal and a test signal, and can execute a user mode and an inspection mode according to the input levels of the read signal and the test signal. It has become. That is, as shown in FIG. 23, when the read signal is “H” and the test signal is “L”, the mode control circuit 18 determines that the mode is the user mode and turns off the switch SW1 and turns on the switch SW2. . As a result, in the user mode, correction of garbled bits can be executed by the majority circuit 15. On the other hand, when the write signal is “H” and the test signal is “H”, the mode control circuit 18 determines that the test mode is set, and turns on the switch SW1 and turns off the switch SW2. Thereby, in the inspection mode, all bits are read as raw data without any correction.

  According to such an embodiment, since all bits can be written in the inspection mode, the inspection time can be shortened. In addition, since all bits of raw data can be read in the inspection mode, it is possible to grasp the state of redundant bits.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
The number of memory cells to which redundant data is written is not limited to two (3 redundancy), but may be one (2 redundancy) or three (4 redundancy) or more. However, in the case of 2 redundancy, since it is not possible to take a majority decision, the majority decision circuit 15 cannot be provided, and only the mismatch detection circuit 16 can be provided.
In the above embodiment, the present invention is applied to a NAND type flash memory device, but may be applied to a NOR type flash memory.
The present invention is not limited to a flash memory device, but may be applied to an EPROM.

  In the drawings, 100 is a flash memory device (semiconductor memory device), 2 is a nonvolatile memory, 4 is an input stage (input means), 6 is an output stage (output means), 15 is a majority circuit (majority means), and 16 is inconsistent. Detection circuit (mismatch detection means), 17 is a processing circuit (processing means), 18 is a mode control circuit (first mode control means, second mode control means), a0, b0... Are first memory cells, a1, a2 , B1, b2... Are second memory cells, and SW1 and SW2 are switches (first switching means, second switching means).

Claims (6)

First memory cells (a0, b0...) To which input data is written and a plurality of second memory cells (a1, a2, b1, b2...) To which redundant data for improving the robustness of the input data are written. Non-volatile memory (2) configured in combination with
Input means (4) for causing the input data to be input to the first memory cell with the same polarity and to input redundant data in which the polarity of the input data is inverted to the second memory cell;
Output means (6) for outputting the input data written in the first memory cell with the same polarity and outputting the redundant data written in the second memory cell with its polarity inverted;
A semiconductor memory device, comprising: majority means (15) for outputting data having a large number of coincident polarities among the input data and redundant data output from the output means. A non-volatile memory configured by combining a first memory cell into which input data is written and one or a plurality of second memory cells into which redundant data for enhancing the robustness of the input data is written;
Input means for inputting the input data to the first memory cell with the same polarity, and inputting redundant data obtained by inverting the polarity of the input data to the second memory cell;
Output means for outputting the input data written in the first memory cell with the same polarity, and outputting the redundant data written in the second memory cell with its polarity inverted;
Mismatch detection means (16) for determining whether the input data output from the output means and the redundant data do not match;
A semiconductor memory device comprising:   3. The semiconductor memory device according to claim 1, further comprising processing means (17) for executing the operation of the majority decision means or the mismatch detection means by software.   4. The semiconductor memory device according to claim 1, wherein the input unit is configured such that a part of the redundant data has the same polarity as the input data. First switching means (SW1, SW2) capable of switching between an effective mode in which polarity inversion by the input means is enabled and an ineffective mode in which polarity inversion by the input means is disabled;
First mode control means (18) for switching the first switching means to the valid mode when executing the user mode, and switching the first switching means to the invalid mode when executing the inspection mode;
The semiconductor memory device according to claim 1, further comprising: A second switching means (SW1, SW2) capable of switching between an effective mode for validating polarity reversal by the output means and an invalid mode for invalidating polarity reversal by the output means;
Second mode control means (18) for switching the second switching means to the effective mode when executing the user mode, and switching the second switching means to the invalid mode when executing the inspection mode;
The semiconductor memory device according to claim 1, further comprising:

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