JP2015084392A - Photodetector - Google Patents

Abstract

An optical detector capable of improving time resolution and suppressing crosstalk is provided.
The photodetector includes a plurality of APDs operating in Geiger mode, a plurality of quenching resistors R1 connected to each APD, and an output electrically connected to each quenching resistor R1. A terminal PAD, a wiring E3 that connects the plurality of quenching resistors R1 resistance and the output terminal PAD, and a trench Tr that is provided around each APD and has a ring shape with a gap partially cut off in plan view It has. The wiring is connected to the output terminal PAD through E3, this gap.
[Selection] FIG.

Description

  The present invention relates to a photodetector that can be used in medical equipment such as a positron CT apparatus (Positron Emission Tomography: PET apparatus) and a CT apparatus.

  Currently, various medical devices are used. A PET device is a device that introduces a drug labeled with an isotope that emits positrons (positrons) into a living body and detects γ-rays resulting from the drug with a plurality of detectors. The PET apparatus includes a ring-shaped gantry (cradle), a cradle (sleeper), and a computer for operation, and a plurality of detectors arranged around the living body are built in the gantry.

  Here, an efficient detector of X-rays or γ-rays can be configured by combining a scintillator and a photodetector.

  Note that a CT / PET apparatus in which an X-ray CT apparatus and a PET apparatus are combined, and a combined diagnostic apparatus in which an MRI (magnetic resonance imaging diagnosis) apparatus is combined with them are also considered.

  A photodetector (photodiode array) applied to the diagnostic apparatus as described above is described in Patent Document 1, for example. In a photodiode array such as SiPM (Silicon Photo Multiplier) or PPD (Pixelated Photon Detector), APDs (avalanche photodiodes) are arranged in a matrix, a plurality of APDs are connected in parallel, and the sum of APD outputs is read. Have. When the APD is operated in the Geiger mode, weak light can be detected.

  That is, when photons (photons) enter the APD, carriers generated inside the APD are output to the outside through a quenching resistor and a signal readout wiring pattern. A current flows through a pixel where an avalanche occurs in the APD, but a voltage drop occurs in a quenching resistance of about several hundred kΩ connected in series to the pixel. Due to this voltage drop, the voltage applied to the amplification region of the APD is lowered, and the multiplication action due to the electron avalanche is terminated. Thus, one pulse signal is output from the APD by the incidence of one photon.

JP 2008-311651 A

  However, the photodiode array has a problem that crosstalk occurs. In order to suppress such crosstalk, it is considered effective to form a trench between each photodiode (pixel). However, as a result of intensive studies by the present inventors, it has been found that simply forming a trench slows the rise of the output pulse, reduces the time resolution of the output, and cannot sufficiently suppress crosstalk. .

  The present invention has been made in view of such problems, and an object of the present invention is to provide a photodetector capable of improving time resolution and suppressing crosstalk.

  In order to solve the above-described problem, a photodetector according to the present invention includes a plurality of APDs operating in Geiger mode, a plurality of quenching resistors connected to each of the APDs, and an electric current connected to each quenching resistor. A ring shape having a gap that is partially cut off in plan view, provided around the APD, and the output terminals connected to each other, wiring connecting the plurality of quenching resistors and the output terminals, respectively And the wiring is connected to the output terminal through the gap.

  By providing the trench, it is possible to prevent the photons generated by the Geiger avalanche from entering the adjacent pixels, and it is possible to prevent the charge generated in one APD from moving to the adjacent APD. Can suppress crosstalk. However, when the wiring crosses over the trench, the parasitic capacitance increases in such a portion and the rise of the output pulse becomes slow. On the other hand, in the structure of this aspect, since the trench has a gap and the wiring is connected to the output terminal through the gap, such a parasitic capacitance does not occur, and the output pulse rises. Becomes steep. Therefore, the time resolution can be improved.

  The trench may include a trench semiconductor region having a conductivity type opposite to that of the APD on which the trench is provided. Since the semiconductor region for trenches has a conductivity type opposite to that of the APD on which the trench is provided, the movement of electric charges to the adjacent APD can be suppressed.

  The trench includes a conductive core material and a trench semiconductor region provided around the core material via an insulating layer and having a conductivity type opposite to that of the side of the APD on which the trench is provided. It is characterized by that.

  When electrical connection is made to the trench, the electrical connection can be easily made by having a conductive core material. As described above, if there is a semiconductor region for trenches, the movement of charges can be suppressed. However, if the potentials on the trench side and the trench side of the APD coincide with each other, a bias is applied to the trench from the substrate side, and charge is unnecessary. In order to contribute to the movement, the core material and the trench semiconductor region are preferably separated via an insulating layer.

  The photodetector further includes a trench connection wiring electrically connected to the trench. In the case where the trench is in a floating state, there is a possibility that an electric charge flows in an alternating manner into the adjacent APD through the capacitance of the trench. If the trench is fixed at a constant potential via the trench connection wiring, the charge flowing into the adjacent APD can be suppressed.

  The photodetector includes a plurality of APDs operating in Geiger mode, a plurality of quenching resistors connected to the APDs, and output terminals electrically connected to the quenching resistors, The wiring board includes a plurality of wirings connecting the quenching resistors and the output terminal, a trench provided around each of the APDs, and a wiring electrically connected to the trench. Also in this case, electrical crosstalk can be suppressed.

  According to the photodetector of the present invention, it is possible to improve time resolution and suppress crosstalk.

FIG. 3 is a circuit diagram of a photodiode array in one photosensitive region. FIG. 2A is a circuit diagram of one photodiode and a quenching resistor, and FIG. 2B is a diagram showing a unit structure in a semiconductor chip for realizing this configuration. FIG. 3 is a plan view of the unit structure shown in FIG. 2. It is a top view of a photodiode array provided with a plurality of unit structures. It is a figure which shows the AA arrow longitudinal cross-section structure of the photodiode array of FIG. It is a top view of a photodiode array provided with a trench. It is a figure which shows the AA arrow longitudinal cross-section structure of the photodiode array of FIG. 1 is a plan view of a photodiode array including a trench having a cut portion. FIG. It is a figure which shows the AA arrow longitudinal cross-section structure of the photodiode array of FIG. 1 is a plan view of a photodiode array including a trench having a cut portion. FIG. It is a figure which shows the AA arrow vertical cross-section structure of the photodiode array of FIG. 10 or FIG. It is a top view of the photodiode array which has a quenching resistance which consists of transparent materials. 3 is a plan view of a photodiode array in which wiring is provided so as to surround the periphery of a semiconductor region 14. FIG. It is a figure which shows the AA arrow longitudinal cross-section structure of the photodiode array of FIG. It is the figure (A) and top view (B) which show the longitudinal cross-sectional structure of a photodiode array. It is a figure which shows the longitudinal cross-sectional structure of the photodiode array when the wiring is not connected to a trench, and is the figure which shows the longitudinal cross-sectional structure of the photodiode array of when the wiring is connected to the trench (B). FIG. 10 is a cross-sectional view of a structure in which a trench connection wiring is added to the structure of FIG. 9. 12 is a cross-sectional view of a structure in which a trench connection wiring is added to the structure of FIG. FIG. 15 is a cross-sectional view of a structure in which a trench connection wiring is added to the structure of FIG. 14. It is a figure which shows the longitudinal cross-sectional structure of the photodiode array provided with the trench of 3 layer structure. It is a figure which shows the longitudinal cross-section structure of a trench vicinity. It is a top view of a photodiode array when a wiring for trench connection is added. A plan view (A) of a specific photodiode array and a plan view (B) of one photodiode. It is a figure of a detector. FIG. 20 is a cross-sectional view of a structure in which Tr3 is omitted in the structure of FIG.

  Hereinafter, the photodetector according to the embodiment will be described. In addition, the same code | symbol shall be used for the same element and the overlapping description is abbreviate | omitted.

  FIG. 1 is a circuit diagram of a photodiode array in one photosensitive region.

  The photodiode array PDA is formed in the photosensitive region of the semiconductor chip. The photodiode array PDA includes a plurality of photodiodes PD and a quenching resistor R1 connected in series to each photodiode PD. The cathodes of the photodiodes PD are commonly connected, and the anodes are commonly connected via a quenching resistor R1. The plurality of photodiodes PD are two-dimensionally arranged.

  All the quenching resistors R1 are connected to the electrode pad PAD via the electrode or the wiring E3. In a semiconductor chip, when the cathode of the photodiode PD is a substrate, the substrate potential is set to a relatively (+) potential, and a signal is extracted from the electrode pad PAD serving as an anode. Note that the cathode and anode in the photodiode can be used interchangeably, and there are N-type and P-type conductivity types in the semiconductor chip, but they can perform the same function even if they are replaced with each other. it can.

  The photodiode PD is an avalanche photodiode (APD) that operates in Geiger mode. In the Geiger mode, a reverse voltage (reverse bias voltage) larger than the breakdown voltage of the APD is applied between the anode / cathode of the APD. That is, a (−) potential is applied to the anode and a (+) potential is applied to the cathode. The polarities of these potentials are relative, and one of the potentials can be a ground potential.

  FIG. 2 is a circuit diagram (A) of one photodiode and a quenching resistor, and a diagram (B) showing a unit structure in a semiconductor chip for realizing this configuration. Since a photodiode array is formed in the semiconductor chip, a plurality of unit structures shown in the figure are two-dimensionally formed.

  The semiconductor region 12 constituting the semiconductor substrate is an N-type (first conductivity type) semiconductor substrate made of Si. The anode of the photodiode PD is a P-type (second conductivity type) semiconductor region 13 (14), and the cathode is an N-type semiconductor region 12. When a photon is incident on a photodiode PD as an APD, photoelectric conversion is performed inside the substrate to generate photoelectrons. Avalanche multiplication is performed in the region near the pn junction interface of the semiconductor region 13, and the amplified electron group flows toward the electrode E <b> 4 formed on the back surface of the semiconductor region 12. The electrode E4 may be provided on the surface side. That is, when a photon is incident on the photodiode PD, the photon is multiplied and extracted as a signal from the electrode or wiring E3 electrically connected to the quenching resistor R1. The wiring E3 is connected to the above-described electrode pad PAD.

  The quenching resistor R1 is formed on the upper insulating layer 17 of the two insulating layers 16 and 17, and is electrically connected to the semiconductor region 14 having a higher impurity concentration than the semiconductor region 13. ing. An electrode E4 that provides a substrate potential is provided on the back surface of the semiconductor substrate, and the electrode E4 is connected to a positive potential, for example.

  The insulating layers 16 and 17 are provided with contact holes, and the semiconductor region 14 and the quenching resistor R1 are electrically connected via the contact electrodes and the wiring E1 (see FIG. 3) in the contact holes. ing. Note that the wirings E1 and E3 are formed on the insulating layer 16.

  FIG. 3 is a plan view of the unit structure shown in FIG. In the following plan views, the description of the insulating layers 16 and 17 is omitted, and the internal structure is shown more clearly.

  The wiring E1 is connected to the quenching resistor R1 through a contact hole provided in the insulating layer 17 (see FIG. 2). The quenching resistor R1 is connected to a wiring E3 located under the contact hole provided in the insulating layer 17 through a contact hole. The wiring E3 is a signal readout wiring, surrounds the periphery of the semiconductor region 14, and has a quadrangular annular shape.

  FIG. 4 is a plan view of a photodiode array having a plurality of unit structures, and FIG. 5 is a diagram showing a vertical cross-sectional configuration of the photodiode array of FIG.

  All the signal readout wirings E3 are electrically connected to the electrode pads PAD. The electrode pad PAD is formed on the insulating layer 16. In the figure, a photodiode array of 2 rows and 2 columns is formed, but this may be N rows × M columns (N and M are integers of 2 or more). In a structure including a plurality of photodiodes, a plurality of semiconductor regions 14 are formed in one semiconductor region 13. In the sectional view of FIG. 5, the quenching resistor R1 is not actually visible, but the quenching resistor R1 is indicated by a chain line for the sake of clarity.

  FIG. 6 is a plan view of a photodiode array having a trench, and FIG. 7 is a view showing a vertical cross-sectional configuration of the photodiode array of FIG.

  This photodiode array is the same as the photodiode array shown in FIG. 5 except that a trench Tr is added.

  In plan view, a trench Tr is formed so as to surround the periphery of the semiconductor region 14, and the wiring E3 is located thereon. The trench is formed by embedding a core material Tr1 in a recess extending inward from the surface of the semiconductor substrate, and a trench semiconductor region Tr3 is provided around the core material Tr1. That is, the trench Tr has a conductivity type opposite to that of the semiconductor region 14 on the side where the trench Tr of the APD is provided, and has a higher impurity concentration than the surroundings (semiconductor regions 12 and 13) in contact with the trench Tr. A region Tr3 is provided.

  The trench semiconductor region Tr3 has a conductivity type opposite to that of the APD on which the trench Tr is provided, so that it can be considered that the movement of charges to the adjacent APD can be suppressed. The parasitic capacitance functions to cause charge transfer.

  Therefore, the photodetector according to the embodiment has been improved as follows.

  FIG. 8 is a plan view of a photodiode array including a trench having a cut portion, and FIG. 9 is a diagram illustrating a vertical cross-sectional configuration of the photodiode array of FIG.

  This photodetector is provided around each APD (semiconductor region 14) in the photodiode array shown in FIG. 6, and has a gap (a portion indicated by C in FIG. 7) that is partially cut off in plan view. The signal line E3 is connected to an electrode pad PAD as an output terminal through this gap.

  Specifically, the photodetector according to the embodiment is electrically connected to a plurality of APDs operating in Geiger mode, a plurality of quenching resistors R1 connected to each APD, and each quenching resistor R1. The output terminal PAD, the wiring E3 connecting the plurality of quenching resistors R1 and the output terminal PAD, and the periphery of each APD (semiconductor region 14) are provided and have gaps partially cut off in plan view. And a trench Tr having a ring shape.

  By providing the trench Tr, the charge generated in one APD can be prevented from moving to the adjacent APD, so that crosstalk can be suppressed in principle. However, when the wiring E3 crosses over the trench, the parasitic capacitance increases in such a portion, and the rise of the output pulse becomes slow. On the other hand, in this structure, the trench Tr has a gap (part C in FIG. 8), and the wiring E3 is connected to the output terminal PAD through the gap. Therefore, such a parasitic capacitance is generated. Without rising, the output pulse rises steeply. Therefore, the time resolution can be improved.

  Further, the trench semiconductor region Tr3 constituting the trench Tr has a conductivity type opposite to that of the semiconductor region 14 on the side where the trench of the APD is provided, and surrounding regions (12, 13) in contact with itself. Higher impurity region. Since the trench semiconductor region Tr3 has a conductivity type opposite to that of the APD on which the trench is provided, the movement of electric charges to the adjacent APD can be suppressed.

  The wiring E3 shown in the figure is provided at a position that does not overlap the semiconductor region 14 as the light receiving surface.

  FIG. 10 is a plan view of a photodiode array including a trench having a cut portion, and FIG. 11 is a diagram showing a vertical cross-sectional configuration of the photodiode array of FIG. 10 or FIG.

  This photodiode array is the same as the photodiode array shown in FIGS. 8 and 9 except that the wiring E3 is provided so as to cross the center of the semiconductor region 14 as the light receiving surface. Even in the case of this structure, it is possible to achieve the same effect as described above, but it is inferior to the above structure in that the wiring E3 suppresses the incidence of light. If the wiring E3 is made of a transparent material such as ITO, such a problem is solved.

  FIG. 12 is a plan view of a photodiode array having a quenching resistance made of a transparent material. The cross-sectional configuration in the figure is the same as that shown in FIG. 11, and only the position of the quenching resistor R1 is different from that in FIG. In this example, the position of the quenching resistor R1 is changed on the semiconductor region 14, and the quenching resistor R1 is made of a transparent material of a metal thin film such as SiCr or WSi. Even in the case of this structure, it is possible to achieve the same effect as described above.

  13 is a plan view of a photodiode array in which wiring is provided so as to surround the periphery of the semiconductor region 14, and FIG. 14 is a diagram showing a vertical cross-sectional configuration of the photodiode array of FIG.

  This structure is different from that shown in FIG. 12 only in the planar shape of the wiring E3, and the other points are the same. The wiring E3 surrounds the periphery of the semiconductor region 14 and stabilizes the substrate surface potential. The wiring E3 is located outside the outer edge of the semiconductor region 14, but it may be located on the outer edge. By using the transparent material described above, the aperture ratio can be increased. Also, by setting the wiring E3, it is possible to generate a sharp pulse due to the electrostatic induction effect caused by the potential difference between the light receiving surface and the wiring E3 when the Geiger avalanche is generated.

  The gap between the trenches can be set to about 5 μm (= L × 10% ± 5%) when the distance between the centers of gravity between adjacent semiconductor regions 14 is 50 μm (= L). Compared with the case where the trench is completely surrounded on all sides of the semiconductor region 14, the length of the trench non-existing region with respect to the entire circumference of the semiconductor region 14 is about 5%.

  Next, a method for fixing the potential of the trench in order to suppress crosstalk will be described.

  FIGS. 15A and 15B are a vertical sectional view and a plan view of the photodiode array. Note that voltage application in the present application is performed by using the drive circuit DRV. Electrons are indicated by black circles and holes are indicated by white circles.

  When photons enter the light receiving surface of the photodiode array and avalanche breakdown occurs in the Geiger mode, the electron / hole pairs multiplied by about 100,000 are output through the quenching resistor R1. The holes drift toward the P-type semiconductor region 14 and the electrons drift toward the N-type semiconductor region 12.

  For example, considering the case where 50 V is applied to the N-type cathode and 0 V is applied to the P-type anode, the generated carriers cannot flow immediately because the quenching resistance R1 is very large, and the light receiving surface. Are accumulated in the semiconductor region 14. As a result, the amount of charge between the PN junctions formed between the semiconductor regions 12 and 13 changes, and is accumulated according to the equation ΔV = ΔQ / C (ΔV is a voltage change, ΔQ is a charge change, and C is a capacitance). A potential change depending on the carrier occurs.

  When a voltage (excess voltage) higher than the breakdown voltage by 5V is applied to the photodiode, the potential of the light receiving surface, which was 0V in the steady state, changes by 5V due to the occurrence of avalanche breakdown (the wiring due to light incidence) The potential of E1 changes from 0V to 5V). That is, a potential difference corresponding to the excess voltage instantaneously occurs between adjacent APDs.

  Since the trench Tr and its surroundings can be regarded as capacitance, a pulse current flows through the trench and its surrounding capacitance in the APD adjacent to the APD in which Geiger avalanche multiplication has occurred ( FIG. 16A). Note that FIG. 16A illustrates a vertical cross-sectional configuration of the photodiode array when no wiring is connected to the trench. In this case, since carriers are generated in the adjacent APD, the carriers are injected into the vicinity region P2 of the PN junction, and Geiger avalanche multiplication occurs, resulting in a false signal. This phenomenon can be considered as electrical crosstalk.

  The above-described trench can greatly reduce the optical crosstalk component, but it does not become zero. For example, when an excess voltage of 5 V occurs, about 10% of crosstalk occurs in the adjacent APD.

  FIG. 16B is a diagram showing a vertical cross-sectional configuration of the photodiode array when wiring is connected to the trench.

  Although the potential of the trench can be floating, it is preferable to fix the potential of the trench (including the trench semiconductor region Tr3) in order to reduce the electrical crosstalk component. Thus, if the potential of the trench located between the APDs is fixed, the influence of the potential change on the adjacent APD is reduced.

  If the core material Tr1 (a refractory metal such as tungsten) in the trench Tr is connected to the wiring E3 (aluminum), a voltage application line different from the anode wiring is formed, and the same 50V as that of the N-type substrate is applied to this line. The potential of the trench is fixed. In this case, electrical crosstalk is reduced. Here, the bias voltage to the trench Tr is set to the same potential as the substrate. In this case, the trench core material Tr1 and the N-type trench semiconductor region Tr3 around the core material Tr1 have the same potential, and it is not necessary to consider the breakdown voltage around the trench.

  As described above, when the trench connection wiring ETr is brought into contact with and electrically connected to the core material Tr1 of the trench, the structures shown in FIGS. The structure is as shown in FIGS.

  The trench connection wiring ETr is in contact with and electrically connected to the core material Tr1 through the contact hole of the insulating layer 16. The trench connection wiring ETr can be applied with the same potential as that of the substrate, but can also be fixed to another potential.

  For example, the potential of the trench Tr can be set to 0 V, which is the same as that of the light receiving portion (semiconductor region 14). In this case, since a voltage of 50 V is applied between the core material Tr1 in the trench and the trench semiconductor region Tr3, an insulating layer Tr2 is formed inside the trench, and the core material Tr1 and the trench semiconductor are formed. The region Tr3 is separated.

  FIG. 20 is a view showing a longitudinal sectional configuration of a photodiode array having such a three-layered trench.

  Electrons generated in the vicinity region P2 of the PN junction try to pass through the three-layer trench Tr, and 0 V is applied to the trench Tr. That is, 0 V, which is the same potential, is applied to the wirings E1 and E3. As a substrate potential, 50 V is applied to the electrode E4.

  FIG. 21 is a diagram showing a vertical cross-sectional configuration in the vicinity of a three-layer trench.

  The trench Tr includes a conductive core material Tr1 and a trench semiconductor region Tr3 provided around the core material Tr1 via an insulating layer Tr2. The trench semiconductor region Tr3 has a conductivity type opposite to that of the APD on which the trench is provided, and has a higher impurity concentration than the surrounding semiconductor regions (12, 13) in contact with the trench semiconductor region Tr3.

When electrical connection is made to the trench Tr, the electrical connection can be easily made by having the conductive core material Tr1 as described above. If there is the trench semiconductor region Tr3, the movement of charges can be suppressed, but if the trench and the potential of the APD on the trench side match, the trench is biased from the substrate side, increasing the breakdown voltage in the vicinity of the trench, In order to contribute to unnecessary movement of charges, it is preferable that the core material Tr1 and the trench semiconductor region Tr3 be separated via the insulating layer Tr2. Insulating layer Tr2 is composed of BPSG or SiO _2.

  A trench connection wiring ETr is connected to the trench Tr. In the case where the trench Tr is in a floating state, there is a possibility that an electric charge flows into an adjacent APD via the capacitance of the trench Tr, but the trench Tr is constant via the trench connection wiring ETr. If it is fixed at the potential, it is possible to suppress the charge flowing into the adjacent APD.

  FIG. 22 is a plan view of a photodiode array in which a trench connection wiring ETr is added to the structure of FIG. In the figure, the trench and the trench connection wiring ETr are located at the overlapping positions except for the position of the electrode pad PAD2. In the case of this structure, since the P + wiring E3 is formed at a different location from the trench, no parasitic capacitance is generated, and the potential of the trench Tr is fixed by the trench connection wiring ETr. The occurrence of crosstalk can be suppressed.

  In the field where high time resolution is required, such as TOF-PET, for example, the smaller the capacitance of the element, the faster the rise of the output pulse waveform is advantageous for time resolution, and an increase in parasitic capacitance is not preferable. Further, since the crosstalk component becomes noise, it affects the fluctuation of the output pulse baseline and causes the time resolution to deteriorate. In the above structure, the formation of the trench suppresses the occurrence of optical crosstalk, and the light receiving portion wiring is not formed on the trench, so that no parasitic capacitance is generated, and the trench portion is formed by another wiring. Since the potential is fixed, it is possible to reduce the pulse current component through the trench capacitance for the adjacent pixels that have undergone voltage changes during the generation of Geiger avalanche. ing.

  FIG. 23 is a plan view (A) of the specific photodiode array of FIG. 22 and a plan view (B) of one photodiode.

  The above-described photodiodes (semiconductor regions 14) are arranged two-dimensionally, and the substrate surface is covered with a passivation film PM. The semiconductor region 13 is formed as a well region inside the semiconductor region 12 as a semiconductor substrate. A high-concentration n-type semiconductor region H is formed around the substrate surface so as to surround the well region, and the electrode E4 is a surface on the surface side of the substrate so as to be in contact with the n-type semiconductor region H. Is provided. The passivation film PM at the three corners of the substrate is removed, and the electrode E4 is exposed.

  The quenching resistor R1 is formed in an annular shape along the outer edge of the semiconductor region 14 and is in contact with the semiconductor region 14 at one location. That is, in the plan view of FIG. 23B, the connection point between the quenching resistor R1 and the aluminum wiring E3 is not in contact with the semiconductor region 14; At the position where the chucking resistor R1 has a small square shape), it is electrically connected to the semiconductor region 14 via an aluminum contact electrode (wiring E1). The wiring E3 surrounds the quenching resistor R1, the trench connection wiring ETr is provided on the outer side, and the trench Tr is located below the wiring E3. The trench connection wiring ETr is connected to the electrode pad PAD2.

  Note that the semiconductor region 14 described above is a diffusion region (semiconductor region) formed by diffusing impurities into the semiconductor layer 13, and has a higher impurity concentration than the semiconductor layer 13. In this example (type 1), a p-type semiconductor layer 13 is formed on an n-type semiconductor region 12, and a p-type semiconductor region 14 is formed on the surface side of the semiconductor layer 13. Therefore, the pn junction constituting the photodiode is formed between the semiconductor region 12 and the semiconductor layer 13.

  As the layer structure of the semiconductor substrate, a structure in which the conductivity type is reversed from the above can be adopted. That is, the (type 2) structure is formed by forming an n-type semiconductor layer 13 on a p-type semiconductor region 12 and forming an n-type high-concentration impurity region 14 on the surface side of the semiconductor layer 13. Is done.

  Also, the pn junction interface can be formed on the surface layer side. In this case, in the (type 3) structure, the n-type semiconductor layer 13 is formed on the n-type semiconductor region 12, and the p-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. It becomes a structure. In the case of this structure, the pn junction is formed at the interface between the semiconductor layer 13 and the semiconductor region 14.

  Of course, even in such a structure, the conductivity type can be reversed. That is, the (type 4) structure is such that a p-type semiconductor layer 13 is formed on a p-type semiconductor region 12 and an n-type high-concentration impurity region 14 is formed on the surface side of the semiconductor layer 13. It becomes.

  In addition, the suitable range of the conductivity type, impurity concentration, and thickness of each layer in the above-described semiconductor structure can be set as follows.

(Type 1)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(N-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 2)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(P-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 3)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(N-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)
(Type 4)
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(P-type / 5 × 10 ¹¹ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Semiconductor region 14 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 10 to 1000 nm)

  The concentration of the semiconductor region Tr3 for trenches may be higher or lower than that of the semiconductor regions 12 and 13. Further, the concentration of the semiconductor region Tr3 for trench may be the same as the concentration of the semiconductor region 12.

  FIG. 25 is a cross-sectional view of the structure in such a case, and is a cross-sectional view of the structure in which Tr3 is omitted in the structure of FIG. In this case, the impurity concentration of the trench semiconductor region Tr3 provided around the core material Tr1 is the same as the impurity concentration of the semiconductor region 12, but may be lower than this. Note that this impurity concentration relationship can be applied to the cross-sectional structure in the above-described embodiment. When the semiconductor region 12 is n-type with a high impurity concentration, the semiconductor region 13 is n-type with a low impurity concentration, and the semiconductor region 14 is p-type, the semiconductor region Tr3 for trenches with a high impurity concentration is It can be omitted. If the semiconductor region adjacent to the inner wall of the trench is n-type having a conductivity type opposite to that of the semiconductor region 14, the above-described effects can be obtained.

An example in which the impurity concentration in the trench semiconductor region Tr3 is lower than that in the semiconductor region 12 will be described below. The above-described properties can be used for the semiconductor region 14.
Semiconductor region 12 (conductivity type / impurity concentration / thickness)
(N-type / 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ / 30 to 700 μm)
Semiconductor region 13 (conductivity type / impurity concentration / thickness)
(P-type / 1 × 10 ¹⁴ to 1 × 10 ¹⁷ cm ⁻³ / 2 to 50 μm)
Trench semiconductor region Tr3 (conductivity type / impurity concentration)
(N-type / 1 × 10 ^{15 to} cm ⁻³ )

  Each semiconductor region 13 can also be separated from each other corresponding to each semiconductor region 14 by forming a well region.

  FIG. 24 shows a detector including the above-described photodiode array (photodetector D1) and scintillator SC, and can be applied to a PET apparatus or a CT apparatus. In this case, when radiation such as X-rays or γ-rays enters the scintillator SC, fluorescence is generated, and the fluorescence is detected by the photodetector D1.

  SC ... scintillator, R1 ... quenching resistor, D1 ... photodetector, Tr ... trench.

Claims (5)

Multiple APDs operating in Geiger mode;
A plurality of quenching resistors respectively connected to each of the APDs;
An output terminal electrically connected to each quenching resistor;
Wiring for connecting the plurality of quenching resistors and the output terminal;
A trench having a ring shape provided around each of the APDs and having a gap partially cut off in plan view;
With
The wiring is connected to the output terminal through the gap.
A photodetector. The trench is
The photodetector according to claim 1, further comprising a trench semiconductor region having a conductivity type opposite to a side of the APD on which the trench is provided. The trench is
A conductive core material;
A trench semiconductor region provided around the core member via an insulating layer and having a conductivity type opposite to the side of the APD on which the trench is provided;
The photodetector according to claim 1, further comprising:   The photodetector according to claim 2, further comprising a wiring electrically connected to the trench. Multiple APDs operating in Geiger mode;
A plurality of quenching resistors respectively connected to each of the APDs;
An output terminal electrically connected to each quenching resistor;
Wiring for connecting the plurality of quenching resistors and the output terminal;
A trench provided around each of the APDs;
A wiring electrically connected to the trench;
A photodetector comprising:

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