JP2015077850A - Circuit board of vehicular display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a vehicular display meter which can be shared over a plurality of kinds of vehicles with different memory constitutions.SOLUTION: A circuit board 3 of a vehicular display 1, which comprises control means 6 controlling a volatile memory 5 and foot patterns 5a, 5b, and 5c to be wired in a daisy chain manner that can selectively package at least two volatile memories 5, is provided with a series resistance between the controller 6 and the foot patterns 5a, and is provided with a foot pattern TRb that can selectively package a series resistance parting the foot pattern 5a and the foot pattern 5b so as to have a wiring length corresponding to the drive frequency of the volatile memories 5. Series termination with the foot pattern TRb opened is carried out in the case of singular package of the volatile memories 5, and the foot pattern TRb is packaged with the series resistance, and parallel termination is carried out in the case of plural package of the volatile memories 5.

Description

  The present invention relates to a circuit board of a display device for a vehicle that can be shared across a plurality of vehicle types.

  In recent years, due to the increase in vehicle information and higher definition of display devices, it has been required for vehicle-mounted instruments to display a wide variety of vehicle-mounted information with highly decorative images. Is required to read and write at high speed.

  DDR-SDRAM (Double Data Synchronous Dynamic Random Access Memory, simply called DDR), DDR2, DDR3, which is an interface circuit that performs high-speed data transfer, while being highly integrated as a memory that reads and writes a large amount of image data at high speed There is a standard called.

  In such communication standards, it is necessary to terminate the line in an appropriate manner to prevent signal reflection due to impedance mismatch at the end, and to prevent waveform distortion due to reflection and to ensure signal integrity. It becomes.

  In particular, when a circuit is constituted by a plurality of DDR3s, a single parallel termination (JESD8-JESD standard) is used as a method of terminating address signals and command signals in terms of ease of ensuring signal integrity. 6) or a double parallel termination method (Class II in JESD8-6) is generally used.

  On the other hand, when a circuit is configured with a single DDR3, signal integrity can be ensured relatively easily. Therefore, using a series termination method in which parallel termination is not arranged on the transmission line is advantageous in terms of cost reduction.

  In addition, in order to reduce the product cost per vehicle type, a circuit board that can be used for a plurality of vehicle types with different required memory capacity and bus width is desired. For example, as in Patent Document 1, The IC socket for mounting the memory with the largest storage capacity among the memory ICs can be mounted on the printed circuit board in advance by the additional capacity so that the memory can be expanded and the area occupied by the printed circuit board IC socket is not increased. And switching means for switching the wiring state corresponding to the difference in the pins of the memory IC to be mounted when the memory IC having a different pin arrangement is mounted due to the storage capacity being different in the IC socket. An indicator is disclosed.

JP-A-4-222002

  As mentioned above, when configuring a circuit board that can be shared for multiple vehicle types that require different memory capacities and bus widths, the purpose is to reduce product costs. It is desirable in terms of cost that the termination method can be switched to a series termination or a parallel termination depending on the number.

  However, in a circuit board where the number of memory mounts can be selected to be singular or plural, when the number of memory mounts is singular, the wiring between the mounted memory and the foot pattern of the unmounted memory is an open stub. Therefore, the signal of the mounted memory is reflected at the end of the stub and returns to the branch point, adversely affects the signal waveform of the mounted memory, and the resistance value used for series termination is uniquely determined. It was difficult and the series termination method could not be selected.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a vehicle display instrument that can be shared across a plurality of vehicle types having different memory configurations at a low cost.

Volatile memory,
Control means for controlling the volatile memory;
A volatile memory foot pattern capable of selectively implementing at least two of the volatile memories;
A wiring board for connecting the volatile memory foot pattern and the control means in a daisy chain, and a circuit board of a display device for a vehicle,
On the wiring between the control means and the first volatile memory foot pattern closest to the control means among the volatile memory foot patterns, a first series resistor is provided,
The first volatile memory foot pattern side is on the wiring between the first volatile memory foot pattern and the second volatile memory foot pattern next to the control means next to the first volatile memory foot pattern. A second series resistor foot pattern capable of selectively mounting a series resistor, which is divided so as to have a wiring length corresponding to the driving frequency of the volatile memory,
When one volatile memory is mounted on the volatile memory foot pattern, the volatile memory is mounted on the first volatile memory foot pattern and a series resistance is added to the second series resistance foot pattern. Not implemented.

A parallel resistance foot pattern capable of selectively mounting a parallel resistance at a position farther from the control means on the wiring than the foot pattern of the volatile memory farthest from the control means mounted on the volatile memory foot pattern Provided,
When two or more volatile memories are mounted on the volatile memory foot pattern, a series resistor is mounted on the second series resistor foot pattern, and a parallel resistor is mounted on the parallel resistor foot pattern.

  A vehicle display instrument that can be shared across a plurality of vehicle types having different memory configurations can be provided at low cost.

The front view of the display apparatus for vehicles by the embodiment of the present invention. The block diagram which shows the electrical constitution of the display apparatus for vehicles by the embodiment. The circuit diagram of the address signal line of the control means and volatile memory by the embodiment.

  A vehicle display device according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 3 of the accompanying drawings.

  The vehicle display device 1 according to this embodiment includes a display unit 2, a circuit board 3, a nonvolatile memory 4, a volatile memory 5, and a control unit 6.

  The display means 2 uses a flat panel display such as a liquid crystal display or an organic EL.

  The circuit board 3 is provided with wiring and foot patterns for mounting a nonvolatile memory 4, a volatile memory 5, and a control means 6 which will be described later.

  The non-volatile memory 4 is, for example, a flash memory, and stores in advance a program of the control means 6 and various image data constituting an instrument display.

  The volatile memory 5 is made of DDR3, for example, and a maximum of three can be selectively mounted on the foot patterns 5a, 5b, and 5c of the volatile memory 5 provided on the circuit board 3.

  The control means 6 is a CPU that incorporates a controller that can control a plurality of volatile memories 5 in its entirety, reads image data stored in advance in the nonvolatile memory 4 into the volatile memory 5 as appropriate, An instrument image corresponding to various vehicle information input from the in-vehicle LAN 7 is constructed and displayed on the display means 2.

  Next, the relationship between the number of mounted volatile memories 5 and the wiring will be described based on the circuit diagram shown in FIG.

  As shown in FIG. 3, the circuit board 3 forms wiring for connecting the plurality of volatile memories 5 to the control means 6 in a daisy chain with respect to the address signal of the volatile memory 5.

  The volatile memory foot pattern (first volatile memory foot pattern) 5a, foot pattern (second volatile memory foot pattern) 5b, and foot pattern (third volatile memory foot pattern) 5c depend on the number of mounting. The volatile memory 5 is mounted as necessary in order from the side closer to the control means 6. More specifically, the volatile memory is mounted in the order of foot patterns 5a, 5b, and 5c according to the number of mounting.

  On the wiring of the circuit board 3, a foot pattern (first series resistance foot pattern) DRa is provided between the control means 6 and the foot pattern 5a, and a foot pattern (second series resistance foot pattern) is provided between the foot pattern 5a and the foot pattern 5b. DRb is arranged. By mounting a damping resistor, a 0Ω resistor, or a jumper on these foot patterns DRa and DRb, wirings at both ends are electrically connected.

  Here, in the foot pattern DRb, when the resistor is not mounted on the foot pattern DRb, the wiring between the foot pattern 5a and the foot pattern 5b is electrically divided. Further, the signal output from the control means 6 is transmitted to a volatile memory mounted on the foot pattern 5a, and wiring that becomes a stub as viewed from the electrical connection relationship between the control means 6 and the foot pattern 5a (see FIG. 3 is totally reflected at the end of the branch point A and the foot pattern DRb), returns to the branch point A again, and affects the signal transmitted to the foot pattern 5a. The foot pattern DRb is arranged at a position having a length which will be described later.

  Specifically, regarding the arrangement of the foot pattern DRb, when the operating frequency of the volatile memory 5 is 500 MHz, from the viewpoint of signal integrity, the rising and falling edges of the transmission signal are sufficiently steep so as to be 3 A description will be given using an example of wiring design to the extent that a double frequency (1.5 GHz) signal can pass.

  The signal wavelength λ is obtained by the following equation from the light velocity c, the wavelength f, and the relative dielectric constant ε when the relative permeability is assumed to be 1.

From the above equation, assuming that the relative dielectric constant ε of the circuit board 3 is 3.8, and assuming that the frequency f of the signal traveling through the wiring of the circuit board 3 is 1.5 GHz, the light velocity c is about 299992458 m / s. Therefore, the signal wavelength λ is about 103 mm.
Here, when the wiring that becomes the stub is λ / 4 (≈25.75 mm), the signal reflected from the wiring end that becomes the stub to the branch point A and the signal transmitted from the control means 6 to the foot pattern 5a are: As a result, the signals cancel each other out of phase (180 ° phase), and a signal is not transmitted correctly between the control means 6 and the volatile memory 5 mounted on the foot pattern 5a.
Therefore, the foot pattern DRb is arranged at a position where the wiring length to be a stub is less than λ / 4.

  On the wiring of the circuit board 3, a foot pattern (parallel resistance foot pattern) TR is arranged at a position on the end of the wiring more than the foot patterns 5a, 5b, 5c. By mounting a parallel resistance on the foot pattern TR, parallel termination is performed using the termination voltage VTT.

  Specifically, a case where one volatile memory is mounted on the circuit board 3 (single mounting) and a case where three volatile memories are mounted (multiple mounting) are shown.

  When mounting one volatile memory 5 on the circuit board 3, the volatile memory 5 is mounted on the foot pattern 5a, and a series resistance (first series resistance) having an appropriate resistance value is mounted on the foot pattern DRa. Nothing is mounted on the foot patterns 5b, 5c, TR. In this configuration, the signal reflected at the end of the wiring between the branch point A and the foot pattern DRb may adversely affect the signal waveform between the volatile memory 5 and the control means 6 mounted on the foot pattern 5a. By setting the wiring length between the branch point A and the foot pattern DRb to be less than λ / 4, the influence can be reduced, and series termination by a resistor mounted on the foot pattern DRa can be performed.

  On the other hand, when three volatile memories 5 are mounted on the circuit board 3, the volatile memory 5 is mounted on each of the foot patterns 5a, 5b, and 5c, the first series resistor is mounted on the foot pattern DRa, and the second pattern is mounted on the foot pattern DRb. Two series resistors are mounted by selecting appropriate resistance values, and parallel resistors are mounted on the foot pattern TR. With this configuration, the circuit board 3 is terminated in parallel by a resistor mounted on the foot pattern TR.

  Thus, the circuit board 3 can be terminated by a series termination when a single volatile memory 5 is mounted, and can be terminated by a parallel termination when a plurality of volatile memories 5 are mounted. A vehicle display instrument that can be shared across a plurality of different vehicle types can be provided at low cost.

Although the embodiment has been described above, the present invention can be applied not only to the circuit configuration of the address signal of the volatile memory 5 but also to the command signal.

DESCRIPTION OF SYMBOLS 1 Display apparatus 2 for vehicles Display means 3 Circuit board 4 Non-volatile memory 5 Volatile memory 5a Foot pattern (1st volatile memory foot pattern)
5b Foot pattern (second volatile memory foot pattern)
5c Foot pattern (third volatile memory foot pattern)
6 Control means 7 Car LAN
DRa foot pattern (first series resistance foot pattern)
DRb foot pattern (second series resistance foot pattern)
TR foot pattern (parallel resistance foot pattern)

Claims (2)

Volatile memory,
Control means for controlling the volatile memory;
A volatile memory foot pattern capable of selectively implementing at least two of the volatile memories;
A wiring board for connecting the volatile memory foot pattern and the control means in a daisy chain, and a circuit board of a display device for a vehicle,
On the wiring between the control means and the first volatile memory foot pattern closest to the control means among the volatile memory foot patterns, a first series resistor is provided,
The first volatile memory foot pattern side is on the wiring between the first volatile memory foot pattern and the second volatile memory foot pattern next to the control means next to the first volatile memory foot pattern. A second series resistor foot pattern capable of selectively mounting a series resistor, which is divided so as to have a wiring length corresponding to the driving frequency of the volatile memory,
When one volatile memory is mounted on the volatile memory foot pattern, the volatile memory is mounted on the first volatile memory foot pattern and a series resistance is added to the second series resistance foot pattern. A circuit board of a display device for a vehicle, which is not mounted. A parallel resistance foot pattern capable of selectively mounting a parallel resistance at a position farther from the control means on the wiring than the foot pattern of the volatile memory farthest from the control means mounted on the volatile memory foot pattern Provided,
When two or more volatile memories are mounted on the volatile memory foot pattern, a series resistance is mounted on the second series resistance foot pattern, and a parallel resistance is mounted on the parallel resistance foot pattern. The circuit board of the vehicle display device according to claim 1.

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