JP2015072998A - Ferroelectric memory and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a ferroelectric memory and a method of manufacturing the same, and suppresses deterioration of a capacitor dielectric film due to generation of hydrogen. A sidewall of a contact hole reaching a lower electrode of a ferroelectric capacitor is covered with a water permeation preventive film, and then buried with a conductive member to form a lower electrode plug. When forming the contact hole for the lower electrode, the contact hole is formed so as not to reach the lower electrode, and the water permeation preventive film is formed on the side wall thereof, and then the lower electrode is exposed. Even if the Pt redeposition film adheres to the side wall of the contact hole, the water permeation preventive film exists, so that H that causes the deterioration of the ferroelectric capacitor by reacting with the H 2 O of the interlayer insulating film does not occur. [Selection] Figure 1

Description

  The present invention relates to a ferroelectric memory and a manufacturing method thereof, for example, a ferroelectric memory in which deterioration of a capacitor dielectric film due to generation of hydrogen is suppressed and a manufacturing method thereof.

  Flash memories and ferroelectric memories (FeRAM: Ferroelectric Random Access Memory) are known as nonvolatile memories that do not lose data even when the power is turned off. Ferroelectric memories have the advantages of lower power consumption and higher speed operation than flash memories.

  A ferroelectric capacitor used in a ferroelectric memory has a structure in which a ferroelectric film is sandwiched between a lower electrode and an upper electrode. The ferroelectric film is formed of a ferroelectric material having ferroelectric properties (polarization properties) such as PZT (lead zirconate titanate).

  In a ferroelectric memory, a predetermined voltage is applied between an upper electrode and a lower electrode to generate polarization in the ferroelectric film. Even if the application of voltage is stopped in this state, polarization (residual polarization) corresponding to the applied voltage remains in the ferroelectric film. The ferroelectric film has two stable polarization states corresponding to the applied voltage. By making one polarization state correspond to “0” and the other polarization state correspond to “1”, the ferroelectric film Data is recorded in the memory (see, for example, Patent Document 1).

However, oxide ferroelectrics are easily reduced by a reducing substance such as hydrogen, and the ferroelectric properties such as remanent polarization are significantly deteriorated. In particular, since a silicon oxide film used for an interlayer insulating film contains H ₂ O in the film formation atmosphere, a structure for protecting the capacitor dielectric film from hydrogen generated by decomposition of H ₂ O is required. . For this reason, it has been proposed to cover a ferroelectric capacitor with a hydrogen barrier film (see, for example, Patent Document 2).

Here, an example of a ferroelectric capacitor constituting a conventional ferroelectric memory will be described with reference to FIG. FIG. 7 is a schematic sectional view of a conventional ferroelectric capacitor. From an interlayer insulating film 61, an adhesion layer 62 made of an Al ₂ O ₃ film, a lower electrode 63 made of Pt, and PZT (lead zirconate titanate). A ferroelectric film 64 and an upper electrode 65 made of IrO ₂ are sequentially deposited. Next, the upper electrode 65 through the adhesion layer 62 are sequentially etched to form a ferroelectric capacitor 66 comprising the lower electrode 63 / ferroelectric film 64 / upper electrode 65. Here, the upper electrode 65 is formed in an island shape, and one upper electrode corresponds to one capacitor, and actually several tens of capacitors are arranged.

Next, interlayer insulation made of SiO ₂ by a CVD (vapor phase growth) method using tetraethylorthosilicate (TEOS: Si (OC ₂ H ₅ ) ₄ ) gas as a reactive gas through a protective film 67 made of an Al ₂ O ₃ film. A film 68 is formed, and then the interlayer insulating film 68 and the protective film 67 are etched to form contact holes reaching the upper electrode 65 and the lower electrode 63.

  Next, the contact hole is filled with a W film 70 through a barrier metal 69 made of a Ti film / TiN film, thereby forming a lower electrode plug 71 and an upper electrode plug 72 to be an extraction electrode. Next, a Ti film 73, an Al film 74, and a Ti film 75 are sequentially deposited, and etched into a predetermined shape to form metal wirings connected to the lower electrode plug 71 and the upper electrode plug 72, whereby the strength shown in FIG. A dielectric capacitor is obtained.

JP 2003-197742 A JP 2010-212574 A

  In such a ferroelectric capacitor, a phenomenon that remanent polarization is reduced occurs in some capacitors. Here, as a result of investigating the lower electrode plug, the reattachment of the lower electrode was adhered to the side wall portion of the contact hole, and the situation will be described with reference to FIG. FIG. 8 is an explanatory view of the situation in the vicinity of a conventional ferroelectric capacitor lower electrode plug.

As shown in FIGS. 8A and 8B, it was confirmed that the Pt reattachment film 78 which is the component of the lower electrode 63 exists on the wall surface of the contact hole in which the lower electrode plug 71 is embedded. As shown in FIG. 8A, the residual polarization does not decrease when the Al ₂ O ₃ redeposition film 77 that is a component of the protective film 67 exists on the wall surface of the contact hole. On the other hand, as shown in FIG. 8B, the residual polarization decreases when the Al ₂ O ₃ redeposition film 77 does not exist on the wall surface of the contact hole and only the Pt redeposition film 78 exists. I understood it. Incidentally, the average thickness of the Al ₂ O ₃ redeposition film 77 in FIG. 8A was 7 nm.

Here, the cause of deterioration of the conventional ferroelectric capacitor will be described with reference to FIG. As shown in FIG. 8A, when the Al ₂ O ₃ redeposition film 77 is present on the wall surface of the contact hole in which the lower electrode plug 71 is buried, the Pt redeposition film 78 and the interlayer insulating film 68 do not contact each other. However, as shown in FIG. 8B, if the Al ₂ O ₃ redeposition film 77 does not exist, the Pt redeposition film 78 and the interlayer insulating film 68 come into contact with each other.

Then, as shown in FIG. 9, hydrogen (H) is generated from the water (H ₂ O) present in the interlayer insulating film 68 by the catalytic effect of platinum, and the generated H is generated in the interlayer insulating film 68 or the protective film 67. / It is considered that the interface of the lower electrode 63 is diffused to reach the ferroelectric film 64 and the ferroelectric film 64 is reduced and deteriorated.

  Therefore, an object of the ferroelectric memory and the manufacturing method thereof is to suppress deterioration of the capacitor dielectric film due to generation of hydrogen.

  From one aspect to be disclosed, a semiconductor substrate, a first insulating film formed above the semiconductor substrate, and a lower electrode formed on the first insulating film and stacked in order from the first insulating film side / Ferroelectric film / Ferroelectric capacitor having an upper electrode, and a second insulating film covering the side surface and the upper surface of the ferroelectric capacitor, provided on the second insulating film, A ferroelectric memory comprising: a contact hole reaching the electrode; a water permeation preventive film covering a wall surface of the contact hole; and a lead electrode embedded in the contact hole via the water permeation preventive film Is provided.

  Further, from another viewpoint to be disclosed, a step of forming a first insulating film above a semiconductor substrate, and a lower electrode, a ferroelectric film, and a layer on the first insulating film in order from the first insulating film side A step of forming a ferroelectric capacitor by laminating an upper electrode; a step of forming a protective film covering the ferroelectric capacitor; a step of forming a second insulating film covering the protective film; and the second insulation. Forming a mask film on the film; selectively etching the second insulating film and the mask film to form a contact hole; and a water permeation preventive film covering the inner surface of the contact hole and the mask film Etching, removing the protective film and the water permeation preventive film on the bottom of the contact hole, the water permeation preventive film and the mask film on the second insulating film, and the contact Ho Within manufacturing method of a ferroelectric memory, comprising a step of forming a conductive member for connecting the the lower electrode electrically it is provided.

  According to the disclosed ferroelectric memory and the manufacturing method thereof, it is possible to suppress deterioration of the capacitor dielectric film due to generation of hydrogen.

1 is a schematic cross-sectional view of a main part of a ferroelectric capacitor according to an embodiment of the present invention. It is explanatory drawing to the middle of the manufacturing process of the ferroelectric capacitor of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 2 of the manufacturing process of the ferroelectric capacitor of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 3 of the manufacturing process of the ferroelectric capacitor of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 4 of the manufacturing process of the ferroelectric capacitor of Example 1 of this invention. FIG. 6 is an explanatory view after FIG. 5 of the manufacturing process of the ferroelectric capacitor of Example 1 of the present invention. It is a schematic sectional drawing of the conventional ferroelectric capacitor. It is explanatory drawing of the condition in the vicinity of the plug for lower electrodes of the conventional ferroelectric capacitor. It is explanatory drawing of the cause of deterioration of the conventional ferroelectric capacitor.

  Here, the ferroelectric memory according to the embodiment of the present invention will be described with reference to FIG. 1. Here, the illustration of the selection transistor and the like is omitted, and only the vicinity of the ferroelectric capacitor is illustrated. FIG. 1 is a schematic cross-sectional view of a principal part of a ferroelectric memory according to an embodiment of the present invention. A semiconductor substrate (not shown) and a first insulating film 1 are formed above the semiconductor substrate. A lower electrode 4 / ferroelectric film 5 / upper electrode 6 are sequentially formed on the first insulating film 1 to form a ferroelectric capacitor 3. A side surface and an upper surface of the ferroelectric capacitor 3 are covered with a second insulating film 8 through a protective film 7.

  After providing a contact hole reaching the lower electrode 4 in the second insulating film 8, a water permeation preventive film 9 covering the wall surface of the contact hole is provided, and a lower electrode plug 12 serving as an extraction electrode through the water permeation preventive film 9 is provided. Form. Normally, after providing a contact hole reaching the upper electrode 6 at the same time, a water permeation preventive film 9 covering the wall surface of the contact hole is provided, and an upper electrode plug 13 serving as an extraction electrode is provided via the water permeation preventive film 9. Form. Next, a wiring 14 connected to the lower electrode plug 12 and the upper electrode plug 13 is formed.

The lower electrode 4 is typically Pt, the ferroelectric film 5 is typically a PZT film, and the upper electrode 6 is typically IrO _2. It is not limited to these materials. For example, Pt may be used as the upper electrode 6. In this case, it is essential to provide the water permeation preventive film 9 on the wall surface of the contact hole for forming the upper electrode plug. The ferroelectric film 5 may also be a Bi-based ferroelectric film of (Bi, Ln) ₄ Ti ₃ O ₁₂ (Ln = La, Nd, Pr, etc.). As a method for forming the ferroelectric film 5, an MOCVD (Metal Organic CVD) method or a sol-gel method may be used in addition to the sputtering method.

The water permeation preventive film 9 and the protective film 7 are typically Al ₂ O ₃ films. The water permeation preventive film 9 is made of a SiN film, a Ti film, a TiN film, a TiAlN film, a TaN film, or the like. It may be used. The lower electrode plug 12 and the upper electrode plug 13 are formed by embedding a conductor film through a barrier metal 10, and TiN, TaN or a Ti / TiN laminated film is typical as the barrier metal. W is a typical conductor film. The material of the wiring is also arbitrary, but typically a laminated film of Ti film 15 / Al film 16 / Ti film 17 is used, but an embedded Cu wiring formed by a damascene method may be used.

The second insulating film 8 is typically a SiO ₂ film formed by a CVD (vapor phase growth) method using tetraethylorthosilicate (TEOS: Si (OC ₂ H ₅ ) ₄ ) gas as a reactive gas. However, the present invention is not limited to the TEOS-CVD film, and is applied to an insulating film containing H ₂ O derived from the manufacturing method.

Next, the manufacturing process of the ferroelectric memory according to the first embodiment of the present invention will be described with reference to FIGS. 2 and 6. FIGS. 4 (e) to 5 (g) show the ferroelectric capacitor. A sectional view of only the vicinity is shown. First, as shown in FIG. 2A, a trench for element isolation is formed in the silicon substrate 21, and a SiO ₂ film is embedded in the trench as an element isolation insulating film 22 that defines an active region. Such an element isolation structure is called STI (Shallow Trench Isolation), but element isolation may be performed by LOCOS (Local Oxidation of Silicon) instead.

  Next, p-type impurities are ion-implanted into the active region to form a p-type well region 23. Next, the surface of the p-type well region 23 is thermally oxidized to form a gate insulating film 24 made of a thermal oxide film. Next, a polysilicon film to be the gate electrode 25 and a cobalt silicide film are formed in this order on the gate insulating film 24 by a CVD method, and a protective film 26 made of a SiN film is formed thereon. These films are patterned to form the gate electrode 25.

Next, using the gate electrode 25 as a mask, n-type impurities are ion-implanted into the p-type well region 23 to form a low-concentration n-type extension region 27. Next, an insulating film such as SiO ₂ is formed on the entire upper surface of the silicon substrate 21 by a CVD method, and the insulating film is etched back to form sidewalls 28 on the side surfaces of the gate electrode 25.

  Next, n-type impurities are ion-implanted into the p-type well region 23 using the sidewall 28 and the gate electrode 25 as a mask, thereby forming a high-concentration n-type drain region 29 and an n-type source region 30. Thus, a selection MOS transistor having a DDD (Double Doped Drain) structure is formed. Next, although not shown, after depositing a Co film on the entire surface, a source electrode and a drain electrode made of Co silicide are formed by heat treatment, and the unreacted Co film is removed.

  Next, the cover insulating film 31 and the first interlayer insulating film 32 are formed in this order on the entire surface by the CVD method, and the upper surface of the first interlayer insulating film 32 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. For example, a silicon oxynitride (SiON) film having a thickness of about 200 nm is used as the cover insulating film 31, and a silicon oxide film having a thickness of about 300 nm is used as the first interlayer insulating film 32, for example.

Next, an Al ₂ O ₃ film having a thickness of 20 nm is formed as the adhesion layer 33 on the first interlayer insulating film 32 by sputtering. Next, a Pt film having a thickness of 150 nm to be the lower electrode 34 is formed on the adhesion layer 33 by sputtering. Next, a ferroelectric film 35 made of lead zirconate titanate (PZT) film added with Ca, Sr and La having a thickness of 90 nm is formed on the lower electrode 34 by sputtering. To do. Next, an IrO ₂ film having a thickness of 200 nm to be the upper electrode 36 is formed on the ferroelectric film 35 by sputtering.

  Next, as shown in FIG. 2B, a resist pattern (not shown) having the pattern shape of the upper electrode of the ferroelectric capacitor is formed on the upper electrode 36, and the upper electrode 36 is formed using this resist pattern as a mask. Etch. Next, the resist pattern is removed, a resist pattern (not shown) having a pattern shape of the ferroelectric film 35 of the ferroelectric capacitor is newly formed, and the ferroelectric film 35 is etched using the resist pattern as a mask. To do. Further, the resist pattern is removed, a resist pattern (not shown) having a pattern shape of the lower electrode 34 of the ferroelectric capacitor is newly formed, and the lower electrode 34 and the adhesion layer 33 are etched using the resist pattern as a mask. To do. As a result, a ferroelectric capacitor 37 having a shape as shown in FIG. 2B is formed.

Next, as shown in FIG. 3C, an Al ₂ O ₃ film with a thickness of 50 nm is formed as a protective film 38 by sputtering. Next, a 1500 nm SiO ₂ film is deposited on the entire surface by TEOS-CVD, and then the upper surface is planarized by CMP to form a second interlayer insulating film 39. Next, as shown in FIG. 3D, an Al ₂ O ₃ film having a thickness of 50 nm to be the mask film 40 is formed by sputtering.

Next, as shown in FIG. 4E, a resist pattern 41 having an opening for a contact hole is provided, and dry etching using CF ₄ is performed using the resist pattern 41 as a mask, thereby protecting the lower electrode side. A first contact hole 42 reaching the film 38 is formed. At this time, since the lower electrode 34 is not exposed, the Pt redeposition film does not adhere to the side wall of the first contact hole 42. On the other hand, the second contact hole 43 reaching the upper electrode 36 is simultaneously formed on the upper electrode side.

Next, as shown in FIG. 4F, after removing the resist pattern 41, an Al ₂ O ₃ film to be the H ₂ O permeation preventive film 44 is formed on the entire surface by sputtering. At this time, an Al ₂ O ₃ film is deposited so that the thickness of the side wall of the first contact hole 42 is 7 nm. If the aspect ratio of the first contact hole 42 is large, an atomic layer deposition method may be used instead of the sputtering method.

Next, as shown in FIG. 5G, dry etching is performed on the entire surface to remove the H ₂ O permeation preventive film 44 and the protective film 38 at the bottoms of the first contact hole 42 and the second contact hole 43, The contact hole 42 reaches the lower electrode 34. At this time, since the mask film 40 and the protective film 38 have the same thickness, the H ₂ O permeation preventive film 44 and the mask film 40 on the second interlayer insulating film 39 are removed, but dry etching has anisotropy. Therefore, the H ₂ O permeation preventive film 44 on the wall surface of the first contact hole 42 remains without being removed. Here, since the surface of the lower electrode 34 is etched, a Pt reattachment film may be formed. However, since the H ₂ O permeation prevention film 44 exists on the wall surface of the first contact hole 42, the Pt reattachment film is formed. There is no contact with the second interlayer insulating film 39.

  Next, as shown in FIG. 5H, a resist pattern 45 having openings corresponding to contact holes for the source / drain regions is formed. Using the resist pattern 45 as a mask, the second interlayer insulating film 39 to the cover insulating film 31 are etched to form contact holes 46 reaching the n-type drain region 29 and the n-type source region 30.

  Next, as shown in FIG. 6I, a Ti film and a TiN film are formed as a barrier metal 47 in the first contact hole 42, the second contact hole 43, and the contact hole 46, and then a W film is embedded. Next, the surface of the conductive film is planarized by performing CMP to form a lower electrode plug 49, an upper electrode plug 50, a drain electrode plug 51, and a source electrode plug 52.

  Next, as shown in FIG. 6J, a Ti film 53, an Al film 54, and a Ti film 55 are sequentially deposited on the entire surface, and etched into a predetermined shape to form a metal wiring 56. The basic structure of the ferroelectric memory is completed. The upper electrode plug 50 is formed with a metal wiring 56 so as to be connected to the drain electrode plug 51.

Thus, in Example 1 of the present invention, when forming the contact hole for the lower electrode, the contact hole was formed so as not to reach the lower electrode, and the H ₂ O permeation preventive film was formed on the side wall thereof. After that, the lower electrode is exposed. Therefore, even if the Pt redeposition film derived from the lower electrode adheres to the side wall of the contact hole, the H ₂ O permeation preventive film exists, so that it reacts with H ₂ O derived from the second interlayer insulating film and reacts with the ferroelectric capacitor H, which causes deterioration of the film, does not occur.

Here, the following supplementary notes are attached to the embodiment of the present invention including the first embodiment.
(Supplementary Note 1) A semiconductor substrate, a first insulating film formed above the semiconductor substrate, and a lower electrode / ferroelectric layer formed on the first insulating film and stacked in order from the first insulating film side A ferroelectric capacitor having a body film / upper electrode, and a second insulating film covering a side surface and an upper surface of the ferroelectric capacitor, provided on the second insulating film, and reaching the lower electrode A ferroelectric memory comprising: a contact hole; a water permeation preventive film covering a wall surface of the contact hole; and an extraction electrode embedded in the contact hole via the water permeation preventive film.
(Appendix 2) The ferroelectric memory as set forth in Appendix 1, wherein the water permeation preventive film is an Al ₂ O ₃ film.
(Supplementary note 3) The ferroelectric memory according to Supplementary note 1 or 2, wherein the lower electrode is made of Pt.
(Supplementary note ₄ ) Any one of Supplementary notes 1 to 3, wherein the second insulating film is a silicon oxide film formed by a vapor phase growth method using Si (OC ₂ H ₅ ) ₄ as a source gas. The ferroelectric memory described in 1.
(Supplementary note 5) The ferroelectric memory according to supplementary note 4, wherein a protective film made of an Al ₂ O ₃ film is interposed between the second insulating film and at least the lower electrode.
(Appendix 6) A step of forming a first insulating film above a semiconductor substrate, and a lower electrode, a ferroelectric film, and an upper electrode are stacked on the first insulating film in that order from the first insulating film side. Forming a ferroelectric capacitor; forming a protective film covering the ferroelectric capacitor; forming a second insulating film covering the protective film; and forming a mask film on the second insulating film. Forming a contact hole by selectively etching the second insulating film and the mask film; forming a water permeation preventive film covering the inner surface of the contact hole and the mask film; Etching and removing the protective film and the water permeation preventive film on the bottom of the contact hole, and the water permeation preventive film and the mask film on the second insulating film; electrode A method for manufacturing a ferroelectric memory, comprising a step of forming a conductive member electrically connected.
(Supplementary note 7) The method for manufacturing a ferroelectric memory according to supplementary note 6, wherein the water permeation preventive film is an Al ₂ O ₃ film.
(Supplementary note 8) The method for manufacturing a ferroelectric memory according to supplementary note 6 or 7, wherein the lower electrode is made of Pt.
(Supplementary note 9) The method for manufacturing a ferroelectric memory according to any one of supplementary notes 1 to _3, wherein the protective film is an Al ₂ O ₃ film.
(Supplementary Note 10) The supplementary notes 6 to 6 are characterized in that the step of forming the second insulating film is a step of forming a silicon oxide film by a vapor phase growth method using Si (OC ₂ H ₅ ) ₄ as a source gas. 10. A method for manufacturing a ferroelectric memory as described in any one of 9 above.

DESCRIPTION OF SYMBOLS 1 1st insulating film 2 Adhesion layer 3 Ferroelectric capacitor 4 Lower electrode 5 Ferroelectric film 6 Upper electrode 7 Protective film 8 Second insulating film 9 Water permeation preventive film 10 Barrier metal 11 Embedded conductor film 12 For lower electrode Plug 13 Upper electrode plug 14 Wiring 15 Ti film 16 Al film 17 Ti film 21 Silicon substrate 22 Element isolation insulating film 23 P-type well region 24 Gate insulating film 25 Gate electrode 26 Protective film 27 Extension region 28 Side wall 29 N-type Drain region 30 n-type source region 31 Cover insulating film 32 First interlayer insulating films 33 and 62 Adhesion layers 34 and 63 Lower electrodes 35 and 64 Ferroelectric films 36 and 65 Upper electrodes 37 and 66 Ferroelectric capacitors 38 and 67 Protection Film 39 Second interlayer insulating film 40 Mask film 41 Resist pattern 42 First contact hole 43 Second contact hole 4 4 H ₂ O permeation preventive film 45 Resist pattern 46 Contact hole 47, 69 Barrier metal 48, 70 W film 49, 71 Lower electrode plug 50, 72 Upper electrode plug 51 Drain electrode plug 52 Source electrode plug 53, 73 Ti film 54, 74 Al film 55, 75 Ti film 56, 76 Metal wiring 61, 68 Interlayer insulating film 77 Al ₂ O ₃ re-adhesion film 78 Pt re-adhesion film

Claims (5)

A semiconductor substrate;
A first insulating film formed above the semiconductor substrate;
A ferroelectric capacitor including a lower electrode / a ferroelectric film / an upper electrode formed on the first insulating film and stacked in order from the first insulating film;
A second insulating film covering a side surface and an upper surface of the ferroelectric capacitor,
A contact hole provided in the second insulating film and reaching the lower electrode;
A water permeation preventive film covering the wall surface of the contact hole;
A ferroelectric memory having an extraction electrode embedded in the contact hole through the water permeation preventive film. The ferroelectric memory according to claim 1, wherein the water permeation preventive film is an Al ₂ O ₃ film.   3. The ferroelectric memory according to claim 1, wherein the lower electrode is made of Pt. Forming a first insulating film above the semiconductor substrate;
Forming a ferroelectric capacitor by laminating a lower electrode, a ferroelectric film and an upper electrode in order from the first insulating film side on the first insulating film;
Forming a protective film covering the ferroelectric capacitor;
Forming a second insulating film covering the protective film;
Forming a mask film on the second insulating film;
Selectively etching the second insulating film and the mask film to form a contact hole;
Forming a water permeation preventive film covering the inner surface of the contact hole and the mask film;
Etching and removing the protective film and the water permeation preventive film on the bottom of the contact hole, and the water permeation preventive film and the mask film on the second insulating film;
Forming a conductive member electrically connected to the lower electrode in the contact hole. A method of manufacturing a ferroelectric memory, comprising: Method of manufacturing a ferroelectric memory according to claim 4, wherein said water permeable barrier layer is Al ₂ O ₃ film.

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