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JP2015069990A - Semiconductor module - Google Patents

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JP2015069990A
JP2015069990A JP2013200138A JP2013200138A JP2015069990A JP 2015069990 A JP2015069990 A JP 2015069990A JP 2013200138 A JP2013200138 A JP 2013200138A JP 2013200138 A JP2013200138 A JP 2013200138A JP 2015069990 A JP2015069990 A JP 2015069990A
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semiconductor module
bare chip
solder
wiring pattern
joint surface
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崇 須永
Takashi Sunaga
崇 須永
昇 金子
Noboru Kaneko
昇 金子
修 三好
Osamu Miyoshi
修 三好
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NSK Ltd
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NSK Ltd
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    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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Abstract

【課題】製造タクトの短縮と製造コストの削減とを実現すると共に、接合部の信頼性を確保することができる半導体モジュールを提供する。【解決手段】半導体モジュール３０は、金属製の基板３１と、基板３１の上に形成された絶縁層３２と、絶縁層３２上に形成された複数の配線パターン３３ａ〜３３ｄと、配線パターン３３ａ上に半田３４ａを介して実装されるベアチップトランジスタ３５と、ベアチップトランジスタ３５の電極Ｓ，Ｇ上と配線パターン３３ｂ，３３ｃ上とを半田３４ｂ，３４ｃを介して接合する、銅コネクタ３６ａ，３６ｂとを備える。銅コネクタ３６ａ，３６ｂはブリッジ形状であり、電極Ｓ，Ｇとの接合面３６ａｆ近傍に幅狭部３６ａｇを設けると共に、電極Ｓ，Ｇとの接合面３６ａｆに応力緩和部３６ａｋを設ける。【選択図】図７Provided is a semiconductor module capable of realizing a reduction in manufacturing tact and a reduction in manufacturing cost and ensuring reliability of a joint. A semiconductor module includes a metal substrate, an insulating layer formed on the substrate, a plurality of wiring patterns formed on the insulating layer, and a wiring pattern on the wiring pattern. Are provided via a solder 34a, and copper connectors 36a and 36b for joining the electrodes S and G of the bare chip transistor 35 and the wiring patterns 33b and 33c via the solders 34b and 34c. . The copper connectors 36a, 36b have a bridge shape, and a narrow portion 36ag is provided in the vicinity of the joint surface 36af with the electrodes S, G, and a stress relaxation portion 36ak is provided on the joint surface 36af with the electrodes S, G. [Selection] Figure 7

Description

本発明は、自動車用電気機器に組み込まれるパワーモジュール等の半導体モジュールに関する。   The present invention relates to a semiconductor module such as a power module incorporated in an automobile electrical device.

昨今、自動車等の車両における種々の電気機器の制御に電子装置が導入されてきた。電子装置が組み込まれた電気機器の一例として電動パワーステアリング装置では、自動車の操舵に係る電動モータが収容される筐体にモータ駆動部が設けられ、このモータ駆動部に電子装置が搭載される。この電子装置は、パワーモジュールとして、モータ駆動部に組み込まれる。   Recently, electronic devices have been introduced to control various electric devices in vehicles such as automobiles. In an electric power steering apparatus as an example of an electric device in which an electronic device is incorporated, a motor driving unit is provided in a housing that houses an electric motor related to steering of an automobile, and the electronic device is mounted on the motor driving unit. This electronic device is incorporated as a power module in the motor drive unit.

パワーモジュールは、電動パワーステアリング装置のような比較的大きな電流で駆動される電気機器の制御に適した、例えば、ＦＥＴ（Ｆｉｅｌｄ Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）、ＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ
Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）等のパワー素子を搭載したいわゆる半導体モジュールとして構成される。この種のパワーモジュールは、車両に搭載されることから車載モジュール（Ｉｎ−ｖｅｈｉｃｌｅ Ｍｏｄｕｌｅ）とも呼ばれる。 The power module is suitable for controlling an electric device driven by a relatively large current such as an electric power steering device, for example, an FET (Field Effect Transistor), an IGBT (Insulated Gate).
It is configured as a so-called semiconductor module on which a power element such as a Bipolar Transistor is mounted. This type of power module is also called an in-vehicle module because it is mounted on a vehicle.

従来、この種の半導体モジュールとして、例えば、特許文献１に記載の技術がある。この技術は、金属基板上の配線パターンとベアチップトランジスタとを接合する電気的配線にワイヤを使用したものである。 また、例えば特許文献２に記載の技術のように、金属基板上に実装される半導体素子を電気的に接続するリード部品を、半導体上の電極よりも大きくすると共に、接触部の信頼性の確保のために複数の接点としたり、接点幅を広くしたりするものもある。 さらに、例えば特許文献３に記載の技術のように、コネクタ配線の応力緩和を行うために、立ち上がり曲げ部を設けたり、配線途中にヒューズ形状（波形状）を設けたりするものもある。   Conventionally, as this type of semiconductor module, for example, there is a technique described in Patent Document 1. In this technique, a wire is used for electrical wiring for joining a wiring pattern on a metal substrate and a bare chip transistor. Further, as in the technique described in Patent Document 2, for example, the lead component for electrically connecting the semiconductor element mounted on the metal substrate is made larger than the electrode on the semiconductor, and the reliability of the contact portion is ensured. For this purpose, some contact points are used and the contact width is widened. Furthermore, as in the technique described in Patent Document 3, for example, there is a case where a rising bent portion is provided or a fuse shape (wave shape) is provided in the middle of the wiring in order to relieve stress of the connector wiring.

特開２００４−３３５７２５号公報JP 2004-335725 A 特開２００７−９５９８４号公報JP 2007-95984 A 特開２０００−１２４３９８号公報JP 2000-124398 A

しかしながら、上記特許文献１に記載の技術にあっては、ワイヤを使用した電気的配線を採用しているため、当該電気的配線をワイヤボンディング装置による実装が必要となる。すなわち、その他の電子部品のはんだ実装とは異なり、製造工程を別で行う必要があり、製造タクトが長くなる。また、ワイヤボンディングの専用設備が必要となるため、製造コストが高くなる。   However, since the technique described in Patent Document 1 employs electrical wiring using wires, it is necessary to mount the electrical wiring using a wire bonding apparatus. That is, unlike the solder mounting of other electronic components, it is necessary to perform the manufacturing process separately, resulting in a long manufacturing tact. In addition, since dedicated equipment for wire bonding is required, the manufacturing cost increases.

また、上記特許文献２に記載の技術にあっては、大型の接点としているため、接合面が大きくなりすぎるために、捩れや熱収縮に弱くなる。そのため、接合部の信頼性を確保することが難しい。さらに、上記特許文献３に記載の技術にあっては、配線途中にヒューズ形状を設けているが、ヒューズ形状は成形が困難であり実用性に乏しい。そこで、本発明は、製造タクトの短縮と製造コストの削減とを実現すると共に、接合部の信頼性を確保することができる半導体モジュールを提供することを課題としている。   Moreover, in the technique of the said patent document 2, since it is set as a large sized contact, since a joining surface becomes large too much, it becomes weak to a twist and heat shrink. For this reason, it is difficult to ensure the reliability of the joint. Furthermore, in the technique described in Patent Document 3, a fuse shape is provided in the middle of the wiring. However, the fuse shape is difficult to form and is not practical. Therefore, an object of the present invention is to provide a semiconductor module capable of realizing reduction in manufacturing tact and reduction in manufacturing cost and ensuring the reliability of the joint.

上記課題を解決するために、本発明に係る半導体モジュールの一態様は、金属製の基板と、該基板の上に形成された絶縁層と、該絶縁層上に形成された複数の配線パターンと、該複数の配線パターンのうち一つの配線パターン上に半田を介して実装されるベアチップトランジスタと、該ベアチップトランジスタの上面に形成された電極上と前記複数の配線パターンのうち他の配線パターン上とを半田を介して接合する、銅板で構成される銅コネクタとを備え、前記銅コネクタは、前記電極上に接合される第１の脚部と、前記配線パターン上に接合される第２の脚部とを有するブリッジ形状であり、前記第１の脚部に、前記電極との接合面とは反対側の端部から前記接合面が形成された端部へ向けて幅が狭くなる幅狭部を設けると共に、前記第１の脚部の前記電極との接合面に、当該接合面に作用する応力を緩和する形状を有する応力緩和部を設けることを特徴としている。   In order to solve the above problems, an aspect of a semiconductor module according to the present invention includes a metal substrate, an insulating layer formed on the substrate, and a plurality of wiring patterns formed on the insulating layer. A bare chip transistor mounted on one of the plurality of wiring patterns via solder, an electrode formed on an upper surface of the bare chip transistor, and another wiring pattern of the plurality of wiring patterns A copper connector made of a copper plate, and the copper connector is joined to the electrode by a first leg and a second leg joined to the wiring pattern. And a narrow portion in which the width of the first leg portion becomes narrower from an end portion on the side opposite to the bonding surface to the electrode toward an end portion where the bonding surface is formed. And providing the first The junction surface between the electrode of the legs of the is characterized by providing a stress relieving portion having a shape to alleviate the stress acting on the joint surface.

すなわち、前記銅コネクタは、熱膨張率及び熱収縮率が前記基板とは異なることにより生じる上下方向、左右方向、前後方向及び捻り方向の変位を吸収可能な形状を有することを特徴としている。このように、ベアチップトランジスタの電極と基板上の配線パターンとの接合を、銅板で構成される銅コネクタを用いることにより、はんだ実装作業で行えるので、ベアチップトランジスタの電極と基板上の配線パターンとの接合をベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われるはんだ実装作業と同一の工程で同時に行うことができる。このため、半導体モジュールの製造タクトを短くすることができると共に、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。   That is, the copper connector is characterized in that it has a shape capable of absorbing displacement in the vertical direction, the horizontal direction, the front-rear direction, and the torsional direction caused by the difference in thermal expansion coefficient and thermal contraction rate from the substrate. In this way, the bonding of the bare chip transistor electrode and the wiring pattern on the substrate can be performed by solder mounting by using a copper connector formed of a copper plate. Bonding can be performed simultaneously in the same process as a solder mounting operation performed when mounting a bare chip transistor or other surface-mounted component on a wiring pattern on a substrate. For this reason, the manufacturing tact of the semiconductor module can be shortened, and dedicated equipment for wire bonding is not required, and the manufacturing cost of the semiconductor module can be reduced.

さらに、銅コネクタをブリッジ形状とすることで、上下左右方向の変位が吸収可能となる。また、銅コネクタのベアチップトランジスタの電極と接合する第１の脚部に幅狭部を設けることで、前後方向及び捻り方向の変位が吸収可能となる。さらにまた、第１の脚部の上記電極との接合面に応力緩和部を設けるので、接合部に生じる応力を緩和することができる。したがって、リフロー工程や作動熱により熱膨張や熱収縮が発生した場合に、銅コネクタとベアチップトランジスタの電極との半田接合を剥がれ難くすることができ、接合部の信頼性を確保することができる。   Furthermore, the displacement in the vertical and horizontal directions can be absorbed by forming the copper connector in a bridge shape. In addition, by providing a narrow portion at the first leg portion that is joined to the bare chip transistor electrode of the copper connector, the displacement in the front-rear direction and the twist direction can be absorbed. Furthermore, since the stress relaxation portion is provided on the joint surface of the first leg portion with the electrode, the stress generated in the joint portion can be relaxed. Therefore, when thermal expansion or thermal contraction occurs due to the reflow process or operating heat, the solder joint between the copper connector and the bare chip transistor electrode can be made difficult to peel, and the reliability of the joint can be ensured.

また、上記において、前記応力緩和部として、前記接合面に切り欠き部を形成したり、前記接合面を薄板で形成したり、前記接合面の角部に面取り部を形成したり、前記接合面の中央に孔を形成したりしてもよい。このように、切り欠き部を形成することで、接合部を２つにすることができると共に、各々の接合部の幅をさらに狭くすることができるため、捻りを受けても追従しやすくなる。また、接点が２つになることで所謂２重系を構成できるので、電気的信頼性が向上する。   Further, in the above, as the stress relaxation portion, a notch portion is formed on the joint surface, the joint surface is formed of a thin plate, a chamfered portion is formed at a corner of the joint surface, or the joint surface You may form a hole in the center of. In this way, by forming the notch portion, the number of joint portions can be reduced to two, and the width of each joint portion can be further narrowed. Moreover, since the so-called dual system can be configured by using two contacts, the electrical reliability is improved.

また、応力緩和部を薄板形状とした場合、板厚が薄いために捩れやすく、変位吸収しやすい。さらに、応力緩和部を先端Ｒ形状とした場合、捻りを受けたときの角部への応力集中を逃がす効果がある。さらにまた、応力緩和部に孔を形成した場合、半田が浸透ぬれ現象により接合面の上面に流れて放射状に広がるので、捻りを受けても半田が剥がれ難い。   Further, when the stress relaxation portion is formed into a thin plate shape, the plate thickness is thin, so that it is easily twisted and easily absorbs displacement. Furthermore, when the stress relaxation portion has a rounded tip shape, there is an effect of escaping the stress concentration at the corner when subjected to twisting. Furthermore, when a hole is formed in the stress relaxation portion, the solder flows to the upper surface of the joint surface due to the permeation wetting phenomenon and spreads radially, so that it is difficult for the solder to peel off even when subjected to twisting.

本発明の半導体モジュールでは、ベアチップトランジスタの電極と基板上の配線パターンとの接合を、銅板で構成される銅コネクタを用いることにより、はんだ実装作業で行えるので、ベアチップトランジスタの電極と基板上の配線パターンとの接合をベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われるはんだ実装作業と同一の工程で同時に行うことができる。このため、半導体モジュールの製造タクトを短くすることができると共に、ワイヤボンディングの専用設備が不要になり、半導体モジュールの製造コストを安価にすることができる。   In the semiconductor module of the present invention, the bare chip transistor electrode and the wiring pattern on the substrate can be joined by a solder mounting operation using a copper connector formed of a copper plate. Bonding to the pattern can be performed simultaneously in the same process as the solder mounting operation performed when the bare chip transistor or other surface-mounted component is mounted on the wiring pattern on the substrate. For this reason, the manufacturing tact of the semiconductor module can be shortened, and dedicated equipment for wire bonding is not required, and the manufacturing cost of the semiconductor module can be reduced.

また、銅コネクタをブリッジ形状とすると共に、ベアチップトランジスタの電極と接合する第１の脚部に幅狭部と応力緩和部とを設けるので、あらゆる方向の変位が吸収可能となる。そのため、リフロー工程での銅コネクタの熱変形を吸収し、接合部の信頼性を確保することができる。さらに、製品使用時における温度変化による銅コネクタの破損を防止することができる。   Further, since the copper connector has a bridge shape and the narrow leg portion and the stress relaxation portion are provided on the first leg portion joined to the electrode of the bare chip transistor, the displacement in any direction can be absorbed. Therefore, the thermal deformation of the copper connector in the reflow process can be absorbed, and the reliability of the joint can be ensured. Furthermore, it is possible to prevent the copper connector from being damaged due to temperature changes during product use.

本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造を示す図である。It is a figure which shows the basic structure of the electric power steering apparatus with which the semiconductor module which concerns on this invention is used. コントローラの制御系を示すブロック図であるIt is a block diagram which shows the control system of a controller 半導体モジュールを含むコントローラの分解斜視図である。It is a disassembled perspective view of the controller containing a semiconductor module. 半導体モジュールの平面図である。It is a top view of a semiconductor module. ベアチップＦＥＴの概略平面図である。It is a schematic plan view of a bare chip FET. ベアチップＦＥＴの電極と基板上の配線パターンとの接続状態を説明するための模式図である。It is a schematic diagram for demonstrating the connection state of the electrode of a bare chip FET, and the wiring pattern on a board | substrate. 銅コネクタの形状を示す斜視図である。It is a perspective view which shows the shape of a copper connector. 応力緩和部の形状を示す図である。It is a figure which shows the shape of a stress relaxation part. 応力緩和部の形状の別の例を示す図である。It is a figure which shows another example of the shape of a stress relaxation part. 応力緩和部の形状の別の例を示す図である。It is a figure which shows another example of the shape of a stress relaxation part. 応力緩和部の形状の別の例を示す図である。It is a figure which shows another example of the shape of a stress relaxation part. 半導体モジュールの製造方法を説明する図である。It is a figure explaining the manufacturing method of a semiconductor module. 応力緩和部の形状の別の例を示す図である。It is a figure which shows another example of the shape of a stress relaxation part.

以下、本発明の実施の形態を図面に基づいて説明する。
図１は、本発明に係る半導体モジュールが用いられる電動パワーステアリング装置の基本構造を示す図である。図１の電動パワーステアリング装置において、操向ハンドル１のコラム軸２は、減速ギア３、ユニバーサルジョイント４Ａ及び４Ｂ、ピニオンラック機構５を経て走行車輪のタイロッド６に連結されている。コラム軸２には、操向ハンドル１の操舵トルクを検出するトルクセンサ７が設けられており、操向ハンドル１の操舵力を補助する電動モータ８が減速ギア３を介してコラム軸２に連結されている。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a basic structure of an electric power steering apparatus in which a semiconductor module according to the present invention is used. In the electric power steering apparatus of FIG. 1, the column shaft 2 of the steering handle 1 is connected to a tie rod 6 of a traveling wheel via a reduction gear 3, universal joints 4 </ b> A and 4 </ b> B, and a pinion rack mechanism 5. The column shaft 2 is provided with a torque sensor 7 that detects the steering torque of the steering handle 1, and an electric motor 8 that assists the steering force of the steering handle 1 is connected to the column shaft 2 via the reduction gear 3. Has been.

電動パワーステアリング装置を制御するコントローラ１０には、バッテリー（図示せず）から電力が供給されるとともに、イグニションキー（図示せず）を経てイグニションキー信号ＩＧＮ（図２参照）が入力される。コントローラ１０は、トルクセンサ７で検出された操舵トルクＴｓと車速センサ９で検出された車速Ｖとに基づいて、アシスト（操舵補助）指令となる操舵補助指令値の演算を行い、演算された操舵補助指令値に基づいて電動モータ８に供給する電流を制御する。コントローラ１０は、主としてマイクロコンピュータで構成されるが、その制御装置の機構及び構成を示すと図２に示すようになる。   Electric power is supplied from a battery (not shown) to the controller 10 that controls the electric power steering device, and an ignition key signal IGN (see FIG. 2) is input via an ignition key (not shown). The controller 10 calculates a steering assist command value serving as an assist (steering assist) command based on the steering torque Ts detected by the torque sensor 7 and the vehicle speed V detected by the vehicle speed sensor 9, and the calculated steering is performed. The current supplied to the electric motor 8 is controlled based on the auxiliary command value. The controller 10 is mainly composed of a microcomputer, and the mechanism and configuration of the control device are as shown in FIG.

トルクセンサ７で検出された操舵トルクＴｓ及び車速センサ９で検出された車速Ｖは制御演算部としての制御演算装置１１に入力され、制御演算装置１１で演算された電流指令値をゲート駆動回路１２に入力する。ゲート駆動回路１２で、電流指令値等に基づいて形成されたゲート駆動信号はＦＥＴのブリッジ構成で成るモータ駆動部１３に入力され、モータ駆動部１３は非常停止用の遮断装置１４を経て３相ブラシレスモータで構成される電動モータ８を駆動する。３相ブラシレスモータの各相電流は電流検出回路１５で検出され、検出された３相のモータ電流ｉａ〜ｉｃは制御演算装置１１にフィードバック電流として入力される。また、３相ブラシレスモータには、ホールセンサ等の回転センサ１６が取り付けられており、回転センサ１６からの回転信号ＲＴがロータ位置検出回路１７に入力され、検出された回転位置θが制御演算装置１１に入力される。   The steering torque Ts detected by the torque sensor 7 and the vehicle speed V detected by the vehicle speed sensor 9 are input to the control arithmetic unit 11 as a control arithmetic unit, and the current command value calculated by the control arithmetic unit 11 is used as the gate drive circuit 12. To enter. In the gate drive circuit 12, a gate drive signal formed based on a current command value or the like is input to a motor drive unit 13 having a FET bridge configuration, and the motor drive unit 13 passes through an emergency stop interrupting device 14 for three phases. An electric motor 8 composed of a brushless motor is driven. Each phase current of the three-phase brushless motor is detected by the current detection circuit 15, and the detected three-phase motor currents ia to ic are input to the control arithmetic device 11 as feedback currents. In addition, a rotation sensor 16 such as a hall sensor is attached to the three-phase brushless motor, and a rotation signal RT from the rotation sensor 16 is input to the rotor position detection circuit 17, and the detected rotation position θ is a control arithmetic unit. 11 is input.

また、イグニションキーからのイグニション信号ＩＧＮはイグニション電圧モニタ部１８及び電源回路部１９に入力され、電源回路部１９から電源電圧Ｖｄｄが制御演算装置１１に入力されるとともに、装置停止用となるリセット信号ＲＳが制御演算装置１１に入力される。さらに、遮断装置１４は、２相を遮断するリレー接点１４１及び１４２で構成されている。   Further, the ignition signal IGN from the ignition key is input to the ignition voltage monitor unit 18 and the power supply circuit unit 19, and the power supply voltage Vdd is input from the power supply circuit unit 19 to the control arithmetic unit 11 and a reset signal for stopping the apparatus. RS is input to the control arithmetic unit 11. Furthermore, the interruption | blocking apparatus 14 is comprised by the relay contacts 141 and 142 which interrupt | block two phases.

また、モータ駆動部１３の回路構成について説明すると、電源ライン８１に対し、直列に接続されたＦＥＴＴｒ１及びＴｒ２、ＦＥＴＴｒ３及びＴｒ４、及びＦＥＴＴｒ５及びＴｒ６が直列に接続されている。そして、電源ライン８１に対して、並列に接続されたＦＥＴＴｒ１及びＴｒ３、ＦＥＴＴｒ５及びＴｒ２、及びＦＥＴＴｒ４及びＴｒ６が接地ライン８２に接続されている。これにより、インバータを構成する。   The circuit configuration of the motor drive unit 13 will be described. FETTr1 and Tr2, FETTr3 and Tr4, and FETTr5 and Tr6 connected in series to the power supply line 81 are connected in series. Further, FETTr1 and Tr3, FETTr5 and Tr2, and FETTr4 and Tr6 connected in parallel to the power supply line 81 are connected to the ground line 82. This constitutes an inverter.

ここで、ＦＥＴＴｒ１及びＴｒ２は、ＦＥＴＴｒ１のソース電極ＳとＦＥＴＴｒ２のドレイン電極Ｄとが直列に接続され、３相モータのｃ相アームを構成し、ｃ相出力ライン９１ｃにて電流が出力される。また、ＦＥＴＴｒ３及びＴｒ４は、ＦＥＴＴｒ３のソース電極ＳとＦＥＴＴｒ４のドレイン電極Ｄとが直列に接続され、３相モータのａ相アームを構成し、ａ相出力ライン９１ａにて電流が出力される。更に、ＦＥＴＴｒ５及びＴｒ６は、ＦＥＴＴｒ５のソース電極ＳとＦＥＴＴｒ６のドレイン電極Ｄとが直列に接続され、３相モータのｂ相アームを構成し、ｂ相出力ライン９１ｂにて電流が出力される。   Here, the FETTr1 and Tr2 are configured such that the source electrode S of the FETTr1 and the drain electrode D of the FETTr2 are connected in series to form a c-phase arm of a three-phase motor, and a current is output from the c-phase output line 91c. In addition, the FETTr3 and Tr4 are configured such that the source electrode S of the FETTr3 and the drain electrode D of the FETTr4 are connected in series to form an a-phase arm of a three-phase motor, and a current is output from the a-phase output line 91a. Further, the FETTr5 and Tr6 are configured such that the source electrode S of the FETTr5 and the drain electrode D of the FETTr6 are connected in series to form a b-phase arm of a three-phase motor, and a current is output from the b-phase output line 91b.

図３は、図１に示す電動パワーステアリング装置の半導体モジュールを含むコントローラ１０の分解斜視図であり、コントローラ１０は、ケース２０と、モータ駆動部１３を含むパワーモジュールとしての半導体モジュール３０と、放熱用シート３９と、制御演算装置１１及びゲート駆動回路１２を含む制御回路基板４０と、電力及び信号用コネクタ５０と、３相出力用コネクタ６０と、カバー７０とを備えている。   3 is an exploded perspective view of the controller 10 including the semiconductor module of the electric power steering apparatus shown in FIG. 1. The controller 10 includes a case 20, a semiconductor module 30 as a power module including the motor drive unit 13, and heat dissipation. Sheet 39, control circuit board 40 including control arithmetic device 11 and gate drive circuit 12, power and signal connector 50, three-phase output connector 60, and cover 70.

ここで、ケース２０は、略矩形状に形成され、半導体モジュール３０を載置するための平板状の半導体モジュール載置部２１と、半導体モジュール載置部２１の長手方向端部に設けられた、電力及び信号用コネクタ５０を実装するための電力及び信号用コネクタ実装部２２と、半導体モジュール載置部２１の幅方向端部に設けられた、３相出力用コネクタ６０を実装するための３相出力用コネクタ実装部２３とを備えている。   Here, the case 20 is formed in a substantially rectangular shape, and is provided on the flat-plate-shaped semiconductor module mounting portion 21 for mounting the semiconductor module 30 and the longitudinal end portion of the semiconductor module mounting portion 21. Three-phase for mounting a power and signal connector mounting portion 22 for mounting the power and signal connector 50 and a three-phase output connector 60 provided at the end in the width direction of the semiconductor module mounting portion 21 And an output connector mounting portion 23.

そして、半導体モジュール載置部２１には、半導体モジュール３０を取り付けるための取付けねじ３８がねじ込まれる複数のねじ孔２１ａが形成されている。また、半導体モジュール載置部２１及び電力及び信号用コネクタ実装部２２には、制御回路基板４０を取り付けるための複数の取付けポスト２４が立設され、各取付けポスト２４には、制御回路基板４０を取り付けるための取付けねじ４１がねじ込まれるねじ孔２４ａが形成されている。更に、３相出力用コネクタ実装部２３には、３相出力用コネクタ６０を取り付けるための取付けねじ６１がねじ込まれる複数のねじ孔２３ａが形成されている。   A plurality of screw holes 21 a into which mounting screws 38 for mounting the semiconductor module 30 are screwed are formed in the semiconductor module mounting portion 21. A plurality of mounting posts 24 for mounting the control circuit board 40 are erected on the semiconductor module mounting portion 21 and the power and signal connector mounting portion 22, and the control circuit board 40 is mounted on each mounting post 24. A screw hole 24a into which a mounting screw 41 for mounting is screwed is formed. Further, the three-phase output connector mounting portion 23 is formed with a plurality of screw holes 23a into which mounting screws 61 for attaching the three-phase output connector 60 are screwed.

また、半導体モジュール３０は、前述したモータ駆動部１３の回路構成を有し、図４に示すように、基板３１に、６個のＦＥＴＴｒ１〜Ｔｒ６、電源ライン８１に接続された正極端子８１ａ、及び接地ライン８２に接続された負極端子８２ａが実装されている。また、基板３１には、ａ相出力ライン９１ａに接続されたａ相出力端子９２ａ、ｂ相出力ライン９１ｂに接続されたｂ相出力端子９２ｂ、及びｃ相出力ライン９１ｃに接続されたｃ相出力端子９２ｃを含む３相出力部９０が実装されている。また、基板３１上には、コンデンサを含むその他の基板実装部品３７が実装されている。更に、半導体モジュール３０の基板３１には、半導体モジュール３０を取り付けるための取付けねじ３８が挿通する複数の貫通孔３１ａが設けられている。   The semiconductor module 30 has the circuit configuration of the motor drive unit 13 described above. As shown in FIG. 4, the substrate 31 has six FETs Tr <b> 1 to Tr <b> 6, a positive terminal 81 a connected to the power supply line 81, and A negative terminal 82a connected to the ground line 82 is mounted. Further, the substrate 31 has a phase output terminal 92a connected to the phase a output line 91a, phase b output terminal 92b connected to the phase b output line 91b, and phase c output connected to the phase c output line 91c. A three-phase output unit 90 including a terminal 92c is mounted. In addition, other board mounting components 37 including a capacitor are mounted on the board 31. Further, the substrate 31 of the semiconductor module 30 is provided with a plurality of through holes 31a through which mounting screws 38 for mounting the semiconductor module 30 are inserted.

ここで、この半導体モジュール３０において、６個のＦＥＴＴｒ１〜Ｔｒ６の基板３１上への実装について説明する。各ＦＥＴＴｒ１〜Ｔｒ６は、ベアチップＦＥＴ（ベアチップトランジスタ）３５で構成され、図５に示すように、ベアチップＦＥＴ３５上にソース電極Ｓとゲート電極Ｇとを備え、また、ベアチップＦＥＴ３５の下面には図示しないドレイン電極を備えている。半導体モジュール３０は、図６に示すように、金属製の基板３１を備え、基板３１の上には、絶縁層３２が形成されている。基板３１は、アルミニウムなどの金属製である。また、この絶縁層３２上には、複数の配線パターン３３ａ〜３３ｄが形成されている。各配線パターン３３ａ〜３３ｄは、銅やアルミニウムなどの金属、又はこの金属を含む合金で構成される。   Here, in the semiconductor module 30, mounting of the six FETs Tr1 to Tr6 on the substrate 31 will be described. Each of the FETs Tr1 to Tr6 is composed of a bare chip FET (bare chip transistor) 35, and includes a source electrode S and a gate electrode G on the bare chip FET 35 as shown in FIG. It has an electrode. As shown in FIG. 6, the semiconductor module 30 includes a metal substrate 31, and an insulating layer 32 is formed on the substrate 31. The substrate 31 is made of a metal such as aluminum. A plurality of wiring patterns 33 a to 33 d are formed on the insulating layer 32. Each wiring pattern 33a-33d is comprised with metals, such as copper and aluminum, or the alloy containing this metal.

そして、複数の配線パターン３３ａ〜３３ｄのうち一つの配線パターン３３ａ上には半田３４ａを介して各ＦＥＴＴｒ１〜Ｔｒ６を構成するベアチップＦＥＴ３５が実装されている。ベアチップＦＥＴ３５の下面に形成されたドレイン電極が半田３４ａを介して配線パターン３３ａに接合される。そして、ベアチップＦＥＴ３５のソース電極Ｓ上と複数の配線パターン３３ａ〜３３ｄのうち他の配線パターン３３ｂ上とがソース電極用銅コネクタ３６ａでそれぞれ半田３４ｅ，３４ｂを介して接合される。   A bare chip FET 35 constituting each of the FETs Tr1 to Tr6 is mounted on one wiring pattern 33a among the plurality of wiring patterns 33a to 33d via solder 34a. The drain electrode formed on the lower surface of the bare chip FET 35 is joined to the wiring pattern 33a via the solder 34a. Then, the source electrode S of the bare chip FET 35 and the other wiring pattern 33b among the plurality of wiring patterns 33a to 33d are joined by the source electrode copper connector 36a via solders 34e and 34b, respectively.

ソース電極用銅コネクタ３６ａは、銅板を打抜き及び曲げ加工することによって形成されるものであり、平板部３６ａａと、平板部３６ａａの一端から延び、半田３４ｅを介してベアチップＦＥＴ３５のソース電極Ｓに接合される接続部３６ａｂと、平板部３６ａａの他端から延び、半田３４ｂを介して配線パターン３３ｂに接合される接続部３６ａｃとを備えている。   The source electrode copper connector 36a is formed by punching and bending a copper plate, extends from one end of the flat plate portion 36aa and the flat plate portion 36aa, and is joined to the source electrode S of the bare chip FET 35 via the solder 34e. And a connecting portion 36ac that extends from the other end of the flat plate portion 36aa and is joined to the wiring pattern 33b via the solder 34b.

また、ベアチップＦＥＴ３５のゲート電極Ｇ上と複数の配線パターン３３ａ〜３３ｄのうち更に他の配線パターン３３ｃ上とがゲート電極用銅コネクタ３６ｂでそれぞれ半田３４ｆ，３４ｃを介して接合される。ゲート電極用銅コネクタ３６ｂは、銅板を打抜き及び曲げ加工することによって形成されるものであり、平板部３６ｂａと、平板部３６ｂａの一端から延び、半田３４ｆを介してベアチップＦＥＴ３５のゲート電極Ｇに接合される接続部３６ｂｂと、平板部３６ｂａの他端から延び、半田３４ｃを介して配線パターン３３ｃに接合される接続部３６ｂｃとを備えている。また、絶縁層３２上に形成された複数の配線パターン３３ａ〜３３ｄのうち更にもう一つ他の配線パターン３３ｄ上には半田３４ｄを介してコンデンサなどの他の基板実装部品３７が実装される。   Further, the gate electrode G of the bare chip FET 35 and the other wiring pattern 33c among the plurality of wiring patterns 33a to 33d are joined by the gate electrode copper connector 36b via solders 34f and 34c, respectively. The gate electrode copper connector 36b is formed by punching and bending a copper plate, extends from one end of the flat plate portion 36ba and the flat plate portion 36ba, and is joined to the gate electrode G of the bare chip FET 35 via the solder 34f. A connecting portion 36bb extending from the other end of the flat plate portion 36ba and connected to the wiring pattern 33c via the solder 34c. In addition, another board mounting component 37 such as a capacitor is mounted on another wiring pattern 33d among the plurality of wiring patterns 33a to 33d formed on the insulating layer 32 via solder 34d.

次に、ソース電極用銅コネクタの形状について説明する。
ソース電極用銅コネクタ３６ａは、図７に斜視図を示すように、平板部３６ａａと、接続部３６ａｂ（第１の脚部）と、接続部３６ａｃ（第２の脚部）とでブリッジ形状となっている。より具体的には、ソース電極用銅コネクタ３６ａは、平板部３６ａａの左右方向（図７のＸ軸方向）一端部に、第１屈曲部３６ａｄを介して接続部３６ａｂの一端が接続されており、接続部３６ａｂの他端は、第２屈曲部３６ａｅを介して外向きの接合面３６ａｆが形成されている。この接合面３６ａｆの下面が半田３４ｅを介してベアチップＦＥＴ３５のソース電極Ｓに接合される。 Next, the shape of the source electrode copper connector will be described.
As shown in the perspective view of FIG. 7, the source electrode copper connector 36a has a bridge shape with a flat plate portion 36aa, a connection portion 36ab (first leg portion), and a connection portion 36ac (second leg portion). It has become. More specifically, in the source electrode copper connector 36a, one end of the connecting portion 36ab is connected to one end of the flat plate portion 36aa in the left-right direction (X-axis direction in FIG. 7) via the first bent portion 36ad. The other end of the connecting portion 36ab is formed with an outward joint surface 36af via the second bent portion 36ae. The lower surface of the bonding surface 36af is bonded to the source electrode S of the bare chip FET 35 via the solder 34e.

また、接続部３６ａｂは、接合面３６ａｆ近傍に幅狭部３６ａｇを有する。幅狭部３６ａｇは、第１屈曲部３６ａｄから第２屈曲部３６ａｅに向けて幅が狭くなるテーパ形状となっている。平板部３６ａａの左右方向他端部には、第３屈曲部３６ａｈを介して接続部３６ａｃの一端が接続されており、接続部３６ａｃの他端は、第４屈曲部３６ａｉを介して外向きの接合面３６ａｊが形成されている。この接合面３６ａｊの下面が半田３４ｂを介して配線パターン３３ｂに接合される。   Further, the connecting portion 36ab has a narrow portion 36ag in the vicinity of the joint surface 36af. The narrow portion 36ag has a tapered shape in which the width becomes narrower from the first bent portion 36ad toward the second bent portion 36ae. One end of the connecting portion 36ac is connected to the other end portion in the left-right direction of the flat plate portion 36aa via the third bent portion 36ah, and the other end of the connecting portion 36ac is directed outward via the fourth bent portion 36ai. A joint surface 36aj is formed. The lower surface of the bonding surface 36aj is bonded to the wiring pattern 33b via the solder 34b.

さらに、接合面３６ａｆには、当該接合面３６ａｆに作用する応力を緩和する形状を有する応力緩和部３６ａｋを設ける。図８〜図１１は、応力緩和部３６ａｋの形状の例を示す図である。図８、図９及び図１１において、符号ＰはソースＰＡＤである。図８に示す応力緩和部３６ａｋは、接合面３６ａｆにスリット（切り込み）を設けたものである。なお、当該スリットは、接合面３６ａｆの先端部を２つの面に分けられるものであれば、その形状や大きさは適宜選択可能である。   Further, the joint surface 36af is provided with a stress relaxation portion 36ak having a shape that relieves stress acting on the joint surface 36af. 8-11 is a figure which shows the example of the shape of the stress relaxation part 36ak. In FIG. 8, FIG. 9 and FIG. 11, the symbol P is a source PAD. The stress relaxation part 36ak shown in FIG. 8 is provided with a slit (cut) in the joint surface 36af. In addition, if the said slit can divide the front-end | tip part of the joint surface 36af into two surfaces, the shape and magnitude | size can be selected suitably.

応力緩和部３６ａｋの別の例としては、例えば図９に示すように、接合面３６ａｆの板厚を薄くするものもある。また、応力緩和部３６ａｋとしては、図１０に示すように、接合面３６ａｆ先端の角に面取り部を設けるものもある。ここで、面取り部は、図１０に示すＲ面取りに代えて、大きな円でもよく、またＣ面取りでもよい。さらに、応力緩和部３６ａｋとしては、図１１に示すように、接合面３６ａｆの中央に孔を設けるものもある。   As another example of the stress relaxation part 36ak, as shown in FIG. 9, for example, there is one in which the thickness of the joint surface 36af is made thin. Further, as the stress relaxation part 36ak, as shown in FIG. 10, there is one in which a chamfered part is provided at a corner of the tip of the joint surface 36af. Here, the chamfered portion may be a large circle or a C chamfer instead of the R chamfer shown in FIG. Furthermore, as the stress relaxation portion 36ak, there is one in which a hole is provided in the center of the joint surface 36af as shown in FIG.

なお、ソース電極用銅コネクタ３６ａの形状は、ソース電極Ｓと配線パターン３３ｂとを接続できるブリッジ形状であれば任意の形状をとることができる。また、応力緩和部３６ａｋの形状についても、ソース電極Ｓと接合できる形状であれば任意の形状をとることができる。但し、半田接合の際に後に述べるリフロー接合を行い、また、半導体モジュール３０が稼働した際に発熱により高温になることから、熱応力を緩和できる形状とする。ゲート電極用銅コネクタ３６ｂについても同様である。このように構成された半導体モジュール３０は、図３に示すように、ケース２０の半導体モジュール載置部２１上に複数の取付けねじ３８により取り付けられる。半導体モジュール３０の基板３１には、取付けねじ３８が挿通する複数の貫通孔３１ａが形成されている。   The shape of the source electrode copper connector 36a can be any shape as long as it is a bridge shape capable of connecting the source electrode S and the wiring pattern 33b. Further, the shape of the stress relaxation portion 36ak can be any shape as long as it can be joined to the source electrode S. However, since reflow bonding, which will be described later, is performed at the time of solder bonding and the semiconductor module 30 is operated, the heat is generated due to heat generation, so that the thermal stress can be relieved. The same applies to the gate electrode copper connector 36b. As shown in FIG. 3, the semiconductor module 30 configured as described above is attached to the semiconductor module mounting portion 21 of the case 20 by a plurality of mounting screws 38. The substrate 31 of the semiconductor module 30 is formed with a plurality of through holes 31a through which the mounting screws 38 are inserted.

なお、半導体モジュール３０を半導体モジュール載置部２１上に取り付けるに際しては、放熱用シート３９を半導体モジュール載置部２１上に取付け、その放熱用シート３９の上から半導体モジュール３０を取り付ける。この放熱用シート３９により、半導体モジュール３０で発生した熱が放熱用シート３９を介してケース２０に放熱される。また、制御回路基板４０は、基板上に複数の電子部品を実装して制御演算装置１１及びゲート駆動回路１２を含む制御回路を構成するものである。制御回路基板４０は、半導体モジュール３０を半導体モジュール載置部２１上に取り付けた後、半導体モジュール３０の上方から半導体モジュール載置部２１及び電力及び信号用コネクタ実装部２２に立設された複数の取付けポスト２４上に複数の取付けねじ４１により取り付けられる。制御回路基板４０には、取付けねじ４１が挿通する複数の貫通孔４０ａが形成されている。   When mounting the semiconductor module 30 on the semiconductor module mounting portion 21, the heat dissipation sheet 39 is mounted on the semiconductor module mounting portion 21, and the semiconductor module 30 is mounted on the heat dissipation sheet 39. The heat generated by the semiconductor module 30 is radiated to the case 20 through the heat dissipation sheet 39 by the heat dissipation sheet 39. The control circuit board 40 constitutes a control circuit including the control arithmetic device 11 and the gate drive circuit 12 by mounting a plurality of electronic components on the board. After the semiconductor module 30 is mounted on the semiconductor module mounting portion 21, the control circuit board 40 has a plurality of standing uprights on the semiconductor module mounting portion 21 and the power and signal connector mounting portion 22 from above the semiconductor module 30. A plurality of mounting screws 41 are mounted on the mounting post 24. The control circuit board 40 has a plurality of through holes 40a through which the mounting screws 41 are inserted.

また、電力及び信号用コネクタ５０は、バッテリー（図示せず）からの直流電源を半導体モジュール３０に、トルクセンサ１２や車速センサ９からの信号を含む各種信号を制御回路基板４０に入力するために用いられる。電力及び信号用コネクタ５０は、半導体モジュール載置部２１に設けられた電力及び信号用コネクタ実装部２２に複数の取付けねじ５１により取り付けられる。   Further, the power and signal connector 50 is used to input a DC power source from a battery (not shown) to the semiconductor module 30 and various signals including signals from the torque sensor 12 and the vehicle speed sensor 9 to the control circuit board 40. Used. The power and signal connector 50 is attached to the power and signal connector mounting portion 22 provided on the semiconductor module mounting portion 21 with a plurality of mounting screws 51.

そして、３相出力用コネクタ６０は、ａ相出力端子９２ａ、ｂ相出力端子９２ｂ、及びｃ相出力端子９２ｃからの電流を出力するために用いられる。３相出用コネクタ６０は、半導体モジュール載置部２１の幅方向端部に設けられた３相出力用コネクタ実装部２３に複数の取付けねじ６１により取り付けられる。３相出力コネクタ６０には、取付けねじ６１が挿通する複数の貫通孔６０ａが形成されている。更に、カバー７０は、半導体モジュール３０、制御回路基板４０、電力及び信号用コネクタ５０、及び３相出力用コネクタ６０が取り付けられたケース２０に対し、制御回路基板４０の上方から当該制御回路基板４０を覆うように取り付けられる。   The three-phase output connector 60 is used to output current from the a-phase output terminal 92a, the b-phase output terminal 92b, and the c-phase output terminal 92c. The three-phase output connector 60 is attached to the three-phase output connector mounting portion 23 provided at the end in the width direction of the semiconductor module mounting portion 21 by a plurality of mounting screws 61. The three-phase output connector 60 is formed with a plurality of through holes 60a through which the mounting screws 61 are inserted. Further, the cover 70 covers the case 20 to which the semiconductor module 30, the control circuit board 40, the power and signal connector 50, and the three-phase output connector 60 are attached from above the control circuit board 40. It is attached to cover.

次に、半導体モジュール３０の製造方法について図１２を参照して説明する。半導体モジュール３０の製造に際し、先ず、図１２（ａ）に示すように、金属製の基板３１の一方の主面上に絶縁層３２を形成する（絶縁層形成工程）。次いで、絶縁層３２上に複数の配線パターン３３ａ〜３３ｄを形成する（配線パターン形成工程）。その後、図１２（ｂ）に示すように、複数の配線パターン３３ａ〜３３ｄ上にそれぞれ半田ペースト（半田３４ａ〜３４ｄ）を塗布する（半田ペースト塗布工程）。そして、図１２（ｃ）に示すように、複数の配線パターン３３ａ〜３３ｄのうち一つの配線パターン３３ａ上に塗布された半田ペースト（半田３３ａ）上にベアチップＦＥＴ３５の一つを搭載するとともに（ベアチップＦＥＴ搭載工程）、他の配線パターン３３ｄ上に塗布された半田ペースト（半田３４ｄ）上にその他の基板実装部品３７を搭載する。その他のベアチップＦＥＴ３５についても、配線パターン３３ａと同一あるいは別個の配線パターン上に搭載する。   Next, a method for manufacturing the semiconductor module 30 will be described with reference to FIG. When manufacturing the semiconductor module 30, first, as shown in FIG. 12A, an insulating layer 32 is formed on one main surface of a metal substrate 31 (insulating layer forming step). Next, a plurality of wiring patterns 33a to 33d are formed on the insulating layer 32 (wiring pattern forming step). Then, as shown in FIG.12 (b), solder paste (solder 34a-34d) is apply | coated on the some wiring patterns 33a-33d, respectively (solder paste application | coating process). Then, as shown in FIG. 12C, one of the bare chip FETs 35 is mounted on the solder paste (solder 33a) applied on one wiring pattern 33a among the plurality of wiring patterns 33a to 33d (bare chip). FET mounting step), another board mounting component 37 is mounted on the solder paste (solder 34d) applied on the other wiring pattern 33d. Other bare chip FETs 35 are also mounted on the same or separate wiring pattern as the wiring pattern 33a.

次いで、図１２（ｄ）に示すように、ベアチップＦＥＴ３５の上面に形成されたソース電極Ｓ及びゲート電極Ｄ上に半田ペースト（半田３４ｅ，３４ｆ）を塗布する（半田ペースト塗布工程）。その後、図１２（ｅ）に示すように、ベアチップＦＥＴ３５のソース電極Ｓ上に塗布された半田ペースト（半田３４ｅ）上及び複数の配線パターン３３ａ〜３３ｄのうちベアチップＦＥＴ３５が搭載された配線パターン３３ａ以外の他の配線パターン３３ｂ上に塗布された半田ペースト（半田３４ｂ）上に、ソース電極用銅コネクタ３６ａを搭載する（ソース電極用銅コネクタ搭載工程）。   Next, as shown in FIG. 12D, a solder paste (solder 34e, 34f) is applied on the source electrode S and the gate electrode D formed on the upper surface of the bare chip FET 35 (solder paste applying step). Thereafter, as shown in FIG. 12E, on the solder paste (solder 34e) applied on the source electrode S of the bare chip FET 35 and the wiring pattern 33a other than the wiring pattern 33a on which the bare chip FET 35 is mounted among the plurality of wiring patterns 33a to 33d. The source electrode copper connector 36a is mounted on the solder paste (solder 34b) applied on the other wiring pattern 33b (source electrode copper connector mounting step).

また、ベアチップＦＥＴ３５のゲート電極Ｇ上に塗布された半田ペースト（半田３４ｆ）上、及び複数の配線パターン３３ａ〜３３ｄのうちベアチップＦＥＴ３５が搭載された配線パターン３３ａ及びソース電極用銅コネクタ３６ａが搭載された配線パターン３３ｂ以外の更に他の配線パターン３３ｃ上に塗布された半田ペースト（半田３４ｃ）上に、ゲート電極用銅コネクタ３６ｂを搭載する（ゲート電極用銅コネクタ搭載工程）。これにより、半導体モジュール中間組立体が構成される。   In addition, on the solder paste (solder 34f) applied on the gate electrode G of the bare chip FET 35, the wiring pattern 33a on which the bare chip FET 35 is mounted among the plurality of wiring patterns 33a to 33d, and the source electrode copper connector 36a are mounted. The gate electrode copper connector 36b is mounted on the solder paste (solder 34c) applied on the other wiring pattern 33c other than the wiring pattern 33b (gate electrode copper connector mounting step). Thereby, the semiconductor module intermediate assembly is configured.

そして、以上の工程により構成された半導体モジュール中間組立体をリフロー炉（図示せず）に入れて、複数の配線パターン３３ａ〜３３ｄのうち一つの配線パターン３３ａとベアチップＦＥＴ３５との半田３４ａを介しての接合、配線パターン３３ｄとその他の基板実装部品３７との半田３４ｄを介しての接合、ベアチップＦＥＴ３５の上面に形成されたソース電極Ｓとソース電極用銅コネクタ３６ａとの半田３４ｅを介しての接合、複数の配線パターン３３ａ〜３３ｄのうち他の配線パターン３３ｂとソース電極用銅コネクタ３６ａとの半田３４ｂを介しての接合、ベアチップＦＥＴ３５の上面に形成されたゲート電極Ｇとゲート電極用銅コネクタ３６ｂとの半田３４ｆを介しての接合、及び複数の配線パターン３３ａ〜３３ｄのうち更に他の配線パターン３３ｃとゲート電極用銅コネクタ３６ｂとの半田３４ｃを介しての接合を一括して行う（接合工程）。これにより、半導体モジュール３０は完成する。   Then, the semiconductor module intermediate assembly constituted by the above steps is put in a reflow furnace (not shown), and the solder 34a between one wiring pattern 33a and the bare chip FET 35 among the plurality of wiring patterns 33a to 33d. Bonding, wiring pattern 33d and other board mounting component 37 via solder 34d, source electrode S formed on the upper surface of bare chip FET 35 and source electrode copper connector 36a via solder 34e The other wiring pattern 33b of the plurality of wiring patterns 33a to 33d is joined to the source electrode copper connector 36a via the solder 34b, the gate electrode G formed on the upper surface of the bare chip FET 35 and the gate electrode copper connector 36b. And joining of the plurality of wiring patterns 33a to 33d via the solder 34f. Collectively performed bonded via the solder 34c of the other wiring patterns 33c and the gate electrode copper connector 36b (bonding step). Thereby, the semiconductor module 30 is completed.

ここで、ベアチップＦＥＴ３５のソース電極Ｓと基板３１上の配線パターン３３ｂとの接続にソース電極用銅コネクタ３６ａを用い、ベアチップＦＥＴ３５のゲート電極Ｇと基板３１上の別の配線パターン３３ｃとの接続にゲート電極用銅コネクタ３６ｂを用いることにより、はんだ実装作業で行えるので、ベアチップＦＥＴ３５のソース電極Ｓと基板３１上の配線パターン３３ｂとの接続及びベアチップＦＥＴ３５のゲート電極Ｇと基板３１上の別の配線パターン３３ｃとの接続を、ベアチップＦＥＴ３５やその他の基板実装部品３７を基板３１上の配線パターン３３ａ，３３ｄ上に実装する際に行われるはんだ実装作業と同一の工程で行うことができる。このため、半導体モジュール３０の製造タクトを短くすることができるとともに、ワイヤボンディングの専用設備が不要になり、半導体モジュール３０の製造コストを安価にすることができる。   Here, the source electrode copper connector 36a is used for connection between the source electrode S of the bare chip FET 35 and the wiring pattern 33b on the substrate 31, and the connection between the gate electrode G of the bare chip FET 35 and another wiring pattern 33c on the substrate 31 is used. Since the gate electrode copper connector 36b is used for solder mounting, the connection between the source electrode S of the bare chip FET 35 and the wiring pattern 33b on the substrate 31 and another wiring on the substrate 31 of the gate electrode G of the bare chip FET 35 and the substrate 31 are provided. The connection with the pattern 33c can be performed in the same process as the solder mounting operation performed when the bare chip FET 35 and other board mounting components 37 are mounted on the wiring patterns 33a and 33d on the board 31. For this reason, the manufacturing tact of the semiconductor module 30 can be shortened, and dedicated equipment for wire bonding is not required, and the manufacturing cost of the semiconductor module 30 can be reduced.

ところで、半導体モジュール３０の基板３１にはアルミニウムが用いられており、ソース電極用銅コネクタ３６ａ及びゲート電極用銅コネクタ３６ｂには銅材が用いられている。アルミニウムの線膨張係数は２３．６×１０−６／℃であり、銅材の線膨張係数は１６．８×１０−６／℃であり、ベアチップＦＥＴ３５のシリコンの線膨張係数は２．５×１０−６／℃である。すなわち、基板３１の方が、銅コネクタ３６ａ及び３６ｂよりも温度変化に対して変形しやすい。 By the way, aluminum is used for the substrate 31 of the semiconductor module 30, and a copper material is used for the copper connector 36a for the source electrode and the copper connector 36b for the gate electrode. The linear expansion coefficient of aluminum is 23.6 × 10 −6 / ° C., the linear expansion coefficient of copper material is 16.8 × 10 −6 / ° C., and the linear expansion coefficient of silicon of the bare chip FET 35 is 2.5 ×. 10 −6 / ° C. That is, the substrate 31 is more easily deformed with respect to temperature changes than the copper connectors 36a and 36b.

そのため、リフロー工程や、電動パワーステアリング（ＥＰＳ）作動中の発熱により高温となると、基板３１及びベアチップＦＥＴ３５と銅コネクタ３６ａ，３６ｂとの膨張率の違いにより、銅コネクタ３６ａ，３６ｂに応力がかかる。このとき、銅コネクタ３６ａ，３６ｂがこの応力を緩和できない構造となっていると、ベアチップＦＥＴ３５との半田接合が剥がれてしまうおそれがある。   Therefore, when the temperature becomes high due to heat generation during the reflow process or the electric power steering (EPS) operation, stress is applied to the copper connectors 36a and 36b due to the difference in expansion coefficient between the substrate 31 and the bare chip FET 35 and the copper connectors 36a and 36b. At this time, if the copper connectors 36a and 36b have a structure that cannot relieve the stress, the solder joint with the bare chip FET 35 may be peeled off.

これに対して、本実施形態では、銅コネクタ３６ａ及び３６ｂをブリッジ形状とし、ベアチップＦＥＴ３５の電極との接合面３６ａｆ付近に幅狭部３６ａｇを設けると共に、ベアチップＦＥＴ３５の電極との接合面３６ａｆに応力緩和部３６ａｋを設ける。このように、銅コネクタ３６ａ，３６ｂをブリッジ形状とすることで、上下左右方向（図７のＺ軸方向，Ｘ軸方向）の変位が吸収可能となる。また、幅狭部３６ａｇを設けることで、曲げの基点を細くすることができ、前後方向（図７のＹ軸方向）及び捻り方向の変位が吸収可能となる。   In contrast, in the present embodiment, the copper connectors 36a and 36b are formed in a bridge shape, a narrow portion 36ag is provided in the vicinity of the bonding surface 36af with the electrode of the bare chip FET 35, and stress is applied to the bonding surface 36af with the electrode of the bare chip FET 35. A relaxation part 36ak is provided. Thus, by making the copper connectors 36a and 36b into a bridge shape, it becomes possible to absorb displacement in the vertical and horizontal directions (Z-axis direction and X-axis direction in FIG. 7). In addition, by providing the narrow portion 36ag, the bending base point can be narrowed, and the displacement in the front-rear direction (Y-axis direction in FIG. 7) and the twist direction can be absorbed.

すなわち、熱膨張、熱収縮により基板３１や銅コネクタ３６ａ，３６ｂに変形が生じた場合であっても、銅コネクタ３６ａ，３６ｂを曲がりやすくすることができる。また、幅狭部３６ａｇを接合面３６ａｆ近傍に設けるので、銅コネクタ３６ａ，３６ｂが幅狭部３６ａｇを基点に曲がったときの、銅コネクタ３６ａ，３６ｂとベアチップＦＥＴ３５との半田接合が剥がれにくい。   That is, even when the substrate 31 and the copper connectors 36a and 36b are deformed due to thermal expansion and contraction, the copper connectors 36a and 36b can be easily bent. Further, since the narrow portion 36ag is provided in the vicinity of the joint surface 36af, the solder joint between the copper connectors 36a and 36b and the bare chip FET 35 is difficult to peel off when the copper connectors 36a and 36b are bent with the narrow portion 36ag as a base point.

さらに、応力緩和部３６ａｋを設けることで、捻り方向への応力を緩和することができる。特に、銅コネクタ３６ａ，３６ｂの応力緩和形状を、図８に示すスリット形状とした場合、ベアチップＦＥＴ３５との接点が２つになると共に、各々の接合部の幅がさらに狭くなるため、捻りを受けても追従しやすくなる。また、接点が２つになることで所謂２重系を構成できるので、電気的信頼性が向上する。   Furthermore, the stress in the twisting direction can be relaxed by providing the stress relaxation part 36ak. In particular, when the stress relaxation shape of the copper connectors 36a and 36b is the slit shape shown in FIG. 8, the number of contact points with the bare chip FET 35 is two and the width of each joint portion is further narrowed. Even easier to follow. Moreover, since the so-called dual system can be configured by using two contacts, the electrical reliability is improved.

また、図９に示す薄板形状とした場合、板厚が薄いために捩れやすく、変位吸収しやすい。図１０に示す先端Ｒ形状とした場合、捻りを受けたときの角部への応力集中を逃がす効果がある。さらに、図１１に示す孔形状とした場合にも、捩りを受けても追従しやすくなる。また、半田が接合面３６ａｆの上面に流れて放射状に広がるので、捻りを受けても半田が剥がれ難い。   Moreover, when it is set as the thin plate shape shown in FIG. 9, since plate | board thickness is thin, it is easy to twist and it is easy to absorb a displacement. The tip R shape shown in FIG. 10 has an effect of releasing stress concentration at the corner when subjected to twisting. Furthermore, even in the case of the hole shape shown in FIG. In addition, since the solder flows on the upper surface of the joint surface 36af and spreads radially, it is difficult for the solder to be peeled off even when twisted.

またさらに、応力緩和部３６ａｋのかわりに、略Ｓ字形状の接続部（第１の脚部および第２の脚部）を設けたソース電極用銅コネクタ３６ａの形状について説明する。図１３に示すように、平板部３６ａａと、接続部３６ａｂ（第１の脚部）と、接続部３６ａｃ（第２の脚部）とでブリッジ形状となっている。より具体的には、ソース電極用銅コネクタ３６ａは、平板部３６ａａの左右方向（図１３のＸ軸方向）の一端部に、第１屈曲部３６ａｄを介して接続部３６ａｂの一端が接続されており、接続部３６ａｂの他端は、第２屈曲部３６ａｅを介して外向きの接合面３６ａｆが形成されている。この接合面３６ａｆの下面が半田３４ｅを介してベアチップＦＥＴ３５のソース電極に接合される。接続部３６ａｂは、第１屈曲部３６ａｄから接合面３６ａｆ近傍まで接続部３６ａｂ（第１の脚部）は略Ｓ字のヒューズ形状になっている。平板部３６ａａの左右方向他端部には、第４屈曲部３６ａｉを介して外向きの接合面３６ａｊが形成されている。接続部３６ａｃは、第３屈曲部３６ａｈから接合面３６ａｊまで接続部３６ａｃ（第２の脚部）は、第１の脚部と同様に略Ｓ字のヒューズ形状になっている。この接続部３６ａｂ（第１の脚部）および接続部３６ａｃ（第２の脚部）に略Ｓ字のヒューズ形状により撓みやすく、変位吸収しやすく、応力緩和の効果としては、接続部３６ａｂ（第１の脚部）および接続部３６ａｃ（第２の脚部）ヒューズ部の伸び縮みするだけでなく、ヒューズ部のＳ字形状部が折れる方向にも変形できるので、板バネの効果が得られ、かつ、ブリッジ形状により上下方向、左右方向への変形吸収が更に可能となる。   Further, the shape of the source electrode copper connector 36a provided with a substantially S-shaped connecting portion (first leg portion and second leg portion) instead of the stress relaxation portion 36ak will be described. As shown in FIG. 13, the flat plate portion 36aa, the connection portion 36ab (first leg portion), and the connection portion 36ac (second leg portion) form a bridge shape. More specifically, in the source electrode copper connector 36a, one end of the connection portion 36ab is connected to one end portion in the left-right direction (X-axis direction in FIG. 13) of the flat plate portion 36aa via the first bent portion 36ad. The other end of the connecting portion 36ab is formed with an outward joint surface 36af via the second bent portion 36ae. The lower surface of the bonding surface 36af is bonded to the source electrode of the bare chip FET 35 via the solder 34e. In the connection portion 36ab, the connection portion 36ab (first leg portion) has a substantially S-shaped fuse shape from the first bent portion 36ad to the vicinity of the joint surface 36af. An outward joint surface 36aj is formed on the other end in the left-right direction of the flat plate portion 36aa via a fourth bent portion 36ai. In the connection portion 36ac, the connection portion 36ac (second leg portion) from the third bent portion 36ah to the joint surface 36aj has a substantially S-shaped fuse shape like the first leg portion. The connection part 36ab (first leg part) and the connection part 36ac (second leg part) are easily bent due to the substantially S-shaped fuse shape, easily absorb displacement, and the effect of stress relaxation is as follows. 1 leg) and connection part 36ac (second leg part) not only the fuse part expands and contracts, but also can be deformed in the direction in which the S-shaped part of the fuse part breaks, so that the effect of the leaf spring is obtained, In addition, the bridge shape further enables deformation absorption in the vertical direction and the horizontal direction.

以上のように、銅コネクタ３６ａ及び３６ｂがリフロー工程で熱変形する場合や、電動パワーステアリング（ＥＰＳ）作動中に基板３１が膨張／収縮する場合でも、適切に変位吸収することができるので、銅コネクタ３６ａ及び３６ｂとベアチップＦＥＴ３５との半田接合の剥がれを防止することができ、電気的接合の信頼性を確保することができる。また、銅コネクタ３６ａ，３６ｂ自身の破損も防止することができる。   As described above, even when the copper connectors 36a and 36b are thermally deformed in the reflow process or when the board 31 expands / shrinks during the electric power steering (EPS) operation, the displacement can be appropriately absorbed. The peeling of the solder joint between the connectors 36a and 36b and the bare chip FET 35 can be prevented, and the reliability of the electrical joint can be ensured. Further, the copper connectors 36a and 36b themselves can be prevented from being damaged.

以上、本発明の実施形態について説明してきたが、本発明はこれに限定されずに種々の変更、改良を行うことができる。例えば、半導体モジュール３０においてベアチップＦＥＴ３５を用いているが、ベアチップＦＥＴ３５に限らず、ベアチップＩＧＢＴなどの他のベアチップトランジスタを用いてもよい。そして、その他のベアチップトランジスタを用いる場合には、銅コネクタにより、ベアチップトランジスタの上面に形成された電極上と複数の配線パターンのうちベアチップトランジスタが接続された配線パターン以外の他の配線パターン上とを半田を介して接合すればよい。これにより、ベアチップトランジスタの電極と基板上の配線パターンとの接合をベアチップトランジスタやその他の表面実装部品を基板上の配線パターン上に実装する際に行われるはんだ実装作業と同一の工程で行うことができる。   As mentioned above, although embodiment of this invention has been described, this invention is not limited to this, A various change and improvement can be performed. For example, although the bare chip FET 35 is used in the semiconductor module 30, other bare chip transistors such as the bare chip IGBT may be used instead of the bare chip FET 35. When other bare chip transistors are used, the copper connector is used to connect the electrodes formed on the top surface of the bare chip transistor and other wiring patterns other than the wiring pattern to which the bare chip transistor is connected among the plurality of wiring patterns. What is necessary is just to join via solder. As a result, the bonding of the bare chip transistor electrode and the wiring pattern on the substrate can be performed in the same process as the solder mounting operation performed when mounting the bare chip transistor or other surface mount components on the wiring pattern on the substrate. it can.

そして、ベアチップトランジスタとしてベアチップＩＧＢＴを用いる場合、ベアチップＩＧＢＴ上に形成されたエミッタ電極及びゲート電極を、それぞれ、銅コネクタを用いて基板上の配線パターンに半田を介して接合することが好ましい。このように、ベアチップＩＧＢＴを用い、ベアチップＩＧＢＴ上に形成されたエミッタ電極及びゲート電極を、それぞれ、銅コネクタを用いて基板上の配線パターンに半田を介して接合する場合には、ベアチップＩＧＢＴのエミッタ電極と基板上の配線パターンとの接続及びベアチップＩＧＢＴのゲート電極と基板上の別の配線パターンとの接合をベアチップＩＧＢＴやその他の表面実装部品を基板上の配線パターン上に実装する際に行われるはんだ実装作業と同一の工程で行うことができる。   And when using bare chip IGBT as a bare chip transistor, it is preferable to join the emitter electrode and gate electrode which were formed on bare chip IGBT to the wiring pattern on a board | substrate via solder, respectively using a copper connector. As described above, when the bare chip IGBT is used and the emitter electrode and the gate electrode formed on the bare chip IGBT are respectively joined to the wiring pattern on the substrate using the copper connector via the solder, the emitter of the bare chip IGBT is used. The connection between the electrode and the wiring pattern on the substrate and the bonding between the gate electrode of the bare chip IGBT and another wiring pattern on the substrate are performed when the bare chip IGBT or other surface-mounted component is mounted on the wiring pattern on the substrate. It can be performed in the same process as the solder mounting operation.

１…操向ハンドル、２…コラム軸、３…減速ギア、４Ａ，４Ｂ…ユニバーサルジョイント、５…ピニオンラック機構、６…タイロッド、７…トルクセンサ、８…電動モータ、９…車速センサ、１０…コントローラ、１１…制御演算装置、１２…ゲート駆動回路、１３…モータ駆動部、１４…非常停止用の遮断装置、１５…電流検出回路、１６…回転センサ、１７…ロータ位置検出回路、１８…ＩＧＮ電圧モニタ部、１９…電源回路部、２０…ケース、２１…半導体モジュール載置部、２１ａ…ねじ孔、２２…電力及び信号用コネクタ実装部、２３…３相出力用コネクタ実装部、２３ａ…ねじ孔、２４…取付けポスト、２４ａ…ねじ孔、３０…半導体モジュール、３１…基板、３１ａ…貫通孔、３２…絶縁層、３３ａ〜３３ｄ…配線パターン、３４ａ〜３４ｄ…半田、３５…ベアチップＦＥＴ（ベアチップトランジスタ）、３６ａ…ソース電極用銅コネクタ、３６ａａ…平板部、３６ａｂ…接続部（第１の脚部）、３６ａｃ…接続部（第２の脚部）、３６ａｄ…第１屈曲部、３６ａｅ…第２屈曲部、３６ａｆ…接合面、３６ａｇ…幅狭部、３６ａｈ…第３屈曲部、３６ａｉ…第４屈曲部、３６ａｊ…接合面、３６ａｋ…応力緩和部、３６ｂ…ゲート電極用銅コネクタ、３６ｂａ…平板部、３６ｂｂ…接続部、３６ｂｃ…接続部、３７…基板実装部品、３８…取付けねじ、３９…放熱用シート、４０…制御回路基板、４０ａ…貫通孔、４１…取付けねじ、５０…電力及び信号用コネクタ、５１…取付けねじ、６０…３相出力用コネクタ、６０ａ…貫通孔、６１…取付けねじ、７０…カバー、８１…電源ライン、８１ａ…正極端子、８２…接地ライン、８２ａ…負極端子、９０…３相出力部、９１ａ…ａ相出力ライン、９１ｂ…ｂ相出力ライン、９１ｃ…ｃ相出力ライン、Ｇ…ゲート電極（電極）、Ｓ…ソース電極（電極）   DESCRIPTION OF SYMBOLS 1 ... Steering handle, 2 ... Column shaft, 3 ... Reduction gear, 4A, 4B ... Universal joint, 5 ... Pinion rack mechanism, 6 ... Tie rod, 7 ... Torque sensor, 8 ... Electric motor, 9 ... Vehicle speed sensor, 10 ... Controller 11, control arithmetic device 12, gate drive circuit 13, motor drive unit 14, interruption device for emergency stop 15, current detection circuit 16, rotation sensor 17, rotor position detection circuit 18, IGN Voltage monitor unit, 19 ... Power supply circuit unit, 20 ... Case, 21 ... Semiconductor module mounting unit, 21a ... Screw hole, 22 ... Power and signal connector mounting unit, 23 ... 3-phase output connector mounting unit, 23a ... Screw Holes, 24 ... mounting posts, 24a ... screw holes, 30 ... semiconductor modules, 31 ... substrates, 31a ... through holes, 32 ... insulating layers, 33a-33d ... wiring patterns, 4a to 34d ... solder, 35 ... bare chip FET (bare chip transistor), 36a ... copper connector for source electrode, 36aa ... flat plate part, 36ab ... connecting part (first leg part), 36ac ... connecting part (second leg part) ), 36ad ... first bent portion, 36ae ... second bent portion, 36af ... joint surface, 36ag ... narrow portion, 36ah ... third bent portion, 36ai ... fourth bent portion, 36aj ... joint surface, 36ak ... stress relaxation Part, 36b ... copper connector for gate electrode, 36ba ... flat plate part, 36bb ... connection part, 36bc ... connection part, 37 ... board mounting component, 38 ... mounting screw, 39 ... heat dissipation sheet, 40 ... control circuit board, 40a ... Through hole, 41 ... Mounting screw, 50 ... Power and signal connector, 51 ... Mounting screw, 60 ... 3-phase output connector, 60a ... Through hole, 61 ... Mounting screw, 70 ... Cover , 81 ... power line, 81a ... positive terminal, 82 ... ground line, 82a ... negative terminal, 90 ... three-phase output section, 91a ... a-phase output line, 91b ... b-phase output line, 91c ... c-phase output line, G ... Gate electrode (electrode), S ... Source electrode (electrode)

Claims (6)

金属製の基板と、該基板の上に形成された絶縁層と、該絶縁層上に形成された複数の配線パターンと、該複数の配線パターンのうち一つの配線パターン上に半田を介して実装されるベアチップトランジスタと、該ベアチップトランジスタの上面に形成された電極上と前記複数の配線パターンのうち他の配線パターン上とを半田を介して接合する、銅板で構成される銅コネクタとを備え、
前記銅コネクタは、前記電極上に接続される第１の脚部と、前記配線パターン上に接続される第２の脚部とを有するブリッジ形状であり、
前記第１の脚部の前記電極との接合面近傍に、前記第１の脚部の他の部分と比較して幅の狭い幅狭部を設けると共に、前記第１の脚部の前記電極との接合面に、当該接合面に作用する応力を緩和する形状を有する応力緩和部を設けることを特徴とする半導体モジュール。 A metal substrate, an insulating layer formed on the substrate, a plurality of wiring patterns formed on the insulating layer, and solder mounted on one wiring pattern among the plurality of wiring patterns A bare chip transistor, and a copper connector composed of a copper plate that joins the electrode formed on the top surface of the bare chip transistor and another wiring pattern among the plurality of wiring patterns via solder,
The copper connector has a bridge shape having a first leg connected to the electrode and a second leg connected to the wiring pattern;
In the vicinity of the joint surface of the first leg with the electrode, a narrower portion having a narrower width than the other part of the first leg is provided, and the electrode of the first leg A semiconductor module, wherein a stress relaxation portion having a shape that relieves stress acting on the joint surface is provided on the joint surface. 前記応力緩和部として、前記接合面に切り欠き部を形成したことを特徴とする請求項１に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein a notch portion is formed in the joint surface as the stress relaxation portion. 前記応力緩和部として、前記接合面を薄板で形成したことを特徴とする請求項１又は２に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein the joining surface is formed of a thin plate as the stress relaxation portion. 前記応力緩和部として、前記接合面の角部に面取り部を形成したことを特徴とする請求項１〜３の何れか１項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein a chamfered portion is formed at a corner portion of the joint surface as the stress relaxation portion. 前記応力緩和部として、前記接合面の中央に孔を形成したことを特徴とする請求項１〜４の何れか１項に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein a hole is formed in the center of the joint surface as the stress relaxation portion. 前記応力緩和部として、前記第１の脚部と前記第２の脚部にそれぞれＳ字のヒューズ形状を形成したことを特徴とする請求項１に記載の半導体モジュール。   The semiconductor module according to claim 1, wherein an S-shaped fuse shape is formed on each of the first leg portion and the second leg portion as the stress relaxation portion.
JP2013200138A 2013-09-26 2013-09-26 Semiconductor module Pending JP2015069990A (en)

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