JP2015060981A - Printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which achieves high connection reliability even if a through hole conductor has voids.SOLUTION: A through hole 10h is formed on a substrate 10, and conductor layers 11, 12 are formed on both sides of the substrate 10. A through hole conductor 10c formed in the through hole 10h includes an upper seed layer 81 and a lower seed layer 82 which close the through hole 10h. The through hole conductor 10c electrically connects the conductor layer 11 with the conductor layer 12.

Description

  The present invention relates to a printed wiring board.

  As a wiring board for mounting an IC chip (semiconductor element), a printed wiring board having a core substrate having a through-hole conductor and a build-up layer formed on the core substrate is known.

  As a technique for manufacturing such a printed wiring board, for example, a technique described in Patent Document 1 is known. In the technique described in Patent Document 1, as shown in FIG. 3 of Patent Document 1, hourglass-shaped through holes are formed in the substrate, and the through holes are filled with plating.

JP 2006-041463 A

  The technique described in Patent Document 1 is suitable for filling through holes for through-hole conductors with plating. However, if the aspect ratio of the through hole for the through hole conductor (the length of the through hole / the diameter of the through hole) increases, it is considered difficult to completely fill the through hole for the through hole conductor with plating.

  An object of the present invention is to provide a printed wiring board having high connection reliability even if a through-hole conductor has a void.

  A printed wiring board according to the present invention includes a substrate having a first surface and a second surface opposite to the first surface and having a through hole, and a first conductor layer formed on the first surface of the substrate And a second conductor layer formed on the second surface of the substrate, a through-hole conductor formed inside the through hole and connecting the first conductor layer and the second conductor layer, Have The through-hole conductor includes an electrolytic plating film and an upper seed layer and a lower seed layer sandwiching the electrolytic plating film in the through hole.

  According to the present invention, it is possible to suppress the movement of voids existing inside the through-hole conductor. For this reason, even if a through-hole conductor has a void, the printed wiring board which has high connection reliability can be provided.

The figure for demonstrating the printed wiring board which concerns on this embodiment The figure for demonstrating the lamination | stacking state of the plating film currently formed in the through-hole The figure for explaining the process of preparing a substrate The figure for demonstrating the process of forming a through-hole The figure for demonstrating the process of forming a 1st seed layer. The figure for demonstrating the process of forming a 2nd plating film The figure for demonstrating the process of forming a 2nd seed layer The figure for demonstrating the process of forming a 2nd plating film The figure for demonstrating the process of forming an etching resist The figure for demonstrating the process of etching the plating film on a board | substrate The figure for demonstrating the process of peeling an etching resist The figure for demonstrating the process of forming an insulating layer on both surfaces of a board | substrate The figure for demonstrating the process of forming opening The figure for demonstrating the process of forming an electroless copper plating film The figure for demonstrating the process of forming a plating resist The figure for demonstrating the process of forming an electrolytic plating film The figure for demonstrating the process of etching the plating film on an insulating layer The figure for demonstrating the wiring board which concerns on the modification 1 The figure for demonstrating the wiring board which concerns on the modification 2 The figure for demonstrating the wiring board which concerns on the modification 3 The figure for demonstrating the wiring board which concerns on the modification 4

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Each of the arrows Z1 and Z2 in the figure indicates the thickness direction of the wiring board. Hereinafter, the Z1 direction indicates the upper side of the wiring board, and the Z2 direction indicates the lower side of the wiring board. On the other hand, each of the arrows X1, X2, Y1, and Y2 indicates a direction orthogonal to the stacking direction of the wiring boards. The main surface of the wiring board is an XY plane. The side surface of the wiring board is an XZ plane or a YZ plane.

When a high current flows through a through-hole conductor including a void, the void may move inside the through-hole conductor. When the void moves to the conductor circuit or the via conductor, the volume of the conductor is reduced, so that the resistance is increased. Therefore, malfunction may occur in the IC mounted on the printed wiring board. Moreover, the connection reliability of a printed wiring board falls. When a void reaches a conductor circuit having a width of 12 μm or less, the conductor circuit may be disconnected.

<Configuration of printed wiring board>
As shown in FIG. 1, the printed wiring board 100 according to the present embodiment includes a wiring board 1000, a buildup layer 2, and a buildup layer 4.

  The wiring board 1000 includes a substrate 10 having a first surface F1 and a second surface F2 opposite to the first surface F1, a first conductor layer 11 formed on the first surface F1 of the substrate 10, and the substrate 10. The second conductor layer 12 formed on the second surface F2 and the through-hole conductor 10c penetrating the substrate 10 and connecting the first conductor layer 11 and the second conductor layer 12 to each other.

  The through-hole conductor 10c is formed inside a through-hole 10h for a through-hole conductor that penetrates the substrate 10, and has a void V1. The through-hole conductor 10c of the present embodiment is a through-hole structure formed of a cylindrical through-hole conductor formed on the inner wall of the through-hole 10h and a resin filled in the cylindrical through-hole conductor. Not included.

  The principal surface in the Z1 direction of the substrate 10 is the first surface F1, and the principal surface in the Z2 direction is the second surface F2. The first surface F1 of the substrate 10 and the first surface of the wiring board 1000 are the same surface, and the second surface F2 of the substrate 10 and the second surface of the wiring board 1000 are the same surface.

The first conductor layer 11 includes a land 11c formed of a conductor around the through-hole conductor 10c formed on the first surface F1 of the substrate 10 and a conductor on the through-hole conductor 10c. Similarly, the second conductor layer 12 includes a land 12c formed of a conductor around the through-hole conductor 10c formed on the second surface F2 of the substrate 10 and a conductor under the through-hole conductor 10c. As shown in FIG. 2, the through-hole conductor 10c is a conductor formed inside the through hole 10h.
The lands 11c and 12c are conductors connected to the through-hole conductor 10c and formed outside the through-hole 10h. The shape of the lands 11c and 12c is generally a circle or an ellipse in the XY plane. The lands 11c and 12c are larger than the through-hole conductor 10c and cover the through-hole conductor 10c.

  Build-up layer 2 is formed on interlayer resin insulation layer 20 formed on first surface F1 of wiring board 1000, conductor layer 21 formed on interlayer resin insulation layer 20, and conductor layer 21. An interlayer resin insulation layer 30 and a conductor layer 31 formed on the interlayer resin insulation layer 30. In the interlayer resin insulation layer 20, a via conductor 20 c that penetrates the interlayer resin insulation layer 20 and connects the conductor layer 11 and the conductor layer 21 is formed. In the interlayer resin insulation layer 30, a via conductor 30 c that penetrates the interlayer resin insulation layer 30 and connects the conductor layer 21 and the conductor layer 31 is formed.

  Build-up layer 4 is formed on interlayer resin insulation layer 40 formed on second surface F2 of wiring board 1000, conductor layer 41 formed on interlayer resin insulation layer 40, and conductor layer 41. An interlayer resin insulation layer 50, and a conductor layer 51 formed on the interlayer resin insulation layer 50. In the interlayer resin insulation layer 40, via conductors 40 c that penetrate the interlayer resin insulation layer 40 and connect the conductor layer 12 and the conductor layer 41 are formed. In the interlayer resin insulation layer 50, via conductors 50 c that penetrate the interlayer resin insulation layer 50 and connect the conductor layer 41 and the conductor layer 51 are formed.

  The interlayer resin insulation layers 20, 30, 40, 50 are formed of resin and inorganic particles such as silica.

  A solder resist layer is formed on the buildup layers 2 and 4. The upper solder resist layer on the buildup layer 2 has an opening. The conductor layer 31 and the via conductor 30c exposed from the opening of the upper solder resist layer on the buildup layer 2 function as a C4 pad. The lower solder resist layer on the buildup layer 4 also has an opening. The conductor layer 51 and the via conductor 50c exposed from the opening of the lower solder resist layer on the buildup layer 4 function as a BGA pad. A C4 bump is formed on the C4 pad, and the printed wiring board 100 and the IC chip are connected via the C4 bump. BGA bumps are formed on the BGA pads, and the printed wiring board 100 and the motherboard are connected via the BGA bumps.

  The substrate 10 is a core substrate of the printed wiring board 100. The substrate 10 is an insulating substrate including a reinforcing material such as glass cloth and a resin such as an epoxy resin. The thickness of the substrate 10 is, for example, not less than 0.1 mm and not more than 0.7 mm. If the thickness of the substrate 10 is less than 0.1 mm, since the strength of the substrate 10 is small, warping of the substrate 10 is likely to occur, and the reliability of the through-hole conductor 10c is reduced. When the thickness of the substrate 10 exceeds 0.7 mm, a large void is generated in the through-hole conductor 10c or the number of voids is increased, so that the reliability of the through-hole conductor 10c is lowered.

  The shape of the through hole 10h may be a straight shape or an hourglass shape. In FIG. 1, an hourglass-shaped through hole 10 h is formed in the substrate 10. The through-hole 10h is formed by irradiating the both surfaces of the substrate 10 with laser light.

  As shown in FIG. 2, the through hole 10 h has a first opening 101 h on the first surface F <b> 1 of the substrate 10 and a second opening 102 h on the second surface F <b> 2 of the substrate 10. The first opening 101h is included in the first surface F1, and the second opening 102h is included in the second surface F2. Of the diameters of the first opening 101h and the second opening 102h, the larger diameter is the diameter of the through hole 10h.

  The through-hole conductor 10c includes a first seed layer 60 formed on the inner wall of the through-hole 10h, a first plating film 70 on the first seed layer 60, and an upper second seed layer on the first plating film 70. 81, a lower second seed layer 82 on the first plating film 70, and second plating films 91 and 92 on the second seed layers 81 and 82.

  The first seed layer 60 is an electroless plating film, a sputtered film, or a deposited film. The first plating film 70 is an electrolytic plating film in the present embodiment, but may be an electroless plating film. A plating film such as an electrolytic plating film or an electroless plating film is preferably formed of copper.

  A void V <b> 1 is formed in the first plating film 70. For example, when the aspect ratio of the through hole 10 h is large, when the growth of plating is fast, or when the unevenness of the inner wall of the through hole 10 h is large, the void V 1 is generated in the first plating film 70.

  As shown in FIG. 2, a second seed layer 81 is formed on the Z1 side on the first plating film 70 forming the through-hole conductor 10c, and a second seed layer 82 is formed on the Z2 side. Yes. The second seed layer 81 is formed on the upper surface of the first plating film 70. The second seed layer 82 is formed on the lower surface of the first plating film 70. That is, the first plating film 70 is sandwiched between the upper second seed layer 81 (upper seed layer) and the lower second seed layer 82 (lower seed layer).

  Whereas the first plating film 70 is an electrolytic plating film, the second seed layers 81 and 82 are an electroless plating film, a sputtered film, a vapor deposition film, an electrolytic plating film, or a conductive paste film. Since the second seed layers 81 and 82 and the first plating film 70 are different films, the movement of the metal forming the first plating film 70 is caused at the interface between the second seed layers 81 and 82 and the first plating film 70. It is thought to be suppressed. Therefore, it is considered that the movement of the void V1 is suppressed.

  From the viewpoint of manufacturing, the second seed layers 81 and 82 are preferably electroless plating films. Alternatively, the second seed layers 81 and 82 are preferably conductive paste films. Since the conductive paste film contains a resin in addition to the metal particles, it is considered that the resin suppresses the movement of the void V1.

  The second seed layers 81 and 82 and the first plating film 70 can also be formed by different methods. For example, the first plating film 70 is formed by electrolytic plating, and the second seed layers 81 and 82 are formed by electroless plating, sputtering, vapor deposition, or printing. However, the second seed layers 81 and 82 are preferably formed by electroless plating. Since the second seed layers 81 and 82 and the first plating film 70 are formed by different methods, it is considered that the metal orientation of the first plating film 70 and the metal orientation of the second seed layers 81 and 82 are different. Alternatively, it is considered that a barrier layer is formed between the first plating film 70 and the second seed layers 81 and 82. These are considered to suppress the movement of the void V1.

  The diameter L1 (average particle diameter) of the metal particles forming the second seed layers 81 and 82 is smaller than the diameter L2 (average particle diameter) of the metal particles forming the first plating film 70. Is preferred. Specifically, the value P0 obtained by the formula (1) is preferably 0.01 to 0.1. Thereby, it is considered that the movement of the void V1 is suppressed.

  P0 = L1 / L2 (1)

  In addition, the main component of the first plating film 70 and the main component of the second seed layers 81 and 82 are the same, and the amount of subcomponents included in the second seed layers 81 and 82 is included in the first plating film 70. Preferably greater than the amount of the components. It is considered that the movement of the main component of the first plating film 70 is suppressed by the subcomponents of the second seed layers 81 and 82, and as a result, the movement of the void V1 is suppressed. When the main component of the first plating film 70 and the second seed layers 81 and 82 is copper, the subcomponent of the second seed layers 81 and 82 may be any of resin, nickel, and cobalt, but is nickel. It is preferable.

  The land 11c formed on the first surface F1 of the substrate 10 includes the copper foil 13, the first seed layer 60 on the copper foil 13, the first plating film 70 on the first seed layer 60, and the first A second seed layer 81 on the plating film 70 and a second plating film 91 on the second seed layer 81 are formed.

  The land 12c formed on the second surface F2 of the substrate 10 includes the copper foil 14, the first seed layer 60 on the copper foil 14, the first plating film 70 on the first seed layer 60, and the first A second seed layer 82 on the plating film 70 and a second plating film 92 on the second seed layer 82 are formed.

The first plating film 70 has a first space 711h and a second space 721h. The first space 711h is a recess formed on the first surface F1 side, and is tapered from the first surface F1 toward the second surface F2. The second space 721h is a recess formed on the second surface F2 side, and is tapered from the second surface F2 toward the first surface F1.
Thus, the bottom of the first space 711h is formed on the inner side of the substrate 10 with respect to the first surface F1, and the bottom of the second space 721h is formed on the inner side of the substrate 10 with respect to the second surface F2.
For this reason, the inside of the through hole 10 h is not completely filled with the first plating film 70. Therefore, in the present embodiment, the volume of the first plating film 70 formed in the through hole 10h is reduced. Therefore, the void V1 in the first plating film 70 can be reduced.

  The second seed layer 81 (upper seed layer) is formed so as to cover the first space 711h. Therefore, the second seed layer 81 also has a third space 811h similar to the first space 711h. The second seed layer 82 (lower seed layer) is formed so as to cover the second space 721h. Therefore, the second seed layer 82 also has a fourth space 821h similar to the second space 721h.

  The second plating film (upper second plating film) 91 is filled in the third space 811h, and the second plating film (lower second plating film) 92 is filled in the fourth space 821h. . Even if the aspect ratio of the through-hole 10h is large, the depth of the third space 811h and the fourth space 821h is reduced by the plating film, so that the third space 811h and the fourth space 821h can be used as an electrolytic plating film or the like. It can be filled with a plating film. Further, since the wall surfaces of the third space 811h and the fourth space 821h are the upper surfaces of the second seed layers 81 and 82, the unevenness is small. Therefore, the third space 811h and the fourth space 821h can be filled with the plating film. Since the third space 811h and the fourth space 821h are tapered toward the center of the substrate 10 in the Z direction, the third space 811h and the fourth space 821h can be filled with the plating film. The shape of the plating film filling the third space 811h and the shape of the plating film filling the fourth space 821h are substantially conical. The third space 811h and the fourth space 821h are filled with the second plating films 91 and 92 that do not include the void V1. The second plating film (upper second plating film) 91 and the second plating film (lower second plating film) 92 are preferably electrolytic plating films.

  In the printed wiring board 100 according to the present embodiment, second seed layers 81 and 82 are formed on both ends of the first plating film 70 including the void V1. For this reason, the movement of the void V1 inside the through-hole conductor 10c is suppressed.

  The movement mechanism of the void V1 is presumed to be electromigration or stress migration. In the present embodiment, since the second seed layers 81 and 82 are formed at both ends of the first plating film 70, it is considered that electromigration and stress migration can be suppressed. It is inferred that the void V <b> 1 remains in the first plating film 70. For this reason, in the present embodiment, disconnection of the via conductors 20c and 40c formed on the lands 11c and 12c of the through-hole conductor 10c and the conductor circuit connected to the lands 11c and 12c of the through-hole conductor 10c is suppressed. Inferred.

  The second seed layers 81 and 82 contain copper as a main component, and contain a metal that easily oxidizes, such as nickel, as a subcomponent. It is presumed that migration is suppressed because the second seed layers 81 and 82 contain a metal that is more easily oxidized than copper. For this reason, it is considered that the void V <b> 1 remains in the first plating film 70.

<Method for Manufacturing Printed Wiring Board 100>
Then, the manufacturing method of the printed wiring board 100 is demonstrated, referring FIGS.

  First, as shown in FIG. 3, a double-sided copper-clad laminate is prepared as a starting material. The double-sided copper clad laminate is formed of the substrate 10, the copper foil 13 laminated on the first surface F1 of the substrate 10, and the copper foil 14 laminated on the second surface F2 of the substrate 10. ing.

  Next, a CO2 laser is irradiated on both sides of the double-sided copper clad laminate as a starting material. Thereby, as shown in FIG. 4, a through hole 10h is formed. Note that laser light irradiation is performed on each side.

  Next, electroless plating is performed on the surface of the substrate 10. Thereby, as shown in FIG. 5, an electroless plating film mainly composed of copper is formed on the surfaces of the copper foils 13 and 14 and the inner wall of the through hole 10h. This electroless plating film is the first seed layer 60.

  Next, electrolytic plating is performed on the surface of the first seed layer 60. Thereby, as shown in FIG. 6, an electrolytic plating film (electrolytic copper plating film) containing copper as a main component is formed on the first seed layer 60. This electrolytic plating film is the first plating film 70. However, the main component of the first plating film 70 may be nickel, titanium, chromium, or the like. A void V <b> 1 is formed inside the first plating film 70.

  For example, when the aspect ratio (the length of the through hole 10h / the diameter of the through hole 10h) is 2 or more, the void V1 is likely to be generated in the first plating film 70. In particular, when the aspect ratio is 2 or more and the thickness D10 of the substrate 10 is 0.2 mm or more, it is difficult to form a plating film that does not include the void V1.

  As shown in FIG. 6, a first space 711h is formed on the upper side of the first plating film 70, and a second space 721h is formed on the lower side. As shown in Expression (2), a value P1 obtained by dividing the depth D711 of the first space 711h by the thickness D10 of the substrate 10 is preferably 0.25 to 0.4. Similarly, as shown in Expression (3), a value P2 obtained by dividing the depth D721 of the second space 721h by the thickness D10 of the substrate 10 is preferably 0.25 to 0.4. . Thereby, it is considered that the amount of the void V1 is reduced or the size of the void V1 is reduced.

P1 = D711 / D10 (2)
P2 = D721 / D10 (3)

  In this embodiment, since the balance between the thickness of the first seed layer 60 formed in the through hole 10h and the thickness of the first plating film 70 is good, a large void or a large number of voids are formed in the first plating film 70. Not. Even if a large current flows through the first plating film 70, the void V <b> 1 remains in the first plating film 70.

  Next, electroless plating is performed on the surface of the electrolytic plating film 70. Thereby, as shown in FIG. 7, second seed layers (electroless plating films) 81 and 82 are formed. For example, the second seed layers 81 and 82 are electroless copper plating films.

  Next, electrolytic plating is performed on the surfaces of the electroless plating films 81 and 82. Thereby, as shown in FIG. 8, second plating films (electrolytic plating films) 91 and 92 are formed. For example, the second plating films 91 and 92 are electrolytic copper plating films.

  Next, as shown in FIG. 9, etching resists 18 and 19 are formed on the second plating films 91 and 92.

  Next, as shown in FIG. 10, the copper foil 13 exposed from the etching resist 18, the first seed layer 60, the first plating film 70, the second seed layer 81, and the second plating film 91 are etched. Removed. Similarly, the copper foil 14 exposed from the etching resist 19, the first seed layer 60, the first plating film 70, the second seed layer 82, and the second plating film 92 are removed by etching.

  Next, as shown in FIG. 11, the etching resists 18 and 19 are removed. Thereby, the through-hole conductor 10c, the first conductor layer 11 including the land 11c, and the second conductor layer 12 including the land 12c are formed. Thereby, the wiring board 1000 is completed.

  Next, as shown in FIG. 12, interlayer resin insulation layers 20 and 40 and copper foils 22 and 42 are formed on both surfaces of wiring board 1000.

  Next, as shown in FIG. 13, openings 20 h and 40 h are formed in the interlayer resin insulation layers 20 and 40.

  As shown in FIG. 14, electroless copper plating films 23 and 43 are formed on the copper foils 22 and 42 and in the openings 20h and 40h.

  As shown in FIG. 15, plating resists 24 and 44 are formed on the electroless copper plating films 23 and 43.

  Thereafter, as shown in FIG. 16, electrolytic plating films 25 and 45 are formed on the electroless copper plating films 23 and 43 exposed from the plating resists 24 and 44.

  Thereafter, the plating resists 24 and 44 are removed using a predetermined stripping solution. Further, unnecessary electroless copper plating films 23 and 43 and copper foils 22 and 42 are removed by the etching process. Thereby, as shown in FIG. 17, conductor layers 21 and 41 including lands 21c and 41c and via conductors 20c and 40c are formed.

  Thereafter, by repeating the same process, as shown in FIG. 1, the conductor layers 31 and 51 including the lands 31c and 51c and the via conductors 30c and 50c are formed, so that the upper and lower sides of the wiring board 1000 are formed. Then, the build-up layers 2 and 4 are formed.

  Through the above steps, the printed wiring board 100 according to the present embodiment is completed. Thereafter, a solder resist layer can be formed on the buildup layers 2 and 4.

<Modification 1>
As shown in FIG. 18, the second plating films 91 and 92 can be eliminated by increasing the thickness of the second seed layers 81 and 82 such as an electroless plating film. Since the second seed layers 81 and 82 are formed at both ends of the plating film 70, the wiring board 1000 shown in FIG. 18 has the same effect as the wiring board 1000 shown in FIG.

<Modification 2>
A wiring board 1000 shown in FIG. 19 includes a third plating film 93 and a third seed layer 83 between the second seed layer 81 and the second plating film 91. The wiring board 1000 of the modified example 2 has the same effect as the wiring board 1000 shown in FIG.

<Modification 3>
The shape of the through hole 10h and the through hole conductor 10c according to the embodiment is an hourglass shape. The shape of the through hole 10h and the through hole conductor 10c may be substantially cylindrical as shown in FIG. 20, for example. In this case, the laser is irradiated from one side of the starting material.

<Modification 4>
In FIG. 1, one via conductor 20c is formed on the land 11c of the through-hole conductor 10c. For example, as shown in FIG. 21, a plurality of via conductors 20c can be formed on the land 11c of the through-hole conductor 10c. Thereby, current flows into the first plating film 70 from a plurality of paths, so that the current density in the first plating film 70 is made uniform. As a result, it is considered that the movement of the void V1 can be suppressed.
Further, since the plurality of via conductors 20c are formed on the land 11c, even if the void V1 moves to a part of the via conductors 20c on the land 11c, the remaining via conductors 20c cause the via conductors 20c and the through holes to pass through. Electrical connection is made between the conductors 10c. For this reason, the connection reliability between the via conductor 20c and the through-hole conductor 10c is unlikely to decrease.

<Modification 5>
The first plating film (electrolytic plating film) 70 may include a plurality of voids V1.

2, 4 Build-up layer 10 Substrate 10c Through-hole conductor 10h Through-hole 11 First conductor layer 11c, 12c, 21c, 31c, 41c, 51c Land 12 Second conductor layer 13, 14, 22, 42 Copper foil 18, 19 Etching Resist 20, 30, 40, 50 Interlayer resin insulation layer 20c, 30c, 40c, 50c Via conductor 20h, 40h Open 21, 31, 41, 51 Conductor layer 23, 43 Electroless copper plating film 24, 44 Plating resist 25, 45 Electrolytic plating film 60 First seed layer 70 First plating film 81 Second seed layer (upper seed layer)
82 Second seed layer (lower seed layer)
83 Third seed layer 91 Second plating film (upper second plating film)
92 Second plating film (lower second plating film)
93 3rd plating film 100 Printed wiring board 101h 1st opening 102h 2nd opening 711h 1st space 721h 2nd space 811h 3rd space 821h 4th space 1000 Wiring board D10 thickness D711, D721 depth F1 1st surface F2 2nd Surface V1 Void

Claims (7)

A substrate having a first surface and a second surface opposite to the first surface and having a through hole;
A first conductor layer formed on the first surface of the substrate;
A second conductor layer formed on the second surface of the substrate;
A through-hole conductor formed inside the through hole and connecting the first conductor layer and the second conductor layer;
A printed wiring board having
The through-hole conductor includes an electrolytic plating film and an upper seed layer and a lower seed layer sandwiching the electrolytic plating film in the through hole. In the printed wiring board of Claim 1,
The upper seed layer and the lower seed layer cover the electrolytic plating film. In the printed wiring board according to claim 2,
The upper seed layer extends from the through-hole conductor to form the first conductor layer, and the lower seed layer extends from the through-hole conductor to form the second conductor layer. ing. In the printed wiring board of Claim 1,
The electrolytic plating film is formed in the through hole so that a first space is formed on the first surface side, and in the through hole so that a second space is formed on the second surface side. Is formed.   The printed wiring board according to claim 1, wherein voids are formed in the electrolytic plating film. In the printed wiring board according to claim 4,
The through-hole conductor includes an upper second plating film formed in the first space and a lower second plating film formed in the second space. In the printed wiring board as described in any one of Claims 1 thru | or 6,
The upper seed layer or the lower seed layer includes nickel.

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