JP2015060853A - Element part separation method and nitride semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To separate an element part and a single crystal substrate with a buffer layer deposited thereon by etching without applying a mechanical stress.SOLUTION: A nitride semiconductor device includes: a single crystal substrate 1; a buffer layer 2 deposited on a surface of the single crystal substrate; a SiOmask 3 provided on a surface of the buffer layer; and nitride semiconductor element structure layers 4a, 4b covering on a SiOmask pattern and on the buffer layer 2 exposed from the SiOmask pattern. In the nitride semiconductor element structure layers, a circumferential groove part 5 dividing the SiOmask pattern into an external region and an internal region is formed. The internal region forms an element part 4b which can be separated from the single crystal substrate by subjecting the SiOmask pattern to wet etching. When wet etching is performed, the element part 4b is fixed to a support 7.

Description

  The present invention relates to an element part peeling method and a nitride semiconductor device including the element part, and in particular, a nitride optical device, a nitride electronic device, and an element part thereof having a structure capable of easily peeling a single device. The present invention relates to a peeling method.

  In recent years, gallium nitride (GaN) single crystal has been widely used as an epitaxial film growth substrate for manufacturing optical devices and electronic devices, and a bulk single crystal manufacturing method has been researched and developed by many organizations to obtain this substrate. Has been. However, since gallium nitride has a high vapor pressure, it is difficult to obtain a large bulk single crystal from melt like silicon or gallium arsenide with good reproducibility. For this reason, it is not easy to produce a large-diameter bulk single crystal that can be used as a gallium nitride device. Gallium nitride single crystal substrates that have been attracting attention in recent years are the growth of gallium nitride on a heterogeneous substrate that has a different lattice constant and thermal expansion coefficient from gallium nitride, such as sapphire, silicon, and silicon carbide, and then the heterogeneous substrate is removed. Is obtained.

  For example, Non-Patent Document 1 reports a method of growing gallium nitride on a sapphire substrate, which is a heterogeneous substrate, and then separating the sapphire substrate. This method irradiates a KrF pulse excimer laser from the sapphire substrate side, decomposes gallium nitride in contact with the sapphire substrate at the interface, and peels the sapphire substrate. In this method, a laser beam is irradiated to the interface between the sapphire substrate and gallium nitride, the laser beam is absorbed by gallium nitride, decomposed into metal gallium and nitrogen, and a gap is formed between sapphire. Is.

  Further, in Patent Document 1, a mask for selective growth partially covering the growth substrate is patterned, the constituent material of the mask is evaporated, and this is covered with the mask on the growth substrate. It forms “re-deposits” that are re-attached to the non-openings. Next, a semiconductor layer is formed by epitaxially growing the semiconductor film from the opening of the growth substrate to cover the mask. Finally, it is described that a gallium nitride single crystal substrate is obtained by adhering a supporting substrate on a semiconductor layer, removing a mask and a re-deposited material by wet etching, and peeling a growth substrate from the supporting substrate.

  Further, Patent Document 2 discloses a method of manufacturing a gallium nitride single crystal substrate using a HVPE (Hydride Vapor Phase Epitaxy) method. In this manufacturing method, a mask having a rectangular cross-sectional covering portion arranged in a stripe shape or a lattice shape and an opening portion formed between the covering portions is formed on a sapphire substrate. In this manufacturing method, after the pattern is formed, the gallium nitride layer is regrown from the opening, and the growth is stopped without covering the upper surface of the mask covering portion. Thereafter, the mask is removed by dry etching to form a space below the nitride semiconductor. Next, after a thicker gallium nitride layer is grown on the gallium nitride layer, the sapphire substrate is peeled off to obtain a gallium nitride single crystal substrate.

JP 2010-147163 A JP 2003-55097 A

W.S. Wong et al: Proceedings of the Symposium on LED for Optoelectronic Applications and 28th state of the Art Programs on Compound Semiconductors 98-2, 377 (1998).

  However, paragraph 0006 of Non-Patent Document 1 states that “when forming a single substrate of gallium nitride, sapphire breaks due to the gas pressure of nitrogen gas generated by decomposition of gallium nitride, and this crack causes contact with sapphire. Defects are generated on the gallium nitride surface. " When such a crack occurs, it is considered that the device manufacturing process becomes difficult, and the light emission characteristics of the optical device formed on the gallium nitride substrate and the characteristics deterioration of the electronic device are caused.

Further, paragraph 0049 of Patent Document 1 states that “the wet etching process selectively etches the SiO ₂ mask 20 and the SiO ₂ reattachment 23 interposed between the sapphire substrate 10 and the GaN film. When it disappears, the sapphire substrate 10 is peeled off. " However, in actuality, the SiO ₂ redeposits existing between the sapphire substrate and the gallium nitride layer are distributed in the form of dots, and it is difficult for the wet etching solution to completely erode between the layers. Further, in a region where no reattachment exists, the sapphire substrate and gallium nitride are directly bonded, and it is difficult to remove the substrate by wet etching. For this reason, the paragraph 0049 of Patent Document 1 also states that “a sapphire substrate can be easily peeled off by applying an external force such as a mechanical shock, a thermal shock, or an ultrasonic wave, even if peeling does not occur. ”.” This causes cracks and defects to be introduced into the gallium nitride single crystal substrate.

  Furthermore, the method described in Patent Document 2 causes irregularities on the gallium nitride single crystal surface side peeled from the sapphire substrate (as in Patent Document 1). This unevenness is caused by a difference in level between the mask and the opening, and cannot be avoided in principle. In other words, the method described in Patent Document 2 is basically a method on the premise that lapping is performed. Paragraph 0039 of Patent Document 2 states that “If the third nitride semiconductor 5 is 300 μm or more, lapping is performed. After the support substrate 1 is removed from the nitride semiconductor substrate by the above, while the grindstone and the substrate wafer are rotated, they are pressed against each other to grind the support substrate side of the nitride semiconductor substrate. Therefore, in the method described in Patent Document 2, it is clear that an extra back surface lapping step is necessary after the substrate is peeled off, and cracks and defects are introduced into the gallium nitride single crystal substrate during lapping as in Patent Document 1. Therefore, it is not easy to manufacture a device having a uniform performance using a substrate manufactured by this method.

  Accordingly, an object of the present invention is to provide an element part peeling method and a nitride semiconductor device capable of etching and peeling a single crystal substrate on which a buffer layer is deposited and an element part without applying mechanical stress. And

  In order to achieve the above object, one means of the present invention includes a single crystal substrate, a buffer layer deposited on the surface of the single crystal substrate, and a nitride semiconductor device structure layer laminated on the surface of the buffer layer. An element portion peeling method for peeling an element portion formed in the nitride semiconductor element structure layer from the nitride semiconductor device, wherein a mask pattern is formed in the region of the element portion on the surface of the buffer layer Laminating a nitride semiconductor element structure layer outside the element portion of the buffer layer and on the surface of the mask pattern; and the nitride from directly above the outer peripheral portion of the mask pattern to at least the outer peripheral portion. A step of forming a circumferential groove between the element portion and another nitride semiconductor element structure layer by dry-etching the semiconductor element structure layer; and Since the constant, the mask pattern is characterized in that it comprises the steps that are wet etched by using the circulation grooves.

  A nitride semiconductor device according to another means of the present invention includes a single crystal substrate, a buffer layer deposited on the surface of the single crystal substrate, a mask pattern provided on the surface of the buffer layer, and the mask pattern And a nitride semiconductor device structure layer covering the surface of the buffer layer exposed from the mask pattern, and the nitride semiconductor device structure layer is divided into an external region and an internal region of the mask pattern A circular groove is formed, and the internal region forms an element portion that can be peeled off from the single crystal substrate by wet etching the mask pattern.

According to these, since the element portion is formed in the interior region of the SiO ₂ mask pattern is peeled off by wet-etching the SiO ₂ mask pattern.

  According to the present invention, the single crystal substrate on which the buffer layer is deposited and the element portion can be etched and peeled without applying mechanical stress.

1 is a schematic cross-sectional view showing a peelable gallium nitride element structure according to a first embodiment of the present invention. It is process drawing which shows the preparation process until peeling the gallium nitride element by this invention. It is a photograph which shows the shape of a mask for experiment (mask) and a window (window). It is an enlarged photograph of a window. It is a graph which shows the relationship between the window width of gallium nitride, and the regrowth width. It is a graph which shows the relationship between the window width of gallium nitride, and the regrowth film thickness. It is a graph showing the SiO ₂ etching rate by hydrofluoric acid after high temperature annealing in an ammonia atmosphere according to the first embodiment. It is a graph which shows the SiN etching rate by the hydrofluoric acid after the high temperature annealing in ammonia atmosphere by this invention. It is sectional drawing which shows the element structure by 2nd Embodiment of this invention.

  Hereinafter, an embodiment of the present invention (hereinafter referred to as “the present embodiment”) will be described in detail with reference to the drawings. Each figure is only schematically shown so that the present invention can be fully understood. Therefore, the present invention is not limited to the illustrated example. Moreover, in each figure, the same code | symbol is attached | subjected about the common component and the same component, and those overlapping description is abbreviate | omitted.

(First embodiment)
The present invention relates to a nitride optical device, a nitride electronic device, and a manufacturing method thereof, which have been developed in view of the above-described problems and have a structure that can be easily peeled off from a growth substrate. Specifically, in selective regrowth of gallium nitride, after growing ELO (Epitaxial Lateral Overgrowth) on the mask region, device structures such as LEDs (Light Emitting Diodes) and transistors are formed by epitaxial growth, followed by photolithography. After patterning by (Photolithography), the gallium nitride is removed by dry etching at the edge of the mask pattern region to a certain depth to provide an opening. Thereafter, the support is fixed to the element portion with an adhesive, and finally the mask is removed by wet etching. By this method, a high-quality gallium nitride optical device or electronic device can be manufactured in a desired size. Of course, it is possible to easily arrange a plurality of devices as a module by sticking an element bonded to a support on an element installation substrate and peeling the support substrate side.

(Description of configuration)
FIG. 1 is a schematic cross-sectional view showing a peelable gallium nitride device structure according to a first embodiment of the present invention. The nitride semiconductor device 10 (10A) includes a single crystal substrate 1, a buffer layer 2 deposited on the entire surface of the single crystal substrate 1, and a rectangular shape provided on the opposite surface of the buffer layer 2 to the substrate. A SiO ₂ mask 3 as a mask pattern, an element structure portion 4a covering the buffer layer exposed from the SiO ₂ mask 3, and a recess of the element structure portion 4a formed on the surface of the SiO ₂ mask 3 An element 4b serving as the element part and a support 7 having the center of the element 4b bonded to each other by an adhesive 6 are provided.

  The element structure part 4a and the element 4b are, for example, a nitride semiconductor element structure layer in which an n-GaN layer, an MQW (Multi Quantum Well) layer and an uppermost clad layer (Mg-doped p-GaN layer) are deposited. The element 4b functions as a light emitting element. The MQW layer usually has a multiple quantum well structure including an InGaN well layer and a GaN or InGaN barrier layer.

The element 4b is partitioned by a dry etching region 5 (5a) as a circumferential groove provided at the end of the region directly above the SiO ₂ mask 3. That is, the circumferential groove portion is formed on the outer peripheral surface of the inner region by dividing the nitride semiconductor element structure layer into the outer region and the inner region of the SiO ₂ mask 3. In addition, the circumferential groove is exposed to the outside air and is exposed to hydrofluoric acid during wet etching described later.

  The configuration of the light emitting element is an example. For example, in the case of an electronic device, a UID (Un-Intentionally doped) -GaN layer and an AlGaN layer are grown instead of an n-GaN layer, an MQW layer and an upper clad layer thereof. The HEMT (High Electron Mobility Transistor) structure can be used.

(Production method)
FIG. 2 is a process diagram showing manufacturing steps until the gallium nitride device according to the present invention is peeled off. Hereafter, the manufacturing process of LED as embodiment of this invention is demonstrated. In the following, the present invention is applicable in principle, so that the regrown gallium nitride crystal has any mixed crystal / layer structure / impurity doping profile within the scope of the present invention.

First, the creator attaches the buffer layer 2 on the surface of an insulating sapphire single crystal substrate 1 (for example, a thickness of 330 μm is usually 2 inches) by MOCVD (Metal Organic Chemical Vapor Deposition) method or MBE (Molecular Beam Epitaxy). ) Method for epitaxial growth over the entire region of the substrate (FIG. 2 (S2)). The buffer layer 2 includes a GaN low-temperature buffer layer having a thickness of 50 nm and a GaN epitaxial layer having a thickness of 1000 nm. The growth of GaN uses TMG, TMA (TriMethyl Aluminum), TMI (TriMethyl Indium), and ammonia (NH ₃ ) as main raw materials. In particular, TMG (TriMethyl Gallium), which is a Ga raw material, is 88 μmol / min, The substrate temperature is 475 ° C. only for the GaN low-temperature buffer layer at a V / III ratio of 2500 and an atmospheric pressure atmosphere of 760 Torr, and the growth temperature of the GaN epitaxial layer thereon is usually 1100 ° C.

(SiO ₂ mask growth)
Next, the producer grows SiO ₂ as a mask material on the prepared single crystal substrate to a thickness of 100 nm by, for example, plasma CVD (FIG. 2 (S4)).
Further, the creator performs pattern formation by normal photolithography (FIG. 2 (S6)). The type of resist, developer, etching solution, etc. may be general-purpose. The size of the mask pattern depends on the size of the element to be manufactured. However, in consideration of a display device using LED elements, each dimension is set to 10 μm × 10 μm, for example, and a Si-GaN layer electrode is placed on the front side. In the case of contact (from the front side), if the electrode area is also 10 μm × 10 μm, the vertical direction is 10 μm and the horizontal direction (10 + 10) μm.

Next, the manufacturer re-grows (selectively grows) the element structure portion 4 that is a gallium nitride layer on the surface of the buffer layer 2 that has a pattern opening and serves as a window portion, using the SiO ₂ film as a mask ( FIG. 2 (S8). This element structure part 4 includes a non-doped GaN epitaxial layer, a Si-doped GaN epitaxial growth layer, an MQW part: In _0.2 Ga _0.8 N well layer, 5 pairs of GaN barrier layers, and Mg-doped Al _0.1 Ga as a cladding layer. It is composed of a _0.9 N layer, which is also an Mg-doped GaN layer.

FIG. 3A is a photograph showing the shapes of an experimental mask and a window, and FIG. 3B is an enlarged photograph of the window. 3A and 3B are images of a plane including a hexagonal <1-100> direction and a <11-20> direction. The window is deposited with SiO ₂ so as to leave the surface of GaN in a rectangular shape. The selective growth is carried out by MOCVD, and the conditions are TMG 88 μmol / min, V / III ratio 2500, reduced pressure atmosphere (50 Torr), growth time 2 min, and growth temperature 1070 ° C.

  Here, in the present method, the growth rate ratio between the vertical growth (outside the mask region) and the lateral growth (on the mask) of the GaN epitaxial layer becomes important. In the inventor's experiment, the growth rate ratio between the mask and the outside of the mask region (regrowth rate ratio) when the source material of Ga is TMG 88 μmol / min, V / III ratio 2500, reduced pressure atmosphere 50 Torr, and growth temperature 1070 ° C. 5.7 times that was obtained.

  FIG. 4A is a graph showing the relationship between the window width and the regrowth width of gallium nitride, and FIG. 4B is a graph showing the relationship between the window width and the regrowth height. The horizontal axis represents the window width [μm], and the vertical axis represents the regrowth width / the regrowth height [μm]. Each figure is measured in four types of series. The film obtained at this time had a pattern with a mask width of 20 μm with respect to an opening width (window width) of 2 μm and a regrowth width of 5 μm. The regrowth height was 0.2 μm on the mask and 0.3 μm from the regrowth start position. From these results, it was found that when a 10 μm square element region is desired, the growth time is 10 μm / {(5 μm-2 μm) / 2} × 2 min = 16.6 minutes.

Next, the maker provides an opening at the end of the mask pattern by patterning by photolithography, and SiO ₂ by ICP-RIE (Inductively Coupled Plasma Reactive Ion Etching) dry etching using boron trichloride (BCl ₃ ) gas or the like. Gallium nitride is removed until the surface of the mask 3 is reached. As a result, a dry etching region 5 (circular groove portion, circular recess portion) is formed, and the element 4b is formed as an isolation island (FIG. 2 (S10)). For example, when the back pressure is 2.5 mTorr, 20 nm is etched in 5 minutes.

Hereinafter, the wet etching of the SiO ₂ mask, which is important in the present embodiment, will be described.
FIG. 5 is a graph showing a SiO ₂ etching rate by hydrofluoric acid (hydrofluoric acid) after high-temperature annealing in an ammonia atmosphere according to the first embodiment. Specifically, the etching rate is shown when the SiO ₂ film grown on the sapphire substrate by plasma CVD and the film is annealed in an ammonia atmosphere at 1070 ° C. for 5 minutes and then wet etched with 50% hydrofluoric acid. . The vertical axis represents the film thickness average value [nm], and the horizontal axis represents the etching time [second].

An SiO ₂ film (indicated by “■” in FIG. 5) that has only been grown by plasma CVD has an etching rate of 120 nm in 26 seconds. This value is calculated to take 36 minutes to etch a 10 μm SiO ₂ film. However, the SiO ₂ film (indicated by “●” in FIG. 5) annealed at a high temperature in an ammonia atmosphere has a reduced etching rate, and it takes 2.5 hours to etch the 10 μm SiO ₂ film. Since the actual SiO ₂ mask 3 is used as a mask during gallium nitride regrowth, it includes a step of annealing in an ammonia atmosphere immediately before gallium nitride regrowth. For this reason, the wet etching of the SiO ₂ mask 3 requires several hours for 10 μm etching.

In other words, the SiO ₂ mask 3 is altered by annealing in an ammonia atmosphere, but since it has a thickness (100 nm), the degree of alteration differs between the surface on the buffer 2 side and the surface on the element 4b side. That is, the etching rate of the SiO ₂ mask 3 can be different between the surface on the buffer 2 side and the surface on the element 4b side.

Next, the manufacturer applies the adhesive 6 to the top of the element 4b (FIG. 2 (S12)), and fixes the element 4b to the support 7 (FIG. 2 (S14)). Finally, the manufacturer removes the SiO ₂ mask 3 using wet etching. Thereby, the element 4b fixed to the support body 7 is peeled from the growth single crystal substrate 1 (FIG. 2 (S16)), and the manufacturing process of the gallium nitride element is completed. Since the element 4 b is fixed to the support 7, it is peeled off from the single crystal substrate 1 without receiving mechanical stress.

Since there is an example in which a silicon nitride film (Si _x N _y ) is used in the regrowth technique, an experiment was conducted to obtain the same knowledge about Si _x N _y . FIG. 6 is a graph showing an Si _x N _y film grown on a sapphire substrate by plasma CVD, and an etching rate when the film is annealed in an ammonia atmosphere at 1070 ° C. for 5 minutes and then wet etched with 50% hydrofluoric acid. It is. The vertical axis represents the film thickness average value [nm], and the horizontal axis represents the etching time [second].

The Si _x N _y film only grown by plasma CVD has an etching rate of 100 nm in 75 seconds. This is a calculation that takes 125 minutes to etch a 10 μm Si _x N _y film. However, the Si _x N _y film annealed at a high temperature in an ammonia atmosphere has an extremely low etching rate, and it takes 833 hours (about 35 days) to etch the 10 μm Si _x N _y film. Since the Si _x N _y film is used as a mask during gallium nitride growth, the Si _x N _y film includes a step of annealing in an ammonia atmosphere immediately before regrowth of gallium nitride. Therefore, it can be seen that the wet etching of the SiN mask cannot be used in the actual manufacturing / mass production process. Patent Documents 1 and 2 describe that this Si _x N _y film is used as a mask material because it is assumed that the entire substrate is peeled off at once. Thus, it is difficult to apply to a single device.

(Second Embodiment)
FIG. 7 is a cross-sectional view showing the device structure of the second embodiment according to the present invention.
A single crystal substrate 1, a buffer layer 2 deposited on the entire surface of the single crystal substrate 1, a rectangular SiO ₂ mask 3 provided on the opposite surface of the buffer layer 2, and a SiO ₂ mask 3 The device structure portion covering the surface and the surface of the buffer layer 2 exposed from the SiO ₂ mask 3 (for example, the n-GaN layer, the MQW layer, and the uppermost cladding layer, and the region immediately above the SiO ₂ mask pattern) 1 has the same structure as FIG. 1. Further, the portion where the center of the element 4b is joined to the support 7 by the adhesive 6 has the same structure as that of FIG.

The difference is that in the fabrication of the circumferential groove (dry etching region 5) by dry etching, following the step of cutting gallium nitride until reaching the SiO ₂ mask 3 by ICP-RIE dry etching using BCl ₃ gas or the like, SF ₆ (Sulfa hexafluoride) SiO ₂ used as a mask by dry etching with gas or the like (the outer peripheral portion of the SiO ₂ mask 3) is removed, and a groove is dug to a part of the buffer layer 2 on the surface of the single crystal substrate 1 It is a point. That is, circumferential grooves, the nitride semiconductor device structure layer (4a, 4b) but the is to divide the outer region and the inner region of the SiO ₂ mask 3, is formed on the outer peripheral side surface of the SiO ₂ mask 3.

According to this structure, when wet etching is performed on the SiO ₂ mask, the wet etching solution is eroded from the lateral direction (perpendicular to the substrate surface). This portion is a portion not exposed to an ammonia atmosphere in gallium nitride regrowth, and an increase in the etching rate due to wet etching can be expected.

(Modification)
The present invention is not limited to the embodiments described above, and various modifications such as the following are possible.
(1) In each of the above embodiments, a gallium nitride LED or HEMT has been mainly described as a device. However, the present invention is not limited to this, but an LD (Laser Diode) or MESFET (Metal Semiconductor Field Effect Transistor). It can also be applied to a JFET (Junction Field Effect Transistor) having a pn junction in the gate region. For example, when the Al composition is 0.3 or more as the AlGaN barrier layer, the process of the present invention can also be applied to a HEMT having a MIS (Metal Insulator Semiconductor) structure having an insulating gate such as an AlN layer. Further, as a specific application of the semiconductor optical / electronic device according to the present invention, it is useful for a display, a backlight, a high-power switching element for electric power or a high-power high-frequency element for which high breakdown voltage characteristics are required.
(2) Although the sapphire substrate is used as the single crystal substrate in the embodiment, a (111) Si substrate or a SiC substrate can also be used. In the above embodiment, as a mask pattern, using the SiO _2, it has been tried silicon nitride film, may be used TiO, and ZrO.

Single crystal substrate 2 buffer layer 3 SiO ₂ mask 4,4a element structure 4b element (element)
5a, 5b Dry etching region (circular groove)
6 Adhesive 7 Support 10, 10A, 10B Nitride Semiconductor Device

Claims (8)

From a nitride semiconductor device comprising a single crystal substrate, a buffer layer deposited on the surface of the single crystal substrate, and a nitride semiconductor element structure layer stacked on the surface of the buffer layer to the nitride semiconductor element structure layer An element part peeling method for peeling the formed element part,
Forming a mask pattern in the region of the element portion on the surface of the buffer layer;
A step of laminating a nitride semiconductor element structure layer outside a region of the element portion of the buffer layer and on a surface of the mask pattern;
The nitride semiconductor device structural layer is dry-etched from immediately above the outer peripheral portion of the mask pattern to at least the outer peripheral portion, thereby forming a circumferential groove portion between the element portion and another nitride semiconductor device structural layer. And steps
And a step of wet etching the mask pattern using the circumferential groove after the element is fixed to a support. The element part peeling method according to claim 1,
The element part peeling method, wherein the dry etching is performed until the surface of the mask pattern is reached. The element part peeling method according to claim 1,
The element etching method according to claim 1, wherein the dry etching is to form the circumferential groove portion including the outer peripheral portion and a part of the buffer layer. The element part peeling method according to any one of claims 1 to 3,
The step of laminating the nitride semiconductor element structure layer includes a step of annealing in an ammonia atmosphere immediately before the lamination. Covering the single crystal substrate, the buffer layer deposited on the surface of the single crystal substrate, the mask pattern provided on the surface of the buffer layer, the surface of the mask pattern and the surface of the buffer layer exposed from the mask pattern A nitride semiconductor device structural layer,
The nitride semiconductor element structure layer is formed with a circumferential groove portion that is divided into an outer region and an inner region of the mask pattern,
In the nitride semiconductor device, the internal region forms an element portion that can be peeled off from the single crystal substrate by wet etching the mask pattern. The nitride semiconductor device according to claim 5,
The nitride semiconductor device, wherein the mask pattern is made of SiO ₂ . The nitride semiconductor device according to claim 6,
The mask pattern is altered in surface by high temperature annealing in an ammonia atmosphere,
The nitride semiconductor device, wherein the alteration state is different between the surface and the surface on the buffer layer side. The nitride semiconductor device according to any one of claims 5 to 7,
The element part is laminated in order of an n-GaN layer, an MQW layer, and a p-GaN layer.