JP2015056088A - Semiconductor device, electronic device, and error notification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To notify software of abnormality that occurs due to an access during circuit operation so that a developer can notice a setting error.SOLUTION: A semiconductor device that transmits a predetermined response to an access from external control means, includes: two or more setting means made to correspond to respective designated addresses each designating an access destination from the external control means; control means controlling the setting means corresponding to the designated address from the external control means on the basis of the access from the external control means by the designated address; and interrupt signal notification means notifying the external control means of an interrupt signal if the control means exerts a starting control over one of the two or more setting means and the external control means accesses the semiconductor device by the designated address corresponding to the other setting means for which the control is limited, out of the two or more setting means.

Description

  The present invention relates to a semiconductor device, an electronic apparatus, and an error notification method.

  In an integrated circuit such as an ASIC (Application Specific Integrated Circuit), it is already known that the setting of a circuit can be changed by performing register access via a CPU (Central Processing Unit).

  In Patent Document 1, the violation detection unit 230 sets an accessible area of an execution program based on an address map for the purpose of preventing inadequate setting due to software malfunction and detecting all violation memory accesses. A violation memory access detection device that identifies and inputs an access signal from the signal line to the memory 120 to identify an access area, and the violation detection unit 230 detects violation access by comparing the access area and the accessible area. Has been.

  Here, in the conventional circuit as in the violating memory access device described in Patent Document 1, if register access is performed at a timing when the register access should not be performed, such as during circuit operation, an abnormal operation occurs. End up.

  Here, the timing at which register access should not be performed is, for example, when the circuit setting is a multi-thread including a thread for starting a circuit and a thread for setting a parameter in the circuit, and the thread for starting the circuit indicates the start timing. An error or a case where activation is performed at the timing when a parameter is set.

  The circuit is designed on the condition that its parameters remain unchanged during circuit operation. For this reason, when register access is performed during operation, such as during circuit operation, the parameters change and an unexpected operation of the designer occurs.

  However, since there is no means for notifying the software developer of the abnormal operation described above, there is a problem in that the software developer is delayed in noticing the incorrect setting of circuit control by software.

  The incorrect setting of circuit control by software is confirmed by the developer by performing a register dump and looking at the parameters after abnormal operation occurs. However, the parameters may appear to be set correctly. In this case, the software developer recognizes the problem on the hardware side, and requests the hardware developer to perform analysis.

  On the other hand, the hardware developer cannot reproduce the problem, and eventually the software developer analyzes the cause again, which takes extra man-hours to analyze the misconfiguration. As a result, the developer is delayed in noticing the incorrect setting of the circuit control by software.

  The present invention has been made in view of such circumstances, and an object thereof is to notify a software side of an abnormality that has occurred due to an access during circuit operation, and to make a developer aware of an erroneous setting.

  In order to solve the above-described problems, the semiconductor device of the present invention is a semiconductor device that returns a predetermined response to access from the external control unit, and corresponds to each designated address that specifies the access destination from the external control unit. Two or more attached setting means, a control means for controlling activation of the setting means corresponding to the designated address based on access by the designated address from the external control means, and one setting of the two or more setting means by the control means In the case where the means is controlled to start, when there is an access from the external control means by the designated address corresponding to the other setting means whose control is restricted among the two or more setting means, the external control means And interrupt signal notification means for notifying the interrupt signal.

  According to the present invention, it is possible to notify a software side of an abnormality that has occurred due to an access during circuit operation, and to make a developer aware of an erroneous setting.

It is a schematic diagram which shows the debugging environment of the main board mounted with ASIC in embodiment of this invention. It is an example of the error message output to the test terminal in the embodiment of the present invention. It is a schematic block diagram of the main board in embodiment of this invention. It is the schematic which shows the internal structure of ASIC in embodiment of this invention. It is the schematic which shows the internal structure of the module in embodiment of this invention. It is the schematic which shows the internal structure of the decoder in embodiment of this invention.

  A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to this embodiment unless it exceeds the gist of the present invention. In addition, in each figure, the same code | symbol is attached | subjected to the part which is the same or it corresponds, The duplication description is simplified thru | or abbreviate | omitted suitably. In the present embodiment, an ASIC is described as a semiconductor device, but any integrated circuit that can be applied to equivalent applications may be used.

  In general, the semiconductor device according to the present embodiment transmits a signal indicating the activation state of a module that has an influence on the operation by the address setting designated by the access when the register is accessed from the CPU. Thereby, it is determined whether the register access is an access that violates the timing, and the result is notified as an interrupt signal.

  FIG. 1 shows a debug environment configuration of a main board on which an ASIC is mounted as an electronic device in the present embodiment. The test terminal 100 is connected to the main board 1 via the serial I / F 50. “Terminal software” installed in the test terminal 100 confirms a debug message output from the main board 1 or sends an instruction to the main board 1.

  Next, an example of an error message displayed on the screen of the test terminal 100 by the “terminal software” will be briefly described with reference to FIG. Here, for example, an error message when the parameter setting timing is wrong is displayed as follows. With this message, it is possible to confirm at which address the register write access is a problem.

[Example of error message]
*** ERROR INT DETECTED ***
PARAM SETTING IN EXECUTE
ADDR = 0X1234

  Next, a schematic configuration of the main board 1 on which the ASIC of this embodiment is mounted will be described with reference to FIG. The main board 1 of this embodiment is generally composed of a CPU 11 as an external control means, a memory 12, and an ASIC 13. Further, the test terminal 100 and the peripheral device 200 are connected to the ASIC 13 via a predetermined interface.

  The ASIC 13 is controlled by the CPU 11 via the CPU I / F. The ASIC 13 returns a predetermined response to access from the CPU 11 via the CP UI / F, and returns an interrupt signal via an interrupt signal line INT described later. Details of the ASIC 13 will be described later.

  The memory 12 includes a nonvolatile memory such as a ROM (Read On Memory), and a volatile memory such as a RAM (Random Access Memory). The ROM stores a program processed by the CPU 11, and the RAM functions as a work memory for executing the program.

  The ASIC 13 is provided with a plurality of interfaces for connection to the outside of the main board 1 and is connected to an interface connector provided on the main board. The serial connector on the main board 1 and the ASIC 13 are connected, and the serial port of the test terminal 100 and the main board 1 are connected to the serial connector via a serial I / F.

  Further, the CPU 11 and the ASIC 13 are connected via an interrupt signal line INT, and an interrupt signal described later is notified from the ASIC 13 to the CPU 11 via the interrupt signal line INT, whereby a setting error notification is notified to the CPU 11. .

  Next, the internal configuration of the ASIC 13 as the semiconductor device of the present embodiment will be described with reference to FIG. It is assumed that the CPU 11 can access an internal register for each module described later.

  In order to access the internal register, the CPU 11 is connected to the ASIC 13 via the CPU I / F. The access sent from the CPU 11 is converted into internal bus specification data by the module CPU 131, and the converted access data is transmitted to each module via the bus 135.

  In the present embodiment, for example, each module provided with the module 132, the module 133, and the module 134 via the bus 135 transmits an interrupt signal to the outside of the ASIC 13 via the interrupt signal line INT described above. Hereinafter, the present embodiment will be described focusing on the module 132.

  Next, the internal configuration of the module according to this embodiment, for example, the module 132 will be described with reference to FIG. The module 132 includes, for example, a decoder 1321 and an internal module 1322. The decoder 1321 decodes CPU access from the CPU 11 via the bus 135. The internal module 1322 performs various processes based on parameters stored in a register described later.

  The decoder 1321 stores the result of decoding the CPU access in a later-described register using a flip-flop. Further, the decoder 1321 passes the parameter value stored in the register to the internal module 1322.

  Here, for example, as access data exchanged with the CPU 11, a signal in “OCP (Open Core Protocol)” is illustrated in the present embodiment. OCP is an on-chip bus standard that does not depend on a specific CPU or bus protocol.

  For example, in FIG. 5, signals such as “MCmd”, “MAddr”, “MData”, “SResp”, and “SData” are exchanged between the CPU 11 and the decoder 1321.

  “MCmd” is a signal indicating the type of command from the CPU 11, “MAddr” is a signal indicating the address of the command, and “MData” is a signal indicating data corresponding to the command. Note that “M” added as an initial of each signal means that when the CPU 11 side is a master and the decoder 1321 side is a slave, a signal is sent from the master to the slave.

  “MCmd” includes “register read” for reading data stored in a register, and “register write” for writing data to a register or rewriting data stored in a register. Further, as “MCmd”, there is “register idle” which sets the register in an idle state.

  Further, “SResp” is a signal returned from the decoder 1321 side to the CPU 11 side, and is a signal for returning the result for the above “MCmd” to the CPU 11 side. “SData” is a signal returned from the decoder 1321 side to the CPU 11 side when the above “MCmd” is a read command to be described later. Note that “S” added as an initial of each signal means that a signal is sent from the slave to the master.

  On the other hand, “parameter E” and “parameter F” illustrated in FIG. 5 are parameters passed from the decoder 1321 to the internal module 1322. As described above, these parameters are parameters stored in the register as a result of decoding the CPU access. “EXEC” is a level signal output from a register control unit 13211 described later and held in, for example, a register 13213 described later.

  Next, the internal configuration of the decoder 1321, which is a feature of the present embodiment, will be described with reference to FIG. The decoder 1321 of this embodiment is generally composed of a register control unit 13211 as a control unit, an interrupt signal notification unit 13212, a register 13213, a register 13214, and a register 13215 as setting units. The register control means 13211 includes parameter rewriting means 13211p.

  The two or more registers described above are associated with each designated address that designates an access destination from the CPU 11 such as “MAddr” described above.

  The register control unit 13211 outputs “EXEC” held in the register 13213 as the level signal described above, thereby controlling the activation of the register corresponding to the designated address based on the access by the designated address from the CPU 11.

  The parameter rewriting means 13211p rewrites parameters set for each of the two or more registers in order to control the activation of the two or more registers. In the present embodiment, these parameters are “parameter E” and “parameter F” as described above, for example.

  Further, in the present embodiment, “parameter E” and “parameter F” are parameters for starting up the register 13214 and the register 13215, for which control is restricted at the time of write access from the CPU 11, for example.

  The interrupt signal notification unit 13212 corresponds to another register whose control is restricted among the two or more registers when the register control unit 13211 controls the activation of one of the two or more registers. When there is an access from the CPU 11 by the designated address, an interrupt signal is notified to the CPU 11.

  In this embodiment, the “one register” is described as the register 13213, and the “other register” is described as the register 13214 and the register 13215. However, the “one register” and the “other register” are It is expressed for the sake of convenience and is not described with the intention of limiting it to a specific register.

  The interrupt signal notifying unit 13212 determines that one register is in an activated state based on the level signal when the activation of the one register is controlled by the level signal output from the register control unit 13211. For example, the interrupt signal notifying unit 13212 determines that the register 13213 is in the activated state based on the level signal “EXEC” described above.

  The interrupt signal notification means 13212 monitors signals such as “MClk”, “MCmd”, and “MAddr” when the decoder 1121 is accessed from the CPU 11, and the register 13213 is activated by the level signal “EXEC”, for example. If it is determined that, the CPU 11 is notified of an interrupt signal.

  More specifically, the interrupt signal notifying means 13212 asserts an interrupt signal when “EXEC” is asserted and there is a write access to a register whose control is restricted while the register 13213 is activated. By doing so, the outside of the decoder is notified that the prohibition setting has been made. As a result, the abnormality that has occurred due to the register access during the circuit operation is notified, so that the developer can notice the erroneous setting. This processing logic is shown below as a pseudo conditional expression.

while (1) begin
if ((MCmd = "Write Access") && (MAddr == Setting prohibited area during startup)) then
INT_mod_a = 1;
end
end

  In this embodiment, for example, when only the register 13213 is activated, an interrupt signal is notified when another register is accessed, but at least two registers are activated. Alternatively, an interrupt signal may be notified.

  In this embodiment, for example, when the register 13213 is in the activated state, an interrupt signal is notified when the register 13214 or the register 13215 is accessed. However, an access invalidation unit may be provided separately. . For example, when the register 13213 is in the activated state, when the register 13214 or the register 13215 is accessed, these accesses are invalidated by the access invalidation means. As a result, the developer can recognize the register setting error.

  In the present embodiment, only the CPU 11 is notified of the interrupt notification by the interrupt signal notification means 13212. However, when two or more CPUs are connected via the bus 135, the interrupt is notified. It is good also as a notification destination CPU selection means which selects which CPU of two or more CPUs an interrupt signal is notified by the signal notification means 13212.

  Further, the interrupt notification means 13212 notifies the interrupt signal as a plurality of interrupt signals for each semantic word extracted from a designated address corresponding to another register whose control is restricted among two or more registers. Also good.

  Each of the above-described embodiments is a preferred embodiment of the present invention, and various modifications can be made without departing from the scope of the present invention. For example, it is possible to execute the control operation in each unit constituting the information processing apparatus of the present embodiment described above using hardware, software, or a combined configuration of both.

  In the case of executing processing using software, it is possible to install and execute a program in which a processing sequence is recorded in a memory in a computer incorporated in dedicated hardware. Alternatively, the program can be installed and executed on a general-purpose computer capable of executing various processes.

1 Main board 11 CPU
12 Memory 13 ASIC
50 Serial I / F
100 test terminal 131 module CPU
132, 133, 134 Module 135 Bus 1321 Decoder 1322 Internal module 13211 Register control means 13211p Parameter rewriting means 13212 Interrupt signal notification means 13213, 13214, 13215 Register

JP 2012-003540 A

Claims (9)

A semiconductor device that returns a predetermined response to access from an external control means,
Two or more setting means associated with each designated address for designating an access destination from the external control means;
Control means for controlling activation of setting means corresponding to the designated address based on access by the designated address from the external control means;
When one of the two or more setting means is controlled to be activated by the control means, the designated address corresponding to another setting means of which the control is restricted among the two or more setting means. When there is an access from the external control means, an interrupt signal notification means for notifying the external control means of an interrupt signal;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the control means comprises parameter rewriting means for rewriting a parameter set for each of the two or more setting means in order to control activation of the two or more setting means.   The interrupt signal notifying unit determines that the one setting unit is in an activated state based on the level signal when the one setting unit is activated by the level signal output from the control unit. The semiconductor device according to claim 2.   The interrupt signal is notified as a plurality of interrupt signals for each semantic word extracted from a designated address corresponding to another setting means whose control is restricted among the two or more setting means. 4. The semiconductor device according to any one of 1 to 3.   The interrupt signal notifying means is a case where at least two setting means of the two or more setting means are controlled to be activated, and the other setting means for which control is restricted among the two or more setting means. 5. The semiconductor device according to claim 1, wherein an interrupt signal is notified to the external control means when there is an access from the external control means with a corresponding designated address. .   When one of the two or more setting means is controlled to be activated by the control means, the designated address corresponding to another setting means of which the control is restricted among the two or more setting means. 6. The semiconductor device according to claim 1, further comprising an access invalidating unit that invalidates an access from the external control unit when accessed from the external control unit. When two or more external control means are connected via a bus,
7. A notification destination external control means selecting means for selecting which of the two or more external control means is to be notified of an interrupt signal by the interrupt signal notifying means. The semiconductor device according to any one of the above. A semiconductor device according to any one of claims 1 to 7,
External control means for performing external control means access to the semiconductor device;
An electronic device comprising: An error notification method for returning a predetermined response to the external control means for an access from an external control means to a semiconductor device having two or more setting means,
Controlling the operation of the two or more setting means associated with each designated address for designating an access destination from the external control means based on an access from the external control means;
When one of the two or more setting means is controlled to be activated, the external control means is designated by a designated address corresponding to another setting means of which control is restricted among the two or more setting means. A step of notifying the external control means of an interrupt signal when accessed from
An error notification method comprising:

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