JP2015050648A - Backflow prevention switch and power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a backflow prevention switch that allows an LDO to output an output voltage approximating a supply voltage Vdd, while preventing a backflow current flowing from an LDO output terminal side to a Vdd terminal side.SOLUTION: The backflow prevention switch for preventing a current backflow from a first terminal to a second terminal includes: a MOS transistor having a source and a back gate connected to the first terminal and a drain connected to the second terminal; and a constant voltage source circuit for bringing the source of the MOS transistor to a high potential side and the gate of the MOS transistor to a low potential side. A power supply device using the switch is also provided.

Description

  The present invention relates to a backflow prevention switch and a power supply device including the backflow prevention switch.

  A series regulator is known as a power supply device that uses a battery or the like as a power source and supplies a constant voltage to electronic equipment with low noise. In particular, a low dropout regulator (LDO) that can operate even when the voltage between the input and output of a transistor serving as a current path is low is used in a wide range.

  The LDO has an input terminal connected to the power supply terminal, inputs the power supply voltage Vdd, and outputs a constant output voltage from the output terminal. The LDO has a PMOS transistor, and has an input terminal connected to the source terminal of the PMOS transistor, an output terminal connected to the drain terminal, and a source terminal and a back gate terminal connected in common. Further, the PMOS transistor has a parasitic diode having a drain terminal as an anode and a back gate terminal as a cathode.

  Here, when the power supply voltage Vdd input to the LDO sharply decreases and the potential of the output terminal of the LDO becomes higher than the potential of the input terminal, the output terminal of the LDO is changed from the output terminal to the input terminal via the parasitic diode of the PMOS transistor. A reverse current flows.

  In order to prevent a backflow current, a method of connecting a backflow prevention switch between an LDO and a power supply terminal is known (for example, Patent Document 1). FIG. 5 shows a conventional power supply device 100 including the LDO 10 and the backflow prevention switch 20.

  The backflow prevention switch 20 inputs the power supply voltage Vdd from the power supply terminal to the input terminal 22 and supplies the output voltage from the output terminal 24 to the LDO 10. The backflow prevention switch 20 includes a PMOS transistor MP1. The PMOS transistor MP1 has a drain terminal connected to the input terminal 22, a source terminal connected to the output terminal 24, a source terminal and a back gate terminal connected in common, and a voltage obtained by dividing the power supply voltage Vdd at the gate terminal. . The PMOS transistor MP1 has a parasitic diode D1 having a drain terminal as an anode and a back gate terminal as a cathode.

The backflow prevention switch 20 turns off the PMOS transistor MP1 when the power supply voltage Vdd drops sharply, and the parasitic diode D1 and the cathode of the parasitic diode D2 of the LDO 10 are connected to each other. Prevents backflow current flowing from the terminal to the Vdd terminal.
[Patent Document 1] JP 2006-157937 A

  However, according to the power supply device 100, the gate-source voltage VGS of the PMOS transistor MP1 of the backflow prevention switch 20 is proportional to the power supply voltage Vdd. Therefore, when the power supply voltage Vdd decreases, the on-resistance of the PMOS transistor MP1 increases, thereby preventing backflow. The voltage drop at the switch 20 increases. Therefore, according to the power supply apparatus 100, it is necessary to make the output voltage of the LDO 10 sufficiently smaller than the voltage range used for the power supply voltage Vdd.

  In view of such circumstances, the present invention has an object to provide a backflow prevention switch that outputs an output voltage close to the power supply voltage Vdd from the LDO while preventing a backflow current flowing from the LDO output terminal side to the Vdd terminal side. To do.

  According to a first aspect of the present invention, there is provided a backflow prevention switch for preventing a backflow of current from a first terminal to a second terminal, wherein a source and a back gate are connected to the first terminal, and a drain is provided to the second terminal. Provided are a backflow prevention switch including a connected MOS transistor, a constant voltage source circuit in which the source of the MOS transistor is on the high potential side and the gate of the MOS transistor is on the low potential side, and a power supply device using the same.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

The structure of the power supply device 1 in this embodiment is shown. A more specific configuration of the constant voltage source circuit 36 according to FIG. 1 is shown. The relationship between the power supply voltage in this embodiment and the gate-source voltage of MOS transistor MP1 is shown. The structure of the power supply device 2 in the modification of this embodiment is shown. The structure of the conventional power supply device 100 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a configuration of a power supply device 1 in the present embodiment. The power supply device 1 receives a power supply voltage Vdd from a power supply terminal and outputs a low noise output voltage from a regulator output terminal. The power supply device 1 includes a regulator 12 and a backflow prevention switch 30.

  The regulator 12 inputs the output voltage from the backflow prevention switch 30 from the input terminal IN as a power supply voltage, and outputs the stabilized output voltage from the output terminal OUT to an external electronic device. The regulator 12 may be an LDO as an example, and includes a MOS transistor MP2, a MOS transistor MP3, a voltage dividing resistor 102, a voltage dividing resistor 104, a reference power supply 106, an operational amplifier 108, and an inverting circuit 110.

  The MOS transistor MP2 may be a PMOS transistor and controls the output voltage of the regulator 12. In the MOS transistor MP2, the source is connected to the input terminal IN of the regulator 12 through a common connection with the back gate, and the drain is connected to the output terminal OUT. Here, the PMOS transistor has a parasitic diode D2 having a drain as an anode and a back gate as a cathode.

  The MOS transistor MP3 may be a PMOS transistor and controls on / off of the MOS transistor MP2. The MOS transistor MP3 has a gate connected to the output side of the inverting circuit 110, a source connected to the input terminal IN of the regulator 12 and the source of the MOS transistor MP2, and a drain connected to the gate of the MOS transistor MP3 and the operational amplifier 108. For example, the MOS transistor MP3 is turned on when a negative voltage logical value L signal is input to the gate, and is turned off when a positive voltage logical value H signal is input.

  One end of the voltage dividing resistor 102 is connected to the drain of the MOS transistor MP2, and the other end is connected to the voltage dividing resistor 104 and the + terminal of the operational amplifier 108. One end of the voltage dividing resistor 104 is connected to the voltage dividing resistor 102 and the + terminal of the operational amplifier 108, and the other end is connected to the ground potential. The voltage dividing resistor 102 and the voltage dividing resistor 104 drop the output voltage from the drain of the MOS transistor MP2 at a constant rate according to the resistance ratio, and input the voltage to the + terminal of the operational amplifier 108.

  The reference power source 106 is connected to the ground potential and the negative terminal of the operational amplifier 108, and supplies the reference potential Vref to the operational amplifier 108.

  The operational amplifier 108 inputs, to the gate of the MOS transistor MP2, a voltage obtained by amplifying the difference between the input voltage from the voltage dividing resistor 102 input to the + terminal and the input voltage input from the reference power supply 106 to the-terminal. As a result, the operational amplifier 108 reduces the fluctuation in the output voltage of the regulator 12 output from the drain of the MOS transistor MP2, controls the on / off of the MOS transistor MP2 so as to approach the voltage value of the reference power supply 106, and outputs the output of the regulator 12 The output voltage from the terminal OUT is stabilized.

  The inverting circuit 110 receives a power-down signal having a positive voltage logic value H from the backflow prevention switch 30 via the PD terminal, and inverts the voltage polarity of the power-down signal to generate a MOS signal as a signal having a negative voltage logic value L. Output to the gate of the transistor MP3.

  The backflow prevention switch 30 is disposed in series between the power supply terminal and the input terminal IN of the regulator 12. The backflow prevention switch 30 has the second terminal 34 on the input side connected to the power supply terminal to input the power supply voltage Vdd, the first terminal 32 on the output side connected to the regulator 12, and outputs the output voltage to the regulator 12. The backflow of current from the first terminal 32 to the second terminal 34 is prevented. The backflow prevention switch 30 includes a MOS transistor MP1 and a constant voltage power supply circuit 36.

  The MOS transistor MP1 may be a PMOS transistor and controls the output voltage of the backflow prevention switch 30. In the MOS transistor MP1, the source and back gate are connected to the first terminal 32 and the positive terminal of the constant voltage source circuit 36, the drain is connected to the second terminal 34, and the gate is connected to the negative terminal of the constant voltage source circuit 36. Connected.

  The constant voltage source circuit 36 is connected between the source and gate of the MOS transistor MP1, and supplies a constant voltage between the gate and source of the MOS transistor MP1 so that the source is on the high potential side and the gate is on the low potential side. . Here, the constant voltage source circuit 36 may provide the MOS transistor MP1 with an output voltage that does not exceed the gate-source breakdown voltage of the MOS transistor MP1.

  The constant voltage source circuit 36 compares the power supply voltage Vdd from the power supply terminal with the output voltage at the output terminal OUT of the regulator 12, and when the power supply voltage Vdd becomes lower than the output voltage of the regulator 12, the constant voltage source circuit 36 supplies the MOS transistor MP1. The voltage output is stopped and a power down signal is supplied to the PD terminal of the regulator 12. As a result, the inverting circuit 110 turns on the MOS transistor MP3, the source-gate voltage of the MOS transistor MP2 becomes 0, and thereby the MOS transistor MP2 turns off. Thus, when the power down signal is input to the PD terminal of the regulator 12, the output of the regulator is stopped. A specific configuration of the constant voltage source circuit 36 will be described later.

  Thus, the power supply device 1 of the present invention controls the MOS transistor MP1 of the backflow prevention switch 30 by the output voltage of the constant voltage source circuit 36 that does not depend on the power supply voltage Vdd. As a result, when the power supply voltage Vdd decreases, the gate-source voltage of the MOS transistor MP1 does not decrease in proportion to the power supply voltage Vdd, and the on-resistance of the MOS transistor MP1 can be prevented from increasing. As a result, the power supply device 1 can output an output voltage closer to the power supply voltage Vdd from the LDO 10.

  FIG. 2 shows a more specific configuration of the constant voltage source circuit 36 shown in FIG. The constant voltage source circuit 36 includes a comparator 302, an inverting circuit 304, a voltage generation unit 310, a current mirror circuit 320, a band gap circuit 322, a first switch SW1, and a second switch SW2.

  The comparator 302 has a power supply terminal and a regulator output terminal connected to the input terminal side, inputs and compares the power supply voltage Vdd and the output voltage from the regulator 12, and indicates that when the power supply voltage Vdd is higher than the regulator output terminal. The comparison result signal is output.

  When the power supply voltage Vdd is larger than the output voltage from the regulator 12, the comparator 302 outputs a signal indicating that (for example, a logical value H), and when the power supply voltage Vdd is smaller than the output voltage from the regulator 12. Outputs a signal indicating that (for example, logical value L). The comparator 302 outputs a comparison result signal (for example, a logical value H or a logical value L) to the inverting circuit 304. Further, the comparator 302 outputs a comparison result signal to the second switch SW2, and controls the opening and closing of the second switch SW2.

  The inverting circuit 304 receives the signal from the comparator 302, inverts the voltage polarity of the signal, and outputs it to the regulator 12. Further, the inverting circuit 304 outputs a signal in which the voltage polarity is inverted to the first switch SW1, and controls opening and closing of the first switch SW1.

  The voltage generator 310 is connected between the first terminal 32 and the gate of the MOS transistor MP1, and generates a voltage between the gate and the source of the MOS transistor MP1. The voltage generation unit 310 includes a diode 312 and a resistor 314 connected in series between the first terminal and the gate and source of the MOS transistor MP1.

  The diode 312 has an anode connected to the source side of the MOS transistor MP1 and a cathode connected to the resistor 314 side. The diode 312 supplies a current supplied from the source of the MOS transistor MP1 to the resistor 314.

  The resistor 314 is connected in series between the diode 312 and the gate of the MOS transistor MP1. The resistor 314 is connected to the first switch SW1 and the second switch SW2 on the gate side of the MOS transistor MP1. Here, the voltage generator 310 generates a potential difference equal to the sum of the forward voltage drop of the diode 312 and the potential difference caused by the current flowing through the resistor 314 between the gate and source of the MOS transistor MP1. A resistor having a small resistance temperature coefficient may be used as the resistor 314.

  The current mirror circuit 320 functions as a constant current source for the voltage generator 310. The current mirror circuit 320 generates a constant current corresponding to the constant voltage supplied from the band gap circuit 322 via the first switch SW1, and supplies the generated constant current to the voltage generation unit 310.

  The band gap circuit 322 generates a constant voltage without depending on the power supply voltage Vdd, and supplies the constant current to the current mirror circuit 320. A diode and a resistor used in the band gap circuit 322 may have characteristics similar to those of the diode 312 and the resistor 314. Since the current mirror circuit 320 and the band gap circuit 322 are conventionally known techniques, a detailed description of the configuration is omitted.

  One end of the first switch SW1 is connected to the current mirror circuit 320, the other end is connected to the gate of the MOS transistor MP1, the resistor 314, and the second switch SW2, and is exclusive of the second switch SW2 by the output of the inverting circuit 304. Thus, the open / close is controlled to short-circuit or open the voltage generator 310 and the current mirror circuit 320 as a current source. The first switch SW1 may be a semiconductor switch. When a positive voltage signal (for example, logic value H) is applied to the gate, the first switch SW1 is opened to cut off the current between the source and the drain, and the negative voltage signal. By applying (for example, logical value L), the switch is closed and a current between the source and the drain flows.

  The second switch SW2 has one end connected to the source of the MOS transistor MP1 and the first terminal 32, the other end connected to the resistor 314, the gate of the MOS transistor MP1, and the first switch SW1. Opening and closing is controlled exclusively with SW1, and the source and gate of the MOS transistor MP1 are short-circuited or opened. The second switch SW2 may be a semiconductor switch, and when a positive voltage signal (for example, logic value H) is applied to the gate, the switch is opened to cut off the current between the source and the drain, and the negative voltage signal By applying (for example, logical value L), the switch is closed and a current between the source and the drain flows.

  Next, the operation of the constant voltage source circuit 36 will be described. When the power supply voltage Vdd input to the second terminal 34 is larger than the output voltage from the regulator 12, the comparator 302 supplies a signal having a logical value H, which is a positive voltage, to the second switch SW2 and the inverting circuit 304.

  The inverting circuit 304 converts the input logic value H signal into a negative voltage logic value L signal and outputs the signal to the first switch SW1. As a result, the first switch SW1 is closed while the second switch SW2 is opened.

  As a result, the current mirror circuit 320 can pass a constant current to the voltage generator 310 via the first switch SW1, a constant voltage VGS1 is generated between the gate and the source of the MOS transistor MP1, and the MOS transistor MP1 is turned on. Turn on.

  Therefore, when the power supply voltage Vdd is larger than the output voltage from the regulator 12, the power supply voltage Vdd is almost not dropped by the backflow prevention switch 30, and a voltage substantially equal to the power supply voltage Vdd is input to the regulator 12.

  When the power supply voltage Vdd is smaller than the output voltage from the regulator 12 (that is, when the reverse bias condition is satisfied), the comparator 302 supplies a negative voltage logical value L signal to the second switch SW2 and the inverting circuit 304.

  The inverting circuit 304 converts the input logic value L signal to a positive voltage logic value H and outputs the signal to the first switch SW1. As a result, the first switch SW1 is opened while the second switch SW2 is closed. As a result, the gate-source voltage of the MOS transistor MP1 becomes 0V, and the MOS transistor MP1 is turned off. Further, the inverting circuit 304 outputs a signal having a logic value H to the regulator 12 as a power down signal. When the regulator 12 receives the power down signal, the regulator 12 stops the operation of the LDO.

  Therefore, when the power supply voltage Vdd is smaller than the output voltage from the regulator 12, the reverse current from the first terminal 32 to the second terminal 34 is prevented by the MOS transistor MP1 and the parasitic diode D1 of the backflow prevention switch 30 in the off state. .

  Thus, according to the power supply device 1 of the present embodiment, the constant voltage source circuit 36 of the backflow prevention switch 30 is based on the result of comparing the magnitude of the power supply voltage Vdd and the output voltage from the regulator 12. Open / close control of SW1 and second switch SW2 is controlled exclusively. Thereby, the power supply device 1 inputs the constant voltage VGS1 between the gate and the source of the MOS transistor MP1 when the power supply voltage Vdd is larger than the output voltage from the regulator 12, and otherwise, between the gate and the source of the MOS transistor MP1. Input 0V. Therefore, the power supply device 1 prevents the reverse current from flowing from the first terminal 32 to the second terminal 34 by turning off the MOS transistor MP1 when the power supply voltage Vdd drops below the output voltage from the regulator 12. Can do.

  FIG. 3 shows the relationship between the power supply voltage and the gate-source voltage of the MOS transistor MP1 in this embodiment. L1 in the figure indicates the gate-source voltage VGS of the MOS transistor MP1 in the power supply device 1 of the present embodiment shown in FIG. 1, and L2 indicates the gate-source voltage of the PMOS transistor MP1 in the conventional power supply device 100 shown in FIG. VGS is shown.

  In the conventional power supply device 100, a voltage obtained by dividing the power supply voltage Vdd is input to the gate of the PMOS transistor MP1. Therefore, the gate-source voltage is a value obtained by multiplying the power supply voltage Vdd by a constant less than 1, as indicated by L2.

  In the power supply device 1 of the present embodiment, the voltage between the gate and the source of the MOS transistor MP1 is a section where the voltage VGS1 is constant regardless of the magnitude of the power supply voltage Vdd when the power supply voltage Vdd is equal to or higher than the reference voltage. Has a section that decreases in accordance with the magnitude of the power supply voltage Vdd.

  Specifically, if the drain-source voltage of the MOS transistor MP1 is VDS1, and the constant voltage generated by the constant voltage source circuit 36 is VGS1, the gate potential of the MOS transistor MP1 is Vdd-VDS1-VGS1. Therefore, when Vdd <VDS1 + VGS1, the gate potential can be less than 0.

  Usually, in the circuit design, the minimum value of the gate potential is designed to be 0V. Therefore, when Vdd <VDS1 + VGS1, the gate-source voltage of the MOS transistor MP1 is set to VGS1 ′ = Vdd− so that the gate potential is not less than 0V. Enter VDS1. In FIG. 3, the source-drain voltage VDS1 is shown as a fixed value for convenience.

  More specifically, the gate potential of the MOS transistor MP1 is the sum of the drain-source voltage of the first switch SW1 and the NMOS drain-source voltage of the output stage of the current mirror circuit 320. When the power supply voltage Vdd decreases and becomes less than VDS1 + VGS1, the NMOS of the output stage of the current mirror circuit 320 decreases and the source-gate voltage decreases, and operates in the non-saturated region. Then, the current that current mirror circuit 320 provides to voltage generation unit 310 decreases, and the voltage generated by voltage generation unit 310 also decreases. In this way, the gate-source voltage VGS1 ′ of the MOS transistor MP1 decreases following the decrease in the power supply voltage Vdd.

  As a result, as indicated by L1, the gate-source voltage of the MOS transistor MP1 is a constant voltage VGS1 in a range where Vdd ≧ VDS1 + VGS1, and the gate-source voltage of the MOS transistor MP1 is in a range where Vdd <VDS1 + VGS1. VGS1 ′ increases or decreases according to Vdd.

  The gate-source voltage does not exceed the gate-source breakdown voltage VGSR of the MOS transistor, but may be a voltage close to the gate-source breakdown voltage VGSR. For example, the gate-source voltage may be 80% or more of the gate-source breakdown voltage VGSR of the MOS transistor. Thereby, the on-resistance of the MOS transistor MP1 can be lowered.

  As described above, the gate-source voltage of the MOS transistor MP1 of the power supply device 1 of the present embodiment shown in L1 of FIG. 3 is between the gate and source of the PMOS transistor MP1 of the conventional power supply device 100 shown in L2 in most regions. It becomes larger than the voltage. As a result, the MOS transistor MP1 of the power supply device 1 of the present embodiment has a smaller on-resistance than the conventional power supply device 100, and can output a high output voltage close to the power supply voltage Vdd from the regulator 12.

  FIG. 4 shows a configuration of the power supply device 2 in a modification of the present embodiment. The power supply device 2 includes a regulator 12 and a backflow prevention switch 30 similar to those of the power supply device 1 according to FIG. 1, but the backflow prevention switch 30 is a regulator connected to an output terminal OUT of the regulator 12 and a circuit driven by the regulator 12. Connected between output terminals. That is, in the power supply device 2, the positions of the regulator 12 and the backflow prevention switch 30 are opposite to those of the power supply device 1. In the power supply device 2, the anode of the parasitic diode D 2 of the regulator 12 and the parasitic diode D 1 of the backflow prevention switch 30 are connected.

  In the power supply device 2, even when the power supply voltage Vdd is high, the power supply voltage Vdd is not directly input to the MOS transistor MP1 of the backflow prevention switch 30. Therefore, a MOS transistor having a low withstand voltage compared to the power supply device 1 can be used as the MOS transistor MP1 of the power supply device 2. In general, as the withstand voltage of the MOS transistor is smaller, the on-resistance can be reduced, so that the MOS transistor MP1 of the power supply device 2 can occupy a smaller area than the power supply device 1.

  In the power supply device 1 according to the present embodiment and the power supply device 2 according to the modification, it has been described that the power supply voltage Vdd is input from the power supply terminal of an external power supply. A power supply for outputting Vdd may be provided. In this case, the power supply included in the power supply device 1 supplies the power supply voltage Vdd to the backflow prevention switch 30, and the power supply included in the power supply device 2 supplies the power supply voltage Vdd to the regulator 12.

  Further, in the power supply device 1 according to the present embodiment and the power supply device 2 according to the modification, the MOS transistor MP1 and the MOS transistor MP2 are PMOS transistors, but both may be replaced by NMOS transistors.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

  DESCRIPTION OF SYMBOLS 1 Power supply device, 2 Power supply device, 10 LDO, 12 Regulator, 20 Backflow prevention switch, 22 Input terminal, 24 Output terminal, 30 Backflow prevention switch, 32 1st terminal, 34 2nd terminal, 36 Constant voltage source circuit, 100 Power supply Device, 102 voltage dividing resistor, 104 voltage dividing resistor, 106 reference power supply, 108 operational amplifier, 110 inverting circuit, 302 comparator, 304 inverting circuit, 310 voltage generating unit, 312 diode, 314 resistor, 320 current mirror circuit, 322 band gap circuit

Claims (10)

A backflow prevention switch for preventing backflow of current from the first terminal to the second terminal,
A MOS transistor having a source and a back gate connected to the first terminal and a drain connected to the second terminal;
A constant voltage source circuit in which the source of the MOS transistor is on the high potential side and the gate of the MOS transistor is on the low potential side;
With backflow prevention switch.   The backflow prevention switch according to claim 1, which is arranged in series between a power supply terminal and an input terminal of the regulator.   The backflow prevention switch according to claim 1, connected between an output terminal of a regulator and a circuit driven by the regulator.   The backflow prevention switch according to any one of claims 1 to 3, wherein an output voltage of the constant voltage source circuit does not exceed a gate-source breakdown voltage of the MOS transistor.   The backflow prevention switch according to claim 2, wherein when the power supply voltage of the power supply terminal becomes lower than the output voltage of the regulator, the voltage output from the constant voltage source circuit is stopped.   6. The backflow prevention switch according to claim 1, wherein the constant voltage source circuit includes a voltage generation unit connected between the first terminal and the gate of the MOS transistor. 7.   The backflow prevention switch according to claim 6, wherein the voltage generation unit includes a diode and a resistor connected in series to the diode.   The constant voltage source circuit includes a first switch that short-circuits or opens between the voltage generator and the current source, and is controlled to open and close exclusively with the first switch, and the gate-source of the MOS transistor is short-circuited or The backflow prevention switch according to claim 6 or 7, further comprising a second switch to be opened. A regulator that outputs an output voltage from the output terminal;
A power supply that outputs power supply voltage from the power supply terminal;
The backflow prevention switch according to claim 2, wherein the second terminal is connected to the power supply terminal, and the first terminal is connected to an input terminal of the regulator;
A power supply device comprising: A regulator that outputs an output voltage from the output terminal;
A power supply that outputs a power supply voltage from a power supply terminal to the regulator;
The backflow prevention switch according to claim 3, wherein the second terminal is connected to the output terminal of the regulator, and outputs an output voltage from the first terminal.
A power supply device comprising:

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