JP2015032090A - Semiconductor device - Google Patents

Abstract

In a semiconductor device using Wide IO technology, a configuration for shortening a clock tree is provided.
A semiconductor device includes a PLL circuit and a plurality of memory controllers. The plurality of memory controllers 83 to 86 control the plurality of stacked memories. In the PLL circuit 81, a plurality of memory controllers 83 to 86 are arranged around. The position of the PLL circuit 81 is determined so that the distance from the PLL circuit 81 to the plurality of memory controllers 83 to 86 is the same.

[Selection] Figure 1

Description

  The present invention relates to a semiconductor device, for example, a semiconductor device having a wide interface.

Conventionally, in a semiconductor device, an interface (IO) for controlling input / output with a peripheral device is arranged in the periphery. For this reason, a semiconductor device generally has a PLL (Phase locked Loop) circuit arranged in the vicinity of the IO.
FIG. 16 illustrates a configuration example of a semiconductor device 90 including a DRAM. The semiconductor device 90 includes a semiconductor substrate (semiconductor body) 91 having SoC (System on Chip) and a DRAM (Dynamic Random Access Memory) 95. The semiconductor substrate 91 is connected to the DRAM 95 on a plane. The details of the SoC included in the semiconductor substrate 91 are shown on the left side of FIG. The semiconductor substrate 91 has a PLL circuit 92 and a memory controller (MEMC) 93 mounted thereon, and a clock signal line 94 is wired. The clock signal line 94 supplies a clock signal from the PLL circuit 92 to the memory controller 93. In the semiconductor device 90, an IO (Input / Output) for the DRAM 95 and other IOs are arranged around the semiconductor substrate 91. Therefore, in the semiconductor device 90, the memory controller 93 and the PLL circuit 92 are arranged around the semiconductor substrate 91 according to the arrangement of the IO.

In recent years, a wide interface (Wide IO) technology has been developed as a memory interface in accordance with the widening of memory bandwidth. In the development of this technology, through-silicon via (TSV) technology and die stacking (die stack) using micro bumps have become possible.
For example, Patent Document 1 discloses a configuration in which an IO (Input / Output) chip is stacked on an interposer substrate and a plurality of DRAM chips are stacked on the memory module in which memory chips are stacked. In the technology disclosed in Patent Document 1, a DRAM chip is provided with a through electrode for passing an electric signal from one surface to the other surface. The IO chip transmits and receives signals and data to and from the DRAM chip in response to signals input from the outside via the interposer substrate. At that time, the IO chip transmits / receives data to / from any DRAM chip through the through-electrode of the DRAM chip.

In addition, Patent Document 2 discloses a semiconductor memory device having a wide input / output of a multi-channel interface system and a semiconductor package including the same, which can support various devices and systems that require high performance and low power. Yes. The semiconductor memory device of Patent Document 2 includes a semiconductor die including a plurality of memory cell arrays, and includes an input / output bump pad portion formed at a central portion of the semiconductor die. The input / output bump pad portion provides a plurality of channels for independently connecting the memory cell arrays to external devices.
In addition, although the technology of Wide IO is not adopted, regarding a semiconductor memory having a plurality of memory chips, Patent Document 3 provides a specification for arranging a DRAM macro and a logic core on the same chip. Yes. The chip of Patent Document 3 includes a multi-bank SDRAM (synchronous DRAM) macro placed at the top and bottom of the chip, and a logic core is placed between the upper and lower SDRAM macros at the center of the chip. Also, a PLL is placed on one side of the center of the chip, and a clock from the PLL is guided to the center of the chip and then buffered before driving the SDRAM macro and logic core.

JP 2006-301863 A JP 2011-166147 A Japanese Patent Laid-Open No. 10-189889

For example, in the semiconductor memory having wide input / output disclosed in Patent Document 2, an input / output bump pad portion is disposed at the center of the semiconductor die. In the Wide IO technology, since the IO is arranged inside the semiconductor substrate as in the semiconductor memory of Patent Document 2, it is preferable to arrange a memory controller in the vicinity of the IO.
However, Patent Document 2 does not pay attention to the arrangement of the PLL circuit that supplies the clock signal to the memory controller. Therefore, for example, as shown in FIG. 16 or Patent Document 3, when the PLL circuit is arranged near the outer periphery of the semiconductor substrate or on one side of the semiconductor substrate, the clock latency becomes long. This causes a problem that timing design becomes difficult. For this reason, in the semiconductor device using the Wide IO technology, a new idea for the arrangement of the PLL circuit is required.
The inventors have found a configuration that shortens the clock tree in a semiconductor device using the Wide IO technology.
Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the semiconductor device includes at least a plurality of memory controllers that control a plurality of memories stacked with the PLL circuit, and the PLL circuit is arranged so that the plurality of memory controllers are arranged around the memory circuit. Is done.

  According to one embodiment, a configuration in which a clock tree is shortened can be provided in a semiconductor device using Wide IO technology.

It is a block diagram which shows the example of arrangement | positioning of the PLL circuit and memory controller of one Embodiment. 2 is a diagram illustrating an example of a stack structure of a Wide IO DRAM and a SoC according to the first embodiment. FIG. 3 is a diagram illustrating an arrangement example of a PLL circuit, a through-silicon via, and a memory controller according to Embodiment 1. FIG. It is a figure which shows an example of the connection by which the clock signal produced | generated by a PLL circuit is supplied. It is a figure which shows another example of the connection by which the clock signal produced | generated by a PLL circuit is supplied. It is a figure which shows an example of the connection relation of a power supply. It is a figure which shows the example of arrangement | positioning of a microbump. It is a figure which shows the other example of arrangement | positioning of a micro bump. It is an example of a layout in the case where a clock signal line is wired between TSV arrays. It is a figure which shows an example of the power supply allocated to TSV. It is a figure which shows an example of the minimum structure of an 8th layer power supply. It is an enlarged view of the minimum composition of the 8th layer power supply. It is a figure which shows an example of the wiring of an 8th layer power supply. It is a figure which shows an example of a structure of TSV of the 9th layer power supply direct access. It is an enlarged view of a 9th layer power supply structure. It is a figure which shows an example of the wiring of 9th layer power supply. It is a figure which shows the example of arrangement | positioning of the PLL circuit of a related semiconductor device.

  Hereinafter, embodiments will be described with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. In the drawings, components having the same configuration or function and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

FIG. 1 is a block diagram illustrating an arrangement example of a PLL circuit and a memory controller according to an embodiment. The semiconductor device 80 according to an embodiment includes a PLL circuit 81 and first to fourth memory controllers 83 to 86 at least in the device. In addition, the semiconductor device 80 can be connected to, for example, memories stacked by through silicon vias on the premise that the semiconductor device 80 has a configuration that can be connected to a plurality of stacked memories. In the semiconductor device 80, first to fourth memory controllers 83 to 86 are arranged around the PLL circuit 81.
The PLL circuit 81 supplies a clock signal to the first to fourth memory controllers 83 to 86.
The first to fourth memory controllers 83 to 86 control a plurality of stacked memories.

  Although FIG. 1 shows a case where four memory controllers 83 to 86 are arranged as a plurality of memory controllers, the number of memory controllers is not limited to four. The semiconductor device 80 changes the number of memory controllers to be mounted according to the configuration of the memory to be stacked, in other words, according to the standard of the memory to be stacked. For example, when a wide IO DRAM is used as the memory to be stacked, each memory is divided into four channels (areas) and controlled. In the case where the memory to be stacked is controlled using a plurality of memory controllers for each channel, the distance from the PLL circuit 81 to the plurality of memory controllers needs to be the same within a predetermined error range. Here, the predetermined error range is, for example, a range in which an error (delay) in time until the clock signal supplied from the PLL circuit reaches each memory controller can be adjusted (delay adjustable), or It is an acceptable range. For example, the error range may be a range in which each memory controller can control a plurality of stacked memories in synchronization based on a clock signal supplied from a PLL circuit. In other words, it is preferable that the distance from one end of each of the plurality of memory controllers to the PLL circuit is the same. One end of the memory controller is, for example, a terminal (clock port) through which a clock signal reaches the memory controller.

  FIG. 1 does not show anything other than the arrangement of the PLL circuit 81 and the first to fourth memory controllers 83 to 86. However, the semiconductor device 80 is connected to a plurality of stacked memories via the IO. A through via is used as an example of IO. For example, the Wide IO technology uses a through silicon via (TSV) as described above. Therefore, in addition to the arrangement example of FIG. 1, the semiconductor device 80 further includes a plurality of through vias arranged between the first to fourth memory controllers 83 to 86 and the PLL circuit 81. In other words, the plurality of memory controllers are arranged in association with each of the plurality of TSV arrays. Further, the semiconductor device 80 includes a clock signal line that supplies a clock signal from the PLL circuit 81 to the first to fourth memory controllers 83 to 86 through a region where a plurality of through vias are arranged.

By using the arrangement example shown in FIG. 1, the clock tree can be shortened and a clock signal can be supplied to a plurality of memory controllers at the same timing. In addition, the arrangement of the TSV array and the memory controller can be easily determined and changed according to the standard of the memory to be stacked. For example, standards and the like determine the arrangement of TSV arrays and the number of channels. Since the memory controllers are arranged around the PLL circuit, even when the number of memory controllers increases or decreases according to the number of channels, the memory controllers can be arranged so as to be substantially equidistant around the PLL circuit.
In addition, compared to the configuration shown in FIG. 16, by arranging a plurality of memory controllers around the PLL circuit, the length of the clock signal line for supplying the clock signal is shortened, in other words, the clock tree is shortened. be able to. By shortening the clock tree, the clock latency can be shortened or the timing design can be facilitated. For example, by arranging the PLL circuit in the center of the 4 channels of the TSV array arranged for Wide IO, a clock tree is formed with the shortest distance to the memory controller associated with the Wide IO 4 channel and the same wiring length in 4 channels. Becomes easier.

  A specific example of the semiconductor device to which the arrangement example shown in FIG. 1 is applied will be described below with reference to the drawings. In each embodiment, a case where a Wide IO DRAM is used as a plurality of stacked memories will be described as an example. However, it goes without saying that the embodiments are applied to the case where other stackable memories are used.

Embodiment 1. FIG.
* Configuration of Embodiment 1 First, a configuration example of a stack structure of a semiconductor device in which a plurality of memories are stacked will be described. FIG. 2 is a diagram showing an example of a stack structure in the case of using a Wide I / O DRAM. The semiconductor device 100 includes a substrate (package substrate) 10, a SoC (System on Chip) 20, a Wide IO DRAM group 30 in which a plurality of Wide IO DRAMs 31 to 34 are stacked, a plurality of micro bumps 40, a plurality of through silicon vias (TSV). ) 50 and a plurality of substrate bumps 60. In the SoC 20 and the Wide IO DRAM group 30, a plurality of through-silicon vias (hereinafter referred to as “TSV” as appropriate) 50 are formed in the silicon layer. FIG. 2 schematically shows a laminated structure, and for ease of explanation, the metal layer of each chip is hatched in the upward direction, the micro bumps 40 are shaded, the TSV 50 is a vertical line, and the substrate bumps 60 are shown. Is shown in a lattice pattern.

The SoC 20 and the Wide IO DRAM 30 group are stacked via a plurality of TSVs 50 and micro bumps 40 to form a stack structure. Specifically, the SoC 20 is laminated directly on the substrate 10 via a plurality of micro bumps 40. In addition, the Wide IO DRAM 31 is stacked directly above the SoC 20 via a plurality of micro bumps 40. Similarly, in the Wide IO DRAM group 30, the plurality of Wide IO DRAMs 31 to 34 are stacked via the plurality of micro bumps 40. The SoC 20 and the Wide IO DRAM group 30 are electrically connected via a plurality of TSVs 50 and micro bumps 40, input / output signals, and supply power.
The micro bump 40 is a bump used for stacking the SoC 20 and the Wide IO DRAM group 30. A substrate bump 60 shown below the substrate 10 is a bump for inputting / outputting signals to / from the outside of the semiconductor device 100 and supplying power.

The SoC 20 includes a memory controller, a PLL circuit, and the like that control the plurality of Wide IO DRAMs 31 to 34.
The Wide IO DRAM group 30 is composed of a plurality of DRAMs having Wide IO as an interface. In FIG. 2, the Wide IO DRAM group 30 shows a structure in which four Wide IO DRAMs 31 to 34 are stacked. However, the structure is not limited to this, and one to three Wide IO DRAMs are stacked. Also good. The Wide IO DRAMs 31 to 34 are stacked via a plurality of micro bumps 40. Hereinafter, “Wide IO DRAM” will be referred to as “DRAM” and “Wide IO DRAM group” as “DRAM group” as appropriate.
The plurality of micro bumps 40 connect the SoC 20 and the plurality of Wide IO DRAMs 31 to 34 through the plurality of TSVs 50.
Each TSV 50 serves to supply power or signals to a plurality of Wide IO DRAMs 31-34.
The plurality of substrate bumps 60 electrically connect the substrate 10 and the outside.
The semiconductor device 100 in FIG. 2 is schematically shown, and the micro bumps 40, the TSVs 50, and the substrate bumps 60 show a part of the arrangement example, and these numbers are the number of bumps of the actual device. Does not reflect.

As described above, the SoC 20 and the DRAMs 31 to 34 are connected through the plurality of micro bumps 40 connected to the TSVs 50 formed in each chip. FIG. 2 shows a mode in which three TSVs 50 are formed in each chip. Actually, however, a large number of TSVs 50 are formed in the chip in accordance with signals and power supplied from the SoC 20 to the DRAM group 30. . In FIG. 2, an example of the connection relationship between the micro bumps 40 and the TSVs 50 is shown and described, and the number and arrangement (positions to be formed) thereof are not considered.
The SoC 20 and the DRAM group 30 are face down in which the metal layer is disposed on the lower side. Therefore, the silicon substrate on which the TSV 50 is formed is laminated so as to be on the upper side of the metal layer. Signals from the SoC 20 to the DRAMs 31 to 34 and supply to the power supply are performed via the TSV.

  In the semiconductor device 100 shown in FIG. 2, each of the DRAMs 31 to 34 constituting the DRAM group 30 is divided into a plurality of regions and controlled by a plurality of memory controllers. Here, it is assumed that the semiconductor device 100 divides each DRAM into four regions, and one memory controller controls one region. In addition, the plurality of memory controllers control each area of the plurality of memories based on the clock signal supplied from the PLL circuit. Therefore, it is necessary to synchronize clock signals supplied to a plurality of memory controllers. Therefore, the delay of the clock signal supplied from the PLL circuit is configured to be the same. In the first embodiment, it is preferable to arrange the PLL circuit at the center of the plurality of memory controllers. In other words, the PLL circuit is arranged at the center of the Wide IO (TSV array) formed by the TSV 50. Since the plurality of memory controllers are arranged accompanying the TSV array, they are arranged so as to surround the PLL circuit. As a result, the distance from the PLL circuit to the plurality of memory controllers can be made the same length or within the allowable error length range. With reference to FIG. 3, the area | region which arrange | positions the PLL circuit, memory controller, and TSV which SoC20 has is demonstrated.

  FIG. 3 is a diagram illustrating an example of the positional relationship of the layout of the TSV, the memory controller, and the PLL circuit formed in the SoC 20 of the first embodiment. Here, the positional relationship between the PLL circuit 21, the four memory controllers 22-0 to 22-3, and the four TSV array areas 23-0 to 23-3 formed in the SoC 20 is shown. In addition, the arrangement of the IO circuit 24 adjacent to the PLL circuit 21 is shown. However, the arrangement of the IO circuit 24 is shown for convenience and is not particularly limited. The IO circuit 24 is preferably arranged so that the distance from the PLL is shortened. FIG. 3 shows an example of the positional relationship when the DRAM group 30 is divided into four channels (four regions). However, there are cases where the DRAM group 30 is divided into regions other than four, and as in FIG. The distance between the plurality of memory controllers may be the same or within an allowable error range. In the following description, the four memory controllers 22-0 to 22-3 may be referred to as MEMC CH00, MEMC CH01, MEMC CH01, and MEMC CH01. Similarly, the four TSV array areas 23-0 to 23-3 may be described as TSVARRAY CH00, TSVARRAY CH01, TSVARRAY CH02, and TSVARRAY CH03.

The PLL circuit 21 supplies a clock signal to the four memory controllers 22-0 to 22-3.
The memory controllers 22-0 to 22-3 control the DRAM group 30. The memory controllers 22-0 to 22-3 are arranged in association with the TSV array areas 23-0 to 23-3, respectively.
The TSV array areas 23-0 to 23-3 are areas where a plurality of TSVs 50 are formed. A plurality of TSVs 50 connected to the DRAM group 30 exist as an array for four channels (an arrangement for each of four regions), and are formed almost at the center of the chip. In other words, the semiconductor device 100 has a region where a plurality of TSVs 50 are arranged for each channel of the divided memory.
Each of the four channels obtained by dividing the memory has an independently controllable configuration and is controlled by a memory controller corresponding to each channel. The PLL circuit 21 is formed at the center of the plurality of TSV array regions 23-0 to 23-3.
The IO circuit 24 is an input / output unit for supplying power to the PLL circuit 21 and for a reference clock, and is disposed adjacent to the PLL circuit 21.
FIG. 3 shows the wiring of the clock signal line 25 in addition to the arrangement of the components described above. The clock signal line 25 is wired so as to pass between the TSV array regions 23-0 to 23-3. The clock signal line 25 forms an H-type clock tree from the PLL circuit 21 to the memory controllers 22-0 to 22-3 of each channel. Accordingly, the PLL circuit 21 has a symmetrical clock wiring structure between the channels in the vertical and horizontal directions. The configuration shown in FIG. 3 facilitates the design with the shortest and equal clock latency.

Next, the connection state of the semiconductor device 100 will be described with reference to FIGS. 4A and 4B. By explaining the connection state, the path through which the reference clock supplied from the PLL circuit 21 is supplied from the plurality of memory controllers 22-0 to 22-3 to the bumps on the DRAM side via the TSV50 will be described.
FIG. 4A is a diagram illustrating an example of a connection in which a clock signal generated by the PLL circuit 21 and other signals are supplied. FIG. 4B is a diagram illustrating an example of a connection in which a clock signal generated by the first PLL circuit and other signals are supplied to the second PLL circuit. 4A and 4B, for ease of explanation, the micro bumps 40 are described by distinguishing them into SoC side micro bumps 40S and DRAM side micro bumps 40D. The SoC side micro bumps 40 </ b> S are micro bumps disposed between the substrate 10 and the SoC 20, and the DRAM side micro bumps 40 </ b> D are micro bumps disposed between the SoC 20 and the DRAM 31.

In FIG. 4A, the SoC 20 side micro bump 40S receives a reference clock signal (REF CLK) from the outside and outputs it to an I / O buffer (I / O BUF). The I / O buffer outputs a reference clock signal to the PLL circuit 21. The PLL circuit 21 generates a clock signal used in the SoC 20 based on the input reference clock signal, and outputs the clock signal to the plurality of memory controllers 22-0 to 22-3. The plurality of memory controllers 22-0 to 22-3 execute various control processes based on the input clock signal. The plurality of memory controllers 22-0 to 22-3 input / output control information (COMMAND / ADDRESS) including a clock (CLOCK), data (DATA), and various commands and addresses with the DRAM group 30.
The plurality of memory controllers 22-0 to 22-3 are connected to the DRAM group 30 via the I / O buffer, the plurality of TSVs 50 arranged in the TSV array areas 23-0 to 23-3, and the DRAM-side micro bump 40D. Is done. Each Wide IO DRAM 31 to 34 constituting the DRAM group 30 is divided into four channels and controlled by the corresponding memory controllers 22-0 to 22-3.

  At this time, the DRAMs 31 to 34 are required to control each channel in synchronization. Therefore, it is necessary for the plurality of memory controllers 22-0 to 22-3 to control the DRAMs 31 to 34 based on the same (synchronized) clock signal, and the plurality of memory controllers 22-0 to 22 to 22 from the PLL circuit 21. The timing at which the clock signal is supplied to -3 is synchronized. Therefore, the length of the clock signal line from the PLL circuit 21 to each of the memory controllers 22-0 to 22-3 is the same, or the length is within a range in which a delay in supply of the clock signal is allowed or adjustable. It is required to determine the arrangement.

In the connection shown in FIG. 4B, the clock signal generated by the first PLL circuit 21-1 is supplied to the second PLL circuit 21-2. In such a configuration, it is only necessary to have a bump on the SoC side that is connected to the first PLL circuit 21-1, and a micro bump that is connected to the PLL circuit 21-2 is not necessary.
4A and 4B, the semiconductor device 100 includes a plurality of memory controllers 22-0 to 22-3 in addition to a path for inputting / outputting data to / from the DRAM group 30 and a plurality of memory controllers 22 from the SoC side micro bump 40S. There is a DIRECT ACCRESS path for supplying power to the DRAM group via the TSV50 and the DRAM-side micro bump 40D or exchanging data with the DRAM group without going through −0 to 22-3.

* Mechanism and effect of the first embodiment The position of the PLL circuit 21 is set to approximately the center of the four channels configured by the TSV array regions 23-0 to 23-3, and the clock tree is made H-shaped so that the four channels are arranged. It is possible to wire with the same length. As a result, the effect of facilitating the timing design can be expected.

Embodiment 2. FIG.
* Configuration of Embodiment 2 In Embodiment 2, details of the arrangement of the plurality of micro bumps 40 will be described. This embodiment will be described with reference to the configuration example of the semiconductor device 100 shown in FIG. 2, the configuration example of the SoC 20 shown in FIG. 3, and the connection example shown in FIG. 4A. The SoC side micro bump 40 </ b> S supplies power and signals supplied from the substrate 10 to the SoC 20. The DRAM-side micro bump 40 </ b> D is connected to the TSV 50 and supplies power and signals supplied from the SoC 20 through the TSV 50 to the DRAM group 30. FIG. 5 is a diagram illustrating an example of a power connection relationship of the semiconductor device 100. The plurality of SoC side micro bumps 40S supply power supplied from the outside to each component of the SoC 20 (VDDQ, VDD, AVDD, AVCCQ, AVSSQ, AVSS, VSS) and power supplied to the DRAM group 30 ( (VDD2, VDDQ, VSS, VSSQ). The power supplies AVDD, AVCCQ, AVSSQ, and AVSS are dedicated power supplies that are supplied to the PLL circuit 21 and its I / O buffer (I / O BUF).

The power supplies VDD and VSS are supplied to the memory controller (MEMC CHX) 22 and its I / O buffer in addition to the PLL circuit 21. In FIG. 5, the memory controller (MEMC CHX) 22 means the four memory controllers 22-0 to 22-3 shown in FIG.
The power supply VDD2 is a power supply supplied only to the DRAM group, and is directly supplied to the DRAM group via the TSV50 and the DRAM side micro bump 40D. On the other hand, the power supplies VDDQ, VSS and VSSQ are supplied to the SoC side I / O buffer and also supplied to the DRAM group via the TSV50 and the DRAM side micro bump 40D.
In addition, FIG. 5 shows a SoC-side micro bump 40S that receives a reference clock (REF CLK). The PLL circuit 21 generates a clock signal using the reference clock received via the SoC side micro bump 40 </ b> S and supplies the clock signal to the memory controller 22.

6 and 7 are diagrams showing arrangement examples of the micro bumps. 6 and 7, the first bump for supplying power only to the PLL circuit 21, the power to the plurality of memories via TSV, the second bump for connecting the clock, data, command, and address signal, to the PLL circuit 21. A third bump for supplying a reference clock signal is shown. The first bump is composed of a SoC-side micro bump 40S that supplies power supplies AVDD, AVCCQ, AVSSQ, and AVSS. The second bump is composed of a DRAM-side micro bump 40D that supplies power supplies VDD, VDD2, VDDQ, VSS, and VSSQ. The third bump is composed of a SoC side micro bump 40S that supplies a reference clock.
The first bump is disposed between the PLL circuit 21 and the TSV array regions 23-0 to 23-3. The second bump is located above the TSV array area 23-0 to 23-3 where the TSV 50 is disposed (FIG. 6) or an area adjacent to the TSV array area 23-0-23-3, for example, a plurality of memory controllers 22. It arrange | positions above the area | region (FIG. 7) where -0-22-3 is arrange | positioned. The third bump is disposed between the PLL circuit 21 and the TSV array regions 23-0 to 23-3. Here, for example, the upper part of the TSV array regions 23-0 to 23-3 is between the DRAM 31 of the SoC 20 shown in FIG. 2 and the position where the TSV 50 formed in the SoC 20 is connected on the DRAM 31 side.

The first and third bumps can also be said to be bumps for the PLL circuit 21. The bump for the PLL circuit 21 is disposed in the center of the TSV array 4 channel, more specifically, in the region surrounded by the 4-channel TSV array region 23-0 to 23-3. The first bump can also be said to be a power supply for the PLL circuit 21 (AVDD, AVCC) and an IO power supply connected to the PLL circuit 21 (AVCCQ, AVSSQ). In FIGS. 6 and 7, the first and third bumps (SoC-side micro bumps 40 </ b> S) indicate the names of uses of the micro bumps.
The second bumps are arranged as shown in FIG. 6 or FIG. 7 according to the region where the bumps can be arranged in the semiconductor device. As shown in FIG. 6, when the DRAM-side micro bump 40D can be disposed above the TSV array regions 23-0 to 23-3, the connection length with the TSV 50 can be shortened. On the other hand, as shown in FIG. 7, when the DRAM side micro bumps 40D cannot be arranged above the TSV array regions 23-0 to 23-3, the wiring between the TSV 50 and the DRAM side micro bumps 40D becomes long. .

* Mechanism and effect of the second embodiment In addition to the arrangement of the SoC 20 described in the first embodiment, specifically, the PLL circuit 21 is arranged in the center of the TSV array regions 23-0 to 23-3, the power supply and the signal Supply needs to be considered. The bump for the PLL circuit 21 inevitably needs to bring the bump position to the center. With such an arrangement, it is possible to reduce the impedance of the power supply and the signal wiring and to exhibit the characteristics of the PLL circuit 21, such as the jitter characteristics, as in the PLL circuit shown in FIG.

Embodiment 3. FIG.
In the third embodiment, signal lines, power supply wiring, and power supply in a semiconductor device in which a Wide IO DRAM is mounted will be described. This embodiment will be described with reference to the drawings used in the above embodiments, such as the configuration example of the semiconductor device 100 shown in FIG. 2 and the configuration example of the SoC 20 shown in FIG. The arrangement of the TSV array and the clock signal line, and details of the TSV array and the power supply will be described below.

FIG. 8 shows an example of a layout when clock signal lines are wired between TSV arrays. FIG. 8 shows a case where the DRAM is divided into four channels for control, and a part of the channel 0 TSV array (TSV CH0) and the channel 3 TSV array (TSV CH3) are shown. 21 is arranged, and the channel 0 memory controller is arranged on the upper side.
The TSV array is composed of a plurality of TSVs 50 formed in the TSV array regions 23-0 to 23-3 shown in FIG. In the present embodiment, the TSV array includes a power supply TSV unit 50P and a signal TSV unit 50S. The power TSV unit 50P is a through via that supplies power (hereinafter referred to as “power through via” as appropriate), and includes a TSV that supplies power and an ESD (Electro-Static-Discharge) protection unit that accompanies the TSV. . The signal TSV unit 50S is a through via that supplies a signal (hereinafter referred to as “signal through via” as appropriate), and includes a TSV that supplies (transfers) a signal and an IO (input / output) unit that accompanies the TSV. . In FIG. 8, TSV is indicated by a white circle, the ESD protection part is indicated by a hatched rectangle, and the IO part is indicated by a vertical rectangle. The TSV array is formed in the silicon layer of the SoC 20 or the DRAMs 31 to 34 shown in FIG. The TSV pitch, which is the interval (distance) between adjacent TSVs, is, for example, 50 μm in the vertical direction and 40 μm in the horizontal direction as shown in FIG. The power supply TSV unit 50P and the signal TSV unit 50S make the IO unit and the ESD protection unit adjacent to one end (such as a lower part or an upper part) of the TSV with respect to the TSV array. This makes it possible to connect the ESD protection element forming the IO portion and the ESD protection portion to the TSV without hindering the vertical signal channel.

A plurality of rectangular regions with a grid indicate repeater regions 71 in which signal line repeaters can be arranged.
The clock signal line 25 is wired from the PLL circuit 21 so as to pass between the TSV array of channel 0 and the TSV array of channel 3 and to pass through one of the repeater regions 71. For example, as shown in FIG. 8, the clock signal line 25 passes through a 120 μm interval region between the channel 0 and the channel 3 in the horizontal direction and passes through a TSV pitch of 50 μm in the vertical direction. For example, the clock signal line 25 is configured by a clock tree of Global Cu.
The clock buffer 72 is arranged in the repeater area 71 on the clock signal line 25. The clock signal line 25 shows an example in which a clock signal is inputted from the PLL circuit 21 shown in FIG. 3 and outputted to the memory controller 22-0 of the channel 0. The clock signal line 25 passes vertically between the wide IOs realized by the TSV array, in other words, between the power supply TSV unit 50P and the signal TSV unit 50S, and the clock buffer 72 is appropriately inserted. With the above layout configuration, the clock signal line 25 forming the clock tree can be configured to pass between the TSV arrays. The semiconductor device 100 has no space for arranging the memory controllers 22-0 to 22-3 between the PLL circuit 21 and the TSV array regions 23-0 to 23-3 shown in FIG. It is difficult to arrange the memory controllers 22-0 to 22-3. Therefore, the clock signal line that supplies the clock signal generated by the PLL circuit 21 can be passed between the TSV array regions 23-0 to 23-3 by the above-described method.

Next, power supply wiring will be described. For power supply wiring, it is necessary to consider supplying power to the TSV with low resistance and securing a region for wiring the signal lines described above. FIG. 9 is a diagram illustrating an example of a power source assigned to a TSV. FIG. 9 shows an example of power supplied from the power TSV unit 50P to the DRAM group 30 in a TSV array of an arbitrary channel. A white circle is a TSV, a double circle is a power supply TSV unit 50P, and a single circle is a signal TSV unit 50S. Each power supply TSV unit 50 in FIG. 9 indicates the type of power supplied to the DRAM group 30, for example, VDD 2 and VDDQ.
In addition, as shown in FIG. 9, a signal-power TSV array including a power TSV unit 50 and a signal TSV unit 50S (hereinafter referred to as “mixed via array” as appropriate) and a signal TSV array (only a signal TSV 50S) ( Hereinafter, it will be described as “signal via array” as appropriate.

  10 to 12 are diagrams showing examples of wiring of the eighth layer power supply (M8 power supply). 13 to 15 are diagrams showing examples of wiring of the ninth layer power source (M9 power source). As the power source, it is necessary to connect not only the power source VSS and VDD supplied to the clock buffer 72 but also the VDDQ and VSSQ supplied to the DRAM to the TSV with a low resistance. In order to connect the power supplied to the DRAM group 30 to the TSV with low resistance, the eighth layer power supply and the ninth layer power supply form a mesh structure (lattice shape), and the connection between the eighth layer power supply and the ninth layer power supply is made. There are points. Details will be described with reference to the drawings.

FIG. 10 is a diagram illustrating an example of the minimum configuration of the eighth layer power source wired to the TSV array. The range indicated by the symbol A is the minimum configuration unit of the eighth layer power supply. The same power supply TSV unit 50P is used for the direct access TSV shown in FIGS. 4A and 4B. Direct access is a through via in which the TSV 50 is directly connected to the PAD. In FIG. 10, the power supply TSV unit 50 </ b> P is connected to the power supply supplied by the TSV among the power supplies indicated by the symbol A. In the drawings referred to hereinafter, as in FIG. 10, TSVs indicated by white lines are connected to the power supplied by the power TSV unit 50 </ b> P among the supplied power.
FIG. 11 shows an enlarged view of the configuration of the power supply and the correspondence (legend) between the power supply type and the line type. FIG. 12 shows an example of the wiring of the eighth layer power source. Reference numeral VDD2 shown in FIG. 12 is a wiring of the power supply VDD2 included (arranged) in the eighth-layer power supply in order to supply the power supply VDD2 to the DRAM group. The power supply VDD2 is wired so that four power supply TSV units 50P included in the TSV array can be connected. As a result, the four power TSV units 50P are supplied with the power VDD2, and supply the power VDD2 to the DRAM group.

  FIG. 13 is a diagram illustrating an example of a direct access TSV configuration of the ninth layer power supply. The direct access power TSV unit 50D is a TSV directly connected to the PAD, and supplies the TSV power to the Direct Access Pin. Further, the direct access signal TSV unit 50S supplies the signal directly to the direct access pin on the DRAM side. The range indicated by the symbol B is the minimum configuration unit of the ninth layer power supply. The range indicated by the symbol C is the ninth layer power supply immediately above the TSV. FIG. 14 shows an enlarged view of the configuration of the power source and the correspondence (legend) between the power source type and the line type. In FIG. 14, the enlarged view of the part enclosed with the dashed-dotted line of FIG. 13 is shown. The power supply VDD shown in FIG. 14 is a wiring serving as a connection point for connecting the eighth layer power supply and the ninth layer power supply. With respect to the power supplies VDDQ, VSS, and VSSQ supplied to the SoC 20 and the DRAM group, by forming a mesh structure, a connection point is set at a point where the power supply wirings of each layer intersect. As a result, the power supplied to the DRAM group 30 can be connected to the TSV with a low resistance.

FIG. 15 shows an example of the wiring of the ninth layer power supply. In FIG. 15, two regions indicated by SIG CH are regions where signal lines are arranged. The area indicated by DA is a direct access TSV. There is a TSV row in which no power is present, and both sides thereof are used as signal channels, and clock signal lines for supplying clock signals are wired. In addition, other signal lines for supplying signals other than the clock signal can be wired in the SIG CH area.
As shown in FIG. 15, a part of the plurality of signal TSV units 50S forms a signal TSV array (signal via array) arranged in the same direction as the wiring direction of the ninth layer power supply. Unlike the signal-power supply array, the signal TSV array does not include the power supply TSV unit 50P. In addition, since the signal TSV array does not need to supply power, wiring for the power is not required. In other words, the power supply line is not wired between the signal TSV array and the array formed by the plurality of adjacent through vias. Therefore, it is possible to form a region where signal lines are wired between the signal TSV array and the adjacent TSV array.
As the number of signal TSV arrays increases, the area where signal lines can be wired increases. On the other hand, when the arrangement of the power supply TSV unit 50P is determined by a standard or the like, it is necessary to devise so that a signal TSV array can be formed.
As described above, this configuration makes it possible to supply power to the clock buffer with VDDQ and VSSQ at low resistance. In addition, by devising the arrangement of the TSV array so that the signal TSV array can be formed, the signal lines can be wired between the power supply lines. In other words, a signal line can be wired between the TSV array adjacent to the signal TSV array. As a result, the wiring length from the PLL circuit to the memory controller can be shortened.

Embodiment 4 FIG.
In the above embodiments, the case where the memory controller controls the DRAMs 31 to 34 by dividing them into four channels has been described as an example. However, the present invention is not limited to this, and the DRAMs 31 to 34 may be controlled by being divided into two or more other division numbers. In one embodiment, the same number of memory controllers as the number of divisions may be arranged around the PLL circuit within a range of equal distances or allowable error distances. By adopting such an arrangement, it is possible to control each memory area of the DRAM divided by a plurality of memory controllers in synchronization. In addition, by arranging the memory controller around the PLL circuit, the wiring length of the clock signal line can be made shorter than when the PLL circuit is arranged around the outer periphery of the SoC.

Other Embodiments In the description of the above-described embodiment, the Wide IO DRAM is used as the semiconductor device in which a plurality of memories are stacked. However, the present invention is not limited to this. In the case of a semiconductor device in which a plurality of memories are stacked, it is effective to use the arrangement example of one embodiment.
In addition, the semiconductor devices described in the above embodiments can be configured in combination.

As described in the above embodiments, the semiconductor device of one embodiment has the following characteristics. The semiconductor device employs a configuration in which the PLL circuit is arranged at the center of the Wide IO TSV4 channel. In addition, the semiconductor device employs a configuration in which a clock signal is supplied to the memory controller through the TSV array in an H-tree. The clock tree preferably has a symmetrical clock tree configuration with respect to each channel.
The semiconductor device preferably employs a structure in which a PLL bump is arranged at the center of the Wide IO TSV4 channel. In order to pass the clock tree between the Wide IO TSVs, it is preferable to create a vertical wiring channel and arrange a clock buffer in that portion.
Further, it is preferable that the semiconductor device has a configuration in which a power supply mesh is formed by the power supplies VDD and VSS and the DRAM VDDQ and VSSQ in order to supply power to the clock buffer.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Not too long.

10 Substrate (package substrate)
20 SoC (System on Chip)
21 PLL circuit 22, 22-0 to 22-3 Memory controller 23-0 to 23-3 TSV array area 30 DRAM group (Wide IO DRAM group)
31-34 DRAM (Wide IO DRAM)
40 Multiple micro bumps 40S SoC side micro bump 40D DRAM side micro bump 50 Multiple through silicon vias (TSV)
50D direct access TSV
50P power supply TSV unit 50S signal TSV unit 60 substrate bump 71 repeater region 72 clock buffer 80, 100 semiconductor device 81 PLL circuits 83-86 first to fourth memory controllers

Claims (20)

A plurality of memory controllers for controlling a plurality of stacked memories;
And a PLL circuit in which the plurality of memory controllers are arranged around.   2. The semiconductor device according to claim 1, wherein the PLL circuit has a distance from each memory controller within a predetermined error range.   The semiconductor device according to claim 2, further comprising a plurality of through vias disposed between the plurality of memory controllers and the PLL circuit.   The semiconductor device according to claim 2, wherein the PLL circuit has the same distance from one end of each of the plurality of memory controllers.   4. The semiconductor device according to claim 3, further comprising a clock signal line for supplying a clock signal from the PLL circuit to the plurality of memory controllers through a region where the plurality of through vias are disposed.   6. The semiconductor device according to claim 5, wherein the clock signal lines are wired so as to form an H-type tree.   6. The semiconductor device according to claim 5, wherein the PLL circuit is arranged such that the lengths of the clock signal lines from the PLL circuit to each memory controller are the same.   The semiconductor device according to claim 5, wherein the clock signal line is horizontally symmetrical. The plurality of memories are composed of DRAM (Dynamic Random Access Memory),
Each memory is divided into multiple areas,
Each area is controlled by one of the plurality of memory controllers,
The semiconductor device according to claim 5, wherein the plurality of memory controllers control each region of the plurality of memories in accordance with a clock signal supplied from the clock signal line. The plurality of through vias are formed to correspond to the regions,
The plurality of through vias are composed of a plurality of through silicon vias (TSV), are formed to correspond to the respective regions, and function to supply either the power source or the signal to the corresponding respective regions. The semiconductor device according to claim 9. A first bump for supplying power to the PLL circuit;
The semiconductor device according to claim 3, wherein the first bump is disposed between the PLL circuit and a region where the plurality of through vias are disposed. A second bump for supplying power to the plurality of memories through the plurality of through vias;
The semiconductor device according to claim 11, wherein the second bump is disposed above a region where the plurality of through vias are disposed. A second bump for supplying power to the plurality of memories through the plurality of through vias;
The semiconductor device according to claim 11, wherein the second bump is disposed above a region where the plurality of memory controllers are disposed. A third bump for supplying a reference clock signal to the PLL circuit;
The semiconductor device according to claim 11, wherein the third bump is disposed between the PLL circuit and a region where the plurality of through vias are disposed.   The semiconductor device according to claim 5, wherein the clock signal line is wired between adjacent through vias.   16. The semiconductor device according to claim 15, wherein at least one of the adjacent through vias constitutes an array in which a plurality of through vias for supplying signals among the plurality of through vias are arranged. The plurality of through vias include a plurality of power through vias for supplying power and a plurality of signal through vias for supplying signals,
A signal via arrangement in which only the plurality of signal through vias are arranged in the same direction as the power supply line,
The semiconductor device according to claim 5, wherein the clock signal line is wired along the signal via array. A controller power supply line for supplying power to the plurality of memory controllers;
A memory power supply line that supplies power to the plurality of memories through the plurality of through vias, and
4. The semiconductor device according to claim 3, wherein the controller power supply line and the memory power supply line are wired in a grid pattern. The plurality of through vias include a plurality of power through vias that supply power to the plurality of memories, and a plurality of signal through vias that supply signals to the plurality of memories,
The semiconductor device according to claim 18, wherein a part of the plurality of signal through vias forms a signal via array arranged in the same direction as the memory power supply line.   The semiconductor device according to claim 19, wherein the signal via array does not include the power supply through via, and has a region where the memory power supply line is not wired between an array formed by a plurality of adjacent through vias. .

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