JP2015029021A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve performance of a semiconductor device by improving stability of operations at the time of writing and at the time of reading of an SRAM on an SOI substrate.SOLUTION: A manufacturing method of a semiconductor device comprises: composing a MOSFETQT2 for transfer which composes an SRAM on an SOI substrate; and forming a diffusion layer D2 into which a high-concentration p-type impurity is introduced on a top face of a semiconductor substrate SB just below a source-drain region connected to a storage node to make an impurity distribution in the semiconductor substrate SB be asymmetric centered on a region just below a gate electrode G1. Accordingly, a threshold voltage of the MOSFETQT2 for transfer at the time of writing of the SRAM is decreased and a threshold voltage at the time of reading of the SRAM is increased.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a technique effectively applied to a semiconductor device using an SOI (Silicon On Insulator) substrate and a method for manufacturing the same.

  Currently, a semiconductor device using an SOI substrate is used as a semiconductor device capable of suppressing short channel characteristics and element variations. In the SOI substrate, a BOX (Buried Oxide) film (buried oxide film) is formed on a support substrate made of high-resistance Si (silicon) or the like, and a thin layer (silicon layer) mainly containing Si (silicon) on the BOX film. , SOI layer). When a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on an SOI substrate, it is possible to suppress short channel characteristics without doping the channel layer with impurities. As a result, it is possible to improve mobility and to improve element variation due to impurity fluctuation. For this reason, by manufacturing a semiconductor device using an SOI substrate, it is possible to improve the integration density and operation speed of the semiconductor device and improve the operation margin by reducing variations.

  In an SRAM (Static Random Access Memory), which is a storage device having a transfer transistor, a load transistor, and a drive transistor, the operation of the SRAM is stabilized when the threshold voltage of the transfer transistor is low during writing. It is known that the effects of can be obtained. In addition, it is known that in the SRAM, when the threshold voltage of the transfer transistor is high at the time of reading, effects such as stabilization of the operation of the SRAM can be obtained.

  In Patent Document 1 (Japanese Patent Laid-Open No. 2011-228877), the impurity concentration in the semiconductor substrate under the MOSFET (Metal Oxide Semiconductor Field Effect Transistor) on the SOI structure substrate is made asymmetric in the gate length direction. Have been described.

  Patent Document 2 (Japanese Patent Laid-Open No. 2000-196103) describes that the impurity concentration in the substrate under the transistor which is an SOI element is asymmetric in the gate length direction.

  Patent Document 3 (Japanese Patent Laid-Open No. 2012-182478) describes that an SRAM access transistor is formed on an SOI substrate.

JP 2011-228677 A JP 2000-196103 A JP 2012-182478 A

  As the miniaturization of semiconductor devices progresses, for example, in an SRAM, it is required to improve the non-destructiveness of stored information and to improve the operation stability of the SRAM by reducing the driving voltage. It has been.

  Other objects and novel features will become apparent from the description of the specification and the accompanying drawings.

  Of the embodiments disclosed in the present application, the outline of typical ones will be briefly described as follows.

  A semiconductor device according to an embodiment forms a transfer MOSFET constituting an SRAM on an SOI substrate, and a high-concentration p-type impurity is formed on the upper surface of the semiconductor substrate immediately below the source / drain region connected to the storage node. Is formed, and the impurity distribution in the semiconductor substrate is asymmetrical with the region immediately below the gate electrode as an axis.

  Also, a method of manufacturing a semiconductor device according to an embodiment includes a transfer MOSFET that constitutes an SRAM on an SOI substrate, and is formed on a semiconductor substrate immediately below a region that forms a source / drain region connected to an accumulation node. A diffusion layer is formed by implanting high-concentration p-type impurities on the upper surface, and the impurity distribution in the semiconductor substrate is made asymmetrical with the region directly below the gate electrode as an axis.

  According to one embodiment disclosed in the present application, the performance of a semiconductor device can be improved. In particular, the driving voltage of the semiconductor device can be reduced.

1 is an equivalent circuit diagram showing a semiconductor device according to a first embodiment of the present invention. 2 is a plan layout showing the semiconductor device according to the first embodiment of the present invention; It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. FIG. 5 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 4. FIG. 6 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 5; FIG. 7 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 6; FIG. 8 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 7; FIG. 9 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 8. FIG. 10 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 9; FIG. 11 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 10; FIG. 12 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 11; FIG. 13 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 12; FIG. 14 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 13; FIG. 15 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 14; FIG. 16 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 15; It is sectional drawing which shows the manufacturing method of the semiconductor device which is a modification of Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. It is a plane layout which shows the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 3 of this invention. It is a plane layout which shows the semiconductor device which is Embodiment 4 of this invention. It is sectional drawing which shows the semiconductor device which is Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which is Embodiment 4 of this invention. FIG. 25 is a cross-sectional view showing a method for manufacturing the semiconductor device following FIG. 24;

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

(Embodiment 1)
In this embodiment mode, the driving transistor that constitutes the SRAM on the SOI substrate uses the fact that the source and the drain are interchanged by the writing operation and the reading operation. An explanation will be given of improving the characteristics of the SRAM by sometimes using an element having a high threshold voltage. As a specific method, the threshold voltage of each transfer transistor at the time of writing and at the time of reading is set by making the impurity concentration in the upper part of the support substrate under the transfer transistor asymmetric in the gate length direction. Change.

  Hereinafter, the structure of an SRAM on an SOI substrate including a plurality of MOS field effect transistors (hereinafter simply referred to as MOSFETs) according to the present embodiment will be described with reference to FIGS. FIG. 1 is an equivalent circuit diagram showing an SRAM memory cell MC according to the first embodiment. FIG. 2 is a planar layout showing a plurality of SRAM memory cells constituting the semiconductor device of the present embodiment. 3 is a cross-sectional view taken along line A1-A1 of FIG.

  First, an equivalent circuit of one memory cell constituting the SRAM will be described. As shown in FIG. 1, this memory cell MC is arranged at the intersection of a data line DL1 and a data line DL2, which are a pair of complementary data lines, that is, a pair of bit lines, and a word line WL1, and is a driving transistor. A load transistor and a transfer transistor. That is, the SRAM memory cell MC includes a pair of driving MOSFETs QD1 and QD2, a pair of load MOSFETs QP1 and QP2, and a pair of transfer MOSFETs QT1 and QT2. The driving MOSFETs QD1 and QD2 and the transfer MOSFETs QT1 and QT2 are constituted by n-channel MOSFETs, and the load MOSFETs QP1 and QP2 are constituted by p-channel MOSFETs.

  Of the six MOSFETs constituting the memory cell MC, the driving MOSFET QD1 and the load MOSFET QP1 constitute a CMOS (Complementary Metal Oxide Semiconductor) inverter INV1, and the driving MOSFET QD2 and the load MOSFET QP2 constitute a CMOS inverter INV2. doing. The storage nodes A and B which are mutual input / output terminals of the pair of CMOS inverters INV1 and INV2 are cross-coupled to form a flip-flop circuit as an information storage unit for storing 1-bit information. The storage node A, which is one input / output terminal of the flip-flop circuit, is connected to one of the source region and the drain region of the transfer MOSFET QT1, and the storage node B, which is the other input / output terminal, is connected to the transfer MOSFET QT2. It is connected to one of the source / drain regions.

  Further, the other of the source / drain regions of the transfer MOSFET QT1 is connected to the data line DL1, and the other of the source / drain regions of the transfer MOSFET QT2 is connected to the data line DL2. One end of the flip-flop circuit, that is, each source region of the load MOSFETs QP1 and QP2 is connected to the power supply voltage Vdd, and the other end, that is, each source region of the drive MOSFETs QD1 and QD2 is connected to the reference voltage Vss.

  Explaining the operation of the above circuit, when the storage node A of one CMOS inverter INV1 is at a high potential (H), the driving MOSFET QD2 is turned on, so that the storage node B of the other CMOS inverter INV2 is at a low potential (L )become. Therefore, the driving MOSFET QD1 is turned off, and the high potential (H) of the storage node A is held. That is, the state of the mutual storage nodes A and B is held by a latch circuit in which a pair of CMOS inverters INV1 and INV2 are cross-coupled, and information is stored while the power supply voltage is applied.

  A word line WL1 is connected to the gate electrodes of the transfer MOSFETs QT1 and QT2, and the conduction and non-conduction of the transfer MOSFETs QT1 and QT2 are controlled by the word line WL1. That is, when the word line WL1 is at a high potential (H), the transfer MOSFETs QT1 and QT2 are turned on, and the latch circuit and the complementary data lines (data lines DL1 and DL2) are electrically connected. The potential states (H or L) of the nodes A and B appear on the data lines DL1 and DL2, and are read as information of the memory cells MC.

  In the read operation, a current flows from the data line DL1 to the storage node A in the transfer MOSFET QT1, and a current flows from the data line DL2 to the storage node B in the transfer MOSFET QT2. That is, at the time of reading, the active regions of the transfer MOSFETs QT1 and QT2 are the source regions on the storage nodes A and B sides and the drain regions on the data lines DL1 and DL2 sides.

  In order to write information into the memory cell MC, the word line WL1 is set to the (H) potential level, the transfer MOSFETs QT1 and QT2 are turned on, and the information on the data lines DL1 and DL2 is transmitted to the storage nodes A and B. In this write operation, a current flows from the storage node A to the data line DL1 in the transfer MOSFET QT1, and a current flows from the storage node B to the data line DL2 in the transfer MOSFET QT2. That is, at the time of writing, the active regions of the transfer MOSFETs QT1 and QT2 are the source regions on the data lines DL1 and DL2 sides and the drain regions on the storage nodes A and B sides. As described above, the transfer MOSFETs QT1 and QT2 are elements in which the direction of current flow is changed by the operation of the SRAM, and the source region and the drain region are switched. As described above, the SRAM can be operated.

  Next, the layout configuration of the SRAM in this embodiment will be described. For example, as shown in FIG. 2, the SRAM memory cell MC includes a pair of drive MOSFETs QD1, QD2, a pair of load MOSFETs QP1, QP2 and a pair of transfer MOSFETs QT1, QT2 formed on an SOI substrate (not shown). 6 field effect transistors. FIG. 2 shows a structure in which a plurality of memory cells MC are arranged in the y direction (first direction) that is a direction along the main surface of the SOI substrate and in the x direction (second direction) orthogonal to the y direction.

  For easy understanding, the boundaries of the memory cells MC arranged in a matrix are shown separated by a two-dot chain line. The memory cells MC adjacent in the y direction or the x direction have a line-symmetric layout with the two-dot chain line as an axis.

  Here, the pair of driving MOSFETs QD1, QD2 and the pair of transfer MOSFETs QT1, QT2 are configured by n-channel MOSFETs, and the pair of load MOSFETs QP1, QP2 are configured by p-channel MOSFETs.

  The semiconductor layer above the SOI substrate is partitioned into a plurality of active regions AN1, AN2, AP1, and AP2 by element isolation regions (not shown). That is, the periphery of the active regions AN1, AN2, AP1, and AP2 is surrounded by the element isolation region, and the layout of these active regions is defined by the element isolation region. A plurality of active regions AN1, AN2, AP1, and AP2 extending in the y direction are arranged side by side in the x direction. The active regions AN1, AN2, AP1, and AP2 are configured by the SOI layer SL shown in FIG. 3, and the semiconductor substrate SB (see FIG. 3) as a support substrate is placed under each MOSFET shown in FIG. 3).

  As shown in FIG. 2, n-type impurities such as P (phosphorus) or As (arsenic) are introduced into the active regions AN1 and AN2 in the active regions AN1 and AN2 in which n-channel MOSFETs are formed. Thus, a source region and a drain region are formed. A gate electrode G1 is formed on the active region AN1 and AN2 between the source region and the drain region via a gate insulating film (not shown).

  The gate electrode G1 extends in the x direction intersecting the y direction in which each of the active regions AN1, AN2, AP1, and AP2 extends. An n-channel MOSFET is configured by the gate electrode G1 formed on the active region AN1 and AN2, and the source / drain regions formed in the active region AN1 and AN2 so as to sandwich the gate electrode G1. ing. Similarly, a p-channel MOSFET is formed by a gate electrode G1 formed on the active region AP1 and AP2, and a source / drain region formed in each of the active region AP1 and AP2 so as to sandwich the gate electrode G1. Is formed.

  For example, in the SRAM memory cell MC, the driving MOSFET QD1 and the transfer MOSFET QT1 are formed on the same active region AN1 by the source region and the drain region formed in the active region AN1 and the two gate electrodes G1. . Similarly, the driving MOSFET QD2 and the transfer MOSFET QT2 are formed on the same active region AN2 by the source and drain regions formed in the active region AN2 and the gate electrode G1. A load MOSFET QP1 is formed by the source and drain regions formed in the active region AP1 and the gate electrode G1. Similarly, a load MOSFET QP2 is formed by the source and drain regions formed in the active region AP2 and the gate electrode G1.

  In the load MOSFETs QP1 and QP2 that are p-channel MOSFETs, p-type impurities such as B (boron) are introduced into the gate electrode G1, and transfer MOSFETs QT1 and QT2, drive MOSFETs QD1 that are n-channel MOSFETs, and In QD2, an n-type impurity such as P (phosphorus) or As (arsenic) is introduced into the gate electrode G1. That is, p-type impurities such as B (boron) are introduced into the gate electrode G1 on the active region AP1 and AP2, and P (phosphorus) is introduced into the gate electrode G1 on the active region AN1 and AN2. Alternatively, an n-type impurity such as As (arsenic) is introduced.

  The memory cells MC adjacent in the x direction share the gate electrode G1 constituting the transfer MOSFET QT1 or QT2. The memory cells MC adjacent in the y direction share the active regions AN1 and AN2, and further share the active region AP1 or AP2. The active regions AN1 and AN2 have a width wider than that of the active regions AP1 and AP2 in the x direction, that is, the gate width direction.

  Contact plugs are connected to the active regions AN1, AN2, AP1, AP2 and the gate electrode G1. The active regions AP1 and AP2 are electrically connected to the gate electrode G1 by shared contact plugs at both ends in the y direction. The shared contact plug is a contact plug that extends over the gate electrode G1 and the active region AP1 or AP2.

  Here, as a feature of the present embodiment, p-type, that is, first conductivity type impurities are implanted at a relatively high concentration into a support substrate (not shown) in a region indicated by a broken line in FIG. A diffusion layer D2 is formed.

  A diffusion layer D2 formed in the vicinity of the upper surface of a semiconductor substrate (not shown) as a support substrate is a pair of source / drain regions constituting the transfer MOSFET QT1 in one memory cell MC. Of these, one of the source / drain regions is formed at a position overlapping with the source / drain region on the side of the adjacent driving MOSFET QD1 in plan view. Further, the diffusion layer D2 is one source / drain region of the pair of source / drain regions constituting the transfer MOSFET QT2 in one memory cell MC, and the source / drain on the adjacent drive MOSFET QD2 side. It is formed at a position overlapping with the region in plan view.

  That is, the diffusion layer D2 is formed immediately below the source / drain region connected to the storage node A or B (see FIG. 1) in the source / drain regions of the transfer MOSFETs QT1 and QT2. A region other than the region where the diffusion layer D2 is formed, that is, a region immediately below the source / drain regions of the transfer MOSFETs QT1 and QT2 connected to the data line DL1 or DL2 (see FIG. 1), for example, or for driving The impurity concentration of the support substrate in the region immediately below the source / drain regions of the MOSFETs QD1, QD2 is lower than that of the diffusion layer D2.

  In other words, the diffusion layer D2 in the semiconductor substrate SB in the vicinity of the source / drain region on the storage node side of the transfer MOSFET has a high p-type impurity concentration, and the semiconductor in the vicinity of the source / drain region on the data line side of the transfer MOSFET. The diffusion layer D3 (see FIG. 3) in the substrate SB has a low p-type impurity concentration. As described above, the diffusion layer D2 is used for the transfer from the region immediately below the gate electrode G1 constituting the transfer MOSFET QT1 or QT2 to the boundary between the transfer MOSFET QT1 or QT2 and the drive MOSFET QD1 or QD2. It is formed along the gate electrode G1 of the MOSFET QT1 or QT2.

  The structure of the semiconductor element of this embodiment having the diffusion layer D2 containing a high-concentration p-type impurity will be described below with reference to FIG. FIG. 3 is a sectional view in the gate length direction of the transfer MOSFET QT2 and the drive MOSFET QD2 arranged in the y direction shown in FIG. FIG. 3 shows a transfer MOSFET region 1A for forming two transfer MOSFETs QT2 and a drive MOSFET region 1B for forming a drive MOSFET QD2 in order from the left side of the drawing. In addition, a driving MOSFET QD2 is further formed in a region (not shown) on the right side of FIG. 3, and two driving MOSFETs QD2 are arranged side by side in the y direction in the same manner as the transfer MOSFET QT2.

  The transfer MOSFET region 1A is a region including two transfer MOSFETs QT2 arranged in the y direction, and the drive MOSFET region 1B is a region including two drive MOSFETs QD2 arranged in the y direction. FIG. 3 shows only one of the two drive MOSFETs QD2 formed in the drive MOSFET region 1B. A plurality of transfer MOSFET regions 1A and drive MOSFET regions 1B are alternately arranged in the y direction.

  As shown in FIG. 3, the semiconductor device of this embodiment includes an SOI substrate including a semiconductor substrate SB that is a support substrate, a BOX film BX on the semiconductor substrate SB, and an SOI layer SL that is a semiconductor layer on the BOX film. Have. The semiconductor substrate SB is a single crystal silicon substrate having a thickness of about 500 μm to 700 μm, for example, and having a high resistance of, for example, 750 Ωcm or more. The semiconductor substrate SB may be connected to the ground potential. The BOX film BX is made of, for example, a silicon oxide film, and the film thickness is 50 nm or less. Here, the thickness of the BOX film is 10 nm. The SOI layer SL is a semiconductor layer made of single crystal silicon having a resistance of about 1 to 10 Ωcm.

  Two transfer MOSFETs QT2 are formed side by side in the transfer MOSFET region 1A on the SOI substrate, and the drive MOSFET QD2 is formed in the drive MOSFET region 1B. Sharing area. Both the driving MOSFET QD2 and the transfer MOSFET QT2 have a gate electrode G1 formed on the SOI layer SL via a gate insulating film GF. The gate insulating film GF is made of, for example, a silicon oxide film and the gate electrode G1 is made of, for example, a polysilicon film. The side wall of the gate electrode G1 is covered with a sidewall SW having a stacked structure of a silicon oxide film and a silicon nitride film.

  The SOI layer SL immediately below the gate electrode G1, that is, the silicon layer is a channel region through which current flows when each MOSFET is driven, and a pair of sources are provided in the SOI layer SL next to the gate electrode G1 so as to sandwich the channel region. A drain region is formed. Each of the pair of source / drain regions has an extension region EX that is an n-type semiconductor layer and has a relatively low impurity concentration, and a diffusion layer D1 that is an n-type semiconductor layer and has an impurity concentration higher than that of the extension region EX. doing. Thus, the source / drain regions have an LDD (Lightly Doped Drain) structure including high-concentration and low-concentration impurity diffusion regions.

  The extension region EX and the diffusion layer D1 are implanted with n-type, that is, second conductivity type impurities (for example, P (phosphorus) or As (arsenic)). The extension region EX is formed in a region closer to the channel region than the diffusion layer D1. That is, the formation position of the extension region EX is closer to the gate electrode G1 than the formation position of the diffusion layer D1.

  On the SOI layer SL exposed from the gate insulating film GF, the gate electrode G1, and the sidewall SW, that is, on the diffusion layer D1, an epitaxial layer EP stacked by the epitaxial growth method is formed. Also in the epitaxial layer EP, a high concentration n-type impurity is implanted to form a diffusion layer D1. A silicide layer S1 is formed on the upper surface of the epitaxial layer EP and the upper surface of the gate electrode G1. The silicide layer S1 is made of, for example, CoSi (cobalt silicide).

  An insulating film ES and an interlayer insulating film CL are sequentially stacked on the SOI substrate so as to cover the driving MOSFET QD2 and the transfer MOSFET QT2. A plurality of contact holes are formed so as to penetrate the interlayer insulating film CL and the insulating film ES, and contact plugs CD, CN, or CP are connected to the plurality of contact holes. The insulating film ES is made of, for example, a silicon nitride film, and functions as an etching stopper film when forming contact holes. The interlayer insulating film CL is made of, for example, a silicon oxide film, and the upper surface thereof is flattened at the same height as the upper surfaces of the contact plugs CD, CN, and CP.

  Each of the contact plugs CD, CN, and CP is a columnar conductor having a similar structure, and is formed, for example, with a barrier conductor film covering a side wall and a bottom surface in the contact hole, and in the contact hole via the barrier conductor film. And a main conductor film completely filling the contact hole. The barrier conductor film includes, for example, Ti (titanium) or TiN (titanium nitride), and the main conductor film is made of, for example, W (tungsten). In FIG. 3, the contact plugs CD, CN and CP are all connected to the source / drain regions of the MOSFETs via the silicide layer S1 and the epitaxial layer EP. As shown in FIG. 2, contact plugs are also connected to the source / drain regions of the other active regions and the gate electrode G1.

  As shown in FIG. 3, the contact plug CD connected to the source / drain region shared by the transfer MOSFETs QT2 arranged in the y direction is connected to the data line DL2 (see FIG. 1) shown in FIG. Further, the contact plug CN connected to the source / drain region shared by the transfer MOSFET QT2 and the drive MOSFET QD2 arranged in the y direction is connected to the storage node B (see FIG. 1). A contact plug CP is connected to the source / drain region of the driving MOSFET QD2, which is not connected to the contact plug CD. The contact plug CP is connected to the reference voltage (Vss) shown in FIG.

  On the interlayer insulating film CL and the contact plugs CD, CN and CP, an interlayer insulating film IL made of, for example, SiOC is formed. In the interlayer insulating film IL, a plurality of wiring grooves that expose the upper surfaces of the contact plugs CD, CN, and CP are formed, and a wiring M1 is formed in each wiring groove. The wiring M1 includes, for example, a barrier conductor film that covers a side wall and a bottom surface in the wiring groove, and a main conductor film that is formed in the wiring groove via the barrier conductor film and completely fills the wiring groove. The barrier conductor film includes, for example, Ta (tantalum) or TaN (tantalum nitride), and the main conductor film is made of, for example, Cu (copper). The wiring M1 is connected to the contact plug CD, CN or CP.

In the semiconductor substrate SB, in the vicinity of the upper surface of the semiconductor substrate SB, a P well WL which is a diffusion layer into which a relatively low concentration p-type impurity (for example, B (boron)) is implanted is formed. The concentration of the p-type impurity in the P well WL is, for example, about 10 ¹⁶ / cm ³ . Here, the P well is uniformly formed near the upper surface of the semiconductor substrate SB across the transfer MOSFET region 1A and the drive MOSFET region 1B. However, the transfer MOSFET region 1A and the drive MOSFET region 1B The concentration of the P well or the impurity implantation depth may be changed.

Here, as a feature of the semiconductor device of this embodiment, a p-type impurity (for example, B (boron)) is implanted at a relatively high concentration in the semiconductor substrate SB and in the vicinity of the upper surface of the semiconductor substrate SB. Thus, the p-type diffusion layer D2 is formed. Further, in the semiconductor substrate SB, in the vicinity of the upper surface of the semiconductor substrate SB, a p-type impurity (for example, B (boron)) is implanted at a relatively low concentration, whereby a p-type diffusion layer D3 is formed. Yes. The concentration of the p-type impurity in the diffusion layer D2 is, for example, 10 ¹⁸ / cm ³ or more and 10 ¹⁹ / cm ³ or less. The concentration of the p-type impurity in the diffusion layer D3 is, for example, 10 ¹⁷ / cm ³ or more and less than 10 ¹⁸ / cm ³ .

  The diffusion layers D2 and D3 are formed shallower than the main surface of the semiconductor substrate SB as compared with the P well WL. That is, the P well WL is formed deeper than the diffusion layers D2 and D3. As described above, the concentration of the p-type impurity in the P well WL is lower than that of the diffusion layers D2 and D3. Further, the concentration of the p-type impurity in the diffusion layer D2 is higher than that of the diffusion layer D3.

  The diffusion layers D2 and D3 are formed immediately below the transfer MOSFET QT2, and the diffusion layer D3 is also formed immediately below the drive MOSFET QD2. Immediately below the transfer MOSFET QT2, the boundary between the diffusion layer D2 and the diffusion layer D3 in the y direction is directly below the gate electrode G1. Here, a boundary between the diffusion layer D2 and the diffusion layer D3 exists immediately below the center of the gate electrode G1 in the y direction.

  That is, in the semiconductor substrate SB in the vicinity of the upper surface of the semiconductor substrate SB, there are a first region and a second region arranged in the gate length direction of the transfer MOSFET QT2 with the region immediately below the gate electrode G1 as a boundary. Is formed with a diffusion layer D2, and a diffusion layer D3 is formed in the second region. Thereby, the concentration of the p-type impurity in each of the first region and the second region is different. That is, the first region is a relatively high concentration p-type semiconductor region, and the second region is a relatively low concentration p-type semiconductor region.

  The diffusion layer D2 is formed immediately below the source / drain region connected to the storage node B (see FIG. 1) of the pair of source / drain regions constituting the transfer MOSFET QT2, and the diffusion layer D3 The source / drain region is formed immediately below the source / drain region connected to the data line DL2 (see FIG. 1). That is, the diffusion layer D2 is formed immediately below one source / drain region of the gate electrode G1 of the transfer MOSFET QT2, and the contact plug CN is connected to the source / drain region, and immediately below the other source / drain region. A diffusion layer D3 is formed on the source / drain region, and a contact plug CD is connected to the source / drain region.

  Thus, the diffusion layers D2 and D3 having different impurity concentrations are formed in the semiconductor substrate SB immediately below the pair of source / drain regions constituting the transfer MOSFET QT2. That is, a p-type semiconductor layer is formed on the semiconductor substrate SB immediately below the transfer MOSFET QT2, and the impurity concentration of the p-type semiconductor layer in the gate length direction is asymmetric with respect to the axis immediately below the gate electrode G1. It has become.

  Also, as shown in FIG. 1, the transfer MOSFET QT1 paired with the transfer MOSFET QT2 has the same structure as the transfer MOSFET QT2 described above. That is, although not shown in the drawing, a p-type diffusion having a high impurity concentration is formed on the upper surface of the semiconductor substrate immediately below the source / drain region connected to the storage node A among the source / drain regions constituting the transfer MOSFET QT1. The p-type diffusion layer formed on the upper surface of the semiconductor substrate immediately below one of the source / drain regions has an impurity concentration lower than the impurity concentration.

  Here, in the transfer MOSFET region 1A and the drive MOSFET region 1B, the transfer MOSFET QT2 and the drive MOSFET QD2 are insulated from the semiconductor substrate SB via the BOX film BX. That is, the diffusion layer D2 and the driving MOSFET QT2 are not electrically connected via a plug or the like penetrating the BOX film BX. That is, the diffusion layer D2 does not constitute a circuit and is insulated from the SOI layer SL.

  As described above with reference to FIG. 1, in the channel region of the transfer MOSFET QT2 shown in FIG. 3, during the SRAM write operation, the storage node B (see FIG. 1) side goes to the data line DL2 (see FIG. 1) side. Current flows. That is, the active region connected to the storage node B via the contact plug CN becomes a source region, and the active region connected to the data line DL2 via the contact plug CD becomes a drain region.

  Further, in the read operation of the information stored in the SRAM, a current flows in the opposite direction to the above in the channel region of the transfer MOSFET QT2. That is, during the read operation, a current flows from the data line DL2 side toward the storage node B side. That is, the active region connected to the data line DL2 via the contact plug CD is a source region accumulation, and the active region connected to the storage node B via the contact plug CN is a drain region.

  Here, in the SRAM, there is a problem that the performance of writing information to the SRAM and the non-destructive performance of the stored information at the time of reading become remarkable due to the miniaturization of the device and the lowering of the drive voltage. That is, if the drive voltage is too low, information may not be written to the SRAM at the time of writing. Further, when the drive voltage is reduced and the current is reduced, the stored information may be destroyed during reading.

  The above problem can be improved by adjusting the threshold voltage of the transfer MOSFET constituting the SRAM. That is, in the write operation, even if the drive voltage is low, information can be written more reliably if the threshold voltage of the transfer MOSFET is low. In the read operation, even if the drive voltage is low, if the threshold voltage of the transfer MOSFET is high, information can be read while avoiding destruction of stored information. Thus, if the failure of writing and the destruction of information at the time of reading can be prevented by lowering the driving voltage, the power saving and miniaturization of the SRAM can be achieved, so that the performance of the semiconductor device is improved. Can do.

  In the present embodiment, the threshold voltage of the transfer MOSFET can be changed at the time of writing and reading using the following two characteristics. That is, the direction in which the current of the transfer MOSFET flows is changed by the write or read operation, and the threshold voltage of the MOSFET changes depending on the impurity concentration in the vicinity of the channel region. The point that the impurity concentration of the semiconductor layer in the vicinity of the layer is dominantly used. Note that the fact that the source region is dominant with respect to the change in threshold voltage means that the impurity concentration of the semiconductor layer in the vicinity of the drain region does not significantly affect the threshold voltage of the MOSFET.

  At the time of reading from the SRAM, a semiconductor region that is located immediately above the high-concentration diffusion layer D2 and includes the diffusion layer D1 connected to the storage node B serves as a source region. In this case, since the diffusion layer D2 having a high impurity concentration is formed in the vicinity of the source region, the threshold voltage of the transfer MOSFET QT2 increases. This utilizes the characteristic that the threshold voltage of the MOSFET increases as the impurity concentration of the channel increases.

  Even if the diffusion layer D2 having a high impurity concentration exists under the source region via the BOX film BX, if the thickness of the BOX film BX is small, the threshold voltage of the transfer MOSFET QT2 is influenced by the diffusion layer D2. Receive. Therefore, in the present embodiment, the thickness of the BOX film BX is set to 50 nm or less in order to increase the threshold voltage of the transfer MOSFET QT2 due to the presence of the diffusion layer D2.

  As described above, since the threshold voltage of the transfer MOSFET QT2 at the time of reading increases, even if the value of the voltage applied to the data line DL2 is small, the information stored in the SRAM can be read without being destroyed.

  At the time of SRAM writing, a semiconductor region that is located immediately above the low-concentration diffusion layer D3 and includes the diffusion layer D1 connected to the data line DL2 serves as a source region. In this case, since the diffusion layer having a high impurity concentration such as the diffusion layer D2 is not formed in the vicinity of the source region, the threshold voltage of the transfer MOSFET QT2 becomes low.

  Thus, since the threshold voltage of the transfer MOSFET QT2 at the time of writing becomes low, information can be written to the SRAM even when the voltage applied to the storage node B, that is, the value of the power supply voltage Vdd is small. That is, it is possible to prevent the information from being difficult to be written to the SRAM due to the drive voltage being lowered and the current being reduced.

  In this embodiment mode, as described above, it is possible to prevent a writing failure and a destruction of information at the time of reading by lowering the driving voltage, so that the operation of the SRAM formed on the SOI substrate can be stabilized. The power saving and miniaturization of the SRAM can be realized. Therefore, the performance of the semiconductor device can be improved. Although the transfer MOSFET QT2 has been described here, the same applies to the transfer MOSFET QT1 (see FIGS. 1 and 2) not shown in FIG.

  Next, a method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 4 to 16 are cross-sectional views showing the method for manufacturing the semiconductor device of the present embodiment, and show a cross-section at the same position as in FIG.

  First, as shown in FIG. 4, a semiconductor substrate SB is prepared in which a BOX film BX and an SOI layer SL are sequentially stacked above. The semiconductor substrate SB is a support substrate made of Si (silicon), the BOX film BX on the semiconductor substrate SB is a silicon oxide film, and the SOI layer SL on the BOX film BX has a resistance of about 1 to 10 Ωcm. It is the layer which consists of. In this embodiment mode, the thickness of the BOX film BX needs to be 50 nm or less, and thus the thickness is set to 10 nm as an example here.

The SOI substrate including the semiconductor substrate SB, the BOX film BX, and the SOI layer SL can be formed by a SIMOX (Silicon Implanted Oxide) method. In other words, O ₂ (oxygen) is ion-implanted with high energy into the main surface of the semiconductor substrate SB made of Si (silicon), and Si (silicon) and oxygen are combined in a subsequent heat treatment, so that the surface is slightly smaller than the surface of the semiconductor substrate. An SOI substrate can be formed by forming a buried oxide film (BOX film) at a deep position. In addition, the SOI substrate is formed by bonding a semiconductor substrate SB having an oxide film formed thereon and another semiconductor substrate made of Si (silicon) by applying high heat and pressure, and then bonding the silicon substrate on one side. It can also be formed by polishing and thinning the layer.

  Next, in a region not shown, an element isolation region is formed using a known method. The element isolation region is a trench opening in the upper surface of the SOI substrate, and is made of an insulating film embedded in the trench reaching the upper surface of the BOX film BX or the intermediate depth of the semiconductor substrate SB.

Next, p-type impurities (for example, B (boron)) are implanted into the semiconductor substrate SB at a relatively low concentration by an ion implantation method, so that P extends from the upper surface of the semiconductor substrate SB to a relatively deep region of the semiconductor substrate SB. A well WL is formed. Note that a p-well is not formed in the formation region of the load MOSFET, which is a p-channel MOSFET (not shown), and n-type impurities (for example, P (phosphorus) or As (arsenic)) are implanted at a low concentration. N well is formed. The concentration of the p-type impurity (for example, B (boron)) in the P well WL is, for example, about 10 ¹⁶ / cm ³ .

Next, as shown in FIG. 5, a p-type impurity (for example, B (boron)) is implanted into the semiconductor substrate SB at a relatively low concentration by an ion implantation method, thereby comparing the semiconductor substrate SB from the upper surface of the semiconductor substrate SB. A diffusion layer D3 is formed over a shallow region. The diffusion layer D3 is formed at a depth shallower than the P well WL in the transfer MOSFET region 1A and the drive MOSFET region 1B. The concentration of the p-type impurity in the diffusion layer D3 is, for example, 10 ¹⁷ / cm ³ or more and less than 10 ¹⁸ / cm ³ . This ion implantation process is performed in a state where a region for forming a load MOSFET, which is a p-channel MOSFET, is covered with a mask such as a photoresist pattern.

  Next, as shown in FIG. 6, a photoresist pattern RP1 is formed on the SOI substrate by using a well-known photolithography technique. The photoresist pattern RP1 is formed from a region overlapping the gate electrode of the transfer MOSFET formed in a later step in plan view, and the gate of the drive MOSFET formed adjacent to the transfer MOSFET in the later step. It is a film exposing a range up to an intermediate region with the electrode. That is, the photoresist pattern RP1 is a film that covers a region between the gate electrodes of two transfer MOSFETs to be formed in the transfer MOSFET region 1A in a later step, and further covers the entire drive MOSFET region 1B. .

  In other words, the opening of the photoresist pattern RP1 exposes a region from the region where the gate electrode is later formed in the transfer MOSFET region 1A to the boundary between the transfer MOSFET region 1A and the drive MOSFET region 1B. That is, the photoresist pattern RP1 is opened so as to expose a region overlapping with one of the source / drain regions of the transfer MOSFET formed in a later step in plan view. A region exposed in the opening of the photoresist pattern RP1 is within a range surrounded by a broken line shown in FIG.

Subsequently, by using the photoresist pattern RP1 as a mask, a p-type impurity (for example, B (boron)) is implanted into the semiconductor substrate SB at a relatively high concentration by an ion implantation method, so that the semiconductor substrate SB is formed from the upper surface of the semiconductor substrate SB. A diffusion layer D2 is formed over a relatively shallow region. The diffusion layer D2 is formed at a shallower depth than the P well WL in the transfer MOSFET region 1A. The concentration of the p-type impurity in the diffusion layer D2 is, for example, 10 ¹⁸ / cm ³ or more and 10 ¹⁹ / cm ³ or less. That is, the diffusion layer D2 has a higher impurity concentration than the diffusion layer D3.

Next, as shown in FIG. 7, after removing the photoresist pattern RP1, a silicon oxide film is formed on the SOI layer SL by using a thermal oxidation method or a CVD (Chemical Vapor Deposition) method. Thereafter, a polysilicon film and a silicon nitride (Si ₃ N ₄ ) film are sequentially formed on the silicon oxide film by using a CVD method or the like, and then the silicon nitride film is patterned by using a photolithography technique and a dry etching method. Thus, an insulating film HM made of a silicon nitride film is formed. Subsequently, the polysilicon film and the silicon oxide film are patterned by a dry etching method using the insulating film HM as a hard mask. Thereby, the gate insulating film GF made of the silicon oxide film is formed on the SOI layer SL, and the gate electrode G1 made of the polysilicon film is formed on the gate insulating film GF.

  The polysilicon film constituting the gate electrode G1 is a low-resistance n-type semiconductor film (doped polysilicon film) by ion-implanting an n-type impurity such as P (phosphorus) or As (arsenic). It is said that. The polysilicon film, which was an amorphous silicon film at the time of film formation, can be changed to a polycrystalline silicon film by heat treatment after film formation (after ion implantation). Here, in the transfer MOSFET region 1A, the gate insulating film GF, the gate electrode G1, and the insulating film HM are formed immediately above the boundary between the diffusion layer D2 and the diffusion layer D3.

Next, as shown in FIG. 8, a silicon oxide film O1 and a silicon nitride (Si ₃ N ₄ ) film N1 are formed using, for example, a CVD method so as to cover the upper surface of the SOI layer SL, the insulating film HM, and the gate electrode G1. A laminated film is formed by sequentially depositing. Thereafter, anisotropic etching is performed by an RIE (Reactive Ion Etching) method or the like to remove a part of the stacked film including the silicon oxide film O1 and the silicon nitride film N1, and to remove the upper surface of the SOI layer SL and the upper surface of the insulating film HM. To expose. As a result, a sidewall-like laminated film composed of the silicon oxide film O1 and the silicon nitride film N1 is formed on the side wall of the gate electrode G1 in a self-aligning manner.

  Here, the silicon oxide film O1 is an insulating film for forming a sidewall, and the silicon nitride film N1 is a dummy used for forming an epitaxial layer, that is, a selective growth layer in a position separated from the gate electrode in a later step. It is an insulating film constituting the sidewall. That is, the laminated film composed of the silicon oxide film O1 and the silicon nitride film N1 forms a dummy sidewall, and the silicon oxide film O1 remains but the silicon nitride film N1 does not remain in the completed semiconductor device. Note that the gate electrode G1 and the dummy sidewall adjacent thereto do not completely cover the diffusion layer D2 formed immediately below them in plan view.

  Next, as shown in FIG. 9, an epitaxial growth method is used to form an epitaxial layer mainly made of Si (silicon) on the upper surface of the SOI layer SL exposed from the gate electrode G1, the silicon oxide film O1, and the silicon nitride film N1. Layer EP is formed. As a result, an epitaxial layer EP, which is a silicon layer whose upper surface is higher than the SOI layer SL, is formed in a lateral region in the y direction with respect to the structure including the gate electrode G1, the silicon oxide film O1, and the silicon nitride film N1. Is done. The epitaxial layer EP is formed with a thickness of 20 to 50 nm at a position spaced from the side wall of the gate electrode G1.

  The epitaxial layer EP is formed beside the gate electrode G1 because the SOI layer SL is extremely thin. That is, one of the reasons for forming the epitaxial layer EP is that it is necessary to supplement the thickness of the SOI layer SL constituting the source / drain region when forming the silicide layer.

  Next, as shown in FIG. 10, the insulating film HM above the gate electrode G1 and the silicon nitride film N1 that is an insulating film for forming the dummy sidewall are removed by wet etching.

  Next, as shown in FIG. 11, an n-type impurity (for example, P (phosphorus) or As (arsenic)) is implanted into the SOI layer SL at a relatively low concentration by ion implantation using the gate electrode G1 as a mask. Thus, an extension region EX is formed on the upper surface of the SOI layer SL and the epitaxial layer EP exposed beside the gate electrode G1 and the gate insulating film GF. The extension region EX is not formed on a part of the upper surface of the SOI layer SL immediately below the gate electrode G1. Further, since the impurity ions implanted in this ion implantation process pass through the silicon oxide film O1 having a thickness of about 5 nm, the extension region EX is also formed in the SOI layer SL immediately below the silicon oxide film O1.

  Next, as shown in FIG. 12, a silicon nitride film N2 is formed so as to cover the exposed surfaces of the gate electrode G1, the silicon oxide film O1, the SOI layer SL, and the epitaxial layer EP by using, for example, the CVD method. To do. Thereafter, the silicon nitride film N2 is partially removed by performing anisotropic etching by the RIE method or the like, and the upper surfaces of the gate electrode G1 and the epitaxial layer EP are exposed. As a result, the silicon nitride film N2 is formed in a self-aligned manner on the side wall of the gate electrode G1 via the silicon oxide film O1, and the sidewall SW including the silicon oxide film O1 and the silicon nitride film N2 is formed.

  Next, as shown in FIG. 13, n-type impurities (for example, P (phosphorus) or As (arsenic)) are ionized at a relatively high concentration from above the semiconductor substrate SB using the gate electrode G1 and the sidewall SW as a mask. By implantation, a diffusion layer D1 is formed in the epitaxial layer EP and the SOI layer SL exposed from the gate electrode G1, the silicon oxide film O1, and the silicon nitride film N2. The extension region EX and the diffusion layer D1 are semiconductor regions constituting source / drain regions. In the source / drain region, an extension region EX including a low concentration impurity is provided between the diffusion layer D1 into which the impurity is introduced at a high concentration and the SOI layer SL which is a channel region immediately below the gate electrode G1. It has an LDD structure. That is, the impurity concentration of the diffusion layer D1 is higher than the impurity concentration of the extension region EX.

  As described above, the transfer MOSFET QT2 and the drive MOSFET QD2, which are n-channel MOSFETs including the gate electrode G1, and the source / drain regions including the extension region EX and the diffusion layer D1, are formed. The transfer MOSFET QT2 is formed in the transfer MOSFET region 1A, and the drive MOSFET QD2 is formed in the drive MOSFET region 1B.

  A transfer MOSFET QT1 and a driving MOSFET QD1 (see FIGS. 1 and 2) having the same structure are formed in other regions not shown. The transfer MOSFET QT1 and the drive MOSFET QD1 adjacent in the y direction share one of the source / drain regions. In other regions not shown, p-channel load MOSFETs QP1 and QP2 (see FIGS. 1 and 2) having a conductivity type different from that of the n-channel MOSFET are also formed.

  Here, in the semiconductor substrate SB directly below the transfer MOSFET QT2, in the vicinity of the upper surface of the semiconductor substrate SB, the diffusion layer D2 and the diffusion layer are diffused in the gate length direction with the region immediately below the gate electrode G1 of the transfer MOSFET QT2 as a boundary. The layer D3 is formed side by side. That is, on the upper surface of the semiconductor substrate SB immediately below the transfer MOSFET QT2, the diffusion layer D2 is formed immediately below one of the pair of source / drain regions of the transfer MOSFET QT2, and the diffusion layer D3 is formed immediately below the other. The boundary between the diffusion layers D2 and D3 is immediately below the center of the gate electrode G1 in the gate length direction.

  The diffusion layer D2 is a semiconductor that extends from a region immediately below the gate electrode G1 of the transfer MOSFET QT2 to a region immediately below an intermediate region between the gate electrode G1 and the gate electrode G1 of the drive MOSFET QD2 adjacent to the transfer MOSFET QT2. It is formed on the upper surface of the substrate SB. This structure is the same in the transfer MOSFET QT1.

  Next, as shown in FIG. 14, after the silicide layer S1 is formed on the gate electrode G1 and the epitaxial layer EP by using a well-known salicide technique, the transfer MOSFET QT2 and the drive MOSFET QD2 are replaced with the insulating film ES and the interlayer insulating film. Cover sequentially with CL. The silicide layer S1 is made of, for example, CoSi (cobalt silicide), and the insulating film ES made of, for example, a silicon nitride film and the interlayer insulating film CL made of, for example, a silicon oxide film are formed by a CVD method or the like. Thereafter, the upper surface of the interlayer insulating film CL is polished and planarized by, for example, a CMP (Chemical Mechanical Polishing) method.

  Next, as shown in FIG. 15, the insulating film ES is used as an etching stopper film, and the interlayer insulating film CL and the insulating film ES are opened by using a photolithography technique and a dry etching method, whereby the upper surface of the silicide layer S1 is formed. A plurality of contact holes are formed to expose. Thereafter, a barrier conductor film containing, for example, Ti (titanium) or TiN (titanium nitride) and a main conductor film made of, for example, W (tungsten) are sequentially formed by using, for example, a sputtering method to completely form each contact hole. Embed in. Subsequently, the barrier conductor film and the main conductor film are polished by, for example, a CMP method to expose the upper surface of the interlayer insulating film CL, so that the contact made of the barrier conductor film and the main conductor film embedded in the plurality of contact holes. Plugs CD, CN and CP are formed.

  Of the pair of source / drain regions of the driving MOSFET QD2, the contact plug CN is connected to the source / drain region shared with the transfer MOSFET QT2, and the contact plug CP is connected to the other source / drain region of the driving MOSFET QD2. The The contact plug CD is connected to the source / drain region of the pair of source / drain regions of the transfer MOSFET QT2 to which the contact plug CN is not connected. The layout shown in FIG. 2 is formed by the above process.

  Next, as shown in FIG. 16, an interlayer insulating film IL and a wiring M1 are formed on the interlayer insulating film CL. The interlayer insulating film IL is made of, for example, SiOC, and is formed by, for example, a CVD method. When the wiring M1 is formed, first, the interlayer insulating film IL is opened using a photolithography technique and a dry etching method, thereby forming a plurality of wiring grooves that expose the upper surfaces of the contact plugs CD, CN, and CP. To do.

  Thereafter, a barrier conductor film containing, for example, Ta (tantalum) or TaN (tantalum nitride) and a main conductor film made of, for example, Cu (copper) are sequentially formed by using, for example, a sputtering method to completely form each wiring groove. Embed in. Thereafter, the barrier conductor film and the main conductor film are polished by, for example, a CMP method to expose the upper surface of the interlayer insulating film IL, whereby the wiring M1 including the barrier conductor film and the main conductor film embedded in the plurality of wiring grooves. Form. Through the above steps, the semiconductor device of this embodiment is completed.

  By performing the above steps, an SRAM including transfer MOSFETs QT1 and QT2, drive MOSFETs QD1 and QD2, and load MOSFETs QP1 and QP2 shown in FIGS. 1 and 2 is formed.

  As described with reference to FIGS. 1 to 3, the semiconductor device according to the present embodiment is one source / drain region of the transfer MOSFET, directly below the source / drain region connected to the storage node. In this semiconductor substrate, a diffusion layer in which p-type impurities are implanted at a high concentration is formed.

  In the above configuration, as shown in FIG. 16, when writing to the SRAM, the p-type impurity concentration of the semiconductor substrate SB in the vicinity of the source region of the transfer MOSFET QT2, that is, the diffusion layer D3 is low. The voltage goes down. Therefore, information can be written to the SRAM even if the value of the voltage applied to the storage node B (see FIG. 1) is small. That is, it is possible to prevent the information from being difficult to be written to the SRAM due to the drive voltage being lowered and the current being reduced.

  At the time of reading from the SRAM, the semiconductor substrate SB in the vicinity of the source region of the transfer MOSFET QT2, that is, the p-type impurity concentration of the diffusion layer D2, is high, so that the threshold voltage of the transfer MOSFET QT2 is high. For this reason, even if the value of the voltage applied to the data line DL2 is small, the information stored in the SRAM can be read without being destroyed. Note that the film thickness of the BOX film BX needs to be 50 nm or less in order to form the high concentration diffusion layer D2 in a region close to the source region.

  In this embodiment mode, as described above, writing failure due to a low driving voltage and destruction of information at the time of reading can be prevented, so that power saving and miniaturization of an SRAM formed on an SOI substrate can be prevented. It becomes possible. Therefore, the performance of the semiconductor device can be improved. Although the transfer MOSFET QT2 has been described here, the transfer MOSFET QT1 (see FIGS. 1 and 2) not shown in FIG. 16 is also provided with a diffusion layer D2 to form a p-type impurity in the semiconductor substrate SB immediately below the transfer MOSFET QT1. By making the concentration asymmetric, the same effect as described above can be obtained.

  Here, the p-type impurity is implanted from above the SOI substrate by ion implantation or the like to form the diffusion layer D2. However, when a pattern is formed on the SOI substrate when performing this ion implantation, a semiconductor is formed. It becomes difficult to perform ion implantation uniformly on the upper surface of the substrate SB, and part of impurities may be implanted into the SOI region. When impurities are excessively introduced into the SOI layer SL in this manner, it becomes difficult for current to flow in the channel between the source region and the drain region, which causes a problem that variations in element characteristics occur.

  On the other hand, in the manufacturing process of the semiconductor device of this embodiment, the p-type is formed by an ion implantation method or the like in the state described with reference to FIG. 6 in a state where a pattern such as a gate electrode is not formed on the SOI substrate. Since the diffusion layer D2 is formed by implanting impurities, the p-type impurity can be prevented from being implanted into the SOI layer SL. That is, here, since the ion implantation for forming the diffusion layers D2 and D3 is performed before the pattern is formed on the SOI substrate, the semiconductor substrate having a predetermined depth, that is, the semiconductor substrate SB is targeted. Impurities can be uniformly implanted into the upper surface of the SB.

  Next, a modification of the semiconductor device of this embodiment is described with reference to FIGS. FIG. 17 shows a cross-sectional view of a variation of the semiconductor device of this embodiment. In FIG. 17, the cross section of the same location as FIG. 3 is shown.

  The semiconductor device of the modification shown in FIG. 17 has substantially the same structure as that of the SRAM described above with reference to FIGS. 1 to 16 except that the diffusion layer D3 is not formed. That is, in the manufacturing process of the semiconductor device according to the modification, the formation process of the diffusion layer D3 described with reference to FIG. 5 is not performed. For this reason, the manufacturing process of the semiconductor device can be simplified.

  Also in this modification, the same effect as the SRAM described above with reference to FIGS. 1 to 16 can be obtained. In other words, by lowering the threshold voltage of the transfer MOSFET QT2 at the time of writing and increasing it at the time of reading, the operation can be stabilized even when the SRAM is operated at a low driving voltage. Even if the diffusion layer D3 is not provided, the concentration of the p-type impurity in the semiconductor substrate SB in the vicinity of the source region at the time of writing of the transfer MOSFET QT2 can be made lower than that of the diffusion layer D2. This is because the threshold voltage of the transfer MOSFET QT2 can be lowered.

  Since the diffusion layer D3 (see FIG. 3) is not formed in the present modification shown in FIG. 17, the diffusion layers D2 and P are formed on the upper surface of the semiconductor substrate SB directly below the transfer MOSFET QT2 with the boundary immediately below the gate electrode G1 as a boundary. A well WL is formed. The P well WL is a semiconductor region having a lower p-type impurity concentration than the diffusion layers D2 and D3. As described above, the above-described effect can be obtained by making the p-type impurity concentration of the semiconductor substrate SB asymmetrical immediately below the gate electrode G1.

(Embodiment 2)
The semiconductor device of the present embodiment has the same structure as the device described in the first embodiment, but its manufacturing method is different from that of the first embodiment. Specifically, the step of forming the diffusion layers D2 and D3 shown in FIG. 3 is performed not after the step of forming the gate electrode G1 but after the formation of the gate electrode G1 in this embodiment. This is different from Form 1. Below, the manufacturing process of the semiconductor device of this Embodiment is demonstrated using FIG.

  In the manufacturing process of the semiconductor device of the present embodiment, first, the P well WL and the diffusion layer D3 are formed on the upper surface of the semiconductor substrate SB constituting the SOI substrate by performing the steps described with reference to FIGS. To do.

  Next, the gate electrode G1, the silicon oxide film O1, and the epitaxial layer EP are formed on the SOI substrate by performing the steps described with reference to FIGS. That is, since the process described with reference to FIG. 6 is not performed here, the diffusion layer D2 is not formed when the process described with reference to FIG. 10 is performed. Next, the extension region EX is formed by performing the process described with reference to FIG.

  Next, as shown in FIG. 18, a photoresist pattern RP2 is formed on the SOI substrate by using a well-known photolithography technique. The photoresist pattern RP2 is formed from a region overlapping with the gate electrode G1 of the transfer MOSFET formed in a later process in plan view, and adjacent to the transfer MOSFET in the later process. This is a film exposing a range up to an intermediate region with the gate electrode G1. That is, the photoresist pattern RP2 is a film that covers a region between the two gate electrodes G1 formed in the transfer MOSFET region 1A and further covers the entire driving MOSFET region 1B.

  In other words, the opening of the photoresist pattern RP2 exposes a region from the region immediately above the gate electrode G1 of the transfer MOSFET region 1A to the boundary between the transfer MOSFET region 1A and the drive MOSFET region 1B. That is, the photoresist pattern RP2 is opened so as to expose a region overlapping with one of the source / drain regions of the transfer MOSFET formed in a later step in plan view. The region exposed in the opening of the photoresist pattern RP2 is within the range surrounded by the broken line shown in FIG. Thus, the photoresist pattern RP2 has the same layout as the photoresist pattern RP1 shown using FIG.

  Here, the region between the adjacent gate electrodes G1 in the transfer MOSFET region 1A is exposed from the photoresist pattern RP2. Both ends of the photoresist pattern RP2 terminate immediately above the centers in the y direction of the two gate electrodes G1 of the transfer MOSFET region 1A. Therefore, in the opening of the photoresist pattern RP2 in the transfer MOSFET region 1A, a part of the upper surface of the gate electrode G1 is exposed from the photoresist pattern RP2 in plan view.

  Subsequently, by using the photoresist pattern RP2 and the gate electrode G1 as a mask, a p-type impurity (for example, B (boron)) is implanted into the semiconductor substrate SB at a relatively high concentration by an ion implantation method. A diffusion layer D2 is formed over a relatively shallow region of the semiconductor substrate SB. The concentration and the formation location of the diffusion layer D2 are the same as those described with reference to FIG.

  In this ion implantation process, not only the photoresist pattern RP2 but also the gate electrode G1 exposed from the photoresist pattern RP2 is used as a mask. However, some of the impurities implanted by ion implantation are introduced into the upper surface of the semiconductor substrate SB through the gate electrode G1, the gate insulating film GF, the SOI layer SL, and the BOX film BX. In addition, a part of the impurity that has passed through the side of the gate electrode G1 and penetrated the SOI layer SL and the BOX film BX and introduced into the upper surface of the semiconductor substrate SB diffuses in the lateral direction in the semiconductor substrate SB. As a result, impurities are also introduced into the upper surface of the semiconductor substrate SB immediately below the gate electrode G1. Therefore, the boundary between the diffusion layer D2 and the diffusion layer D3 is present immediately below the gate electrode G1 in the present embodiment as in the first embodiment.

  Thereafter, the same process as that described with reference to FIGS. 12 to 16 is performed, whereby a semiconductor device having a structure similar to the structure shown in FIG. 16 is completed. As described above, the semiconductor device formed in the present embodiment has the same structure as the semiconductor device described in the first embodiment. Therefore, in the semiconductor device of the present embodiment, the same effects as those of the semiconductor device of the first embodiment described with reference to FIGS. 1 to 3 can be obtained.

  Further, when the semiconductor device manufacturing method of the present embodiment is used, the diffusion layers D2 and D3 shown in FIG. 18 are formed, and the threshold voltage of the transfer MOSFET QT2 at the time of writing and reading is adjusted. Similar to the first embodiment, the effect of enabling writing at a low voltage and preventing the destruction of data at the time of reading is obtained.

  Here, in the manufacturing method of the semiconductor device of the present embodiment, the diffusion layer D2 is formed after the gate electrode G1 is formed. As described above, in the ion implantation process for forming the diffusion layer D2, since the gate electrode G1 exposed from the photoresist pattern RP2 is used as a mask, the position of the end portion of the diffusion layer D2 formed in the semiconductor substrate SB is It is determined in a self-aligned manner with respect to the shape of the gate electrode G1. For this reason, it is possible to obtain an effect that the position of the boundary between the diffusion layers D2 and D3 under the transfer MOSFET QT2 is not easily displaced with respect to the pattern of the gate electrode G1.

  Therefore, in the manufacturing method of the semiconductor device of the present embodiment, since the formation position of the diffusion layer D2 is defined by the gate electrode G1, even if a deviation occurs in the formation position of the photoresist pattern RP2, the diffusion layer D2 It is possible to prevent the formation position from being shifted. Therefore, variation in the formation position of the diffusion layer D2 with respect to the gate electrode G1 can be prevented, so that variation in MOSFET characteristics can be prevented.

  Here, the formation of the diffusion layer D2 is described after the extension region EX is formed. However, the diffusion layer D2 is formed after the step of removing the silicon nitride film N1 (see FIG. 9) described with reference to FIG. Therefore, it may be formed before the extension region EX forming step described with reference to FIG.

  Further, as described with reference to FIG. 17 in the first embodiment, the structure in which the diffusion layer D3 is not formed may also be employed in the semiconductor device of the present embodiment.

(Embodiment 3)
The semiconductor device of the present embodiment will be described below with reference to FIGS. FIG. 19 is a planar layout showing a plurality of SRAM memory cells constituting the semiconductor device of the present embodiment. 20 is a cross-sectional view taken along line A1-A1 of FIG.

  As shown in FIGS. 19 and 20, the structure of the semiconductor device of the present embodiment is almost the same as that of the first embodiment. However, the diffusion layer D2 includes not only the transfer MOSFET region 1A but also the drive MOSFET region 1B. It differs from the first embodiment in that it extends to the lower part. In FIG. 19, the outline of the diffusion layer D2 is indicated by a broken line. As indicated by the broken line, the diffusion layer D2 is formed not only in the semiconductor substrate near the gate electrodes G1 of the transfer MOSFETs QT1 and QT2, but also in the semiconductor substrate immediately below the drive MOSFETs QD1 and QD2.

  In other words, the diffusion layer D2 is formed in the semiconductor substrate that overlaps the region between the two gate electrodes G1 constituting each of the two transfer MOSFETs QT2 adjacent to each other with the two drive MOSFETs QD2 in the y direction in plan view. It is formed near the upper surface of the semiconductor substrate.

  As shown in FIG. 20, in the transfer MOSFET region 1A, a diffusion layer D3 that terminates immediately below the gate electrode G1 of each transfer MOSFET QT2 between adjacent transfer MOSFETs QT2 without sandwiching the drive MOSFET QD2 therebetween. Is formed. The above configuration is the same in the region where the transfer MOSFET QT1 and the drive MOSFET QD1 are provided (see FIG. 19). Note that the diffusion layer D3 may not be formed as in the modification described with reference to FIG. 17 in the first embodiment.

  In the semiconductor device of the present embodiment, the same effect as that of the first embodiment can be obtained by making the impurity concentration of the semiconductor substrate SB immediately below the transfer MOSFETs QT1 and QT2 asymmetric in the gate length direction. Further, a diffusion layer D2 having a p-type impurity concentration higher than that of the P well WL and the diffusion layer D3 is formed on the entire upper surface of the semiconductor substrate SB immediately below the driving MOSFET QD2, so that the area under the channel regions of the driving MOSFETs QD1 and QD2 is reduced. Since the p-type impurity concentration can be increased, the short channel characteristics of the driving MOSFETs QD1 and QD2 immediately above the diffusion layer D2 can be improved. Thereby, the performance of the semiconductor device can be improved.

  Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIG. FIG. 21 is a cross-sectional view showing the method of manufacturing the semiconductor device of the present embodiment, and shows a cross section at the same position as FIG.

  In the manufacturing process of the semiconductor device of the present embodiment, first, the P well WL and the diffusion layer D3 are formed on the upper surface of the semiconductor substrate SB constituting the SOI substrate by performing the steps described with reference to FIGS. To do.

  Next, as shown in FIG. 21, a photoresist pattern RP3 is formed on the SOI substrate by using a well-known photolithography technique. The photoresist pattern RP3 is a film that covers a region between the gate electrodes of two transfer MOSFETs to be formed in one transfer MOSFET region 1A in a later process. The other regions and the driving MOSFET region 1B are exposed from the photoresist pattern RP3.

  In other words, the opening portion of the photoresist pattern RP3 opens between two adjacent transfer MOSFET regions 1A across the drive MOSFET region 1B in the y direction, and the source of the transfer MOSFET formed in a later step. Of the drain region, the region forming the source / drain region at the end in the y direction between the transfer MOSFET regions 1A is exposed. The region exposed in the opening of the photoresist pattern RP3 is within the range surrounded by the broken line shown in FIG.

  Subsequently, using the photoresist pattern RP3 as a mask, a p-type impurity (for example, B (boron)) is implanted into the semiconductor substrate SB at a relatively high concentration by an ion implantation method, so that the semiconductor substrate SB is formed from the upper surface of the semiconductor substrate SB. A diffusion layer D2 is formed over a relatively shallow region. In the transfer MOSFET region 1A, the formation depth of the P well WL and the concentration of the p-type impurity in the diffusion layers D2, D3 and the P well WL are the same as those in the first embodiment.

  The diffusion layer D2 thus formed is also formed in the driving MOSFET region 1B in addition to the same region as that of the first embodiment described with reference to FIG. Thus, the difference between the present embodiment and the first embodiment is that the diffusion layer D2 is formed so as to extend over the entire driving MOSFET region 1B.

  Thereafter, the steps described with reference to FIGS. 7 to 16 are performed, whereby the semiconductor device of the present embodiment shown in FIGS. 19 and 20 is completed.

  When the semiconductor device manufacturing method of the present embodiment is used, as described above with reference to FIGS. 19 and 20, the same effects as those of the first embodiment can be obtained, and the driving MOSFETs QD1 and QD2 can be obtained. Short channel characteristics can be improved. Thereby, the performance of the semiconductor device can be improved.

  Further, the opening of the photoresist pattern RP3 shown in FIG. 21 is larger than the opening of the photoresist pattern RP1 shown in FIG. Thus, compared with the case where the diffusion layer D2 is formed only in the transfer MOSFET region 1A (see FIG. 6), in the manufacturing process of the semiconductor device of the present embodiment, the photoresist pattern RP3 for forming the diffusion layer D2 is used. Therefore, the ion implantation for forming the diffusion layer D2 is facilitated. That is, since the opening of the photomask is large, impurities can be implanted more uniformly into the surface to be ion-implanted. Therefore, it is possible to prevent the impurity concentration of the diffusion layer D2 from varying, and thus it is possible to prevent the characteristics of the transfer MOSFET QT2 from varying.

  Here, as in the first embodiment, the step of forming the diffusion layer D2 before the formation of the gate electrode G1 has been described. However, as in the second embodiment, the diffusion layer D2 is formed after the formation of the gate electrode G1. May be formed.

(Embodiment 4)
In the present embodiment, an n-type impurity (for example, As (arsenic) or P (phosphorus)) having a conductivity type opposite to that of the p-type is implanted into the semiconductor substrate, so that the semiconductor substrate immediately below the transfer MOSFET. An explanation will be given of making the distribution of the impurities in the inside asymmetric.

  First, the semiconductor device of this embodiment will be described with reference to FIGS. FIG. 22 is a plan layout showing a plurality of SRAM memory cells constituting the semiconductor device of the present embodiment. 23 is a cross-sectional view taken along line A1-A1 of FIG.

  As shown in FIGS. 22 and 23, the structure of the semiconductor device of the present embodiment is almost the same as that of the first embodiment, but in this embodiment, diffusion layers D2 and D3 (see FIGS. 2 and 3). Is not formed. Here, as shown in FIGS. 22 and 23, a diffusion layer D4, which is a semiconductor layer in which an n-type impurity is implanted, and a p-type diffusion layer D5 described later are formed in the semiconductor substrate SB.

  In FIG. 22, the outline of the diffusion layer D4 formed in the semiconductor substrate (not shown) in plan view is indicated by a broken line. Diffusion layer D4 is formed in a region overlapping in plan view with a region between two gate electrodes G1 constituting each of transfer MOSFETs QT2 adjacent in the y direction. As shown in FIGS. 22 and 23, the diffusion layer D4 is formed in the semiconductor substrate SB within the semiconductor substrate SB so as to overlap with a source / drain region shared by two adjacent transfer MOSFETs QT2 in plan view. It is formed near the upper surface. Both ends of the diffusion layer D4 are terminated just below the center in the y direction of the respective gate electrodes G1 of the two transfer MOSFETs QT2.

  Further, as shown in FIG. 23, a diffusion layer D5 into which a p-type impurity (for example, B (boron)) is introduced at a relatively high concentration is formed in the semiconductor substrate SB and in the vicinity of the upper surface of the semiconductor substrate SB. ing. In the transfer MOSFET region 1A and the drive MOSFET region 1B, the diffusion layer D5 is formed on the upper surface of the semiconductor substrate SB other than the region where the diffusion layer D4 is formed. That is, the region where the diffusion layer D5 is formed in the transfer MOSFET region 1A and the drive MOSFET region 1B is the same as the diffusion layer D2 (see FIG. 20) described in the third embodiment. The region where the diffusion layer D4 is formed in the transfer MOSFET region 1A and the drive MOSFET region 1B is the same as the diffusion layer D3 (see FIG. 20) described in the third embodiment.

The concentration of the p-type impurity in the diffusion layer D5 is, for example, 10 ¹⁷ / cm ³ or more and 10 ¹⁹ / cm ³ or less. The concentration of the n-type impurity in the diffusion layer D4 is, for example, 10 ¹⁶ / cm ³ or more and 10 ¹⁷ / cm ³ or less. The impurity concentration of the P well WL is the same as that in the first embodiment. That is, the concentration of the p-type impurity in the diffusion layer D5 is higher than that of the P well WL. Further, it is conceivable that p-type impurities are distributed in the diffusion layer D4, but the concentration of the p-type impurities in the diffusion layer D4 is lower than the concentration of the p-type impurities in the diffusion layer D5. The formation depth of the diffusion layers D4 and D5 is the same as that of the diffusion layers D2 and D3 (see FIGS. 2 and 3), and is shallower than the formation depth of the P well WL.

  In the first embodiment, the concentration of the p-type impurity in the semiconductor substrate under the transfer MOSFET is made asymmetric by implanting the p-type impurity into a specific region on the upper surface of the semiconductor substrate. On the other hand, in this embodiment, the concentration of the p-type impurity in the semiconductor substrate under the transfer MOSFET is reduced by implanting an n-type impurity into a specific region on the upper surface of the semiconductor substrate on which the p-type semiconductor layer is formed. It is intended to be asymmetric.

  Here, as shown in FIG. 23, the diffusion which is an n-type semiconductor layer in the source / drain region of the transfer MOSFET QT2 immediately below the source / drain region connected to the data line via the contact plug CD. A layer D4 is formed, and a diffusion layer D5 into which a high-concentration p-type impurity is implanted is formed in other regions on the upper surface of the semiconductor substrate SB. That is, the diffusion layer D5 is formed immediately below the source / drain region of the transfer MOSFET QT2 connected to the storage node via the contact plug CN.

  Since the diffusion layer D4 having a p-type impurity concentration lower than that of the diffusion layer D5 exists immediately below the source region of the transfer MOSFET QT2 at the time of SRAM writing, the threshold voltage of the transfer MOSFET QT2 becomes low. Further, since the diffusion layer D5 having a p-type impurity concentration higher than the diffusion layer D4 exists immediately below the source region of the transfer MOSFET QT2 at the time of reading from the SRAM, the threshold voltage of the transfer MOSFET QT2 becomes low. In this way, it is possible to adjust the threshold voltage of the transfer MOSFET QT2 in which the source region and the drain region are switched during writing and reading.

  By reducing the threshold voltage of the transfer MOSFET QT2 at the time of writing, information can be written to the SRAM even when the value of the voltage applied to the storage node B is small. That is, it is possible to prevent the information from being difficult to be written to the SRAM due to the drive voltage being lowered and the current being reduced.

  Further, by increasing the threshold voltage of the transfer MOSFET QT2 at the time of reading, even if the value of the voltage applied to the data line DL2 (see FIG. 1) is small, the information stored in the SRAM is read without being destroyed. be able to.

  In this embodiment mode, as described above, it is possible to prevent a writing failure and a destruction of information at the time of reading by lowering the driving voltage, so that the operation of the SRAM formed on the SOI substrate can be stabilized. The power saving and miniaturization of the SRAM can be realized. Therefore, the performance of the semiconductor device can be improved. Although the transfer MOSFET QT2 has been described here, the transfer MOSFET QT1 (see FIG. 22) not shown in FIG. 23 also has the same structure as the transfer MOSFET QT2, and the above effects can be obtained.

  Here, in order to realize the asymmetric structure of the p-type impurity, the p-type impurity is not implanted into the semiconductor substrate SB immediately below each of the pair of source / drain regions of the transfer MOSFET QT2 at different concentrations. A structure in which an n-type impurity is implanted into a part of the semiconductor substrate SB on which the diffusion layer D5 is formed is used. Therefore, the difference in impurity concentration between the diffusion layers D4 and D5 under the transfer MOSFET QT2 becomes large, and the change in the threshold voltage of the transfer MOSFET QT2 during writing and reading becomes significant.

  That is, the threshold voltage of the transfer MOSFET QT2 is lower during writing, and the threshold voltage of the transfer MOSFET QT2 is higher during reading. As a result, it is possible to perform the write operation and the read operation more stably than in the case where p-type impurities are implanted at different concentrations into the semiconductor substrate SB immediately below the pair of source / drain regions of the transfer MOSFET QT2. is there.

  Next, the manufacturing process of the semiconductor device of this embodiment will be described with reference to FIGS. 24 and 25 are cross-sectional views showing the method of manufacturing the semiconductor device of the present embodiment, and show a cross section at the same position as in FIG.

  In the manufacturing process of the semiconductor device of the present embodiment, first, the P well WL is formed on the upper surface of the semiconductor substrate SB constituting the SOI substrate by performing the process described with reference to FIG.

Next, as shown in FIG. 24, the semiconductor substrate SB is compared with the semiconductor substrate SB from the upper surface of the semiconductor substrate SB by implanting a p-type impurity (for example, B (boron)) at a relatively high concentration by ion implantation. A diffusion layer D5 is formed over a shallow region. The diffusion layer D5 is formed at a depth shallower than the P well WL in the transfer MOSFET region 1A and the drive MOSFET region 1B. The concentration of the p-type impurity in the diffusion layer D5 is, for example, 10 ¹⁷ / cm ³ or more and 10 ¹⁹ / cm ³ or less. This ion implantation process is performed in a state where a region for forming a load MOSFET, which is a p-channel MOSFET, is covered with a mask such as a photoresist pattern.

  Next, as shown in FIG. 25, a photoresist pattern RP4 is formed on the SOI substrate by using a well-known photolithography technique. The photoresist pattern RP4 is a film that exposes a region between the gate electrodes of two transfer MOSFETs to be formed in the transfer MOSFET region 1A in a later process, and other regions in the transfer MOSFET region 1A. The region for forming the load MOSFET and the drive MOSFET region 1B are covered with a photoresist pattern RP4.

  Subsequently, by using the photoresist pattern RP4 as a mask, an n-type impurity (for example, As (arsenic) or P (phosphorus)) is implanted into the semiconductor substrate SB at a relatively high concentration by an ion implantation method. The diffusion layer D4 is formed over a relatively shallow region of the semiconductor substrate SB. The diffusion layer D4 is formed in the same region as the diffusion layer D3 described with reference to FIG. 20 in the transfer MOSFET region 1A. Thus, in this embodiment, the diffusion layer D5 having a high p-type impurity concentration is formed by the process described with reference to FIG. 24, and the diffusion layer D4 having a low p-type impurity concentration is formed by the process described using FIG. Form. The boundary between the diffusion layers D4 and D5 in the y direction exists in a region immediately below the gate electrode G1 formed in a later step.

  Thereafter, the steps described with reference to FIGS. 7 to 16 are performed, whereby the semiconductor device of the present embodiment shown in FIGS. 22 and 23 is completed.

When the method for manufacturing a semiconductor device of the present embodiment is used, the effect described above with reference to FIGS. 22 and 23 is obtained by making the p-type impurity concentration of the semiconductor substrate SB immediately below the transfer MOSFET QT2 asymmetric. Can do. Further, when the concentration of the p-type impurity in the diffusion layer D5 is, for example, 10 ¹⁸ / cm ³ or more, the short channel characteristics of the driving MOSFETs QD1 and QD2 can be improved as in the second embodiment.

  Note that the transfer MOSFET QT1 (see FIG. 22) not shown in FIG. 23 is also provided with diffusion layers D4 and D5 so that the p-type impurity concentration of the semiconductor substrate SB immediately below the transfer MOSFET QT1 is asymmetrical. An effect similar to the effect can be obtained.

  Although the step of forming the diffusion layer D4 before the formation of the gate electrode G1 has been described here as in the first embodiment, the diffusion layer D4 is formed after the formation of the gate electrode G1 as in the second embodiment. May be formed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

1A Transfer MOSFET region 1B Drive MOSFET region AN1, AN2, AP1, AP2 Active region BX BOX film CD, CN, CP Contact plug CL Interlayer insulating film D1-D5 Diffusion layer EP Epitaxial layer ES Insulating film EX Extension region G1 Gate electrode GF Gate insulating film HM Insulating film IL Interlayer insulating film M1 Wiring O1 Silicon oxide film N1, N2 Silicon nitride film QD1, QD2 Driving MOSFET
QP1, QP2 Load MOSFET
QT1, QT2 Transfer MOSFET
RP1 to RP4 Photoresist pattern SB Semiconductor substrate SL SOI layer (silicon layer)
SW side wall WL P well

Claims (16)

A semiconductor substrate having a first region and a second region in the vicinity of the upper surface;
A first insulating film on the semiconductor substrate;
A semiconductor layer on the first insulating film;
A gate electrode formed on the semiconductor layer via a second insulating film;
A pair of source / drain regions formed by introducing a first conductivity type impurity into a semiconductor layer next to the gate electrode;
Have
The semiconductor substrate, the first insulating film, and the semiconductor layer constitute an SOI substrate,
The gate electrode and the source / drain region constitute a field effect transistor,
The first region and the second region are arranged with a region immediately below the gate electrode as a boundary in the gate length direction of the field effect transistor,
The semiconductor device, wherein an impurity concentration of the first conductivity type in the first region is different from an impurity concentration of the first conductivity type in the second region. The semiconductor device according to claim 1,
The first region is a semiconductor region of the first conductivity type;
The second region is a semiconductor region of the first conductivity type,
The semiconductor device, wherein the first region has an impurity concentration of the first conductivity type higher than that of the second region. The semiconductor device according to claim 2,
In the semiconductor substrate near the upper surface of the semiconductor substrate, the formation depth is deeper than that of the first region and the second region, and the impurity concentration of the first conductivity type is higher than that of the first region and the second region. A semiconductor device in which a low diffusion layer is formed. The semiconductor device according to claim 1,
The first region is a semiconductor layer of the first conductivity type,
The semiconductor device, wherein the second region is a semiconductor layer of a second conductivity type different from the first conductivity type. The semiconductor device according to claim 1,
The semiconductor device, wherein the first region is present immediately below one of the pair of source / drain regions, and the second region is present immediately below the other. The semiconductor device according to claim 1,
The semiconductor device, wherein the field effect transistor is an element in which a source region and a drain region are switched by an operation of a circuit including the field effect transistor. The semiconductor device according to claim 6.
An SRAM including a driving transistor, a load transistor and a transfer transistor;
The field effect transistor is the transfer transistor;
The first region exists immediately below the source / drain region shared by the transfer transistor and the driving transistor adjacent to each other in the pair of source / drain regions,
The semiconductor device, wherein the first region has an impurity concentration of the first conductivity type higher than that of the second region. The semiconductor device according to claim 7.
The semiconductor device, wherein the first region exists immediately below the driving transistor adjacent to the transfer transistor. (A1) A semiconductor substrate having a first region and a second region adjacent to each other in a predetermined direction in the vicinity of the upper surface, a first insulating film formed on the semiconductor substrate, and formed on the first insulating film A step of preparing an SOI substrate constituted by the formed semiconductor layer;
(B1) implanting impurities of the first conductivity type into the first region;
(C1) forming a gate electrode on the semiconductor layer via a second insulating film;
(D1) forming a field effect transistor including the gate electrode and the source / drain region by forming a pair of source / drain regions in the semiconductor layer beside the gate electrode;
Have
A method of manufacturing a semiconductor device, wherein the first region and the second region arranged in the gate length direction of the field effect transistor with the region immediately below the gate electrode as a boundary have different impurity concentrations of the first conductivity type. . In the manufacturing method of the semiconductor device according to claim 9,
A method for manufacturing a semiconductor device, wherein the step (b1) is performed before the step (c1). In the manufacturing method of the semiconductor device according to claim 9,
A method of manufacturing a semiconductor device, wherein the step (b1) is performed after the step (c1) and before the step (d1). In the manufacturing method of the semiconductor device according to claim 9,
(A2) further comprising a step of implanting the first conductivity type impurity into the second region;
The method of manufacturing a semiconductor device, wherein the first region has an impurity concentration of the first conductivity type higher than that of the second region. In the manufacturing method of the semiconductor device according to claim 9,
(A3) further comprising a step of implanting an impurity of a second conductivity type different from the first conductivity type into the second region;
The method of manufacturing a semiconductor device, wherein the first region has an impurity concentration of the first conductivity type higher than that of the second region. In the manufacturing method of the semiconductor device according to claim 9,
The method of manufacturing a semiconductor device, wherein the field effect transistor is an element in which a source region and a drain region are switched by an operation of a circuit including the field effect transistor. 15. The method of manufacturing a semiconductor device according to claim 14,
An SRAM including a driving transistor, a load transistor and a transfer transistor;
The field effect transistor is the transfer transistor;
The first region exists immediately below the source / drain region shared by the transfer transistor and the driving transistor adjacent to each other in the pair of source / drain regions,
The method of manufacturing a semiconductor device, wherein the first region has an impurity concentration of the first conductivity type higher than that of the second region. In the manufacturing method of the semiconductor device according to claim 15,
The method of manufacturing a semiconductor device, wherein the first region exists immediately below the driving transistor adjacent to the transfer transistor.

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