JP2015015409A - Semiconductor device - Google Patents

Abstract

An object of the present invention is to suppress an increase in Cgd while reducing a gate resistance, thereby improving a high-frequency gain of a semiconductor device.
A source wiring having a pad electrode, a drain wiring having a pad electrode, a contact, a source electrode, a drain electrode, and a first gate on a substrate having an FET layer structure formed thereon. An electrode 112 and a second gate electrode 114 are formed. One end portions of the first gate electrode 112 and the second gate electrode 114 are connected by a first gate wiring 116 which is a signal input portion, and the other end portion is a second gate which is a termination portion. They are connected by wiring 118. The source wiring 100, the drain wiring 104, the first gate electrode 112, and the second gate electrode 114 are arranged in parallel to each other in the longitudinal direction.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a field effect transistor, and more particularly to a semiconductor device used for a high-frequency amplifier that amplifies a high-frequency signal.

  In a base station of a wireless communication device such as a mobile phone, a high frequency amplifier is used to amplify a transmission signal. The high frequency amplifier includes a control unit, an input / output matching unit, an amplification element, and the like. In order to improve the performance of the high-frequency amplifier, the characteristics of the amplifying element that is an element for amplifying a signal are particularly important.

  The amplifying element includes an internal matching circuit, a field effect transistor (hereinafter referred to as FET: Field Effect Transistor), and a package for mounting them. In FETs for high frequency amplification applications, increasing the gain in the high frequency band is extremely important. When the high-frequency gain of the FET is low, it is necessary to have a multistage amplifier configuration in which elements are connected in multiple stages in order to obtain a desired signal amplification factor. However, the power consumption increases as the number of stages increases, amplifiers become larger due to the increase in size of amplification elements and heat dissipation devices, and the matching adjustment between stages of each element becomes complicated and the design becomes complicated. . That is, it is desirable that the number of stages is small, and it is extremely important to increase the gain of the FET. In general, a comb structure is an advantageous structure for increasing the gain. Here, the comb structure will be described. When the gate resistance is large in the FET, the input signal input from the gate is attenuated and the gain is reduced. In the comb structure, the gate resistance of each finger is reduced by connecting a large number of FETs with short gate finger lengths in parallel. The number of fingers is designed according to the desired output power.

  In the comb structure, the gate resistance decreases as the finger length is shortened. However, shortening the fingers increases the number of fingers connected in parallel to obtain a desired output power. That is, the shorter the finger length, the longer the element length in the direction perpendicular to the finger, and the larger the aspect ratio of the semiconductor chip forming the FET. If the aspect ratio is too large, problems such as chip breakage during conveyance in the manufacturing process occur. Further, when a semiconductor chip is mounted on a package, there is a certain error in the mounting position, but the error in the wire length increases as the lateral width of the chip increases. During high frequency operation, the inductance component of the wire cannot be ignored, and when the wire length error becomes large as described above, the input impedance differs depending on the position in the chip, and the uniformity of the operation is impaired. That is, problems such as non-uniform current density occur between FETs connected in parallel and a region where the temperature is locally high occur. Thus, since there is an upper limit to the aspect ratio that can be practically selected, there is a limit to the reduction in gate resistance even if the comb structure is adopted. On the other hand, in the field of wireless communication, further increase in communication frequency is accelerating, and further reduction in gate resistance is desired for higher gain in the high frequency band.

  As a method for reducing the gate resistance, an approach such as increasing the gate length (thickening the electrode) or increasing the electrode film thickness can be considered. However, in the FET, the shorter the gate length, the smaller the parasitic capacitance and the higher the high frequency gain. Further, if the electrode film thickness is large, microfabrication becomes difficult and the gate length cannot be shortened. That is, although the gate resistance can be lowered by the above-described approach, the parasitic capacitance increases due to the increase in the length of the gate, so that it cannot be a solution for increasing the gain.

  As a method for reducing the gate resistance in the comb structure, a structure shown in FIG. 10 has been proposed (Patent Document 1). The FET of FIG. 10 includes a gate wiring pattern that connects the input ends of the gate electrodes connected in parallel and a gate wiring pattern that connects the terminal ends of the gate electrodes, and connects the two gate wiring patterns. The feeder line is provided. By providing a power supply line, signals can be input from both ends of the gate, the effective finger length can be shortened, and the effective gate resistance can be reduced.

JP-A-7-142512

  In the prior art of FIG. 7, the gate wiring pattern connecting the terminal portions of the gate electrode intersects with the drain wiring, and the gate-drain parasitic capacitance (hereinafter referred to as Cgd) increases. Cgd forms a feedback path from the drain wiring as the output terminal to the gate electrode as the input terminal. Therefore, if Cgd is large, the amplified output signal is fed back to the input side, and the high-frequency gain is reduced. Therefore, the conventional technique has a problem that the improvement of the high frequency gain due to the reduction of the gate resistance is partially offset by the increase of Cgd, and a sufficient improvement effect cannot be obtained.

  Therefore, in view of such problems, an object of the present invention is to provide an FET having a good high-frequency gain by suppressing an increase in Cgd while reducing gate resistance.

  In order to solve the above-described problem, an FET of the present invention includes first and second gate electrodes arranged in parallel with a first direction, and in parallel with a second direction perpendicular to the first direction. A first gate wiring disposed and electrically connecting one end of the first gate electrode and one end of the second gate electrode; and parallel to the second direction, the first gate A second gate wiring that electrically connects the other end of the electrode and the other end of the second gate electrode and the first and second gate electrodes are arranged in parallel with the first direction. And a power supply line that electrically connects the first gate wiring and the second gate wiring, and is disposed between the power supply line and the first gate electrode in parallel with the first direction. Between the first source wiring and the feeder line and the second gate electrode, the first wiring is arranged in parallel with the first direction. Second and a source wiring of a semiconductor layer located below the feed line is inactive region, wherein said first and second gate lines does not intersect either the drain wiring.

  In the present invention, the source wiring of the comb FET is divided into two parts, the first and second source wirings, and the power supply line is provided between them, so that the source wiring and the power supply line do not intersect. When the power supply line intersects with the source wiring, the gate-source parasitic capacitance (hereinafter, Cgs) increases. When Cgs increases, a part of the input signal input from the gate leaks to the source wiring that is the ground terminal, so that the high-frequency gain decreases. Therefore, an increase in Cgs is undesirable. As described above, in the present invention, an increase in Cgs due to the addition of the feeder line can be minimized.

  In addition, when the semiconductor layer located below the power supply line is an active region, the power supply line and the source wiring are electrically coupled via the active region, and Cgs increases. Therefore, it is desirable that the semiconductor layer located below the feeder line is an inactive region. The inactive region is formed by inactivating the semiconductor layer by ion implantation, for example.

  Furthermore, as described above, an increase in Cgd is undesirable because it causes a decrease in high-frequency gain. In the present invention, since the drain wiring and the gate wiring do not intersect, the increase in Cgd can be minimized.

  Thus, according to the present invention, the effective finger length can be shortened and the gate resistance can be reduced while suppressing an increase in Cgs and Cgd. That is, the improvement of the high frequency gain by reducing the gate resistance is not impaired by the increase of Cgs and Cgd.

  Note that the feeder line may be formed directly on the inactive semiconductor layer, but in order to further reduce Cgs by further increasing the shielding of electrical coupling with the source wiring, an insulating layer is formed on the semiconductor layer, A power supply line may be formed on the insulating layer. Note that the insulating layer is not particularly limited, but silicon oxide or silicon nitride is preferable.

  Further, the feeder line does not have to be the same wiring layer as the gate electrode. The lower the resistance, the more effective the power supply line is for reducing the gate resistance. For example, the power supply line may be formed of a plated wiring layer. Although the plated wiring layer is difficult to finely process, it is easy to reduce the resistance by increasing the thickness of the plated wiring layer, and is suitable for a power supply line that does not need to be as fine as the gate electrode. In this case, for example, the gate wiring may be formed in the same wiring layer as the gate electrode, and the gate wiring and the power supply line may be connected via a contact.

  Furthermore, the widths of the first and second source wirings that sandwich the feeder line may be appropriately designed as necessary. For example, the source and drain wiring width may be defined by the maximum drain current. That is, the electrode width is designed so that the current flowing through both electrodes is equal to or less than the current density that can ensure reliability during long-term operation. Since the current values flowing through the source and drain wirings are substantially equal, the widths of both electrodes are designed to be approximately equal in the conventional comb structure. In the present invention, since the source wiring is divided into two, the sum of the electrode widths of the first and second source wirings may be designed to be approximately equal to the drain wiring width. On the other hand, the width of the source and drain wirings may be defined by heat dissipation rather than current density. That is, when the thermal requirements are severe, the finger spacing may be designed to be large so that the heat dissipation is sufficient. In this case, since it is important to increase the finger spacing in order to disperse the heat source, it is not always necessary to increase the electrode width. That is, by making the sum of the electrode widths of the first and second source wirings according to the present invention smaller than the drain wiring width, an increase in chip size when the feeder line is arranged can be suppressed to a minimum. . In this way, the source wiring width may be appropriately designed in consideration of the current density requirement and the heat dissipation requirement.

  According to the present invention, increase in Cgd can be suppressed while reducing gate resistance, and high frequency gain of a semiconductor device can be improved.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a sectional view of the same semiconductor device (a sectional view taken along line A-A ′ in FIG. 1). It is a top view at the time of connecting the semiconductor device in parallel. It is a top view of the semiconductor device concerning a 2nd embodiment of the present invention. It is a top view of the semiconductor device concerning a 3rd embodiment of the present invention. FIG. 6 is a sectional view of the semiconductor device (a sectional view taken along line A-A ′ in FIG. 5). It is the figure which compared the high frequency gain characteristic of the semiconductor device in a prior art and the 3rd Embodiment of this invention. It is a top view at the time of connecting the semiconductor device which concerns on the 3rd Embodiment of this invention in parallel. It is a top view of the semiconductor device concerning a 4th embodiment of the present invention. It is a top view of the semiconductor device which concerns on a prior art.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, the numerical values described below are all exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numerical values. Further, although not particularly limited, the present invention relates to a semiconductor device formed on a compound semiconductor substrate including an SOI (Silicon On Insulator) semiconductor substrate, a high resistance silicon substrate, gallium nitride, and gallium arsenide. Especially preferred.

(First embodiment)
FIG. 1 is a plan view of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along the line AA ′ in FIG.

  The semiconductor device according to the first embodiment of the present invention includes a source wiring 100 including a pad electrode and a pad electrode on a substrate 127 (not shown in FIG. 1) on which an FET layer structure is formed. A drain wiring 104, a contact 106, a source electrode 108, a drain electrode 110, a first gate electrode 112, and a second gate electrode 114 are formed. One end portions of the first gate electrode 112 and the second gate electrode 114 are connected by a first gate wiring 116 which is a signal input portion, and the other end portion is a second gate which is a termination portion. They are connected by wiring 118. The first gate wiring 116 and the second gate wiring 118 are connected to the feeder line 122 and further connected to the gate electrode pad 120. In order to avoid an increase in parasitic capacitance due to the coupling between the power supply line and the source, the semiconductor layer located below the power supply line 122 is, for example, ion-implanted and is inactive having high resistance (semi-insulating property and below resistance measurement limit). Layer 124 is assumed.

  The source wiring 100, the drain wiring 104, the first gate electrode 112, and the second gate electrode 114 are arranged in parallel to each other in the longitudinal direction. That is, these wirings have a so-called comb structure (finger structure).

  In FIG. 1, a drain wiring 104, a first gate electrode 112, a source wiring 100, a power supply line 122, a source wiring 100, a second gate electrode 114, and a drain wiring 104 are provided from the left side along the line AA ′. It has been. A first FET 125 is formed by the drain wiring 104, the first gate electrode 112, and the source wiring 100 on the left side of the power supply line 122, and the source wiring 100, the second gate electrode 114, and the drain wiring 104 on the right side of the power supply line 122. A second FET 126 is formed.

  As shown in FIG. 2, the feeder line 122 is formed on the inactive layer 124. An interlayer insulating film 128 is formed on the substrate 127.

  According to the above configuration, for a semiconductor device having a comb-shaped electrode (or wiring) pattern, the source wiring 100 is divided into two parts, and the first gate electrode 112 and the second gate electrode 100 are divided between the divided source wirings 100. By providing the power supply line 122 of the gate electrode 114, the intersection between the power supply line 122, the drain wiring 104, the first gate electrode 112, and the second gate electrode 114 can be eliminated, so that the gate-drain capacitance Cgd is reduced. And effective gate resistance can be reduced.

  FIG. 3 shows a plan view when the semiconductor devices shown in FIG. 1 are connected in parallel.

  Similar to a normal comb-shaped FET, in the present invention, a desired output power can be obtained by appropriately designing the number of fingers connected in parallel. At this time, according to the present invention, even if the number of fingers connected in parallel is increased, the gate wiring and the drain wiring do not cross each other, and the increase in Cgd can be reduced.

(Second Embodiment)
FIG. 4 shows a plan view of a semiconductor device according to the second embodiment of the present invention.

  In the semiconductor device according to the second embodiment, the first gate electrode 112 and the second gate electrode 114 are interrupted at the center with respect to the semiconductor device according to the first embodiment. The fourth gate electrode 134 is formed, the contact 106, the source electrode 108, and the drain electrode 110 are provided corresponding to the third gate electrode 132 and the fourth gate electrode 134, respectively. The gate electrode 132 and the fourth gate electrode 134 are connected to the second gate wiring 118. Note that an isolation region 137 is formed between the first gate electrode 112 and the second gate electrode 114 and the third gate electrode 132 and the fourth gate electrode 134.

  The third FET 135 is formed by the third gate electrode 132, the source electrode 108, and the drain electrode 110, and the fourth FET 136 is formed by the fourth gate electrode 134, the source electrode 108, and the drain electrode 110.

  The semiconductor device according to the second embodiment will be described in detail. The source wiring 100 including the pad electrode on the substrate 127 (not shown in FIG. 4) on which the FET layer structure is formed, the pad electrode The provided drain wiring 104, contact 106, source electrode 108, drain electrode 110, first gate electrode 112, and second gate electrode 114 are formed. End portions of the first gate electrode 112 and the second gate electrode 114 are connected by a first gate wiring 116 which is a signal input portion. The first gate wiring 116 and the second gate wiring 118 are connected to the feeder line 122 and further connected to the gate electrode pad 120. In order to avoid an increase in parasitic capacitance due to the coupling between the power supply line and the source, the semiconductor layer located below the power supply line 122 is, for example, ion-implanted and is inactive having high resistance (semi-insulating property and below resistance measurement limit). Layer 124 is assumed.

  The source wiring 100, the drain wiring 104, the first gate electrode 112, and the second gate electrode 114 are arranged in parallel to each other in the longitudinal direction. That is, these wirings have a so-called comb structure (finger structure).

  In FIG. 4, the drain wiring 104, the first gate electrode 112, the source wiring 100, the power supply line 122, the source wiring 100, the second gate electrode 114, and the drain wiring 104 are provided from the left side along the line AA ′. It has been. A first FET 125 is formed by the drain wiring 104, the first gate electrode 112, and the source wiring 100 on the left side of the power supply line 122, and the source wiring 100, the second gate electrode 114, and the drain wiring 104 on the right side of the power supply line 122. A second FET 126 is formed.

  In the present embodiment, the first and second source electrodes, the first and second drain electrodes, and the first and second gate electrodes in the first embodiment are each divided into two inactive regions. In the first embodiment, since both ends of the gate electrode are connected by the feeder line, an electrically closed loop circuit is formed. When such a closed loop circuit is formed, depending on the structure of the FET, the signal A input from one end of the gate and the signal B input from the other end of the gate are superimposed on the gate electrode, Operational stability may be reduced. For example, when the signal A and the signal B are opposite in phase, the high frequency gain is reduced by weakening the signals. In this embodiment, operation instability caused by such a closed loop circuit can be suppressed. In this embodiment, the chip size becomes larger when compared with the same gate width than in the first embodiment. Therefore, when a stable operation can be obtained in the configuration of the first embodiment, it is not necessary to use this embodiment.

(Third embodiment)
FIG. 5 is a plan view of a semiconductor device according to the third embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line AA ′ in FIG.

  As shown in FIG. 6, the power supply line 122 is formed on the interlayer insulating film 128. Thereby, the coupling with the source wiring 100 can be further reduced, and the increase in Cgs can be minimized.

  Further, when the power supply line is formed of an upper layer wiring such as a plated layer, the resistance of the power supply line can be reduced and the effective gate resistance can be further reduced. As described above, the gate electrode layer has a relatively large wiring resistance because it is difficult to increase the electrode film thickness because of the fine processing of the gate electrode. Therefore, the resistance of the feeder line can be reduced by forming the feeder line with a low-resistance wiring layer above the gate electrode. In the present embodiment, the feeder line is connected to the first and second gate wirings via contacts.

  FIG. 7 shows a comparison of high frequency gains of the semiconductor device according to the present embodiment and the semiconductor device according to the prior art. The measured FET has a gate width of 0.8 mm and a frequency of 2.14 GHz. It can be seen that the present invention improves the high-frequency gain.

  FIG. 8 shows a plan view when the semiconductor devices shown in FIG. 5 are connected in parallel.

  Note that the third embodiment and the second embodiment may be implemented in combination.

(Fourth embodiment)
FIG. 9 illustrates a plan view of a high frequency amplifier using the semiconductor device of the present invention. The high-frequency amplifier is configured by mounting a semiconductor substrate 208, an input matching substrate 206, and an output matching substrate 210 on a package 202. The package includes an input terminal 200 and an output terminal 216. An FET which is an amplifying element according to the present invention is formed on a semiconductor substrate. The input matching board and the input terminal are electrically connected by a wire 204. Similarly, the output matching substrate and the output terminal are electrically connected by a wire 204. The semiconductor substrate includes an input terminal connected to the gate electrode and an output terminal connected to the drain electrode. The input terminal and the input terminal of the semiconductor substrate are electrically connected by a wire 204. Similarly, the output terminal and the output terminal of the semiconductor substrate are electrically connected by a wire 204. The source wiring is grounded via the via 218.

  An input matching circuit pattern 212 is formed on the input matching substrate. Similarly, an output matching circuit pattern 214 is formed on the output matching substrate. The input / output matching circuit pattern is formed of a wiring layer, and the wiring width and wiring length are designed so that a desired input / output impedance can be obtained. As described above, since a large number of short finger FETs are connected in parallel in order to achieve both high output and high gain, the aspect ratio of the semiconductor substrate often increases. The input / output matching substrate is provided to match the input / output impedance of the FET with the input / output terminal. In general, in the input / output board, a contrivance is made to minimize the non-uniformity of the transmission path of the high-frequency signal due to the difference in length between the input / output terminal and the semiconductor substrate by gradually changing the wiring width. However, it is difficult to achieve uniform uniformity, and there is an upper limit to the aspect ratio of the FET. Also, if the aspect ratio is large, the wire length is likely to change due to manufacturing variations in the substrate mounting process. For example, when the input matching board is mounted in parallel to the input terminals, the wire lengths connecting the input terminals and the input matching board are equal. However, when the input matching board does not face the input terminal in parallel due to variations in mounting, a difference occurs in the wire length, and the difference becomes larger as the longer side of the input matching board is longer. Different wire lengths will change the input impedance. Therefore, the operation of the FET becomes non-uniform due to variations in wire length. Such non-uniformity is undesirable because it causes local heat generation and phase variation, resulting in a decrease in gain and malfunction due to oscillation. That is, there is a lower limit to the finger length that can be selected in practice, but according to the present invention, even if the finger length is the same, the effective gate resistance is reduced and the increase in Cgd is suppressed, so that the gain is increased Is possible.

  When used in a relatively low frequency region such as 1 GHz or less, the input / output matching substrate may be omitted. Even in such a case, the above-described problems due to manufacturing variations in the wire length between the input / output terminals and the semiconductor substrate are the same. That is, the usefulness of the present invention does not change depending on the presence or absence of the input / output matching substrate.

  In addition, you may implement combining the above embodiment suitably. The descriptions in the above embodiments are all examples embodying the present invention, and the present invention is not limited to these examples. Various techniques that can be easily configured by those skilled in the art using the technology of the present invention. It can be expanded to examples.

  The present invention is useful as a semiconductor device used for a high frequency amplifier of a mobile communication base station.

100 source wiring 104 drain wiring 106 contact 108 source electrode 110 drain electrode 112 first gate electrode 114 second gate electrode 116 first gate wiring 118 second gate wiring 120 gate electrode pad 122 power supply line 124 inactive layer 125 First FET
126 Second FET
127 Substrate 128 Interlayer insulating film 132 Third gate electrode 134 Fourth gate electrode 135 Third FET
136 Fourth FET
137 Separation region 141 Input terminal 142 Gate terminal 143 Drain terminal 144 Output terminal 145 Wire 200 Input terminal 202 Package 204 Wire 206 Input matching substrate 208 Semiconductor substrate 210 Output matching substrate 212 Input matching circuit pattern 214 Output matching circuit pattern 216 Output terminal 218 Via

Claims (3)

A field effect transistor formed on a semiconductor substrate,
First and second gate electrodes arranged parallel to the first direction;
Arranged parallel to a second direction perpendicular to the first direction, one end of the first gate electrode;
A first gate wiring electrically connecting one end of the second gate electrode;
A second gate wiring disposed in parallel with the second direction and electrically connecting the other end of the first gate electrode and the other end of the second gate electrode;
Between the first and second gate electrodes, a power supply line disposed in parallel with the first direction and electrically connecting the first gate wiring and the second gate wiring;
A first source electrode disposed in parallel with a first direction between the feeder line and the first gate electrode;
A second source electrode disposed in parallel with the first direction between the feeder line and the second gate electrode;
The semiconductor layer located below the feeder line is an inactive region,
A semiconductor device characterized in that the first and second gate wirings do not intersect with the drain electrode. A field effect transistor formed on a semiconductor substrate,
First, second, third and fourth gate electrodes disposed parallel to the first direction;
An inactive region disposed parallel to a second direction perpendicular to the first direction;
A first gate wiring disposed in parallel with the second direction and electrically connecting one end of the first gate electrode and one end of the second gate electrode;
A second gate wiring arranged in parallel with the second direction and electrically connecting one end of the third gate electrode and one end of the fourth gate electrode;
Between the first and third gate electrodes and the first and third gate electrodes, the first gate wiring and the second gate wiring are arranged in parallel with a first direction. An electrically connected feed line;
A first source electrode disposed in parallel with a first direction between the feeder line and the first gate electrode;
A second source electrode disposed in parallel with the first direction between the feeder line and the second gate electrode;
A third source electrode disposed in parallel with the first direction between the feeder line and the third gate electrode;
A fourth source electrode disposed in parallel with the first direction between the feeder line and the fourth gate electrode;
The semiconductor layer located below the feeder line is an inactive region,
The other ends of the first and second gate electrodes and the other ends of the third and fourth gate electrodes are both on the inactive region,
A semiconductor device characterized in that the first and second gate wirings do not intersect with the drain electrode. The semiconductor device according to claim 1 or 2,
A semiconductor device, wherein the power supply line is formed on an insulating film.