JP2014239266A - Solid state image pickup device and driving method of the same - Google Patents

Abstract

A residual charge of a photoelectric conversion film is reduced. A plurality of pixels arranged in a matrix on a semiconductor substrate, a column signal line provided for each column of pixels, and a reset potential applied to each pixel are provided. The pixel 42 includes an amplification transistor 4, a selection transistor 5, a reset transistor 3, and a photoelectric conversion unit 1, and the photoelectric conversion unit 1 is formed above a semiconductor substrate. The amplification transistor 4 outputs a signal voltage corresponding to the potential of the pixel electrode to the column signal line 9 via the selection transistor 5, and the source of the reset transistor 3 is reset to the pixel electrode. The drain of the transistor 3 is connected to the reset drain line 16, and the horizontal blanking period of the first frame in the imaging of the first frame and the second frame After the completion and electronic shutter drive before a predetermined period of the second frame to turn on the reset transistor. [Selection] Figure 2A

Description

  The present invention relates to a solid-state imaging device, and more particularly to a stacked solid-state imaging device and a driving method thereof.

  In general solid-state imaging devices, an embedded photodiode structure is used as a light receiving unit. However, in Patent Document 1, a photoelectric conversion layer is formed on a control electrode constituting a solid-state amplification device, and a transparent electrode layer is formed thereon. And a device that changes optical information into an electrical signal with a good S / N ratio by applying the applied voltage to the control electrode via the conversion layer, a so-called stacked solid-state imaging device is disclosed. .

  A stacked solid-state imaging device has a configuration in which a photoelectric conversion film is formed on a semiconductor substrate on which a pixel circuit is formed via an insulating film. For this reason, it is possible to use a material having a large light absorption coefficient such as amorphous silicon for the photoelectric conversion film. For example, in the case of amorphous silicon, green light having a wavelength of 550 nm can be almost absorbed with a thickness of about 0.4 nm.

  However, in the solid-state imaging device disclosed in Patent Document 1, charges are likely to remain in the photoelectric conversion unit particularly after imaging a high-luminance subject, and the image of the previous frame remains as an afterimage in the next frame due to the influence of the residual charges. Have a problem.

  Therefore, Patent Document 2 discloses a technique for irradiating light to a photoelectric conversion unit from a light irradiation mechanism newly provided in a solid-state imaging device so as not to generate residual charges in the photoelectric conversion unit.

Japanese Patent Laid-Open No. 55-120182 JP 2004-146769 A

  In order to prevent a residual charge from being generated by the method as disclosed in Patent Document 2, a light irradiation mechanism is required, and it is difficult to realize it in the current situation where downsizing of a solid-state imaging device is required.

  In view of such problems, an object of the present invention is to reduce the residual charge of the photoelectric conversion unit without requiring a light irradiation mechanism.

  The present invention has the following configuration as one means for achieving the above object.

  In order to solve the above problems, a solid-state imaging device of the present invention includes a semiconductor substrate, a plurality of pixels arranged in a matrix on the semiconductor substrate, a column signal line provided for each column of the plurality of pixels, A solid-state imaging device provided for each column of the plurality of pixels and including a reset drain line that applies a reset potential to the plurality of pixels, wherein the pixel includes an amplification transistor, a selection transistor, a reset transistor, and a photoelectric conversion unit. The photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side, and the pixel electrode of the photoelectric conversion film A transparent electrode formed on a surface opposite to the pixel electrode, the amplification transistor has a gate connected to the pixel electrode, and the signal voltage corresponding to the potential of the pixel electrode is selected. Output to a column signal line through a transistor, the source of the reset transistor is connected to the pixel electrode, the drain of the reset transistor is connected to the reset drain line, and the first frame and the first frame following the first frame In imaging with two frames, the reset transistor is turned on for a predetermined period after the end of the horizontal blanking period of the first frame and before driving the electronic shutter of the second frame.

  Preferably, the predetermined period is the entire period from the end of the horizontal blanking period of the first frame to before the electronic shutter driving of the second frame.

  Preferably, the reset transistor is turned on and off a plurality of times after the horizontal blanking period of the first frame and before driving the electronic shutter of the second frame.

  In order to solve the above problems, a driving method of a solid-state imaging device according to the present invention is provided for a semiconductor substrate, a plurality of pixels arranged in a matrix on the semiconductor substrate, and a column of the plurality of pixels. A solid-state imaging device driving method comprising: a column signal line; and a reset drain line that is provided for each column of the plurality of pixels and applies a reset potential to the plurality of pixels, wherein the pixels include an amplification transistor and a selection transistor A reset transistor and a photoelectric conversion unit, wherein the photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side, A transparent electrode formed on a surface of the photoelectric conversion film opposite to the pixel electrode, and the amplification transistor has a gate connected to the pixel electrode, the potential of the pixel electrode The signal voltage is output to the column signal line through the selection transistor, the source of the reset transistor is connected to the pixel electrode, the drain of the reset transistor is connected to the reset drain line, In imaging with the second frame following the first frame, the reset transistor is turned on for a predetermined period after the end of the horizontal blanking period of the first frame and before driving the electronic shutter of the second frame. And

  According to the present invention, the residual charge of the laminated film can be discharged and the afterimage can be suppressed.

1 is a diagram showing a chip configuration of a stacked solid-state imaging device according to a first embodiment of the present invention. The figure which shows the detail of a structure of the pixel part which concerns on the same embodiment, and its peripheral circuit Sectional drawing of the unit pixel which concerns on the same embodiment The figure which shows an example of the detail of a structure of the peripheral circuit which concerns on the same embodiment Circuit diagram for explaining the operation of the solid-state imaging device according to the embodiment Timing chart for explaining the operation of the solid-state imaging device according to the embodiment Timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the embodiment Timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the second embodiment of the present invention Timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the third embodiment of the present invention Timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the fourth embodiment of the present invention

  Hereinafter, a solid-state imaging device and a camera system according to embodiments of the present invention will be described with reference to the drawings.

  In the drawings, elements that represent substantially the same configuration, operation, and effect are denoted by the same reference numerals. In addition, the numerical values described below are all exemplified for specifically explaining the present invention, and the present invention is not limited to the illustrated numerical values. Furthermore, the connection relationship between the components is exemplified for specifically explaining the present invention, and the connection relationship for realizing the function of the present invention is not limited to this. Furthermore, in many cases, the source electrode and the drain electrode of the FET have the same structure and function and are not clearly distinguished, but in the following description, for convenience, the electrode to which a signal is input is referred to as the drain electrode and the output. This electrode is referred to as a source electrode.

(First embodiment)
FIG. 1 shows a chip configuration of a stacked solid-state imaging device according to this embodiment. FIG. 2A shows details of the configuration of the pixel portion 43 and its peripheral circuits. FIG. 2B shows a cross-sectional view of the unit pixel 42. FIG. 2C shows an example of the detailed configuration of the row scanning circuit 33 and the multiplexer circuit 41. FIG. 3 is a circuit diagram of the solid-state imaging device according to the present embodiment. In FIG. 2A, the unit pixels 42 are described for “2 rows and 2 columns”, but the number of rows and the number of columns of the unit pixels 42 may be arbitrarily set.

  As shown in FIG. 1, the solid-state imaging device, that is, the sensor chip 52 includes a pixel reset signal line 7, a pixel address signal line 8, a vertical signal line 9, a reset drain line 16, a column selection transistor 27, a column scanning circuit (horizontal scanning unit). ) 29, horizontal signal line 30, output amplifier 31, row scanning circuit (vertical scanning unit) 33, multiplexer circuit (MUX) 41, VOUT terminal 32, pixel unit 43, CDS (Correlated Double Sampling) circuit 45, timing control circuit 50 And a storage diode initialization voltage generation circuit 53.

  In the pixel unit 43, a plurality of unit pixels 42 are arranged in a matrix on a semiconductor substrate, and the vertical signal line 9 is provided for each column of the unit pixels 42. In the sensor chip 52, the unit pixel 42 of the pixel unit 43 is selected by the row scanning circuit 33 and the multiplexer circuit 41.

  As shown in FIG. 2A, each unit pixel 42 includes a photoelectric conversion unit 1, a storage unit 2 having one end connected to the photoelectric conversion unit 1, a source connected to the vertical signal line 9, and a drain connected to the power supply line 6. An amplifying transistor 4 having a gate connected to the storage unit 2, a gate connected to the pixel reset signal line 7, a drain connected to the reset drain line 16, and an amplifying transistor 4 connected in series. The selected transistor 5 is provided. The selection transistor 5 is inserted between the source of the amplification transistor 4 and the vertical signal line 9, but may be inserted between the drain of the amplification transistor 4 and the power supply line 6.

  As shown in FIG. 2B, an amplification transistor 4, a selection transistor 5, and a reset transistor 3 are formed on a semiconductor substrate 71 made of silicon. The amplification transistor 4 includes a gate electrode 72, a diffusion layer 73 that is a drain, and a diffusion layer 74 that is a source. The selection transistor 5 includes a gate electrode 75, a diffusion layer 74 that is a drain, and a diffusion layer 76 that is a source. The source of the amplification transistor 4 and the drain of the selection transistor 5 are a common diffusion layer 74. The reset transistor 3 includes a gate electrode 77, a diffusion layer 78 that is a drain, and a diffusion layer 79 that is a source. The diffusion layer 73 and the diffusion layer 78 are separated by the element isolation region 80.

  An insulating film 84 is formed on the semiconductor substrate 71 so as to cover each transistor. The photoelectric conversion unit 1 is formed on the insulating film 84. The photoelectric conversion unit 1 includes a photoelectric conversion film 81 made of amorphous silicon or the like formed above a semiconductor substrate, a pixel electrode 82 formed on the surface of the photoelectric conversion film 81 on the semiconductor substrate 71 side, and photoelectric conversion. A transparent electrode 83 formed on the surface of the film 81 opposite to the pixel electrode 82; The pixel electrode 82 is connected to the gate electrode 72 of the amplification transistor 4 and the diffusion layer 78 that is the source of the reset transistor 3 through a contact 85. The diffusion layer 78 connected to the pixel electrode 82 functions as a storage diode (storage unit 2).

  The row scanning circuit 33 supplies various timing signals to the pixel unit 43 via the pixel reset signal line 7, the pixel address signal line 8, and the like. The column scanning circuit 29 supplies the column selection signal 28 to the column selection transistor 27 to sequentially read out the signal of the pixel unit 43 to the horizontal signal line 30. The output amplifier 31 amplifies the signal transmitted through the horizontal signal line 30 and outputs the amplified signal to the VOUT terminal 32.

  The pixel reset signal line 7 is a signal line through which a reset signal is transmitted, and is provided for each row of the unit pixels 42 in order to reset the signal of the unit pixel 42 in the corresponding row.

  The CDS circuit 45 is provided for each vertical signal line 9, and a potential difference at any two different timings in the corresponding vertical signal line 9, that is, a potential during a reset operation (a vertical signal line when the reset transistor 3 is on). 9 is output from the CDS output node 26 in accordance with the difference between the potential at the time of signal output and the potential at the time of signal output (the potential of the vertical signal line 9 when the reset transistor 3 is off).

  The CDS circuit 45 includes capacitors 19 and 25, a sample transistor 20 whose on / off is controlled by a sample transistor control signal 21, and a clamp transistor 22 whose on / off is controlled by a clamp transistor control signal 23 and connected to the clamp signal line 24. Have

  The vertical signal line 9 is connected to a pixel load transistor 10 whose on / off is controlled by a pixel load transistor control line 11.

  The reset drain line 16 is connected to the drain of the reset transistor 3 whose on / off is controlled by the pixel reset signal line 7.

  The timing control circuit 50 supplies a vertical scanning signal 40 to the row scanning circuit 33, supplies a row selection signal 35 and a reset signal 36 to the multiplexer circuit 41, and supplies a horizontal scanning signal 39 to the column scanning circuit 29.

  The multiplexer circuit 41 controls the output of the row selection signal 35 and the reset signal 36 to the pixel unit 43. The multiplexer circuit 41 is provided between the timing control circuit 50 and the unit pixel 42, and selectively supplies a reset signal 36 to the pixel reset signal line 7 corresponding to the unit pixel 42 of a predetermined row, and the row selection signal 35 is supplied. This is selectively supplied to the pixel address signal line 8 corresponding to the unit pixel 42 in a predetermined row.

  The reference voltage generation circuit 51 supplies a pixel load transistor control signal LG to the pixel load transistor control line 11 and a clamp signal NCDC to the clamp signal line 24, respectively.

  The storage diode initialization voltage generation circuit 53 connected to the reset drain line 16 supplies the reset potential of the unit pixel 42 to the reset drain line 16.

  Next, the operation of the solid-state imaging device according to this embodiment will be described.

  FIG. 4 is a timing chart for explaining the operation of the solid-state imaging device according to the present embodiment. Here, only the operation of one unit pixel 42 in a certain frame is shown.

  In the solid-state imaging device according to the present embodiment, light is converted into an electric signal S by the photoelectric conversion unit 1 that is a laminated film, and the electric signal S is stored in the storage unit 2. In this embodiment, since it is assumed that light is converted into a positive electrical signal S, the potential of the storage unit 2 rises. Here, at time T1, the potential of the pixel address signal line 8 is changed from the low level to the high level, and the selection transistor 5 is turned on. Similarly, by raising the potential of the pixel load transistor control line 11 from the low level at time T1, the electric signal S is impedance-converted by the source follower circuit formed by the amplification transistor 4 and the pixel load transistor 10, The signal is input to the CDS circuit 45 through the vertical signal line 9. At time T1, the sample transistor control signal 21 and the clamp transistor control signal 23 are changed from low level to high level, and the electric signal S is once sampled and held by the CDS circuit 45. At time T2, the clamp transistor control signal 23 is set to a low level.

  Next, when the potential of the pixel reset signal line 7 is changed from the low level to the high level at time T3 and the reset transistor 3 is turned on, the electrical signal S stored in the storage unit 2 is reset (initialized), and the storage unit The potential of 2 drops.

  Next, at time T4, the potential of the pixel reset signal line 7 is set to a low level. The reset electric signal N of the storage unit 2 is input to the CDS circuit 45 via the vertical signal line 9. In the CDS circuit 45, the electric signal S and the electric signal N are differentiated, and the difference is output to the CDS output node 26 and treated as the pixel signal P.

  Next, at time T5, the potentials of the pixel address signal line 8 and the pixel load transistor control line 11 are set to a low level. Further, the sample transistor control signal 21 is set to a low level. As a result, the pixel signal P is accumulated in the capacitor 25.

  After time T5, the column selection transistor 27 is turned on by the column selection signal 28 from the column scanning circuit 29, whereby the previous pixel signal P is read out to the horizontal signal line 30 and amplified by the output amplifier 31 and then to the VOUT terminal 32. Is output externally.

  A period required to read out the pixel signal P from time T1 to time T5 is referred to as a horizontal blanking period. In the case of a general CMOS type solid-state imaging device, the potential of the pixel reset signal line is at a low level from time T5 to the horizontal blanking period of the next frame. However, since the solid-state imaging device according to the present embodiment uses a laminated film as the photoelectric conversion unit 1, the charge remains in the laminated film after a short reset from time T3 to time T4, and the next frame is imaged. This may cause an afterimage. Therefore, in order to suppress the afterimage, the potential of the pixel reset signal line 7 is set to a high level only for a predetermined period between time T5 and the horizontal blanking period of the next frame, and is not discharged by reset from time T3 to time T4. The remaining charge of the laminated film is discharged before driving the electronic shutter of the next frame.

  FIG. 5 is a timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the present embodiment. The horizontal blanking period in a certain frame is from time T1 to time T5, and the horizontal blanking period in the next frame is from time T1 'to time T5'. At a predetermined time T6 after time T5, the potential of the pixel reset signal line 7 is set to a high level. Thereafter, the potential of the pixel reset signal line 7 is maintained at the high level until time T7 when the electronic shutter driving of the next frame is performed, and the potential of the pixel reset signal line 7 is changed from the high level to the low level at time T7. That is, the reset transistor 3 is on from time T6 to time T7. By this driving, the residual charge of the laminated film is discharged from time T6 to time T7.

  After time T7, the accumulation of the electric signal S in the accumulation unit 2 starts, and the electric signal S continues to be accumulated until the potential of the pixel reset signal line 7 becomes high level again at time T3 'of the next frame. That is, the period from time T7 to time T3 'is the exposure period of the solid-state imaging device according to the present embodiment.

  Thus, in the solid-state imaging device according to the present embodiment, the residual charge of the stacked film is discharged by setting the potential of the pixel reset signal line 7 to the high level during the period from time T6 to time T7. The afterimage of the frame can be suppressed.

(Second Embodiment)
Hereinafter, although the solid-state imaging device according to the second embodiment of the present invention will be described, the description will focus on parts different from the first embodiment.

  FIG. 6 is a timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the present embodiment. At a predetermined time T6 after time T5, the potential of the pixel reset signal line 7 is set to a high level. Thereafter, in the period up to time T7 when the electronic shutter drive of the next frame is performed, an operation of maintaining the potential of the pixel reset signal line 7 at a high level for a predetermined period is performed a plurality of times, and the potential of the pixel reset signal line 7 is increased at time T7. From level to low level. That is, from time T6 to time T7, the operation in which the reset transistor 3 is turned on / off a plurality of times and the reset transistor 3 is turned on for a predetermined period is realized a plurality of times. By this driving, the residual charge of the stacked film is discharged a plurality of times during the period from time T6 to time T7.

  As described above, in the solid-state imaging device according to the present embodiment, the operation of maintaining the potential of the pixel reset signal line 7 at a high level for a predetermined period is performed a plurality of times in the period from time T6 to time T7. The residual charge of the film can be discharged, and the afterimage of the next frame can be suppressed. Further, as in the first embodiment, power consumption can be reduced as compared with the case where the potential of the pixel reset signal line 7 is kept at the high level during the period from time T6 to time T7.

(Third embodiment)
Hereinafter, the solid-state imaging device according to the third embodiment of the present invention will be described, but the description will focus on parts that are different from the first embodiment.

  FIG. 7 is a timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the present embodiment. A high level potential is applied to the pixel reset signal line 7 in a pulse form from a predetermined time T6 after the time T5 to a time T7 when the electronic shutter drive of the next frame is performed, and the potential of the pixel reset signal line 7 is lowered at the time T7. Level. That is, from time T6 to time T7, the reset transistor 3 is repeatedly turned on and off in a short period according to the potential change of the pixel reset signal line 7. By this driving, the residual charge of the laminated film is discharged from time T6 to time T7.

  As described above, in the solid-state imaging device according to the present embodiment, in the period from time T6 to time T7, the potential of the pixel reset signal line 7 is set to a high level in a pulsed manner, so that the residual charge of the stacked film is reduced. The afterimage of the next frame can be suppressed. In addition, as in the first embodiment, compared to the case where the potential of the pixel reset signal line 7 is kept at a high level during the period from time T6 to time T7, vibration is applied to the charge remaining in the stacked film, and more Residual charges can be discharged reliably.

(Fourth embodiment)
Hereinafter, a solid-state imaging device according to the fourth embodiment of the present invention will be described, but the description will focus on parts that are different from the first embodiment.

  FIG. 8 is a timing chart for explaining the residual charge discharging operation of the solid-state imaging device according to the present embodiment. The potential of the pixel reset signal line 7 is set to a high level in a pulse shape for a predetermined period from time T6. Thereafter, in the period up to time T7 when the electronic shutter drive of the next frame is performed, an operation of setting the potential of the pixel reset signal line 7 to a high level in a pulse shape for a predetermined period is performed a plurality of times, and at time T7, the pixel reset signal line 7 The potential is changed from high level to low level. That is, ON / OFF in a short period is repeated a plurality of times from time T6 to time T7 according to the potential change of the pixel reset signal line 7. By this driving, the residual charge of the stacked film is discharged a plurality of times during the period from time T6 to time T7.

  As described above, in the solid-state imaging device according to the present embodiment, the operation of setting the potential of the pixel reset signal line 7 to a high level in a pulse shape for a predetermined period is performed a plurality of times in the period from time T6 to time T7. Thus, the residual charge of the laminated film can be discharged and the afterimage of the next frame can be suppressed. In addition, as compared with the second embodiment, by changing the potential in a pulse shape, the residual charge can be discharged more reliably by applying vibration to the charge remaining in the laminated film. Further, as in the third embodiment, the power consumption can be reduced compared to the case where the potential of the pixel reset signal line 7 is continuously changed during the period from time T6 to time T7.

  Although the solid-state imaging device of the present invention has been described based on the embodiment, the present invention is not limited to this embodiment. The present invention includes various modifications made by those skilled in the art without departing from the scope of the present invention. Moreover, you may combine each component in several embodiment arbitrarily in the range which does not deviate from the meaning of invention.

  The solid-state imaging device according to the present invention is effective as a small, thin, and highly sensitive image pickup device.

DESCRIPTION OF SYMBOLS 1 Photoelectric conversion part 2 Accumulation part 3 Reset transistor 4 Amplification transistor 5 Selection transistor 6 Power supply line 7 Pixel reset signal line 8 Pixel address signal line 9 Vertical signal line 10 Pixel load transistor 11 Pixel load transistor control line 16 Reset drain line 19, 25 Capacitor 20 Sample transistor 21 Sample transistor control signal 22 Clamp transistor 23 Clamp transistor control signal 24 Clamp signal line 26 CDS output node 27 Column selection transistor 28 Column selection signal 29 Column scanning circuit 30 Horizontal signal line 31 Output amplifier 32 VOUT terminal 33 Row scanning Circuit 35 Row selection signal 36 Reset signal 39 Horizontal scanning signal 40 Vertical scanning signal 41 Multiplexer circuit 42 Unit pixel 43 Pixel unit 45 CDS circuit 50 Tie Control circuit 51 Reference voltage generation circuit 52 Sensor chip 53 Storage diode initialization voltage generation circuit 71 Semiconductor substrate 72, 75, 77 Gate electrodes 73, 74, 76, 78, 79 Diffusion layer 80 Element isolation region 81 Photoelectric conversion film 82 Pixel Electrode 83 Transparent electrode 84 Insulating film 85 Contact

Claims (6)

A semiconductor substrate;
A plurality of pixels arranged in a matrix on the semiconductor substrate;
A column signal line provided for each column of the plurality of pixels;
A solid-state imaging device provided for each column of the plurality of pixels, and including a reset drain line that applies a reset potential to the plurality of pixels;
The pixel includes an amplification transistor, a selection transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side, and a side opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on the surface of
The amplification transistor has a gate connected to the pixel electrode, and outputs a signal voltage corresponding to the potential of the pixel electrode to a column signal line through the selection transistor,
A source of the reset transistor is connected to the pixel electrode;
The drain of the reset transistor is connected to the reset drain line,
In imaging of the first frame and the second frame following the first frame,
The solid-state imaging device, wherein the reset transistor is turned on for a predetermined period after the end of the horizontal blanking period of the first frame and before driving the electronic shutter of the second frame. The solid-state imaging device according to claim 1,
The solid-state imaging device according to claim 1, wherein the predetermined period is an entire period from the end of the horizontal blanking period of the first frame to before the electronic shutter driving of the second frame. The solid-state imaging device according to claim 1,
The solid-state imaging device according to claim 1, wherein the reset transistor is turned on and off a plurality of times after the horizontal blanking period of the first frame and before the electronic shutter driving of the second frame. A semiconductor substrate;
A plurality of pixels arranged in a matrix on the semiconductor substrate;
A column signal line provided for each column of the plurality of pixels;
A solid-state imaging device driving method comprising a reset drain line that is provided for each of the plurality of pixels and applies a reset potential to the plurality of pixels,
The pixel includes an amplification transistor, a selection transistor, a reset transistor, and a photoelectric conversion unit,
The photoelectric conversion unit includes a photoelectric conversion film formed above the semiconductor substrate, a pixel electrode formed on a surface of the photoelectric conversion film on the semiconductor substrate side, and a side opposite to the pixel electrode of the photoelectric conversion film. A transparent electrode formed on the surface of
The amplification transistor has a gate connected to the pixel electrode, and outputs a signal voltage corresponding to the potential of the pixel electrode to a column signal line through the selection transistor,
A source of the reset transistor is connected to the pixel electrode;
The drain of the reset transistor is connected to the reset drain line,
In imaging of the first frame and the second frame following the first frame,
The solid-state imaging device driving method, wherein the reset transistor is turned on for a predetermined period after the horizontal blanking period of the first frame and before the electronic shutter driving of the second frame. The solid-state imaging device according to claim 4,
The solid-state imaging device driving method according to claim 1, wherein the predetermined period is an entire period from the end of the horizontal blanking period of the first frame to before the electronic shutter driving of the second frame. The solid-state imaging device according to claim 4,
The solid-state imaging device driving method, wherein the reset transistor is turned on and off a plurality of times after the horizontal blanking period of the first frame and before the electronic shutter driving of the second frame.

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