JP2014236044A - Protective circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a protective circuit which solves such a problem that since the resistance value of each discharge path for passing a discharge current is different depending on the arrangement place of each diode element, a large current flows through some of a plurality of diode elements, and thereby the diode elements are destroyed or the wiring on the discharge path is fused, and to provide a semiconductor device.SOLUTION: An intermediate layer 302 has a one conductivity type side interconnection M3 conducting with each one conductivity type diffusion layer 204, and a reverse conductivity type interconnection M3 conducting with each reverse conductivity type diffusion layer 203, where a plurality of one conductivity type side interconnections M3 and reverse conductivity type interconnections M3 are extended in a second direction, and juxtaposed alternately in a first direction. The resistance value of a one conductivity type side interconnection at the end, among the one conductivity type side interconnections M3, and the resistance value of a reverse conductivity type side interconnection at the end, among the reverse conductivity type side interconnections M3, are lower than the resistance value of other one conductivity type side interconnections M3 and other reverse conductivity type side interconnections M3.

Description

  The present invention relates to a protection circuit for protecting an internal circuit, and more particularly to an electrostatic protection circuit for protecting an internal circuit from ESD (Electro Static Discharge).

  In a semiconductor device such as a DRAM (Dynamic Random Access Memory) device, an ESD protection circuit for protecting an internal circuit from ESD is often provided in the vicinity of a power supply pad (see Patent Documents 1 and 2).

  The ESD protection circuit usually has a plurality of diode elements connected in parallel between the power supply pad and the ground terminal. Then, when a negative surge voltage is applied to the power supply pad by ESD, each diode element included in the ESD protection circuit is forward-biased, and the discharge current due to ESD becomes a plurality of discharges corresponding to each diode element. It flows to the ground terminal through each of the paths. As a result, the discharge current flowing through the internal circuit can be suppressed, and the internal circuit can be protected.

JP 2007-150150 A JP 2007-42718 A

  However, in the ESD protection circuit described above, the resistance value of each discharge path through which the discharge current flows differs depending on the arrangement location of each diode element, so that a large amount of current flows in a part of the plurality of diode elements, and the diode elements are destroyed. The inventors of the present application have revealed that problems such as melting of wiring on the discharge path may occur.

  15-20 is a figure for demonstrating the mechanism in which said problem generate | occur | produces. Specifically, FIG. 15 is a circuit diagram showing an ESD protection circuit, FIG. 16 is a top view showing a layout of the ESD protection circuit, and FIG. 17 is cut along line AA ′ in FIG. 18 is a cross-sectional view taken along the line BB ′ of FIG. 16, FIG. 19 is a cross-sectional view taken along the line CC ′ of FIG. 16, and FIG. It is sectional drawing cut | disconnected by 16 DD 'line.

  As shown in FIG. 15, the ESD protection circuit 100 ′ includes diode elements 101 ′ to 104 ′ connected in parallel between the PAD 110 ′ that is a power supply pad and the ground terminal VSS. The PAD 110 'is connected to the internal circuit 130' via the ESD protection circuit 100 'and the resistor 120'.

  Specifically, as shown in FIGS. 16 to 20, the ESD protection circuit 100 ′ extends along a predetermined direction on the semiconductor substrate, and a plurality of ESD protection circuits 100 ′ are alternately arranged in a direction orthogonal to the predetermined direction. N + diffusion layer 151 ′ and P + diffusion layer 152 ′. The N + diffusion layer 151 ′ and the P + diffusion layer 152 ′ are formed in a PWell (not shown), and the N + diffusion layer 151 ′ forms the cathode of the diode elements 101 ′ to 104 ′, and the P + diffusion layer 152 ′ and PWell forms the anodes of the diode elements 101′-104 ′.

  Further, on each N + diffusion layer 151 ′ and each P + diffusion layer 152 ′, via CT0 ′, metal wiring M1 ′, via CT1 ′, and metal wiring M2 ′ are stacked in this order in parallel with the diffusion layers. Yes. Further, a via CT2 'and a metal wiring M3' are stacked in this order on the metal wiring M2 '. A plurality of metal wirings M3 'are arranged in parallel in a direction orthogonal to each metal wiring M2'. Each metal wiring M3 ′ is connected to a metal wiring M2 ′ stacked on each N + diffusion layer 151 ′ or a metal wiring M2 ′ stacked on each P + diffusion layer 152 ′ via the via CT2 ′. Connected alternately. Thereby, each metal wiring M3 'is electrically connected to each N + diffusion layer 151' or each P + diffusion layer 152 '.

  On the metal wiring M3 ′, two metal wirings M4 ′ provided along a direction orthogonal to the metal wiring M3 ′ are formed, and the metal wiring M2 ′ electrically connected to each N + diffusion layer 151 ′. The metal wiring M2 ′ that is electrically connected to each P + diffusion layer 152 ′ is connected to a separate metal wiring M4 ′ through a via CT3 ′. The metal wiring M4 ′ connected to the metal wiring M2 ′ conducted to each N + diffusion layer 151 ′ is connected to the PAD 110 ′, and the metal wiring M4 ′ connected to the metal wiring M2 ′ conducted to each P + diffusion layer 152 ′. Is connected to the ground terminal VSS.

  In the ESD protection circuit 100 ′, the current output from the PAD 110 ′ passes through the metal wiring M4 ′, the via CT3 ′, and the metal wiring M3 ′ to the connection point E between the metal wiring M3 ′ and the via CT2 ′. The flow then flows to the connection point F between the metal wiring M2 ′ and the via CT1 ′ via the via CT2 ′ and the metal wiring M2 ′, and further via the via CT1 ′, the metal wiring M1 ′ and the via CT0 ′. Then, discharge to a point G on the N + diffusion layer 151 ′ of the diode element. The discharged current flows to the P + diffusion layer 152 ′ adjacent to the N + diffusion layer 151 ′, and then the via CT0 ′, the metal wiring M1 ′, the via CT1 ′, the metal wiring M2 ′, the via CT2 ′, and the metal The current flows to the point H on the metal wiring M4 ′ via the wiring M3 ′ and the via CT3 ′, and is then discharged to the ground terminal VSS.

  As shown in FIGS. 15 to 20, one N + diffusion layer 151 ′ is adjacent to the P + diffusion layer 152 ′ disposed at the end of the ESD protection circuit 100 ′. Two N + diffusion layers 151 'are adjacent to the P + diffusion layer 152' disposed in the center. For this reason, the current is discharged from the two N + diffusion layers 151 ′ to the P + diffusion layer 152 ′ disposed in the center, and more current is generated than the P + diffusion layer 152 ′ disposed at the end. Flowing.

  Therefore, the resistance value of the diode element arranged at the central portion is lower than the resistance value of the diode element arranged at the end portion, and a large amount of current flows through the diode element arranged at the central portion. When a surge voltage is applied by ESD, a large amount of current flows intensively to the diode element arranged at the center, and the diode element is destroyed or the metal wiring on the path passing through the diode element melts. Problems such as trapping occur.

  In the ESD protection circuit 100 ′, only one metal wiring M4 ′ connected to the ground terminal VSS is provided at the center of the ESD protection circuit 100 ′. By providing the metal wiring M4 ′ connected to the ground terminal VSS in the part or the like, it is possible to ensure a large electrostatic withstand voltage. However, in this case, there is a problem that the occupation area of the ESD protection circuit 100 ′ in the semiconductor device increases. In order to suppress an increase in the occupied area, it is conceivable to provide a plurality of metal wirings M4 ′ connected to the ground terminal VSS while making the metal wiring M4 ′ thin. In this case, the thick metal wiring M4 is provided. The electrostatic withstand voltage may be lower than when 'is one.

The protection circuit according to the present invention comprises:
A one-conductivity-type semiconductor region, and a one-conductivity-type diffusion layer and a reverse-conductivity-type diffusion layer formed in the semiconductor region, wherein the one-conductivity-type diffusion layer and the reverse-conductivity-type diffusion layer are A plurality of diode layers extending in a first direction and alternately arranged in a second direction intersecting the first direction;
Each of the one conductivity type diffusion layer has a one conductivity type side wiring and the opposite conductivity type diffusion layer has a reverse conductivity side wiring, and the one conductivity type side wiring and the reverse conductivity side wiring are An intermediate layer on the diode layer that extends in the second direction and is arranged in parallel in the first direction.
The resistance value of the one conductivity type side wiring at the end in each one conductivity type side wiring and the reverse conductivity type side wiring at the end in each reverse conductivity type side wiring is the other one conductivity type side wiring and other It is lower than the resistance value of the reverse conductivity type wiring.

  A semiconductor device according to the present invention includes the protection circuit.

  According to the present invention, a reverse conductivity side wiring, a reverse conductivity type diffusion layer, a semiconductor region, a one conductivity type diffusion layer, and a plurality of discharge paths passing through the one conductivity side wiring are formed, and the one conductivity type side wiring at the end Since the resistance value of the reverse conductive side wiring is lower than that of the other one conductivity type side wiring and the other reverse conductivity type side wiring, it becomes possible to reduce the resistance value of the discharge path at the end of each discharge path. Therefore, it is possible to prevent a large amount of current from flowing intensively through the diode element disposed in the center.

It is a circuit diagram showing an ESD protection circuit of a 1st embodiment of the present invention. It is a top view which shows the layout of the ESD protection circuit of the 1st Embodiment of this invention. It is sectional drawing of the ESD protection circuit of the 1st Embodiment of this invention. It is sectional drawing of the ESD protection circuit of the 1st Embodiment of this invention. It is sectional drawing of the ESD protection circuit of the 1st Embodiment of this invention. It is sectional drawing of the ESD protection circuit of the 1st Embodiment of this invention. It is a top view which shows the layout of the ESD protection circuit of the 2nd Embodiment of this invention. It is sectional drawing of the ESD protection circuit of the 2nd Embodiment of this invention. It is a figure which shows the measuring point of resistance value. It is a figure which shows the measuring point of resistance value. It is a figure which shows the measuring point of resistance value. It is a figure for demonstrating an example of the effect of the 1st Embodiment and 2nd Embodiment of this invention. It is a figure for demonstrating an example of the effect of the 1st Embodiment and 2nd Embodiment of this invention. It is a figure for demonstrating an example of the effect of the 1st Embodiment and 2nd Embodiment of this invention. It is a circuit diagram which shows the ESD protection circuit of related technology. It is a top view which shows the layout of the related art ESD protection circuit. It is sectional drawing of the ESD protection circuit of related technology. It is sectional drawing of the ESD protection circuit of related technology. It is sectional drawing of the ESD protection circuit of related technology. It is sectional drawing of the ESD protection circuit of related technology.

  Embodiments of the present invention will be described below with reference to the drawings. In the following description, components having the same function may be denoted by the same reference numerals and description thereof may be omitted.

  FIG. 1 is a circuit diagram showing an ESD protection circuit according to a first embodiment of the present invention. As shown in FIG. 1, the ESD protection circuit 100 includes a plurality of diode elements 101 to 104 provided between a PAD 110 that is a power supply pad and a ground terminal VSS. Specifically, the PAD 110 is connected to the internal circuit 130 via the resistor 120. The ESD protection circuit 100 is provided between the wiring 140 connecting the PAD 110 and the internal circuit 130 and the ground terminal VSS. Although four diode elements are shown in FIG. 1, the number is not limited to four in practice. The ESD protection circuit 100 is an electrostatic protection circuit that protects the internal circuit 130 from a surge voltage applied to the PAD 110.

  FIG. 2 is a top view showing the layout of the ESD protection circuit 100. 3 is a cross-sectional view of the ESD protection circuit 100 along the line AA ′ in FIG. 2, and FIG. 4 is a cross-sectional view of the ESD protection circuit 100 along the line BB ′ in FIG. 5 is a cross-sectional view of the ESD protection circuit 100 taken along the line CC ′ of FIG. 2, and FIG. 6 is a cross-sectional view of the ESD protection circuit 100 taken along the line DD ′ of FIG. is there.

  3 to 6, the discharge path through which the current from the PAD 110 flows is indicated by a dotted line with an arrow. Further, the directions intersecting each other in the semiconductor substrate surface are defined as the X direction and the Y direction, and the direction perpendicular to the semiconductor substrate surface is defined as the Z direction.

  As shown in FIGS. 2 to 6, the ESD protection circuit 100 includes a Pwell 202 that is a P-type semiconductor region formed in the semiconductor substrate 201, and an N + diffusion layer 203 and a P + diffusion layer formed in the Pwell 202. 204.

  A plurality of N + diffusion layers 203 and P + diffusion layers 204 extend in the X direction, which is the first direction on the semiconductor substrate 201, and are alternately arranged in parallel in the Y direction, which is the second direction intersecting the X direction. ing.

  The PWell 202, each N + diffusion layer 203, and each P + diffusion layer 204 constitute a plurality of diode elements. Specifically, each N + diffusion layer 203 is a layer that forms the cathode of each diode element. Each P + diffusion layer 204 is a layer that supplies a ground level voltage to the PWell 202, and together with the PWell 202, forms an anode of a diode element.

  The PWell 202 is an example of a one-conductivity type semiconductor region, the N + diffusion layer 203 is an example of a reverse conductivity type diffusion layer, and the P + diffusion layer 204 is an example of a one-conduction type diffusion layer. Further, the PWell 202, the N + diffusion layer 203, and the P + diffusion layer 204 form a diode layer 301.

  A lower layer 302 is formed on the diode layer 301. In the lower layer 302, a plurality of first vias CT0, which are provided on the N + diffusion layer 203 and the P + diffusion layer 204 along the X direction, are first wirings extending in the X direction. The metal wiring M1, the plurality of second vias CT1 provided along the X direction, and the metal wiring M2 as the second wiring extending in the X direction are stacked in this order.

  An intermediate layer 303 is formed on the lower layer 302. In the intermediate layer 303, a plurality of metal wirings M3 that are third wirings are stacked on the metal wirings M2 via vias CT2 that are third vias.

  The metal wiring M3 extends in the Y direction, and a plurality of metal wirings M3 are arranged in parallel along the X direction. The via CT2 connects each metal wiring M2 such that each metal wiring M3 is connected to every other metal wiring M2 intersecting with the metal wiring M3, and adjacent metal wirings M3 are connected to different metal wirings M2. Are provided along the X direction.

  As a result, the metal wiring M3 is divided into a reverse-conduction-type side wiring that conducts to the N + diffusion layer 203 and a one-conduction-type side wiring that conducts to the P + diffusion layer 204. Hereinafter, the metal wiring M3 serving as the one-conductivity-type side wiring is referred to as the one-conductivity-side metal wiring M3, and the metal wiring M3 serving as the reverse-conductivity-type side wiring is referred to as the reverse-conductivity-side metal wiring M3.

  An upper layer 304 is formed on the intermediate layer 303. In the upper layer 304, a metal wiring M4 extending along the X direction via the via CT3 is formed on each of the metal wirings M3. There are two metal wirings M4. One metal wiring M4 is provided at the end of the ESD protection circuit 100 and is a power supply wiring that is electrically connected to the PAD 110, and the other metal wiring M4 is provided at the center of the protection circuit. Terminal wiring that is electrically connected to the ground terminal VSS. The terminal wiring is a power supply line that supplies a ground potential as a predetermined potential. In the via CT3, the metal wiring M3 on the one conductivity type side is electrically connected to the metal wiring M4 connected to the PAD 110, and the metal wiring M3 on the opposite conductivity type side is electrically connected to the metal wiring M4 connected to the ground terminal VSS. Are provided along the X direction.

  3 to 6, a plurality of vias CT <b> 0 to CT <b> 3 are described as one for simplification. For example, in FIG. 3, one via CT0 to CT2 is shown for each N + diffusion layer 203 and P + diffusion layer 204, but actually there are a plurality of vias for each N + diffusion layer 203 and P + diffusion layer 204. .

  In the above configuration, the resistance values of the metal wiring M3A at the end of the metal wiring M3 on the one conductivity type side and the metal wiring M3B at the end of the metal wiring M3 on the reverse conductivity type side are the other resistance values, respectively. It is assumed that the resistance value is lower than that of the metal wiring M3. Specifically, the metal wiring M3 is made of the same material, and each of the metal wirings M3A and M3B is thicker than the other metal wiring M3.

  In the ESD protection circuit 100 described above, the discharge current discharged from the PAD 110 flows to each of the metal wirings M3 on the reverse conductivity type via the metal wiring M4 and the via CT3, and thereafter, the via CT2, the metal wiring M2, Each of N + diffusion layers 203 is discharged via via CT1, metal wiring M1 and via CT0. Then, the discharge current flows to the P + diffusion layer 204 through the PWell 202, and from there, each of the metal wiring M3 on the one conductivity type side through the via CT0, the metal wiring M1, the via CT1, the metal wiring M2, and the via CT2. Flowing into. Then, the discharge current is discharged to the ground terminal VSS through the via CT03 and the metal wiring M4.

  At this time, since the resistance values of the metal wirings M3A and M3B at the ends are lower than the resistance values of the other metal wirings M3, the resistance values of the discharge paths at the ends of the discharge paths through which the discharge current flows are lowered. Therefore, it is possible to suppress a large amount of current from flowing intensively through the diode element disposed in the central portion. Further, since the number of metal wirings M4 connected to the ground terminal VSS has not increased, it is possible to suppress an increase in the occupation area of the ESD protection circuit 100.

  In this embodiment, the one conductivity type is P-type and the reverse conductivity type is N-type, but the one conductivity type may be N-type and the reverse conductivity type may be P-type. In this case, the metal wiring M4 that is electrically connected to the metal wiring M3 on the opposite conductivity type side is connected to the power supply terminal instead of the ground terminal VSS. In this case, the metal wiring M4 that is electrically connected to the metal wiring M3 on the opposite conductivity type side serves as a power supply line that supplies a power supply potential as a predetermined potential.

  Further, as described above, the number of diode elements is not limited to four. Specifically, the diode element may be at least the first and second diode elements. For example, at least the diode element 101 (first diode element) and the diode element 102 (second diode element) may be provided. In this case, the number of contact holes, which are the vias CT0 to CT3 provided in the path connecting the diode element 101 and the wiring 140, is the number of contacts that are the vias CT0 to CT3 provided in the path connecting the diode element 102 and the wiring 140. It is different from the number of holes. The first wirings are metal wirings M1 to M3 provided in a path connecting the diode element 101 and the wiring, and the metal wirings M1 to M3 are provided in the path connecting the diode element 102 and the wiring. The width of the second wiring is different.

  As described above, the protection circuit (100) according to the present embodiment includes the one conductivity type semiconductor region (202), the one conductivity type diffusion layer (204) formed in the semiconductor region (202), and the reverse conductivity type. A diffusion layer (204) of one conductivity type and a diffusion layer (203) of opposite conductivity type extending in a first direction (X direction). What is the first direction? A plurality of diode layers (301) arranged alternately in the intersecting second direction (Y direction), one conductivity type side wiring (M3) conducting to each one conductivity type diffusion layer (204), and each reverse The conductive type diffusion layer (203) and the reverse conductive side wiring (M3) that conducts are provided, and the one conductive type side wiring (M3) and the reverse conductive side wiring (M3) are arranged in the second direction (Y direction). An intermediate layer (303) on the diode layer that extends and is arranged in parallel in the first direction (X direction) alternately. The one-conductivity-type side wiring (M3A) at the end in each one-conductivity-type side wiring (M3) and the reverse-conductivity-type side wiring (M3B) at the end in each reverse-conductivity-type side wiring (M3) Is configured to be lower than the resistance values of the other one conductivity type side wiring (M3) and the other reverse conductivity type side wiring (M3).

  Further, in the protection circuit (1) of this embodiment, each one-conductivity-type side wiring (M3) and each reverse-conductivity-type side wiring (M3) are formed of the same material, and the one-conductivity-type side wiring (M3A) at the end And each of the opposite conductivity type wiring (M3B) at the end is configured to be thicker than the other one conductivity type wiring (M3) and the other opposite conductivity type wiring (M3).

  In addition, the protection circuit (100) of the present embodiment further includes a lower layer (302) formed between the diode layer (301) and the intermediate layer (303), and each of the lower layers (302) has one conductivity type. A plurality of first vias (CT0) provided in the first direction (X direction) on the diffusion layer (204) and the opposite conductivity type diffusion layer (203), extending in the first direction. The first wiring (M1) existing, a plurality of second vias (CT1) provided along the first direction, and the second wiring (M2) extending in the first direction are stacked in order. The one-conductivity-type-side wiring (M1) is electrically connected to each of the wirings stacked on the one-conductivity-type diffusion layer (204) of the second wiring via the via (CT2). The side wiring (M1) is that of the wiring stacked on each of the opposite conductivity type diffusion layers (203) of the second wiring. Les and configured to conduct through a via (CT2).

  The protection circuit (100) of the present embodiment further includes an upper layer (304) formed on the intermediate layer (303), and the upper layer (304) includes each one-conductivity-type side wiring (M3). A terminal wiring (M4) that is electrically connected via the via (CT3) and electrically connected to the ground terminal (VSS) or the power supply terminal, and is connected to each reverse conductivity type side wiring (M3) via the via, and a power supply And a power supply wiring (M4) having a conductive pad.

  In addition, the semiconductor device of the present embodiment supplies the pad (110), the internal circuit (130), the wiring (140) connecting the pad (110) and the internal circuit (130), and a predetermined potential. A protection circuit (100) comprising at least first and second diode elements (101, 102) provided between the power line (M4) and the wiring (140) and the power line (M4), The number of first contact holes (CT0 to CT3) provided in the path connecting the first diode element (101) and the wiring (140) is the number of the second diode element (102) and the wiring (140). And a protection circuit (100) different from the number of second contact holes (CT0 to CT3) provided in the path connecting the two.

  In the semiconductor device of the present embodiment, the protection circuit (100) includes the first wirings (M1 to M3) provided in the path connecting the wiring (140) and the first diode element (101), A second wiring (M1 to M3) provided in a path connecting the wiring (140) and the second diode element (102), and the widths of the first wiring and the second wiring are different; Configured as follows.

  In addition, the semiconductor device of the present embodiment supplies the pad (110), the internal circuit (130), the wiring (140) connecting the pad (110) and the internal circuit (130), and a predetermined potential. Power supply line (M4), a power supply line (M4) for supplying a constant potential, and at least first and second diode elements (101, 101) provided between the wiring (140) and the power supply line (M4). 102), the wiring width of the first wirings (M1 to M3) provided in the path connecting the wiring (140) and the first diode element (101) is the wiring (140) and the second diode element (102) are configured to be different from the wiring width of the second wirings (M1 to M3) provided in the path connecting the second diode element (102).

  In the semiconductor device of this embodiment, the protection circuit (100) is an electrostatic protection circuit that protects the internal circuit (130) from the surge voltage applied to the pad (110).

  Next, a second embodiment will be described.

  FIG. 7 is a top view showing a layout of the ESD protection circuit 100 of the present embodiment. 8 is a cross-sectional view of the ESD protection circuit 100 taken along the line D-D ′ of FIG. 7 in FIG.

  The ESD protection circuit 100 shown in FIGS. 7 and 8 is more conductive than the one-conductivity-type side metal wiring M3A, as compared with the ESD protection circuit 100 of the first embodiment shown in FIGS. The resistance value of each one-conductivity-type metal wiring M3 increases toward the metal wiring M3 at the center of the mold-side metal wiring M3, and the opposite-conductivity-type metal wiring M3B at the end. To the metal wiring M3 at the center of the metal wiring M3 on the opposite conductivity type side, the resistance value of the metal wiring M3 on the opposite conductivity type side increases.

  Specifically, the metal wiring M3 is formed of the same material, and the metal wiring M3 on the one conductivity type side becomes thinner from the metal wiring M3A toward the metal wiring M2 on the one conductivity type side in the center, and The metal wiring M3 on the reverse conductivity type side is narrower from the metal wiring M3B toward the metal wiring M3 on the reverse conductivity type side in the center.

  In the present embodiment, since the difference in resistance value between the discharge path at the end of the discharge path through which the discharge current flows and the discharge path in the center can be made smaller than in the first embodiment, It is possible to more significantly suppress a large amount of current from flowing intensively through the arranged diode elements.

  As described above, the protection circuit (100) according to the present embodiment changes from the one conductivity type side wiring (M3A) at the end to the one conductivity type side wiring (M3) at the center of the one conductivity type side wiring (M3). The resistance value of each one-conductivity-type side wiring (M3) increases, and the reverse-conductivity at the center of each reverse-conductivity-type side wiring (M3) from the reverse-conductivity-type side wiring (M3B) at the end The resistance value of each reverse conductivity type side wiring (M3A) is increased toward the mold side wiring (M3).

  Further, in the protection circuit (100), each one conductivity type side wiring (M3) and each reverse conductivity type side wiring (M3) are formed of the same material, and each one conductivity type side wiring (M3A) is connected to each one conductivity type. Each one conductivity type side wiring (M3) becomes thinner toward one conductivity type side wiring (M3) at the center of the mold side wiring (M3) and the opposite conductivity type side wiring ( Each reverse-conductivity-type side wiring (M3) is configured to become thinner from M3B) toward the reverse-conductivity-type-side wiring (M3) at the center of each reverse-conductivity-type side wiring (M3).

  Next, the effect of each embodiment will be described in more detail.

  Here, the resistance value of the discharge path in the ESD protection circuit 100 ′ of the related technology shown in FIGS. 15 to 20 and the resistance of the discharge path in the ESD protection circuit 100 described in the first and second embodiments. Compare the value.

  FIG. 9 is a diagram showing discharge paths in the related art, FIG. 10 is a diagram showing discharge paths in the first embodiment, and FIG. 11 is a diagram showing discharge paths in the second embodiment. .

  Specifically, FIGS. 9 to 11 show the layout of the ESD protection circuit 100 ′ of the related art and the ESD protection circuit 100 described in the first and second embodiments. In 100 'and 100, anodes 1A to 5A and cathodes 1B to 4B of diode elements are arranged in parallel.

  Here, the resistance value of the discharge path passing through the cathode 2A and the anode 3B is calculated. Specifically, the discharge current discharged from the PAD (110 ′ or 110) is a first point that is the intersection of the metal wiring (M3 ′ or M3A) on the opposite conductivity type side and the via (CT2 or CT2 ′). Flows to B, D, F, H, I, J, L and then to the second point 2, 4, 6, 8, 10, 12 which is the N + diffusion layer (151 ′ or 203) corresponding to the cathode 2A Discharged. The discharged discharge current corresponds to the anode 3B, and is a third point 1, 3, 5, 7, 9, 11 that is a P + diffusion layer (152 ′ or 204) adjacent to the second point. , 13 flows to the fourth point A, C, E, G, I, K, M, which is the intersection of the metal wiring (M3 ′ or M3) on one conductive side and the via (CT2 ′ or CT2), and It is discharged to the ground terminal VSS.

  Hereinafter, the discharge path passing through the points X and Y is referred to as a discharge path (XY), and the discharge paths (A-1, B-2, C-3, D-4) shown in FIGS. , E-5, F-6, G-7, H-8, I-9, J-10, K-11, L-12, M-13).

  FIG. 12 shows discharge paths (A-1, B-2, C-3, D-4, E-5, F-6, G-7, H-8, I-9, J-10, K- 11, L-12, M-13). FIG. 13 is a graph of the resistance values shown in FIG. 12, and FIG. 14 is arranged at the center in FIG. Discharge path (B-2, C-3, D-4, E-5, F-6, G-7, H-8, I-9, J-10, K-11, L-12) portion This is an enlargement of the graph. Note that the channel resistance values in the Pwell of the diode element are all measured as constant.

  As shown in FIGS. 12 and 13, in the related art, the difference in resistance value between the path A-1 having the highest resistance value and the path H-8 having the lowest resistance value was 6.143Ω. In the first embodiment, the difference in resistance value between the path A-1 having the highest resistance value and the path I-9 having the lowest resistance value is 2.1572Ω. In the second embodiment, the resistance value is The difference in resistance value between the highest path A-1 and the lowest path J-10 is 1.38758Ω. Therefore, in the first embodiment, the difference in resistance value is reduced by 65%, and in the second embodiment, the difference in resistance value is reduced by 77.5%.

  Also, as shown in FIG. 14, in the discharge path arranged in the center, the difference in resistance value between the path having the highest resistance value and the path having the lowest resistance value is 0.8399Ω in the related art. In contrast, in the first embodiment, it is 0.4703Ω, and in the second embodiment, it is 0.3652Ω. That is, the variation in resistance value in the discharge path disposed in the center is also suppressed.

  In each embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration. For example, a semiconductor device including the ESD protection circuit 100 is also an embodiment of the present invention.

100 ESD protection circuit 101-104 Diode element 110 PAD
201 Semiconductor substrate 202 PWell
203 N + diffusion layer 204 P + diffusion layer 301 Diode layer 302 Lower layer 303 Intermediate layer 304 Upper layer M1 to M4 Metal wiring CT0 to CT3 Via

Claims (12)

A one-conductivity-type semiconductor region, and a one-conductivity-type diffusion layer and a reverse-conductivity-type diffusion layer formed in the semiconductor region, wherein the one-conductivity-type diffusion layer and the reverse-conductivity-type diffusion layer are A plurality of diode layers extending in a first direction and alternately arranged in a second direction intersecting the first direction;
Each of the one conductivity type diffusion layer has a one conductivity type side wiring and the opposite conductivity type diffusion layer has a reverse conductivity side wiring, and the one conductivity type side wiring and the reverse conductivity side wiring are An intermediate layer on the diode layer that extends in the second direction and is arranged in parallel in the first direction.
The resistance value of the one conductivity type side wiring at the end in each one conductivity type side wiring and the reverse conductivity type side wiring at the end in each reverse conductivity type side wiring is the other one conductivity type side wiring and other A protection circuit lower than the resistance value of the reverse conductivity type wiring. Each one conductivity type side wiring and each reverse conductivity type side wiring are formed of the same material,
The one conductivity type side wiring at the end and the opposite conductivity type side wiring at the end are thicker than the other one conductivity type side wiring and the other reverse conductivity type side wiring, respectively. The protection circuit described.   The resistance value of each one conductivity type side wiring increases from the one conductivity type side wiring at the end toward the one conductivity type side wiring at the center among the one conductivity type side wirings, The resistance value of each reverse conductivity type side wire increases from the reverse conductivity type side wire toward the reverse conductivity type side wire in the center among the reverse conductivity type side wires. Protection circuit. Each one conductivity type side wiring and each reverse conductivity type side wiring are formed of the same material,
Each one conductivity type side wiring becomes thinner from one conductivity type side wiring at the end toward one conductivity type side wiring at the center of each one conductivity type side wiring, and the opposite conductivity type at the end 4. The protection circuit according to claim 3, wherein each of the reverse conductivity type side wires becomes narrower from the side wire toward the reverse conductivity type side wire at the center among the reverse conductivity type side wires. Further comprising a lower layer formed between the diode layer and the intermediate layer;
In the lower layer, a plurality of first vias provided in the first direction and extending in the first direction on the diffusion layers of one conductivity type and diffusion layers of the opposite conductivity type. A first wiring, a plurality of second vias provided along the first direction, and a second wiring extending in the first direction are stacked in this order.
Each one conductivity type side wiring is electrically connected to each of the wirings stacked on each one conductivity type diffusion layer of the second wiring through a via, and each reverse conductivity type side wiring is connected to the second wiring. 5. The protection circuit according to claim 1, wherein the protective circuit is electrically connected to each of the wirings stacked on each of the opposite conductivity type diffusion layers through vias. Further comprising an upper layer formed on the intermediate layer,
The upper layer is
A terminal wiring that is electrically connected to each one-conductivity-type-side wiring through a via and that is electrically connected to a ground terminal or a power supply terminal;
6. The protection circuit according to claim 1, further comprising: a power supply wiring connected to each reverse-conductivity-type side wiring through a via and having a power supply pad conductive. 7.   A semiconductor device comprising the protection circuit according to claim 1. Pad,
Internal circuitry,
Wiring connecting between the pad and the internal circuit;
A power supply line for supplying a predetermined potential;
A protection circuit comprising at least first and second diode elements provided between the wiring and the power supply line, wherein the first circuit is provided in a path connecting the first diode element and the wiring. The number of contact holes in the semiconductor device includes a protection circuit different from the number of second contact holes provided in a path connecting the second diode element and the wiring.   The protection circuit includes a first wiring provided in a path connecting the wiring and the first diode element, and a second wiring provided in a path connecting the wiring and the second diode element. 9. The semiconductor device according to claim 8, further comprising: a wiring, wherein the first wiring and the second wiring have different widths.   The semiconductor device according to claim 8, wherein the protection circuit is an electrostatic protection circuit that protects the internal circuit from a surge voltage applied to the pad. Pad,
Internal circuitry,
A wiring connecting the pad and the internal circuit;
A power supply line for supplying a predetermined potential;
A protection circuit including at least first and second diode elements provided between the wiring and the power supply line, wherein the protection circuit is provided in a path connecting the wiring and the first diode element. A semiconductor device comprising: a wiring width of the first wiring; and a protection circuit different from a wiring width of the second wiring provided in a path connecting the wiring and the second diode element.   The semiconductor device according to claim 11, wherein the protection circuit is an electrostatic protection circuit that protects the internal circuit from a surge voltage applied to the pad.

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