JP2014230134A - Delay adjustment circuit - Google Patents

Abstract

A delay adjustment circuit capable of improving the resolution of adjustment of delay amount while reducing current consumption is provided by a PMOS transistor MP1 and an NMOS transistor MN1 between terminals u1 to u3. A critical path that minimizes the propagation delay of the signal of level transition is configured, and a critical path that minimizes the propagation delay of the signal of high level transition is configured by the NMOS transistor MN2 and the PMOS transistor MP2 between the terminals d1 to d3. . In each stage, the transistors are connected via switch circuits SWP1, SWP1, and SWP2, SWN2, and each stage has a logically similar configuration to the inverter gate. Since the switch circuits SWP1, SWP1, and SWP2, SWN2 are provided, the through current between the transistors is suppressed, and the current consumption is reduced. [Selection] Figure 2

Description

  The technology disclosed in the present application relates to a delay adjustment circuit capable of adjusting a delay amount, and more particularly to a delay adjustment circuit used for signal timing adjustment in a digital integrated circuit.

  Conventionally, in a digital integrated circuit, a delay adjustment circuit such as a so-called DLL (Delay Locked Loop) circuit is used for signal timing adjustment. The DLL circuit is configured by serially connecting delay units having a basic delay time in multiple stages. Selection units such as a selection switch are provided at the output end of each delay unit, and a signal having a desired delay time is extracted by selection of the selection unit. As the delay unit, an inverter gate or a buffer gate in which a plurality of inverter gates are connected in series is used (for example, Patent Document 1).

Japanese Patent Laid-Open No. 11-145798

  However, since the delay unit is composed of a circuit based on an inverter gate, the delay time obtained by the delay unit is reduced for the purpose of improving the resolution of delay time adjustment in the delay adjustment circuit. When speeding up, the threshold voltage of each MOS transistor constituting the inverter gate may be reduced. As a result, there is a possibility that the through current between the power supply voltage and the ground voltage may increase during the period when the input signal of the delay unit transitions due to switching. Moreover, there is a risk that the leakage current at the time of off may become a level that cannot be ignored due to the reduction of the threshold voltage of the MOS transistor. This is a problem because the current consumption increases.

  In this respect, in the background art exemplified in Patent Document 1 and the like, by connecting the switch means in series to the waveform shaping circuit (inverter gate) and turning off the switch means immediately after the output of the waveform shaping circuit is inverted, This is intended to reduce the through current flowing in the waveform shaping circuit. However, in this case, a time constant circuit composed of a resistor and a capacitor is formed in the input path of the waveform shaping circuit, and a gentle curve obtained by charging and discharging the capacitor with the time constant circuit is drawn and input. It is assumed that the signal to be changed changes. Even after the signal output from the waveform shaping circuit is inverted, the input signal is still changing. The background art only describes that the through current is suppressed after the inversion of the signal output from the waveform shaping circuit. It is a problem that the through current cannot be sufficiently suppressed by switching the signal input to the inverter gate.

  The technology disclosed in the present application has been proposed in view of the above problems, and an object thereof is to provide a delay adjustment circuit capable of improving the resolution of delay amount adjustment while reducing current consumption. To do.

  The delay adjustment circuit according to the technique disclosed in the present application is configured by connecting delay buffers in multiple stages in series. The first configuration of the delay buffer is a configuration related to signal propagation. A first conductivity type first MOS transistor and a second conductivity type first MOS transistor are provided, and a first delay signal in which a unit delay time is given to an input of a level transition in the first direction of the first signal is output. In addition, the second conductivity type second MOS transistor and the first conductivity type second MOS transistor are provided, and a unit for a level transition input in a second direction opposite to the first direction of the second signal in phase with the first signal is provided. A second delay signal with a delay time is output.

  The first conductivity type first MOS transistor has a gate terminal receiving a first signal and a source terminal connected to a first power source. The second conductivity type first MOS transistor has a gate terminal connected to the drain terminal of the first conductivity type first MOS transistor, a source terminal connected to the second power source, and a first delay signal output from the drain terminal. Thus, a buffer circuit having a shortest signal propagation delay with respect to the level transition of the first signal in the first direction is configured. In the second conductivity type second MOS transistor, the gate terminal receives the second signal, and the source terminal is connected to the second power source. The first conductivity type second MOS transistor has a gate terminal connected to the drain terminal of the second conductivity type second MOS transistor, a source terminal connected to the first power supply, and a second delay signal output from the drain terminal. Thereby, a buffer circuit having a shortest signal propagation delay with respect to the level transition of the second signal in the second direction is configured.

  The second configuration of the delay buffer is a configuration related to prevention of a through current. First and second switch circuits connected in parallel between the drain terminal of the first conductivity type first MOS transistor and the drain terminal of the second conductivity type second MOS transistor; and the drain terminal of the second conductivity type first MOS transistor; A third switch circuit and a fourth switch circuit connected in parallel are provided between the drain terminal of the first conductivity type second MOS transistor.

The first switch circuit includes first conductive type third and fourth MOS transistors connected in series. The gate terminal of the first conductivity type third MOS transistor is connected to the drain terminal of the second conductivity type first MOS transistor, and the gate terminal of the first conductivity type fourth MOS transistor is the first conductivity type second MOS transistor of the preceding delay buffer. Connected to the drain terminal.
The second switch circuit includes second conductive type third and fourth MOS transistors connected in series. The gate terminal of the second conductivity type third MOS transistor is connected to the drain terminal of the second conductivity type first MOS transistor of the preceding delay buffer, and the gate terminal of the second conductivity type fourth MOS transistor is the first conductivity type second MOS transistor. Connected to the drain terminal.
The third switch circuit includes first conductive type fifth and sixth MOS transistors connected in series. The gate terminal of the first conductivity type fifth MOS transistor is connected to the drain terminal of the first conductivity type first MOS transistor of the preceding delay buffer, and the gate terminal of the first conductivity type sixth MOS transistor is the second delay buffer of the next delay buffer. Connected to the drain terminal of the second conductivity type second MOS transistor.
The fourth switch circuit includes second conductivity type fifth and sixth MOS transistors connected in series. The gate terminal of the second conductivity type fifth MOS transistor is connected to the drain terminal of the first conductivity type first MOS transistor of the next-stage delay buffer, and the gate terminal of the second conductivity type sixth MOS transistor is the same as that of the delay buffer of the previous stage. Connected to the drain terminal of the second conductivity type second MOS transistor.

  In the delay adjustment circuit, the first and second delay signals output from the delay buffer are input to the delay buffer of the next stage as the first and second signals of the next stage, respectively, and are connected in series in multiple stages.

In the delay adjustment circuit according to the technique disclosed in the present application, the first configuration of the delay buffer configures a critical path that has the shortest propagation delay time as a path through which the level transition in the first direction of the first signal propagates. A delay of unit delay time is given. Further, a critical path having the shortest propagation delay time is formed as a path through which the level transition in the second direction of the second signal propagates, and a delay of unit delay time is given. Thereby, a delay signal in which a unit delay time is given for each delay buffer is obtained for each of the level transition in the first direction of the first signal and the level transition in the second direction of the second signal. The delay time can be adjusted with the resolution of the unit delay time according to the position where the output signal is taken out of the delay buffers connected in series in multiple stages.
Further, the second configuration of the delay buffer includes the first and second switch circuits connected in parallel and the third and fourth switch circuits connected in parallel, so that the drains of the first conductivity type first MOS transistors are respectively provided. Penetration at the time of signal level transition between the terminal and the drain terminal of the second conductivity type second MOS transistor and between the drain terminal of the second conductivity type first MOS transistor and the drain terminal of the first conductivity type second MOS transistor Current can be suppressed.

1 is a configuration diagram of a system to which a technique disclosed in the present application is applied. It is a circuit diagram of the delay buffer of the embodiment according to the present application. It is a circuit diagram showing a delay adjustment circuit of a first embodiment. 3 is a timing chart for explaining the operation of the delay adjustment circuit according to the first embodiment; It is a circuit diagram which shows the delay adjustment circuit of 2nd Embodiment. It is a circuit diagram which shows another example of the switch circuit provided in the delay buffer of embodiment.

  For example, the transmission-side functional circuit 1 that sends various signals to the reception-side functional circuit such as the high-speed memory 2 through the wiring path 3 wired on the circuit board has a skew generated between the signals to be transmitted. In order to adjust, a DLL circuit 11 may be provided for each signal. Taking the case of the high-speed memory 2 as an example of the receiving side functional circuit, the transmission signal is a clock signal CK, a chip select signal CS, a row address strobe signal RAS, a column address strobe signal CAS, and a number of control signals, a number of addresses. The signals AD0, AD1, AD2,... And a large number of data signals DQ0, DQ1, DQ2,. In such a case, the total number of DLL circuits 11 provided for each signal to be transmitted becomes large, and it is required to reduce the total value of current consumption during operation and standby.

  The delay buffer and the delay adjustment circuit configured by the delay buffer described below are preferably used for the delay line of the DLL circuit 11, for example. The delay time can be adjusted with the resolution of the unit delay time obtained as the critical path with the shortest propagation delay time for the signal propagation path in the delay buffer. This is a circuit capable of reducing current consumption during operation and standby due to the above.

  FIG. 2 shows a circuit diagram of the delay buffer 10. First, a first configuration that is a configuration related to signal propagation will be described. The two input terminals u1 and d1 to which the in-phase signal is input are connected to the gate terminals of the PMOS transistor MP1 and the NMOS transistor MN2, respectively. The drain terminals of the PMOS transistor MP1 and the NMOS transistor MN2 are respectively connected to the gate terminals of the NMOS transistor MN1 and the PMOS transistor MP2 in the next stage. The drain terminals of the next-stage NMOS transistor MN1 and PMOS transistor MP2 are connected to output terminals u3 and d3, respectively.

  The path from the input terminal u1 to the output terminal u3 constitutes a buffer circuit in which the signal propagation path is a critical path having the shortest propagation delay time. This is a critical path through which a signal input to the input terminal u1 propagates with a critical delay time along an edge where the signal transitions from a high level to a low level. The path from the input terminal d1 to the output terminal d3 constitutes a buffer circuit in which the signal propagation path is a critical path having the shortest propagation delay time. This is a critical path through which a signal input to the input terminal d1 propagates with a critical delay time on an edge where the signal transitions from a low level to a high level. Here, the critical delay time is a propagation delay time when the delay buffer 10 propagates along a critical path constituting the buffer circuit. This is the unit delay time that the delay buffer 10 gives to the input signal. The delay time of the delay buffer 10 is defined by a critical path, and this delay time is defined as a unit delay time, and a resolution for adjusting the delay time is provided in the delay adjustment circuits 20 and 30 described later in which the delay buffer 10 is connected in multiple stages. To do.

  On the other hand, for the opposite edge, that is, the edge where the signal input to the input terminal u1 transitions from low level to high level, and the edge where the signal input to the input terminal d1 transitions from low level to high level, In each path, that is, the path from the input terminal u1 to the output terminal u3 and the path from the input terminal d1 to the output terminal d3, the signal propagates with a delay of unit delay time.

  As apparent from the fact that the drain terminal of the PMOS transistor MP1 and the drain terminal of the NMOS transistor MN2 and the drain terminal of the PMOS transistor MP2 and the drain terminal of the NMOS transistor MN1 are connected by a switch circuit, which will be described later, respectively. If the time difference between transitions is discarded, the circuit operates logically at the same potential. Further, the input terminals u1 and d1 and the output terminals u3 and d3 are also logically at the same potential if the time difference of signal transition is discarded. Accordingly, it can be said that the PMOS transistor MP1 and the NMOS transistor MN2 and the PMOS transistor MP2 and the NMOS transistor MN1 logically have a circuit configuration equivalent to that of the inverter gate.

  Next, a second configuration that is a configuration related to prevention of through current will be described. Between the drain terminal of the PMOS transistor MP1 and the drain terminal of the NMOS transistor MN2, switch circuits SWP1 and SWN1 connected in parallel with each other are interposed. In the switch circuit SWP1, two PMOS transistors MP3 and MP4 are connected in series. Similarly, in the switch circuit SWN1, two NMOS transistors MN3 and MN4 are connected in series. Terminals p11, p12, n11, and n12 are connected to the gate terminals of the PMOS transistors MP3 and MP4 and the NMOS transistors MN3 and MN4, respectively.

  Similarly, switch circuits SWP2 and SWN2 connected in parallel are interposed between the drain terminal of the PMOS transistor MP2 and the drain terminal of the NMOS transistor MN1. In the switch circuit SWP2, two PMOS transistors MP5 and MP6 are connected in series. Similarly, the switch circuit SWN2 has two NMOS transistors MN5 and MN6 connected in series. Terminals p21, p22, n21, and n22 are connected to the gate terminals of the PMOS transistors MP5 and MP6 and the NMOS transistors MN5 and MN6, respectively.

  FIG. 3 shows the delay adjustment circuit 20 of the first embodiment. The delay buffer 10 is configured by serial connection in multiple stages. In the delay adjustment circuit 20, as an example, a case where five stages of delay buffers X1 to X5 are connected in series is shown. Two stages of inverter gates I1 and I2 are arranged in the preceding stage of the delay buffer X1 to constitute the first stage buffer circuit. The input signal IN is input to the input terminal of the inverter gate I1.

  Connection to each terminal of the delay buffer X1 will be described. The output terminal of the inverter gate I2 is connected to the input terminals u1 and d1, and the signal inz is input. The output terminals u3 and d3 are connected to the input terminals u1 and d1 of the delay buffer X2 at the next stage, respectively, and the signals X1. u3, X1. d3 is output. The terminals p11 and p12 of the switch circuit SWP1 are connected to the output terminal u3 and the output terminal of the inverter gate I2, respectively, and the signals X1. u3 and inz are input. The output terminals d1 and d3 of the inverter gate I2 are connected to the terminals n11 and n12 of the switch circuit SWN1, respectively, and the signals inz, X1. d3 is input. The output terminal of the inverter gate I1 and the terminal d2 of the next-stage delay buffer X2 are connected to the terminals p21 and p22 of the switch circuit SWP2, respectively, and the signals inx, X2. d2 is input. The terminals n21 and n22 of the switch circuit SWN2 are connected to the terminal u2 of the next-stage delay buffer X2 and the output terminal of the inverter gate I1, respectively. u2 and inx are input.

  The connection relationship of each terminal of the delay buffer X2 in the next stage is relatively the same as that for each terminal of the delay buffer X1. Here, the output terminals of the inverter gates I1 and I2 correspond to the terminals u2 and d2 and the terminals u3 and d3 of the delay buffer 10, respectively.

  Specifically, it is as follows. The output terminals u3 and d3 are connected to the input terminals u1 and d1 of the delay buffer X3 in the next stage, respectively, and the signals X2. u3, X2. d3 is output. An output terminal u3 and a terminal d3 of the preceding delay buffer X1 are connected to the terminals p11 and p12 of the switch circuit SWP1, respectively. u3, X1. d3 is input. The terminals n11 and n12 of the switch circuit SWN1 are connected to the terminal u3 and the output terminal d3 of the delay buffer X1 in the previous stage, respectively, and the signals X1. u3, X2. d3 is input. The terminals p21 and p22 of the switch circuit SWP2 are connected to the terminal u2 of the delay buffer X1 at the previous stage and the terminal d2 of the delay buffer X3 at the next stage, respectively. u2, X3. d2 is input. The terminals n21 and n22 of the switch circuit SWN2 are connected to the terminal u2 of the delay buffer X3 at the next stage and the terminal d2 of the delay buffer X1 at the previous stage, respectively. u2, X1. d2 is input.

  Further, since the connection relationship of the terminals of the next-stage delay buffers X3 to X5 is relatively the same as that for the terminals of the delay buffer X2, description thereof will be omitted.

  FIG. 4 is a timing chart of signals related to the input / output of the delay buffer X1 provided in the delay adjustment circuit 20. Since the signals related to the delay buffers X2 to X5 are sequentially operated in the same manner, the following description is omitted.

  For the high level transition of the input signal IN, the terminals d1 to d3 are critical paths. In response to the high level transition of the input signal IN, the signal inx transitions to the low level and the signal inz transitions to the high level sequentially from the output terminals of the inverter gates I1 and I2. In response to the low level transition of the signal inx, the circuit of the delay buffer X1 <X1. SWN2> is turned off. Switch circuit <X1. This is because in SWN2>, the NMOS transistor MN6 is turned off via the terminal n22.

  Further, in response to the high level transition of the signal inz, the PMOS transistor MP1 is turned off, the NMOS transistor MN2 is turned on, and the terminal d2 is at the low level (the signal X1.d2 is at the low level transition). Further, the switch circuit of the delay buffer X1 <X1. SWP1> is turned off. Switch circuit <X1. This is because in SWP1>, the PMOS transistor MP4 is turned off via the terminal p12. At this time, the switch circuit of the delay buffer X1 <X1. SWN1> is in the off state. For this reason, the terminal u2 is separated from the terminal d2, and the charge is not extracted by the NMOS transistor MN2. The terminal u2 is maintained in the high level state by the PMOS transistor MP1 that was turned on at the low level before the high level transition of the input signal IN. Both the PMOS transistor MP1 and the NMOS transistor MN2 are turned on by the signal inz, but the switch circuit <X1. SWP1>, <X1. Since both SWN1> are off, the through current accompanying switching between the PMOS transistor MP1 and the NMOS transistor MN2 does not flow.

  At this time, the terminal d2, which is a critical path at the time of the high transition of the input signal IN, is in a state of transitioning to the low level (signal X1.d2 = L). On the other hand, the terminal u2, which is not a critical path in this case, is maintained in a high level state (signal X1.u2 = H).

  Signal X1. In response to the low level transition of d2, the PMOS transistor MP2 is turned on, and the terminal d3 is at the high level (signal X1.d3 is at the high level transition). At this time, the switch circuit of the delay buffer X1 <X1. SWP2>, <X1. Both SWN2> are in the off state. For this reason, the terminal u3 is disconnected from the terminal d3, and no charge is supplied by the PMOS transistor MP2. At this time, the NMOS transistor MN1 receives the signal X1. Although u2 is at the high level, it is in the on state, but the switch circuit <X1. SWP2>, <X1. Since both SWN2> are in an off state, no through current flows between the PMOS transistor MP2.

  Signal X1. When d3 transits to the high level, the switch circuit <X1. SWN1> is turned on. Switch circuit <X1. This is because in SWN1>, the NMOS transistor MN4 is turned on via the terminal n12. Switch circuit <X1. When SWN1> is turned on, the terminal d2 and the terminal u2 are connected. As a result, the switch circuit <X1. Charge is extracted by the NMOS transistor MN2 through SWN1>, and the terminal u2 becomes the low level having the same potential as the terminal d2. In this case, however, the extraction of the charge by the NMOS transistor MN2 is caused by the switch circuit <X1. Since the switching is performed via SWN1>, the low-level transition of the terminal u2 is gentler than the low-level transition of the terminal d2, which is a critical path in this case.

  Also, signals X1. The high level transition of d3 is propagated to the next-stage delay buffer X2, the terminal d2 of the delay buffer X2 is transitioned to the low level (signal X2.d2 is the low level transition), and the terminal d3 of the delay buffer X2 is further switched to the high level. Transition to level (signal X2.d3 transitions to high level). In this case, the operation of each switch circuit and the like is the same as in the case of the delay buffer X1, and the description thereof is omitted.

  When the terminal d2 of the delay buffer X2 transitions to a low level (the signal X2.d2 transitions to a low level), the switch circuit of the delay buffer X1 <X1. SWP2> is turned on. Switch circuit <X1. This is because in SWP2>, the PMOS transistor MP6 is turned on via the terminal p22. Switch circuit <X1. When SWP2> is turned on, the terminal d3 and the terminal u3 are connected. At this time, the terminal u2 is changed to the low level, and the NMOS transistor MN1 is in the off state. As a result, the switch circuit <X1. Charge is supplied by the PMOS transistor MP2 via SWP2>, and the terminal u3 becomes a high level having the same potential as the terminal d3. However, in this case, the charge supply by the PMOS transistor MP2 is caused by the switching circuit <X1. Since the switching is performed via SWP2>, the high-level transition of the terminal u3 is gentler than the high-level transition of the terminal d3 that is a critical path in this case.

  By the above sequence, the high level transition of the input signal IN propagates through the delay buffer X1. In this case, the signal propagation path composed of the NMOS transistor MN2 and the PMOS transistor MP2 becomes a critical path. The signal level transition in this path is a steep transition that maximizes the driving capability of the transistor. As a result, the high-level transition of the input signal IN propagates through the critical path with the shortest delay time. This delay time is given as a unit delay time, and signals X1. It is output as d3.

  On the other hand, the signal propagation path composed of the PMOS transistor MP1 and the NMOS transistor MN1 is not a critical path. The level transition of the signal in this path is the switch circuit <X1. SWN1>, <X1. Since this is performed via SWP2>, the level transition is gentler than the level transition in the critical route. By making the signal level of the terminals u2 and u3 the same as the level of the terminals d2 and d3 by gradual level transition, the level transition (low level transition) on the opposite side of the input signal IN is prepared. In the low level transition of the input signal IN, the signal propagation path constituted by the PMOS transistor MP1 and the NMOS transistor MN1 becomes a critical path.

  The level transition of the terminals u2 and u3 is delayed from the terminals d2 and d3 in the critical path because the switch circuit interposed between the terminals <X1. SWN1>, <X1. This is because the ON state of SWP2> is delayed with respect to the level transition of the terminals d2 and d3. In this control, the signal propagation path composed of the PMOS transistor MP1 including the terminals u2 and u3 and the NMOS transistor MN1 is not a critical path, and the level only needs to be changed before the low level transition of the input signal IN. Based. Thereby, at the time of level transition of the terminals d2 and d3, the terminals d2 and d3 can be disconnected from the terminals u2 and u3, and a through current generated when both are connected can be suppressed.

  Next, the low level transition of the input signal IN will be described. In this case, the terminals u1 to u3 are critical paths. In response to the low level transition of the input signal IN, the signal inx transitions to the high level and the signal inz transitions to the low level sequentially from the output terminals of the inverter gates I1 and I2. In response to the high level transition of the signal inx, the switch circuit of the delay buffer X1 <X1. SWP2> is turned off. Switch circuit <X1. This is because in SWP2>, the PMOS transistor MP5 is turned off via the terminal p21.

  Further, in response to the low level transition of the signal inz, the NMOS transistor MN2 is turned off, the PMOS transistor MP1 is turned on, and the terminal u2 is at the high level (the signal X1.u2 is at the high level transition). Further, the switch circuit of the delay buffer X1 <X1. SWN1> is turned off. Switch circuit <X1. This is because in SWN1>, the NMOS transistor MN3 is turned off via the terminal n11. At this time, the switch circuit of the delay buffer X1 <X1. SWP1> is in the off state. For this reason, the terminal d2 is disconnected from the terminal u2, and no charge is supplied by the PMOS transistor MP1. The terminal d2 is maintained in the low level state by the NMOS transistor MN2 that was turned on at the high level before the low level transition of the input signal IN. Both the NMOS transistor MN2 and the PMOS transistor MP1 are turned on by the signal inz, but the switch circuit <X1. SWP1>, <X1. Since both SWN1> are in the off state, a through current due to switching between the NMOS transistor MN2 and the PMOS transistor MP1 does not flow.

  At this time, the terminal u2, which is a critical path at the time of the low transition of the input signal IN, is in a state of transitioning to the high level (signal X1.u2 = H). On the other hand, the terminal d2, which is not a critical path in this case, is maintained in a low level state (signal X1.d2 = L).

  Signal X1. In response to the high level transition of u2, the NMOS transistor MN1 is turned on, and the terminal u3 is at the low level (signal X1.u3 is at the low level transition). At this time, the switch circuit of the delay buffer X1 <X1. SWP2>, <X1. Both SWN2> are in the off state. For this reason, the terminal d3 is separated from the terminal u3, and the charge is not extracted by the NMOS transistor MN1. At this time, the PMOS transistor MP2 is connected to the signal X1. d2 is in the on state due to the low level, but the switch circuit <X1. SWP2>, <X1. Since both SWN2> are in the off state, no through current flows between the NMOS transistor MN1.

  Signal X1. When u3 transitions to the low level, the switch circuit <X1. SWP1> is turned on. Switch circuit <X1. This is because in SWP1>, the PMOS transistor MP3 is turned on via the terminal p11. Switch circuit <X1. When SWP1> is turned on, the terminal u2 and the terminal d2 are connected. As a result, the switch circuit <X1. Charge is supplied by the PMOS transistor MP1 via SWP1>, and the terminal d2 becomes a high level having the same potential as the terminal u2. However, in this case, the charge supply by the PMOS transistor MP1 is caused by the switching circuit <X1. Since the switching is performed via SWP1>, the high-level transition of the terminal d2 is more gradual than the high-level transition of the terminal u2, which is a critical path in this case.

  Also, signals X1. The low level transition of u3 is propagated to the delay buffer X2 in the next stage, the terminal u2 of the delay buffer X2 is transitioned to the high level (the signal X2.u2 is the high level transition), and the terminal u3 of the delay buffer X2 is further switched to the low level. Transition to level (signal X2.u3 transitions to low level). In this case, the operation of each switch circuit and the like is the same as in the case of the delay buffer X1, and the description thereof is omitted.

  When the terminal u2 of the delay buffer X2 transits to a high level (the signal X2.u2 transits to a high level), the switch circuit <X1. SWN2> is turned on. Switch circuit <X1. This is because in SWN2>, the NMOS transistor MN5 is turned on via the terminal n21. Switch circuit <X1. When SWN2> is turned on, the terminal u3 and the terminal d3 are connected. At this time, the terminal d2 is transited to the high level, and the PMOS transistor MP2 is in the off state. As a result, the switch circuit <X1. The charge is extracted by the NMOS transistor MN1 through SWN2>, and the terminal d3 becomes a low level having the same potential as the terminal u3. However, in this case, the charge extraction by the NMOS transistor MN1 is performed by the switch circuit <X1. Since the switching is performed via SWN2>, the low-level transition of the terminal d3 is more gradual than the low-level transition of the terminal u3 that is a critical path in this case.

  With the above sequence, the low level transition of the input signal IN propagates through the delay buffer X1. In this case, the signal propagation path composed of the PMOS transistor MP1 and the NMOS transistor MN1 is a critical path. The signal level transition in this path is a steep transition that maximizes the driving capability of the transistor. As a result, the low level transition of the input signal IN propagates through the critical path with the shortest delay time. This delay time is given as a unit delay time, and signals X1. Output as u3.

  On the other hand, the signal propagation path constituted by the NMOS transistor MN2 and the PMOS transistor MP2 is not a critical path. The level transition of the signal in this path is the switch circuit <X1. SWP1>, <X1. Since this is performed via SWN2>, the level transition is gentler than the level transition in the critical route. By making the signal level of the terminals d2 and d3 the same as the level of the terminals u2 and u3 by gradual level transition, the level transition on the opposite side of the input signal IN (high level transition) is prepared.

  The level transition of the terminals d2 and d3 is delayed from the terminals u2 and u3 in the critical path because the switch circuit interposed between the terminals <X1. SWP1>, <X1. This is because the turning on of SWN2> is delayed with respect to the level transition of the terminals u2 and u3. In this control, the signal propagation path constituted by the NMOS transistor MN2 including the terminals d2 and d3 and the PMOS transistor MP2 is not a critical path, and the level only has to be changed before the high level transition of the input signal IN. Based. Thereby, at the time of level transition of the terminals u2 and u3, the terminals u2 and u3 and the terminals d2 and d3 can be separated, and a through current generated when both are connected can be suppressed.

  FIG. 5 shows the delay adjustment circuit 30 of the second embodiment. The delay adjustment circuit 20 of the first embodiment includes a delay buffer X1a instead of the inverter gates I1 and I2 and the delay buffer X1. The delay buffer X1a has the same circuit configuration as that of the delay buffer 10 (FIG. 2). In the delay buffer 1a, the power supply voltage vdd is connected to the terminals p11, p12, p21, and p22 to the switch circuits SWP1 and SWP2 configured by PMOS transistors, and the switches to the switch circuits SWN1 and SWN2 configured by NMOS transistors are connected. A ground voltage vss is connected to the terminals n11, n12, n21, and n22.

  With this configuration, the switch circuits SWP1, SWP2, SWN1, and SWN2 are always maintained in an on state. Accordingly, the drain terminals of the PMOS transistor MP1 and the NMOS transistor MN2 and the PMOS transistor MP2 and the NMOS transistor MN1 are always connected, and the configuration is equivalent to that of a normal inverter gate. Therefore, the delay buffer 1a has a configuration equivalent to a buffer circuit in which inverter gates are connected in two stages.

  The delay adjustment circuit 30 (FIG. 5) of the second embodiment includes a delay buffer X1a instead of the inverter gates I1 and I2, which are the first stage buffer circuits in the delay adjustment circuit 20 (FIG. 3). Signals X1... Output from the delay buffer X1a. u2, X1. u3, and signals X1. d2, X1. d3 can be replaced with an output signal from the inverter gate I1 and an output signal from the inverter gate I2. A buffer circuit composed of inverter gates is not required.

  As a result, the first-stage buffer circuit is constituted by the delay buffer 10, so that the signal X1. The low level transition of d2 is signal X1. It becomes steeper than the low level transition of u2. As a result, the NMOS transistor MN2 is first turned off, and then the PMOS transistor MP1 is turned on. A through current path is not formed, and the through current can be suppressed. In addition, in the low level transition of the input signal IN, the signals X1. The high level transition of u2 is signal X1. It becomes steeper than the high-level transition of d2. As a result, the PMOS transistor MP1 is first turned off, and then the NMOS transistor MN2 is turned on. A through current path is not formed, and the through current can be suppressed.

  The connection relationship between the delay buffers X2 to X5 after the second stage of the delay adjustment circuit 30 is the same as the configuration of the delay buffers X2 to X5 after the second stage of the delay adjustment circuit 20 (FIG. 3). Description is omitted.

  FIG. 6 is a circuit diagram of a switch circuit SWa showing another example of the switch circuits SWP1 and SWN1 and the switch circuits SWP2 and SWN2 provided in the delay buffer 10 (FIG. 2). FIG. 6 illustrates another example of the configuration related to the switch circuits SWP1 and SWN1, but it goes without saying that the configuration related to the switch circuits SWP2 and SWN2 can be similarly replaced.

  The switch circuit SWa includes a PMOS transistor MPS and a NOR gate OR1 instead of the switch circuit SWP1. Further, an NMOS transistor MNS and an AND gate AND1 are provided in place of the switch circuit SWN1. The input terminals of the NOR gate OR1 are connected to terminals p11 and p12, and the input terminal of the AND gate AND1 is connected to n11 and n12.

  Here, in the delay buffer 10, the PMOS transistor MP1 is an example of a first conductivity type first MOS transistor, and the power supply voltage vdd is an example of a first power supply. The NMOS transistor MN1 is an example of a second conductivity type first MOS transistor, and the ground voltage vss is an example of a second power supply. Here, the signal input to the terminal u1 is an example of the first signal, and the direction of transition of the signal input to the terminal u1 to the low level is an example of the first direction. The signal output from the terminal u3 is an example of the first delay signal.

  The NMOS transistor MN2 is an example of a second conductivity type second MOS transistor, and the PMOS transistor MP2 is an example of a first conductivity type second MOS transistor. Here, the signal input to the terminal d1 is an example of the second signal, and the direction of transition of the signal input to the terminal d1 to the high level is an example of the second direction. The signal output from the terminal d3 is an example of the second delay signal.

  The switch circuit SWP1 is an example of a first switch circuit, and the PMOS transistors MP3 and MP4 of the switch circuit SWP1 are examples of a first conductivity type third MOS transistor and a first conductivity type fourth MOS transistor, respectively. The switch circuit SWN1 is an example of a second switch circuit, and the NMOS transistors MN3 and MN4 of the switch circuit SWN1 are examples of a second conductivity type third MOS transistor and a second conductivity type fourth MOS transistor, respectively.

  The switch circuit SWP2 is an example of a third switch circuit, and the PMOS transistors MP5 and MP6 of the switch circuit SWP2 are examples of a first conductivity type fifth MOS transistor and a first conductivity type sixth MOS transistor, respectively. The switch circuit SWN2 is an example of a fourth switch circuit, and the NMOS transistors MN5 and MN6 of the switch circuit SWN2 are examples of a second conductivity type fifth MOS transistor and a second conductivity type sixth MOS transistor, respectively.

  A buffer circuit composed of inverter gates I1 and I2 is an example of a buffer gate. Here, the signal output from the inverter gate I1 is an example of an inverted input signal, and the signal output from the inverter gate I2 is an example of a delayed input signal. The delay buffer X1a is an example of a first-stage delay buffer.

  As described above in detail, according to the delay adjustment circuits 20 and 30 of the embodiment, the delay buffer 10 is configured to be connected in series in multiple stages. The delay buffer 10 includes a first configuration related to signal propagation and a second configuration related to prevention of through current. The first configuration includes a PMOS transistor MP1 and an NMOS transistor MN1, and forms a critical path with the shortest signal propagation delay with respect to a low-level transition of a signal input from the terminal u1 and is given a unit delay time. From the terminal u3. In addition, an NMOS transistor MN2 and a PMOS transistor MP2 are provided, a critical path with the shortest signal propagation delay with respect to a high-level transition of a signal input from the terminal d1 is formed, and a signal to which a unit delay time is given is output from the terminal d3. Output.

  Thereby, a delay signal to which a unit delay time is given for each delay buffer 10 is obtained for each of the low level transition and the high level transition. In the delay adjustment circuits 20 and 30 connected in series in multiple stages, the delay time can be adjusted with the resolution of the unit delay time according to the position where the output signal is extracted from each of the delay buffers 10 connected in multiple stages.

  Further, switch circuits SWP1, SWN1, and SWP2, SWN2 are provided between the drain terminal of the PMOS transistor MP1 and the drain terminal of the NMOS transistor MN2, and between the drain terminal of the PMOS transistor MP2 and the drain terminal of the NMOS transistor MN1, respectively. Is provided. Thereby, the through current at the time of transition of the signal level can be suppressed. Current consumption and standby current can be reduced.

  In addition, according to the delay adjustment circuit 30 of the second embodiment, the delay buffer X1a is provided instead of the buffer circuit constituted by the inverter gates I1 and I2. As a result, in the delay buffer X1a, the through current of the first stage buffer circuit is changed from the buffer circuit constituted by the inverter gates I1 and I2 while the logical configuration is the same as that of the buffer circuit constituted by the inverter gates I1 and I2. Can be reduced. In the high level transition of the input signal IN, the signals X1. The low level transition of d2 is signal X1. It becomes steeper than the low level transition of u2, and the signal X1. The high level transition of u2 is signal X1. This is because it becomes steeper than the high-level transition of d2. As a result, in the former case, the NMOS transistor MN2 is turned off first, and then the PMOS transistor MP1 is turned on. In the latter case, the PMOS transistor MP1 is turned off first, and then the NMOS transistor MN2 is turned on. In either case, a through current path is not formed, and the through current can be suppressed.

  Needless to say, the technology disclosed in the present application is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Transmission side functional circuit 2 High speed memory 3 Wiring path | route 10, X1-X5, X1a Delay buffer 11 DLL circuit 20, 30 Delay adjustment circuit u1, d1 Input terminal p11, p12, p21, p22, n11, n12, n21, n22 terminal u3, d3 Output terminal AND1 AND gates I1, I2 Inverter gates MN1-MN6, MNS NMOS transistors MP1-MP6, MPS PMOS transistor OR1 NOR gates SWP1, SWP2, SWN1, SWN2, SWa Switch circuit IN Input signal

Claims (3)

A first delay signal to which a unit delay time is given with respect to level transition in the first direction of the input first signal is output, and the first direction of the second signal input in phase with the first signal Includes a delay buffer that outputs a second delay signal to which the unit delay time is given with respect to the level transition in the opposite second direction, connected in series in multiple stages,
The delay buffer is
A first conductivity type first MOS transistor having a gate terminal receiving the first signal and a source terminal connected to a first power source;
A second conductivity type first MOS transistor having a gate terminal connected to the drain terminal of the first conductivity type first MOS transistor, a source terminal connected to a second power source, and outputting the first delay signal from the drain terminal;
A second conductivity type second MOS transistor having a gate terminal receiving the second signal and a source terminal connected to the second power source;
A first conductivity type second MOS transistor having a gate terminal connected to the drain terminal of the second conductivity type second MOS transistor, a source terminal connected to the first power source, and outputting the second delay signal from the drain terminal;
A first switch circuit connecting between a drain terminal of the first conductivity type first MOS transistor and a drain terminal of the second conductivity type second MOS transistor;
A second switch circuit provided in parallel with the first switch circuit;
A third switch circuit connecting the drain terminal of the second conductivity type first MOS transistor and the drain terminal of the first conductivity type second MOS transistor;
A fourth switch circuit provided in parallel with the third switch circuit,
The first switch circuit includes a first conductive type third MOS transistor and a first conductive type fourth MOS transistor connected in series,
The second switch circuit includes a second conductive type third MOS transistor and a second conductive type fourth MOS transistor connected in series,
The third switch circuit includes a first conductivity type fifth MOS transistor and a first conductivity type sixth MOS transistor connected in series,
The fourth switch circuit includes a second conductive type fifth MOS transistor and a second conductive type sixth MOS transistor connected in series,
A gate terminal of the first conductivity type third MOS transistor is connected to a drain terminal of the second conductivity type first MOS transistor;
A gate terminal of the first conductivity type fourth MOS transistor is connected to a drain terminal of the first conductivity type second MOS transistor of the preceding delay buffer;
The gate terminal of the second conductivity type third MOS transistor is connected to the drain terminal of the second conductivity type first MOS transistor of the preceding delay buffer;
A gate terminal of the second conductivity type fourth MOS transistor is connected to a drain terminal of the first conductivity type second MOS transistor;
The gate terminal of the first conductivity type fifth MOS transistor is connected to the drain terminal of the first conductivity type first MOS transistor of the preceding delay buffer;
The gate terminal of the first conductivity type sixth MOS transistor is connected to the drain terminal of the second conductivity type second MOS transistor of the delay buffer in the next stage,
The gate terminal of the second conductivity type fifth MOS transistor is connected to the drain terminal of the first conductivity type first MOS transistor of the next-stage delay buffer;
A gate terminal of the second conductivity type sixth MOS transistor is connected to a drain terminal of the second conductivity type second MOS transistor of the preceding delay buffer;
The first and second delay signals are output to the delay buffer of the next stage as first and second signals of the next stage, respectively. Before the delay buffer connected in series in multiple stages,
An input signal is input and a buffer gate composed of two stages of inverter gates connected in series is provided.
The first-stage delay buffer of the delay buffers to which the inverted input signal output from the first-stage inverter gate of the buffer gate and the delay-input signal output from the next-stage inverter gate are input,
The delayed input signal is input to gate terminals of the first conductivity type fourth MOS transistor and the second conductivity type third MOS transistor,
2. The delay adjustment circuit according to claim 1, wherein the inverted input signal is input to gate terminals of the first conductivity type fifth MOS transistor and the second conductivity type sixth MOS transistor. Of the delay buffers connected in series in multiple stages, the first stage delay buffer is:
Gate terminals of the first conductivity type third to fifth MOS transistors are connected to the second power source,
2. The delay adjustment circuit according to claim 1, wherein gate terminals of the second conductivity type third to fifth MOS transistors are connected to the first power supply. 3.

Images