JP2014229711A - Semiconductor device - Google Patents

Abstract

The reliability and performance of a semiconductor device having a capacitor element are improved. A lower electrode LE of a capacitor element C1 is provided in any one of a plurality of wiring layers formed on a semiconductor substrate, and two wirings higher than the wiring layer in which the lower electrode LE is formed. In the layer, the upper electrode UE of the capacitive element C1 is provided above the lower electrode LE. Then, the floating electrode FE located between the lower electrode LE and the upper electrode UE is provided in the wiring layer one layer above the wiring layer in which the lower electrode LE is formed. [Selection] Figure 8

Description

  The present invention relates to a semiconductor device, and can be suitably used for a semiconductor device having a capacitor, for example.

  Various semiconductor devices are manufactured by forming MISFETs (Metal Insulator Semiconductor Field Effect Transistors), capacitive elements, and the like on a semiconductor substrate and connecting the elements with wiring. As a capacitive element formed on a semiconductor substrate, there is a MIM (Metal Insulator Metal) type capacitive element.

  Japanese Unexamined Patent Application Publication No. 2009-33029 (Patent Document 1) describes a technique related to wiring of a DRAM.

  Japanese Patent Laying-Open No. 2005-183739 (Patent Document 2) describes a technique in which a capacitor element is formed by electrodes having a plurality of wirings arranged in a comb shape.

  Japanese Patent Laying-Open No. 2009-224737 (Patent Document 3) describes a technique related to an MIM type capacitive element in which electrodes are formed with a comb-shaped metal pattern.

JP 2009-33029 A JP 2005-183739 A JP 2009-224637 A

  Even in a semiconductor device having a capacitor element, it is desired to improve the reliability as much as possible. Alternatively, it is desired to improve the performance as much as possible. Alternatively, it is desirable to improve reliability and improve performance.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, the first electrode of the capacitive element is provided in any one of the plurality of wiring layers formed on the semiconductor substrate, and is 2 rather than the wiring layer in which the first electrode is formed. In the upper wiring layer, the second electrode of the capacitive element is provided above the first electrode. In the wiring layer one layer higher than the wiring layer on which the first electrode is formed, the first electrode and the A floating electrode is provided between the second electrode.

  According to one embodiment, the first metal pattern and the second metal pattern are provided on any one of the plurality of wiring layers formed on the semiconductor substrate, and the first metal pattern and the second metal pattern are provided. A third metal pattern and a fourth metal pattern are provided in a wiring layer one layer above the wiring layer on which the pattern is formed. The first metal pattern and the third metal pattern are electrically connected to each other to form one electrode of a capacitive element, and the second metal pattern and the fourth metal pattern are electrically connected to each other. The other electrode of the capacitive element is formed. The first metal pattern includes a plurality of first electrode portions extending in a first direction, and the second metal pattern includes a plurality of second electrode portions extending in the first direction. The first electrode portions and the second electrode portions are alternately arranged in a second direction intersecting the first direction. The third metal pattern includes a plurality of third electrode portions extending in the first direction, and the fourth metal pattern includes a plurality of fourth electrode portions extending in the first direction. The third electrode portion and the fourth electrode portion are alternately arranged in the second direction. Each of the plurality of first electrode portions is disposed between the third electrode portion and the fourth electrode portion adjacent to each other in the second direction in a plan view, and the plurality of second electrode portions Each is disposed between the third electrode portion and the fourth electrode portion adjacent in the second direction in plan view.

  According to one embodiment, the first metal pattern for forming one electrode of the capacitive element on any one of the plurality of wiring layers formed on the semiconductor substrate, and the other of the capacitive elements And a second metal pattern for forming the electrode. The first metal pattern includes a plurality of first electrode portions extending in a first direction, and the second metal pattern includes a plurality of second electrode portions extending in the first direction. The first electrode portions and the second electrode portions are alternately arranged in a second direction intersecting the first direction. In the wiring layer in which the first metal pattern and the second metal pattern are formed, a floating electrode is formed between the first electrode portion and the second electrode portion adjacent to each other in the second direction.

  According to one embodiment, the reliability of a semiconductor device can be improved.

  Alternatively, the performance of the semiconductor device can be improved.

  Alternatively, the reliability of the semiconductor device can be improved and the performance of the semiconductor device can be improved.

It is principal part sectional drawing of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is a principal part top view of the semiconductor device of one embodiment. It is principal part sectional drawing of the semiconductor device of a 1st examination example. It is principal part sectional drawing of the semiconductor device of the 2nd examination example. It is principal part sectional drawing of the semiconductor device of one embodiment. It is a graph which shows voltage distribution when a predetermined voltage is applied to the electrode of the capacitive element of FIG. It is a graph which shows voltage distribution when a predetermined voltage is applied to the electrode of the capacitive element of FIG. It is a graph which shows voltage distribution when a predetermined voltage is applied to the electrode of the capacitive element of FIG. It is a top view which shows a floating electrode. It is a top view which shows a floating electrode. It is principal part sectional drawing of the semiconductor device of a 1st modification. It is principal part sectional drawing of the semiconductor device of other embodiment. It is principal part sectional drawing of the semiconductor device of other embodiment. It is principal part sectional drawing of the semiconductor device of other embodiment. It is a principal part top view of the semiconductor device of other embodiments. It is a principal part top view of the semiconductor device of other embodiments. It is a principal part top view of the semiconductor device of other embodiments. It is principal part sectional drawing of the semiconductor device of other embodiment. It is principal part sectional drawing of the semiconductor device of a 3rd examination example. It is principal part sectional drawing of the semiconductor device of the 4th examination example. It is a principal part top view of the semiconductor device of other embodiments. It is a principal part top view of the semiconductor device of other embodiments. It is a principal part top view of the semiconductor device of other embodiments. It is principal part sectional drawing of the semiconductor device of other embodiment. It is a principal part top view of the semiconductor device of other embodiments. It is a principal part top view of the semiconductor device of other embodiments. It is a principal part top view of the semiconductor device of other embodiments. It is principal part sectional drawing of the semiconductor device of other embodiment. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one Embodiment. FIG. 33 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 32; FIG. 34 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 33; FIG. 35 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 34; FIG. 36 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 35; FIG. 37 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 36; FIG. 38 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 37; FIG. 39 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 38; FIG. 40 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 39; FIG. 41 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 40; FIG. 42 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 41; FIG. 43 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 42; FIG. 44 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 43; FIG. 45 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 44; FIG. 46 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 45; FIG. 47 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 46; It is principal part sectional drawing which shows the wiring layer which formed wiring. It is sectional drawing which shows the formation process of an interlayer insulation film.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
<Structure of semiconductor device>
The semiconductor device of the present embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is a semiconductor device having a capacitor.

  FIG. 1 is a cross-sectional view of main parts of the semiconductor device of the present embodiment, and FIGS. 2 to 5 are plan views of main parts of the semiconductor device of the present embodiment. 1 is a cross-sectional view of a MISFET formation region and a capacitor formation region in the semiconductor device of the present embodiment, and FIGS. 2 to 5 are plan views of the capacitor formation region in the semiconductor device of the present embodiment. It is shown.

  1 substantially corresponds to the cross section taken along the line A1-A1 in FIGS. However, in the cross-sectional view of FIG. 1, the illustration of the insulating film IL6 and the structure above the wiring M5 embedded in the insulating film IL6 is omitted. Further, the MISFET formation region and the capacitor formation region in FIG. 1 correspond to different planar regions in the same semiconductor device (the same semiconductor substrate SB). The MISFET formation region and the capacitor formation region in FIG. 1 may or may not be adjacent to each other, but for the sake of easy understanding, the cross-sectional view of FIG. A sectional view of the capacitor formation region is shown next to the figure.

  2 to 5 show the same planar region (capacitor formation region here) in the same semiconductor device (semiconductor substrate SB), but the layers shown in FIGS. 2 to 5 are different. Yes. That is, FIG. 3 shows a planar layout of the layer in which the upper electrode UE is formed in the capacitor formation region (that is, the wiring layer ML3), and FIG. 4 shows the layer in which the floating electrode FE is formed in the capacitor formation region ( That is, a planar layout of the wiring layer ML2) is shown, and FIG. 5 shows a planar layout of the layer in which the lower electrode LE is formed in the capacitor formation region (that is, the wiring layer ML1). Further, FIG. 2 shows a planar layout in which FIGS.

  In the semiconductor device of this embodiment, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed in a MISFET formation region, and a capacitor element C1 is formed in a capacitor formation region that is a region (planar region) different from the MISFET formation region. Yes. A specific configuration of the semiconductor device of the present embodiment will be described with reference to FIGS.

  As shown in FIG. 1, the semiconductor substrate SB constituting the semiconductor device of the present embodiment is made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm. The semiconductor substrate SB forming the semiconductor device of the present embodiment has a capacitor forming region in which the capacitor element C1 is formed and a MISFET forming region in which a field effect transistor such as a MISFET is formed. FIG. 2 shows a cross-sectional view of the capacitor formation region and the MISFET formation region.

  As shown in FIG. 1, an element isolation region ST is formed on the main surface of the semiconductor substrate SB. The element isolation region ST is formed by embedding an insulating film such as silicon oxide in a groove (element isolation groove) formed in the semiconductor substrate SB. That is, the element isolation region ST is formed of a trench formed in the semiconductor substrate SB and embedded with an insulating film. The element isolation region ST can be formed by an STI (Shallow Trench Isolation) method.

  An active region is defined by the element isolation region ST. The active region is a substrate region of the semiconductor substrate SB and corresponds to a region where the element isolation region ST is not formed on the main surface of the semiconductor substrate SB.

  As shown in FIG. 1, a p-type well region PW is formed in a semiconductor substrate SB in a MISFET formation region, and an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor :) is formed on the p-type well region PW. MIS type field effect transistor) Q1 is formed. The MISFET Q1 includes a gate insulating film GI formed on the surface of the p-type well region PW, a gate electrode GE formed on the gate insulating film GI, and n for source / drain formed in the p-type well region PW. Type semiconductor region SD. That is, the gate electrode GE is formed on the p-type well region PW via the gate insulating film GI. The source / drain n-type semiconductor regions SD are formed in regions on both sides of the gate electrode GE in the semiconductor substrate SB (p-type well region PW). A region under the gate electrode GE in the semiconductor substrate SB (p-type well region PW) is a region where a channel of the MISFET Q1 is formed, that is, a channel formation region. A pair of n-type semiconductor regions SD are opposed to each other in the gate length direction of the gate electrode GE with the channel formation region interposed therebetween.

  The gate insulating film GI is made of, for example, a silicon oxide film, and the gate electrode GE is made of, for example, a polycrystalline silicon film into which impurities are introduced. The n-type semiconductor region SD may have an LDD (Lightly doped Drain) structure. In this case, a sidewall insulating film, also referred to as a sidewall spacer, is formed on the sidewall of the gate electrode GE.

  Metal silicide layers (not shown) can also be formed on the surfaces (surface layer portions) of the gate electrode GE and the n-type semiconductor region SD by a salicide (Salicide: Self Aligned Silicide) technique, respectively. As this metal silicide layer, for example, a cobalt silicide layer or a nickel silicide layer can be used.

  Further, although the case where the n-channel type MISFET Q1 is formed on the main surface of the semiconductor substrate SB has been illustrated and described, a p-channel type MISFET can be formed by reversing the conductivity type. In addition, both an n-channel MISFET and a p-channel MISFET can be formed on the main surface of the semiconductor substrate SB. The number of MISFETs formed on the main surface of the semiconductor substrate SB can be variously changed. Further, a semiconductor element other than the MISFET can be formed on the main surface of the semiconductor substrate SB.

  FIG. 1 shows a case where no semiconductor element is formed on the main surface of the semiconductor substrate SB in the capacitor formation region, and an element isolation region ST is formed on the main surface of the semiconductor substrate SB in the capacitor formation region. Is formed. As another form, a semiconductor element such as a MISFET or a MOS (Metal Oxide Semiconductor) type capacitive element can be formed on the main surface of the semiconductor substrate SB in the capacitor formation region.

  As shown in FIG. 1, an insulating film (interlayer insulating film) IL1 is formed on the main surface (entire main surface) of the semiconductor substrate SB so as to cover the gate electrode GE. The insulating film IL1 is formed of a laminated film of a silicon nitride film (lower layer side) and a thicker silicon oxide film (upper layer side), or a single film of a silicon oxide film.

  When the insulating film IL1 is formed, an uneven shape is formed on the upper surface of the insulating film IL1 due to a base step (for example, a step of the gate electrode GE). The upper surface of the insulating film IL1 is flattened by polishing the upper surface (surface) by a CMP (Chemical Mechanical Polishing) method. Therefore, the structure above the insulating film IL1 (a multilayer wiring structure including wirings M1 to M5 described later) is formed on the flat upper surface (front surface) of the insulating film IL1.

  The insulating film IL1 has contact holes (openings, holes, through holes) penetrating the insulating film IL1, and plugs made of a conductive film mainly composed of a tungsten (W) film are formed in the contact holes. (Conductor part, connecting conductor part) PG is formed and embedded. In the MISFET formation region, the contact hole and the plug PG filling the contact hole are formed above the n-type semiconductor region SD, the top of the gate electrode GE, and the like.

  As shown in FIG. 1, a plurality of wiring layers including wirings M1 to M5, that is, a multilayer wiring structure is formed on the insulating film IL1.

  That is, an insulating film (interlayer insulating film) IL2 is formed on the insulating film IL1 in which the plug PG is embedded, and a wiring groove and a wiring M1 embedded in the groove are formed in the insulating film IL2. Is formed. The insulating film IL2 can be a single-layer insulating film or a stacked film of a plurality of insulating films. The wiring M1 can be formed using a damascene technology (here, a single damascene technology), and can be a copper wiring (damascene copper wiring, embedded copper wiring) containing copper as a main component.

  The wiring M1 is a wiring of the lowermost wiring layer (that is, the wiring layer ML1) in the multilayer wiring structure. Here, in the multilayer wiring structure formed on the semiconductor substrate SB (that is, on the insulating film IL1), the lowermost wiring layer is denoted by a reference numeral ML1 and is referred to as a wiring layer ML1. In the multilayer wiring structure formed on the semiconductor substrate SB (that is, on the insulating film IL1), the wiring layer that is one layer above the wiring layer ML1 is referred to as a wiring layer ML2 with a reference numeral ML2, and the wiring layer ML2 The wiring layer that is one layer higher than that is denoted by a reference numeral ML3 and is referred to as a wiring layer ML3. In the multilayer wiring structure formed on the semiconductor substrate SB (that is, on the insulating film IL1), the wiring layer that is one layer above the wiring layer ML3 is referred to as a wiring layer ML4 with a reference numeral ML4, and the wiring layer ML4. The wiring layer that is one layer higher than that is denoted by the reference numeral ML5 and is referred to as a wiring layer ML5. Accordingly, the wiring M1 is a wiring of the wiring layer ML1, a wiring M2 described later is a wiring of the wiring layer ML2, a wiring M3 described later is a wiring of the wiring layer ML3, and a wiring M4 described later is a wiring layer. ML4 is a wiring, and a wiring M5 described later is a wiring of the wiring layer ML5.

  In FIG. 1, reference numerals ML1 to ML5 are not shown. In FIG. 1, the layer in which the wiring M1 and the lower electrode LE are formed corresponds to the wiring layer ML1, and the wiring M2 and the floating electrode FE are formed. The layer in which the wiring M3 and the upper electrode UE are formed corresponds to the wiring layer ML3. In FIG. 1, the layer in which the wiring M4 is formed corresponds to the wiring layer ML4, and the layer in which the wiring M5 is formed corresponds to the wiring layer ML5.

  As shown in FIGS. 1 to 5, in the capacitor formation region, the lower electrode LE is formed in the same layer as the wiring M1 in the same process. That is, the wiring M1 and the lower electrode LE are formed in the same wiring layer ML1. For this reason, both the wiring M1 and the lower electrode LE are formed in the same process using the damascene technique, and are embedded in the insulating film IL2. Specifically, the wiring M1 and the lower electrode LE are embedded in grooves (or openings) formed in the insulating film IL2. The lower electrode LE and the wiring M1 are made of the same conductive material. In addition, a wiring M1 is integrally connected to the lower electrode LE, and a predetermined potential can be supplied to the lower electrode LE through the wiring M1 connected to the lower electrode LE.

  As shown in FIG. 1, an insulating film (interlayer insulating film) IL3 is formed on the insulating film IL2 in which the wiring M1 and the lower electrode LE are embedded. The insulating film IL3 can be a single-layer insulating film or a stacked film of a plurality of insulating films.

  In the insulating film IL3, a trench for wiring and a wiring M2 embedded in the trench are formed. The wiring M2 can be formed using a damascene technology (here, dual damascene technology), and can be a copper wiring containing copper as a main component (damascene copper wiring, embedded copper wiring). The wiring M2 is a wiring of the wiring layer ML2. The bottom surface of the wiring M2 is located in the middle of the thickness of the insulating film IL3.

  The wiring M2 is electrically connected to the wiring M1 through a via portion V2 formed integrally with the wiring M2. That is, the via portion V2 is disposed between the wiring M2 and the wiring M1, the upper surface of the via portion V2 is integrally connected to the lower surface of the wiring M2, and the lower surface (bottom surface) of the via portion V2 is It is in contact with the upper surface of the wiring M1. The via portion V2 is integrally formed of the same conductive film as the wiring M2, and the via portion V2 is formed together with the wiring M2 when the wiring M2 is formed by the dual damascene technique. A via portion V2 and via portions V3, V4, and V5, which will be described later, are conductive connection members that are arranged between wirings of different layers and connect wirings of different layers.

  The via portion V2 can also be formed in a separate process from the wiring M2. In this case, the via portion V2 is formed by the same process as the plug PG, the wiring M2 is formed by a single damascene technique, and the via portion V2 is formed. The bottom surface (bottom surface) of the contact portion is in contact with the top surface of the wiring M1, and the top surface of the via portion V2 is in contact with the bottom surface of the wiring M2.

  As shown in FIGS. 1 to 5, in the capacitor formation region, the floating electrode FE is formed in the same layer as the wiring M2 in the same process. That is, the wiring M2 and the floating electrode FE are formed in the same wiring layer ML2. That is, the wiring M2 and the floating electrode FE are formed in the wiring layer ML2 that is one layer higher than the wiring layer ML1 in which the wiring M1 and the lower electrode LE are formed. For this reason, both the wiring M2 and the floating electrode FE are formed in the same process using the damascene technique, and are embedded in the insulating film IL3. Specifically, the wiring M2 and the floating electrode FE are each embedded in a groove (or opening) formed in the insulating film IL3. The floating electrode FE and the wiring M2 are made of the same conductive material. The bottom surface (lower surface) of the floating electrode FE is located in the middle of the thickness of the insulating film IL3. The height position of the bottom surface (lower surface) of the floating electrode FE and the height position of the bottom surface (lower surface) of the wiring M2 are substantially the same. Note that when the trench is formed in the insulating film, the depth of the trench becomes deeper as the planar dimension is larger, which reflects that the dimension (side dimension) of the floating electrode FE is larger than the width of the wiring M2. Thus, the height position of the bottom surface of the floating electrode FE may be lower than the height position of the bottom surface of the wiring M2.

  The floating electrode FE is set to a floating potential. That is, the floating electrode FE is in an electrically floating state (floating state). The floating electrode FE is not connected to the lower electrode LE by a conductor, and is not connected to an upper electrode UE, which will be described later, by a conductor. For this reason, the via part V2 is not connected to the floating electrode FE, and the via part V2 is not disposed under the floating electrode FE.

  When a potential (voltage) higher than the other of the lower electrode LE and the upper electrode UE is applied (supplied) to one of the lower electrode LE and the upper electrode UE, charges are accumulated in the capacitive element C1. . That is, when accumulating charges in the capacitive element C1, different voltages are applied to the lower electrode LE and the upper electrode UE through a conductor such as a wiring. That is, when accumulating charges in the capacitive element C1, the upper electrode UE is set to a higher potential (high voltage) than the lower electrode LE, or the lower electrode LE is set to a higher potential (high voltage) than the upper electrode UE. ). However, the floating electrode FE is at a floating potential, and voltage is not applied to the floating electrode FE through a conductor such as a wiring when charges are accumulated in the capacitor C1. For this reason, the floating electrode FE can also be regarded as a dummy electrode.

  As shown in FIG. 1, an insulating film (interlayer insulating film) IL4 is formed on the insulating film IL3 in which the wiring M2 and the floating electrode FE are embedded. The insulating film IL4 can be a single-layer insulating film or a stacked film of a plurality of insulating films.

  In the insulating film IL4, a trench for wiring and a wiring M3 embedded in the trench are formed. The wiring M3 can be formed using a damascene technique (here, dual damascene technique), and can be a copper wiring (a damascene copper wiring or a buried copper wiring) containing copper as a main component. The wiring M3 is a wiring of the wiring layer ML3. The bottom surface of the wiring M3 is located in the middle of the thickness of the insulating film IL4.

  The wiring M3 is electrically connected to the wiring M2 through a via portion V3 formed integrally with the wiring M3. That is, the via portion V3 is disposed between the wiring M3 and the wiring M2, the upper surface of the via portion V3 is integrally connected to the lower surface of the wiring M3, and the lower surface (bottom surface) of the via portion V3 is It is in contact with the upper surface of the wiring M2. The via portion V3 is integrally formed of the same conductive film as the wiring M3. When the wiring M3 is formed by the dual damascene technique, the via portion V3 is also formed together with the wiring M3.

  The via portion V3 can also be formed in a separate process from the wiring M3. In that case, the via portion V3 is formed by the same process as the plug PG, the wiring M3 is formed by a single damascene technique, and the via portion V3. The bottom surface (bottom surface) of the contact portion is in contact with the top surface of the wiring M2, and the top surface of the via portion V3 is in contact with the bottom surface of the wiring M3.

  As shown in FIGS. 1 to 5, in the capacitor formation region, the upper electrode UE is formed in the same layer as the wiring M3 in the same process. That is, the wiring M3 and the upper electrode UE are formed in the same wiring layer ML3. That is, the wiring M3 and the upper electrode UE are formed in the wiring layer ML3 that is one layer higher than the wiring layer ML2 in which the wiring M2 and the floating electrode FE are formed. For this reason, the wiring M3 and the upper electrode UE are both formed in the same process using the damascene technique, and are embedded in the insulating film IL4. Specifically, the wiring M3 and the upper electrode UE are each embedded in a groove (or an opening) formed in the insulating film IL4. The upper electrode UE and the wiring M3 are made of the same conductive material. The bottom surface (lower surface) of the upper electrode UE is located in the middle of the thickness of the insulating film IL4. The height position of the bottom surface (lower surface) of the upper electrode UE and the height position of the bottom surface (lower surface) of the wiring M3 are substantially the same. Note that, when the trench is formed in the insulating film, the depth of the trench becomes deeper as the planar dimension is larger, which reflects that the dimension (side dimension) of the upper electrode UE is larger than the width of the wiring M3. Thus, the height position of the bottom surface of the upper electrode UE may be lower than the height position of the bottom surface of the wiring M3. Further, a wiring M3 is integrally connected to the upper electrode UE, and a predetermined potential can be supplied to the upper electrode UE through the wiring M3 connected to the upper electrode UE.

  In the capacitor formation region, the floating electrode FE is disposed above the lower electrode LE, and the upper electrode UE is disposed above the floating electrode FE. The upper electrode UE and the floating electrode FE are not connected by a conductor. That is, no direct current flows between the upper electrode UE and the floating electrode FE. Further, the lower electrode LE and the floating electrode FE are not connected by a conductor. That is, no direct current flows between the lower electrode LE and the floating electrode FE. Further, the upper electrode UE and the lower electrode LE are not connected by a conductor. That is, no direct current flows between the upper electrode UE and the lower electrode LE. For this reason, the via portion V3 that electrically connects the upper electrode UE and the floating electrode FE is not disposed between the upper electrode UE and the floating electrode FE, and the lower electrode LE and the floating electrode FE Between these, the via portion V2 that electrically connects the lower electrode LE and the floating electrode FE is not disposed.

  In this application, when referring to the connection relationship of a plurality of members made of conductors (corresponding to electrodes or wirings), when expressing as “not connected by a conductor” or “not connected by a conductor” This means that the conductive path connected by is not formed between the members.

  A capacitive element (capacitor) C1 is formed by the lower electrode LE, the upper electrode UE, and the insulating films IL3 and IL4 between the lower electrode LE and the upper electrode UE. The lower electrode LE is one electrode of the capacitive element C1, the upper electrode UE is the other electrode of the capacitive element C1, and the insulating films IL3 and IL4 interposed between the lower electrode LE and the upper electrode UE include It functions as a capacitive insulating film (dielectric film) of the capacitive element C1. The capacitive element C1 is a MIM (Metal Insulator Metal) type capacitive element.

  However, in the capacitive element C1, the floating electrode FE is disposed between the lower electrode LE and the upper electrode UE. For this reason, the insulating film IL3 interposed between the lower electrode LE and the floating electrode FE and the insulating film IL4 interposed between the upper electrode UE and the floating electrode FE form a capacitive insulating film (dielectric material) of the capacitive element C1. Film). The capacitor element C1 can be formed by forming the lower electrode LE, the floating electrode FE, and the upper electrode UE in this order from the bottom in the capacitor formation region.

  As shown in FIG. 5, the lower electrode LE can have a rectangular planar shape, for example, and the floating electrode FE can have a rectangular planar shape as shown in FIG. In addition, the upper electrode UE can have, for example, a rectangular planar shape as shown in FIG. In addition, the lower electrode LE and the upper electrode UE can have the same planar shape and planar dimensions (planar area) so that the lower electrode LE and the upper electrode UE overlap (match) in plan view. By doing so, the capacitance value of the capacitive element C1 can be increased while suppressing the area occupied by the capacitive element C1.

  Note that “plan view” or “view in plan” refers to the case of viewing in a plane parallel to the main surface of the semiconductor substrate SB.

  As shown in FIG. 1, an insulating film (interlayer insulating film) IL5 is formed on the insulating film IL4 in which the wiring M3 and the upper electrode UE are embedded. The insulating film IL5 can be a single-layer insulating film or a stacked film of a plurality of insulating films.

  In the insulating film IL5, a trench for wiring and a wiring M4 embedded in the trench are formed. The wiring M4 can be formed using a damascene technique (here, dual damascene technique), and can be a copper wiring (a damascene copper wiring or a buried copper wiring) containing copper as a main component. The wiring M4 is a wiring of the wiring layer ML4. The bottom surface (lower surface) of the wiring M4 is located in the middle of the thickness of the insulating film IL5.

  The wiring M4 is electrically connected to the wiring M3 through a via portion V4 formed integrally with the wiring M4. That is, the via portion V4 is disposed between the wiring M4 and the wiring M3, the upper surface of the via portion V4 is integrally connected to the lower surface of the wiring M4, and the lower surface (bottom surface) of the via portion V4 is It is in contact with the upper surface of the wiring M3. The via portion V4 is integrally formed of the same conductive film as the wiring M4. When the wiring M4 is formed by the dual damascene technique, the via portion V4 is also formed together with the wiring M4.

  The via portion V4 can also be formed in a separate process from the wiring M4. In that case, the via portion V4 is formed by the same process as the plug PG, the wiring M4 is formed by a single damascene technique, and the via portion V4. The lower surface (bottom surface) of the contact portion contacts the upper surface of the wiring M3, and the upper surface of the via portion V4 contacts the lower surface of the wiring M4.

  An insulating film (interlayer insulating film) IL6 is formed over the insulating film IL5 in which the wiring M4 is embedded. The insulating film IL6 can be a single-layer insulating film or a stacked film of a plurality of insulating films.

  In the insulating film IL6, a trench for wiring and a wiring M5 embedded in the trench are formed. The wiring M5 can be formed using damascene technology (here, dual damascene technology) and can be copper wiring (damascene copper wiring, embedded copper wiring) containing copper as a main component. The wiring M5 is a wiring of the wiring layer ML5. The bottom surface (lower surface) of the wiring M5 is located in the middle of the thickness of the insulating film IL6.

  The wiring M5 is electrically connected to the wiring M4 through a via portion V5 formed integrally with the wiring M5. That is, the via portion V5 is disposed between the wiring M5 and the wiring M4, the upper surface of the via portion V5 is integrally connected to the lower surface of the wiring M5, and the lower surface (bottom surface) of the via portion V5 is It is in contact with the upper surface of the wiring M4. The via portion V5 is integrally formed of the same conductive film as the wiring M5. When the wiring M5 is formed by the dual damascene technique, the via portion V5 is also formed together with the wiring M5.

  The via portion V5 can also be formed in a separate process from the wiring M5. In that case, the via portion V5 is formed by the same process as the plug PG, the wiring M5 is formed by a single damascene technique, and the via portion V5. The bottom surface (bottom surface) of the contact portion contacts the top surface of the wiring M4, and the top surface of the via portion V5 contacts the bottom surface of the wiring M5.

  On the insulating film IL6 in which the wiring M5 is embedded, an upper insulating film, wiring, bonding pad, uppermost protective film, and the like are further formed as necessary, but illustration and description thereof are omitted here.

  In the present embodiment, the lower electrode LE is formed in the same layer as the wiring M1, the floating electrode FE is formed in the same layer as the wiring M2, and the upper electrode UE is formed in the same layer as the wiring M3. As another form, the lower electrode LE may be formed in the same layer as the wiring M2, the floating electrode FE may be formed in the same layer as the wiring M3, and the upper electrode UE may be formed in the same layer as the wiring M4. As another form, the lower electrode LE may be formed in the same layer as the wiring M3, the floating electrode FE may be formed in the same layer as the wiring M4, and the upper electrode UE may be formed in the same layer as the wiring M5. That is, the wiring layer for forming the lower electrode LE can be changed, but when the lower electrode LE is formed in any wiring layer, the floating electrode FE is one more than the wiring layer in which the lower electrode LE is formed. The upper electrode UE is formed in a wiring layer one layer higher than the wiring layer in which the floating electrode FE is formed. Further, when not only the wirings M1 to M5 but also wirings higher than the wiring M5 are formed (that is, when the wiring layer has six or more layers), the lower electrode LE is formed in a wiring layer above the wiring M3. In this case as well, the floating electrode FE is formed in a wiring layer one layer higher than the wiring layer in which the lower electrode LE is formed, and the upper electrode UE is a wiring in which the floating electrode FE is formed. The wiring layer is formed one layer above the layer.

  That is, a wiring structure (multilayer wiring structure) including a plurality of wiring layers is formed above the semiconductor substrate SB. In this embodiment, any three consecutive layers of the plurality of wiring layers are formed. The lower electrode LE, the floating electrode FE, and the upper electrode UE may be formed in the wiring layer. At this time, the floating electrode FE is formed in a wiring layer one layer higher than the wiring layer in which the lower electrode LE is formed, and the upper electrode UE is a wiring layer one layer higher than the wiring layer in which the floating electrode FE is formed. It is necessary to form a layer. In the present embodiment, since the lower electrode LE, the floating electrode FE, and the upper electrode UE are formed in the three wiring layers, the wiring structure (multilayer wiring structure) formed above the semiconductor substrate SB has at least three layers. It is necessary to include a wiring layer.

<About study example>
Next, a study example studied by the present inventors will be described.

  FIG. 6 is a cross-sectional view of the main part of the semiconductor device of the first study example studied by the present inventors, and FIG. 7 is a cross-sectional view of the main part of the semiconductor device of the second study example studied by the present inventor. FIG. 8 is a fragmentary cross-sectional view of the semiconductor device of the present embodiment. 6 to 8 show the insulating films IL2, IL3, and IL4 and electrodes (capacitance element electrodes) embedded in the capacitor formation region. The insulating film IL1 and the structure below it are shown in FIGS. The illustration of the insulating film IL5 and the structure above it is omitted. That is, in FIG. 1, the insulating films IL2, IL3, and IL4 in the capacitor formation region and the electrodes embedded therein (lower electrode LE, floating electrode FE, and upper electrode UE) are extracted and shown in FIG. FIG. 6 and FIG. 7 show regions corresponding to FIG. 8 in the case of the first study example and the second study example.

  In the first study example shown in FIG. 6, in the capacitor formation region, the electrode DE1 is formed in the same layer as the wiring M1 in the same process, and the electrode DE2 is formed in the same layer as the wiring M2 in the same process. In addition, the electrode DE3 is formed in the same layer as the wiring M3 in the same process. Therefore, the electrode DE1 is embedded in a groove (opening) formed in the insulating film IL2, the electrode DE2 is embedded in a groove (opening) formed in the insulating film IL3, and the electrode DE3 is And embedded in a groove (opening) formed in the insulating film IL4.

  The bottom surface of the electrode DE2 is located in the middle of the thickness of the insulating film IL3, and the insulating film IL3 (the insulating film IL3 in a portion located below the bottom surface of the electrode DE2) is between the electrode DE1 and the electrode DE2. Intervene. The bottom surface of the electrode DE3 is located in the middle of the thickness of the insulating film IL4. Between the electrode DE2 and the electrode DE3, the insulating film IL4 (the insulating film IL4 in a portion positioned below the bottom surface of the electrode DE3) is provided. ) Is present.

  The electrode DE2 and the electrode DE1 are not connected by a conductor, and the electrode DE2 and the electrode DE3 are not connected by a conductor. However, the electrode DE3 and the electrode DE1 are connected by a conductor. That is, although not shown, the electrode DE3 and the electrode DE1 are the wiring M3 formed integrally with the electrode DE3, the wiring M1 connected integrally with the electrode DE1, the wiring M2, and the via. They are electrically connected via the parts V2 and V3. For this reason, the same potential is supplied to the electrode DE3 and the electrode DE1.

  In the case of the first study example of FIG. 6, the electrode DE1, the electrode DE2, the electrode DE3, the insulating film IL3 between the electrode DE1 and the electrode DE2, and the insulating film IL4 between the electrode DE3 and the electrode DE2. The capacitor element C101 is formed. The electrode DE2 is one electrode of the capacitive element C101, the electrode DE1 and the electrode DE3 are the other electrode of the capacitive element C101, the insulating film IL3 interposed between the electrode DE1 and the electrode DE2, and the electrode DE3 And the insulating film IL4 interposed between the electrode DE2 function as a capacitive insulating film (dielectric film) of the capacitive element C101.

  In the case of the first study example in FIG. 6, the capacitance value of the capacitive element C101 can be easily increased. However, according to the study of the present inventors, it has been found that the following problems arise.

  That is, in recent years, semiconductor devices have been reduced in size and thickness, and accordingly, the thickness of an interlayer insulating film for forming a multilayer wiring structure has been reduced. The reduction in the thickness of the interlayer insulating film corresponds to the reduction in the thickness of each of the insulating films IL3 and IL4 in the first study example of FIG.

  In a capacitor element, by applying different potentials to one electrode and the other electrode, a potential difference is generated between one electrode and the other electrode, and electric charge is accumulated in the capacitor element. That is, in a capacitor element, a low voltage is applied to one electrode, and a higher voltage than that is applied to the other electrode, whereby charges are accumulated in the capacitor element.

  In the case of the first study example of FIG. 6, when accumulating charges in the capacitive element C101, a low voltage is applied to the electrode DE2, and a higher voltage is applied to the electrodes DE1 and DE3, or a low voltage is applied. A voltage is applied to the electrode DE1 and the electrode DE3, and a higher voltage is applied to the electrode DE2. At this time, a predetermined potential difference (potential difference between the voltage applied to the electrode DE2 and the voltage applied to the electrodes DE1 and DE3) is generated between the electrode DE1 and the electrode DE2 and between the electrode DE3 and the electrode DE2. Become. Therefore, when the thickness of the insulating films IL3 and IL4 is reduced, the thickness of the insulating film IL3 interposed between the electrode DE1 and the electrode DE2 and the thickness of the insulating film IL4 interposed between the electrode DE3 and the electrode DE2 are reduced. This leads to a reduction in thickness, and thus the withstand voltage and TDDB (Time Dependent Dielectric Breakdown) life of the capacitive element C101 are reduced. In addition, when the voltage applied between the electrodes DE1, DE3 and DE2 is high, for example, when the voltage is 12 V or more, the insulating film interposed between the electrodes DE1, DE3 and the electrode DE2 is thin. It is difficult to ensure a breakdown voltage and a TDDB life.

  Therefore, in order to improve the breakdown voltage of the capacitive element, it is conceivable to apply the second study example of FIG.

  In the second study example shown in FIG. 7, in the capacitor formation region, the lower electrode LE201 is formed in the same layer as the wiring M1, and the upper electrode UE201 is formed in the same layer as the wiring M3. It is formed with. For this reason, the lower electrode LE201 is embedded in a groove (opening) formed in the insulating film IL2, and the upper electrode UE201 is embedded in a groove (opening) formed in the insulating film IL4. The bottom surface (lower surface) of the upper electrode UE201 is located in the middle of the thickness of the insulating film IL4, and the insulating film IL4 (lower than the bottom surface of the upper electrode UE201) is positioned between the lower electrode LE201 and the upper electrode UE201. Insulating film IL4) and insulating film IL3 (for the entire thickness of insulating film IL3) are interposed. The lower electrode LE201 and the upper electrode UE201 are not connected by a conductor.

  In the case of the second study example in FIG. 7, the capacitive element C201 is formed by the lower electrode LE201, the upper electrode UE201, and the insulating films IL3 and IL4 between the lower electrode LE201 and the upper electrode UE201. The lower electrode LE201 is one electrode of the capacitive element C201, the upper electrode UE201 is the other electrode of the capacitive element C201, and the insulating films IL3 and IL4 interposed between the lower electrode LE201 and the upper electrode UE201 are It functions as a capacitive insulating film (dielectric film) of the capacitive element C201.

  In the case of the second study example of FIG. 7, the electrode of the capacitive element C201 is constituted by the lower electrode LE201 in the same layer as the wiring M1 and the upper electrode UE201 in the same layer as the wiring M3. For this reason, in the case of the second study example in FIG. 7, the spacing between the electrodes of the capacitor element is larger than in the case of the first study example in FIG. 6, so that the breakdown voltage and the TDDB life of the capacitor element can be improved. .

  That is, in the case of the first study example of FIG. 6, the distance between the electrodes of the capacitive element is the distance (distance) L101 between the electrode DE1 and the electrode DE2, and the distance (distance) between the electrode DE2 and the electrode DE3. Corresponding to L102. The distance L101 between the electrode DE1 and the electrode DE2 is defined by the distance between the wiring layer ML1 and the wiring layer ML2, and the distance L102 between the electrode DE2 and the electrode DE3 is the wiring layer ML2 and the wiring layer ML3. Will be defined by the interval between. On the other hand, in the second study example of FIG. 7, the distance between the electrodes of the capacitive element corresponds to the distance (distance) L201 between the lower electrode LE201 and the upper electrode UE201. The distance L201 between the electrode UE201 is defined by the distance between the wiring layer ML1 and the wiring layer ML3. Therefore, the distance L201 between the lower electrode LE201 and the upper electrode UE201 in the second study example of FIG. 7 is the distance L101 between the electrode DE1 and the electrode DE2 in FIG. It becomes larger than the distance L102 between DE3 (that is, L201> L101 and L201> L102). As the distance between the electrode to which the high potential is applied and the electrode to which the low potential is applied in the capacitor is increased, the withstand voltage and the TDDB life of the capacitor are improved. For this reason, compared with the case of the first study example of FIG. 6, the case of the second study example of FIG. 7 improves the withstand voltage and the TDDB life of the capacitor element because the gap between the electrodes of the capacitor element is larger. be able to.

  However, in the case of the second study example in FIG. 7, the capacitance value of the capacitive element C201 becomes smaller by the increase in the distance L201 between the lower electrode LE201 and the upper electrode UE201. That is, in the case of the second study example of FIG. 7, the insulating films IL3 and IL4 interposed between the lower electrode LE201 and the upper electrode UE201 function as a capacitive insulating film of the capacitive element C201, and the lower electrode LE201 and the upper electrode A distance L201 between the UE 201 and the UE 201 is equal to the thickness of the capacitive insulating film. For this reason, in the case of the second study example in FIG. 7, the thickness of the capacitive insulating film is defined by the distance between the wiring layer ML1 and the wiring layer ML3. Therefore, in the case of the second study example in FIG. 7, in the capacitive element C201, since the gap L201 between the lower electrode LE201 and the upper electrode UE201 is large and the capacitive insulating film is thick, the capacitance value of the capacitive element C201 is large. Will become smaller. In order to secure the capacitance value of the capacitive element C201, it is necessary to increase the areas of the lower electrode LE201 and the upper electrode UE201. Therefore, in the semiconductor device, the area required to form the capacitive element C201 is increased. This leads to an increase in the area of the semiconductor device. This is disadvantageous for downsizing (smaller area) of the semiconductor device.

<Main features and effects>
The semiconductor device of this embodiment includes a semiconductor substrate SB, a wiring structure (multilayer wiring structure) formed on the semiconductor substrate SB and including a plurality of wiring layers, and a capacitance formed in the wiring structure (multilayer wiring structure). The plurality of wiring layers of the wiring structure (multilayer wiring structure) includes a first wiring layer, a second wiring layer that is one layer above the first wiring layer, And a third wiring layer that is one layer above the second wiring layer. Then, the first electrode (here, the lower electrode LE) of the capacitive element C1 is formed in the first wiring layer, and the second electrode (here, the upper electrode UE) of the capacitive element C1 is formed in the third wiring layer. The second electrode (upper electrode UE) is arranged above the first electrode (lower electrode LE), and the second wiring layer includes a first electrode (lower electrode LE), a second electrode (upper electrode UE), and A floating electrode FE located between the two is formed.

  As shown in the first study example of FIG. 6 described above, in the case where electrodes for applying different potentials in the capacitive element are arranged in a certain wiring layer and a wiring layer one layer above it, the breakdown voltage of the capacitive element and the TDDB Life may be reduced. Further, as shown in the second study example of FIG. 7 described above, when electrodes for applying different potentials in the capacitive element are arranged in a certain wiring layer and the wiring layer two layers above it, the breakdown voltage and TDDB life of the capacitive element are arranged. However, the capacitance value of the capacitive element becomes small, and it becomes difficult to secure the capacitance value required for the circuit configuration.

  On the other hand, in the present embodiment, the lower electrode LE of the capacitive element C1 is formed in any one of the plurality of wiring layers formed on the semiconductor substrate SB, and the wiring one layer higher than that is formed. The floating electrode FE is formed in the layer, and the upper electrode UE of the capacitive element C1 is formed in the wiring layer one layer higher than the floating electrode FE. Specifically, as shown in FIGS. 1 and 8, the lower electrode LE is formed in the same layer as the wiring M1 (that is, in the wiring layer ML1), and in the same layer as the wiring M2 (that is, 1 from the wiring layer ML1). The floating electrode FE is formed in the upper wiring layer ML2, and the upper electrode UE is formed in the same layer as the wiring M3 (that is, in the wiring layer ML3 one layer higher than the wiring layer ML2).

  In the present embodiment, the upper electrode UE is formed in the wiring layer (wiring layer ML3 in the case of FIG. 8) two layers above the wiring layer (wiring layer ML1 in the case of FIG. 8) on which the lower electrode LE is formed. Therefore, as compared with the case of the first study example of FIG. 6, the interval between the electrodes of the capacitive element can be increased, so that the breakdown voltage and the TDDB life of the capacitive element C1 can be improved.

  That is, in the case of the first study example in FIG. 6, the thickness of the insulating film interposed between the electrodes to which different potentials are applied in the capacitive element (that is, the insulating film functioning as the capacitive insulating film) is the same as that of the electrode DE1 and the electrode DE2. This corresponds to the thickness of the insulating film IL3 interposed between the electrodes DE2 and DE3, or the thickness of the insulating film IL4 interposed between the electrodes DE2 and DE3. On the other hand, in the present embodiment, the thickness of the insulating film interposed between the electrodes to which different potentials are applied in the capacitor element (that is, the insulating film functioning as the capacitor insulating film) is the same as that of the lower electrode LE and the floating electrode FE. This is the sum of the thickness of the insulating film IL3 interposed therebetween and the thickness of the insulating film IL4 interposed between the floating electrode FE and the upper electrode UE. For this reason, compared with the case of the first study example of FIG. 6 described above, in this embodiment, an insulating film interposed between electrodes to which different potentials are applied in the capacitor element (that is, an insulating film functioning as a capacitor insulating film). The thickness of can be increased. When the insulating film interposed between electrodes to which different potentials are applied in the capacitor element (that is, the insulating film functioning as a capacitor insulating film) is thicker, the withstand voltage of the capacitor element is higher, and the TDDB life of the capacitor element is also increased. become longer. Therefore, as compared with the case of the first study example in FIG. 6, the present embodiment has an insulating film interposed between electrodes to which different potentials are applied in the capacitive element (that is, an insulating film functioning as a capacitive insulating film). ) Is increased, the breakdown voltage of the capacitor can be increased, and the TDDB life of the capacitor can be increased. For this reason, the reliability of the semiconductor device having a capacitor can be improved.

  In the present embodiment, the upper electrode UE is formed in the wiring layer (wiring layer ML3 in the case of FIG. 8) two layers above the wiring layer (wiring layer ML1 in the case of FIG. 8) on which the lower electrode LE is formed. At the same time, the floating electrode FE is formed in the wiring layer (wiring layer ML2 in the case of FIG. 8) one layer above the wiring layer (wiring layer ML1 in the case of FIG. 8) on which the lower electrode LE is formed. That is, the wiring layer (in the case of FIG. 8) between the wiring layer (in the case of FIG. 8 the wiring layer ML1) in which the lower electrode LE is formed and the wiring layer in which the upper electrode UE is formed (the wiring layer ML3 in FIG. 8). Forms a floating electrode FE in the wiring layer ML2). The floating electrode FE is disposed between the lower electrode LE and the upper electrode UE. In the present embodiment, since the floating electrode FE is disposed between the lower electrode LE and the upper electrode UE, the capacitance element C1 is compared with the second study example of FIG. 7 in which the floating electrode FE is not provided. The capacity value can be increased.

  That is, in the case of the second study example in FIG. 7, the distance L201 between the lower electrode LE201 and the upper electrode UE201 (that is, the distance from the upper surface of the lower electrode LE201 to the lower surface of the upper electrode UE201) is the same as that of the capacitor insulating film. Since the thickness is increased, the capacitance value of the capacitive element C201 is reduced by increasing the thickness of the capacitive insulating film. On the other hand, in this embodiment, the floating electrode FE is disposed between the lower electrode LE and the upper electrode UE, so that the effective thickness of the capacitive insulating film is reduced by the thickness of the floating electrode FE. be able to.

  That is, in the present embodiment, the effective thickness of the capacitive insulating film is such that the distance L1 between the lower electrode LE and the floating electrode FE (that is, the distance from the upper surface of the lower electrode LE to the lower surface of the floating electrode FE) and the upper part. This corresponds to the sum of the distance L2 between the electrode UE and the floating electrode FE (that is, the distance from the upper surface of the floating electrode FE to the lower surface of the upper electrode UE). In other words, in the present embodiment, the effective thickness of the capacitive insulating film is the distance L3 between the lower electrode LE and the upper electrode UE (that is, the distance from the upper surface of the lower electrode LE to the lower surface of the upper electrode UE). From this, the thickness T1 of the floating electrode FE is subtracted. Therefore, the distance L3 between the lower electrode LE and the upper electrode UE in the present embodiment of FIG. 8 is the same as the distance L201 between the lower electrode LE201 and the upper electrode UE201 in the second study example of FIG. In this case, the effective thickness of the capacitive insulating film is smaller in the present embodiment of FIG. 8 by the thickness T1 of the floating electrode FE than in the second study example of FIG. Accordingly, the capacitance value of the capacitive element can be increased in the present embodiment in FIG. 8 than in the second study example in FIG. Further, since the effective thickness of the capacitive insulating film can be reduced and the capacitance value of the capacitive element C1 can be increased in the present embodiment of FIG. 8 than in the second study example of FIG. 7, the capacitive element C1 occupies. The area (corresponding to the areas of the lower electrode LE and the upper electrode UE) can be reduced. This is advantageous for miniaturization (small area) of the semiconductor device.

  Thus, in the present embodiment, the upper electrode UE is formed in the wiring layer two layers above the wiring layer in which the lower electrode LE is formed, and the wiring layer one layer higher than the wiring layer in which the lower electrode LE is formed. Since the floating electrode FE is formed on the upper electrode UE and the floating electrode FE is disposed between the lower electrode LE and the upper electrode UE, the withstand voltage of the capacitive element C1 can be increased. In addition, the TDDB life of the capacitive element C1 can be extended. Further, the capacitance value of the capacitive element C1 can be increased. As a result, the reliability of the semiconductor device having the capacitor can be improved. In addition, the performance of the semiconductor device having a capacitor can be improved. In addition, a semiconductor device having a capacitor can be reduced in size.

  9 to 11 are graphs showing voltage distributions when a predetermined voltage is applied to the electrodes of the capacitive element. 9 corresponds to the case of the first study example of FIG. 6, FIG. 10 corresponds to the case of the second study example of FIG. 7, and FIG. 11 shows the case of the present embodiment of FIG. It corresponds to. The horizontal axis of the graphs of FIGS. 9 to 11 corresponds to the position in the thickness direction, and the vertical axis of the graphs of FIGS. 9 to 11 corresponds to the voltage (potential).

  In the case of the first study example in FIG. 6, the voltage distribution at the position of the two-dot chain line TS1 in FIG. 6 when the voltage Vb is applied to the electrode DE2 and the voltage Va is applied to the electrodes DE1 and DE3 is 9 corresponds to the graph of FIG. 9, and the position on the two-dot chain line TS1 of FIG. 6 corresponds to the horizontal axis of the graph of FIG. Further, in the case of the second study example in FIG. 7, the voltage distribution at the position of the two-dot chain line TS2 in FIG. 7 when the voltage Vb is applied to the upper electrode UE201 and the voltage Va is applied to the lower electrode LE201. Corresponds to the graph of FIG. 10, and the position on the two-dot chain line TS2 of FIG. 7 corresponds to the horizontal axis of the graph of FIG. In the case of the present embodiment shown in FIG. 8, the voltage distribution at the position of the two-dot chain line TS3 in FIG. 8 when the voltage Vb is applied to the electrode UE and the voltage Va is applied to the lower electrode LE is as follows. 11 corresponds to the graph of FIG. 11, and the position on the two-dot chain line TS2 of FIG. 8 corresponds to the horizontal axis of the graph of FIG.

  In the case of the first study example in FIG. 6, as shown in the graph of FIG. 9, the potential difference between the electrode DE1 and the electrode DE2 is Vb−Va, and the potential difference between the electrode DE3 and the electrode DE2 is also Vb. −Va. For this reason, in the case of the first study example in FIG. 6, the electric field strength in the insulating film (IL3) between the electrode DE1 and the electrode DE2 is (Vb−Va) / L101, and the electrode DE3 and the electrode DE2 The electric field strength in the insulating film (IL4) is (Vb−Va) / L102.

  In the case of the second study example shown in FIG. 7, the potential difference between the lower electrode LE201 and the upper electrode UE201 becomes the voltage Vb−Va as shown in the graph of FIG. 10, and thus the lower electrode LE201 and the upper electrode UE201. The electric field strength in the insulating films (IL3, IL4) between the two is (Vb−Va) / L201.

  In the case of the present embodiment shown in FIG. 8, the potential difference between the lower electrode LE and the upper electrode UE is Vb−Va as shown in the graph of FIG. The electric field strength in the insulating films (IL3, IL4) is (Vb−Va) / (L1 + L2).

  When the electrode DE1, the lower electrode LE201, and the lower electrode LE are formed in the same manner, the electrode DE2 and the floating electrode FE are formed in the same manner, and the electrode DE3, the upper electrode UE201, and the upper electrode UE are formed in the same manner, L1 = L101, L2 = L102, and L1 + L2 + T1 = L3 = L201 hold. Based on this assumption, the case of the first study example of FIG. 6 (corresponding to the graph of FIG. 9), the case of the second study example of FIG. 7 (corresponding to the graph of FIG. 10), and the present embodiment of FIG. A comparison with the case of the form (corresponding to the graph of FIG. 11) is as follows.

  That is, the electric field strength in the thickness direction applied to the insulating film between the electrodes of the capacitive element (corresponding to the slope of the graphs in FIGS. 9 to 11) corresponds to the case of the first study example in FIG. 6 (corresponding to the graph in FIG. 9). ) Is the largest, the case of the second study example in FIG. 7 (corresponding to the graph of FIG. 10) is the smallest, and in the case of the present embodiment of FIG. 8 (corresponding to the graph of FIG. 11), Become.

  Therefore, the electric field strength in the thickness direction applied to the insulating film (capacitor insulating film) between the electrodes of the capacitive element (corresponding to the slope of the graphs in FIGS. 9 to 11) is the case of the first study example in FIG. In the case of the present embodiment of FIG. 8 (corresponding to the graph of FIG. 11), the case of the second study example of FIG. 7 (corresponding to the graph of FIG. 10) is smaller than the case of this embodiment of FIG. It becomes even smaller. For this reason, the withstand voltage between the electrodes of the capacitive element and the TDDB life of the capacitive element are more in the case of the present embodiment of FIG. 8 (FIG. 11) than in the first study example of FIG. 6 (corresponding to the graph of FIG. 9). (Corresponding to the graph of FIG. 10) is further improved.

  On the other hand, the capacitance value of the capacitive element is larger in the case of the present embodiment in FIG. 8 (corresponding to the graph in FIG. 11) than in the second study example in FIG. 7 (corresponding to the graph in FIG. 10). Thus, in the case of the first study example of FIG. 6 (corresponding to the graph of FIG. 9), the size is further increased.

  That is, in the case of the first study example in FIG. 6, the capacitance value of the capacitor element is large, but there is a concern about the withstand voltage of the capacitor element and the TDDB life. In the case of the second study example in FIG. Although the TDDB life is excellent, the capacitance value of the capacitive element becomes too small. In the case of the present embodiment in FIG. 8, it is possible to achieve both the securing of the capacitance value of the capacitive element and the improvement of the breakdown voltage and TDDB life of the capacitive element.

  Even when a multilayer wiring structure is formed on a semiconductor substrate and a capacitive element is provided in the multilayer wiring structure, it is possible to adjust the thickness of the capacitive insulating film of the capacitive element by changing the thickness of the interlayer insulating film in the multilayer wiring structure. Have difficulty. In other words, the thickness of each of the plurality of interlayer insulating films constituting the multilayer wiring structure is often determined by factors other than the capacitive element formed in the multilayer wiring structure. In addition, changing the thickness of the interlayer insulating film constituting the multilayer wiring structure causes an increase in development cost. For this reason, when the first study example of FIG. 6 is adopted, there is a concern about the withstand voltage of the capacitor and the TDDB life as the interlayer insulating film is thinned. On the other hand, when the second study example of FIG. Although the withstand voltage and the TDDB life of the capacitive element are improved to an excessive extent, the capacitance value of the capacitive element becomes insufficient, and the occupation area of the capacitive element must be remarkably increased.

  That is, when it is desired to improve the breakdown voltage and the TDDB life of the capacitive element as compared with the case of the first study example of FIG. 6, but to increase the capacitance value as compared with the case of the second study example of FIG. The thickness of the interlayer insulating film (IL3, IL4) is increased in the case of the first study example in FIG. 6, or the thickness of the interlayer insulating film (IL3, IL4) is increased in the case of the second study example in FIG. It is necessary to make it thinner. However, it is difficult to adjust the thickness of the interlayer insulating films (IL3, IL4) in accordance with the capacitive element, resulting in an increase in development cost.

  Therefore, if the present embodiment of FIG. 8 is adopted, the withstand voltage of the capacitive element and the capacitance element can be improved more than the case of the first study example of FIG. 6 without changing the thickness of the interlayer insulating film constituting the multilayer wiring structure. The TDDB life can be improved, and the capacitance value can be made larger than in the case of the second study example in FIG. That is, by adopting the present embodiment of FIG. 8 and forming the upper electrode UE in the wiring layer two layers above the wiring layer in which the lower electrode LE is formed, the breakdown voltage and TDDB life of the capacitive element are improved, By disposing the floating electrode FE between the lower electrode LE and the upper electrode UE, the capacitance value of the capacitive element can be increased. Therefore, the withstand voltage and TDDB life of the capacitor and the capacitance value of the capacitor can be adjusted without changing the thickness of the interlayer insulating film constituting the multilayer wiring structure. Therefore, the reliability and performance of a semiconductor device having a capacitor can be improved, and the development cost of the semiconductor device can be suppressed or reduced.

  In the present embodiment, the floating electrode FE is disposed between the lower electrode LE and the upper electrode UE. However, the lower electrode LE, the floating electrode FE, and the upper electrode UE are disposed so as to overlap in plan view. ing. In the present embodiment, as shown in the plan views of FIGS. 2 to 5, the planar dimension (planar area) of the floating electrode FE is the planar dimension (planar area) of the lower electrode LE and the planar dimension of the upper electrode UE. The lower electrode LE, the floating electrode FE, and the upper electrode UE substantially coincide with each other in plan view. Accordingly, since the floating electrode FE hardly protrudes from the lower electrode LE or the upper electrode UE in a plan view, it is possible to avoid an increase in the area of the capacitive element due to the floating electrode FE. In addition, since the corner of the floating electrode FE is not disposed at a position included in the lower electrode LE and the upper electrode UE in plan view, electric field concentration at the corner of the floating electrode FE can be prevented. Accordingly, it is possible to avoid deterioration of the reliability of the insulating film starting from the corner of the floating electrode FE, so that the reliability of the semiconductor device having the capacitor can be improved.

  As another form, as FIG. 12 shows, the planar dimension (plane area) of floating electrode FE can also be made larger than each plane dimension (plane area) of the lower electrode LE and the upper electrode UE. Here, FIG. 12 is a plan view showing the floating electrode FE, and FIG. 12 shows a case where the planar dimensions of the floating electrode FE are larger than the planar dimensions of the lower electrode LE and the upper electrode UE. In FIG. 12, the floating electrode FE is indicated by a solid line, and the outer peripheral positions of the lower electrode LE and the upper electrode UE are indicated by a dotted line. In the case of FIG. 12, the planar dimensions of the floating electrode FE are larger than those of the lower electrode LE and the upper electrode UE, and the floating electrode FE includes the lower electrode LE and the upper electrode UE in plan view.

  Since the floating electrode FE is formed by the damascene method, the depth of the groove or opening formed in the insulating film (IL3) for embedding the floating electrode FE increases as the planar dimension (planar area) increases. Accordingly, the thickness T1 of the floating electrode FE is increased. For this reason, when the planar dimension (planar area) of the floating electrode FE is larger than each planar dimension (planar area) of the lower electrode LE and the upper electrode UE, the thickness T1 of the floating electrode FE is increased. Since the thickness of the portion of the insulating film IL3 interposed between the floating electrode FE and the lower electrode LE can be reduced, the effective thickness of the capacitive insulating film can be reduced, and the capacitance value is increased accordingly. can do. Therefore, when the planar dimension (planar area) of the floating electrode FE is made larger than each planar dimension (planar area) of the lower electrode LE and the upper electrode UE, the capacitance value of the capacitive element can be further increased.

  By making the planar dimension (planar area) of the floating electrode FE larger than the planar dimension (planar area) of the upper electrode UE, for example, the thickness T1 of the floating electrode FE is larger than the thickness T2 of the upper electrode UE (T1>). T2). The thicknesses T1 and T2 are shown in FIG.

  As still another form, as shown in FIG. 13, the planar dimension (planar area) of the floating electrode FE can be made smaller than each planar dimension (planar area) of the lower electrode LE and the upper electrode UE. Here, FIG. 13 is a plan view showing the floating electrode FE, and FIG. 13 shows a case where the planar dimensions of the floating electrode FE are smaller than the planar dimensions of the lower electrode LE and the upper electrode UE. In FIG. 13, the floating electrode FE is indicated by a solid line, and the outer peripheral positions of the lower electrode LE and the upper electrode UE are indicated by dotted lines. In the case of FIG. 13, the planar dimension of the floating electrode FE is smaller than that of the lower electrode LE and the upper electrode UE, and the floating electrode FE is included in the lower electrode LE and the upper electrode UE in plan view.

  As shown in FIG. 13, when the planar dimension (planar area) of the floating electrode FE is smaller than each planar dimension (planar area) of the lower electrode LE and the upper electrode UE, the thickness T1 of the floating electrode FE is small. As a result, the thickness of the insulating film IL3 in the portion interposed between the floating electrode FE and the lower electrode LE can be increased, so that the effective thickness of the capacitive insulating film can be increased. For this reason, although the capacitance value of the capacitive element becomes small, the electric field strength in the thickness direction in the insulating film interposed between the floating electrode FE and the lower electrode LE can be reduced, so that the breakdown voltage and TDDB life of the capacitive element can be reduced. This is advantageous in terms of improvement.

  By making the planar dimension (planar area) of the floating electrode FE smaller than the planar dimension (planar area) of the upper electrode UE, for example, the thickness T1 of the floating electrode FE is smaller than the thickness T2 of the upper electrode UE (T1 < T2). The thicknesses T1 and T2 are shown in FIG.

  The present embodiment is effective when applied to a case where the voltage (potential difference) applied between the lower electrode LE and the upper electrode UE is high. For example, a voltage of 12 V or more is applied to the lower electrode LE and the upper electrode UE. If it is applied in the case of applying between the two, the effect is extremely large.

<Modification>
Next, a modification of the present embodiment will be described.

  FIG. 14 is a fragmentary cross-sectional view of a semiconductor device according to a first modification of the present embodiment, and corresponds to FIG.

  In the case of FIG. 1 described above, the capacitor element C1 is formed using three wiring layers. However, in the case of the first modification example shown in FIG. 14, the capacitor element C1 is formed using five wiring layers. .

  That is, in the case of FIG. 1 described above, the lower electrode LE of the capacitive element C1 is formed in the first wiring layer which is one of the plurality of wiring layers formed on the semiconductor substrate SB, The floating electrode FE is formed in the second wiring layer one layer above the one wiring layer, and the upper electrode UE of the capacitive element C1 is formed in the third wiring layer one layer above the second wiring layer. ing.

  On the other hand, in the case of the first modified example of FIG. 14, the electrode LE1 is formed on the first wiring layer which is one of the plurality of wiring layers formed on the semiconductor substrate SB, and the first LE The floating electrode FE1 is formed in the second wiring layer that is one layer higher than the second wiring layer, and the electrode UE1 is formed in the third wiring layer that is one layer higher than the second wiring layer. This is the same as the case of the present embodiment in FIG. Here, the electrode LE1 corresponds to the lower electrode LE, the floating electrode FE1 corresponds to the floating electrode FE, and the electrode UE1 corresponds to the upper electrode UE.

  In the case of the first modified example of FIG. 14, the floating electrode FE2 is formed in the fourth wiring layer that is one layer above the third wiring layer, and the fifth wiring that is one layer above the fourth wiring layer is formed. An electrode LE2 is formed on the layer. That is, in the case of the first modified example of FIG. 14, the electrode LE1 is formed in any wiring layer formed on the semiconductor substrate SB, and the floating electrode FE1 is formed in the wiring layer one layer higher than that. The electrode UE1 is formed in the wiring layer one layer higher than that, the floating electrode FE2 is formed in the wiring layer one layer higher than that, and the electrode LE2 is formed in the wiring layer one layer higher than that. Yes. The electrode UE1 is disposed above the electrode LE1, the floating electrode FE1 is disposed between the electrode LE1 and the electrode UE1, the electrode LE2 is disposed above the electrode UE1, and the floating electrode FE2 is disposed between the electrode UE1 and the electrode LE2. Is arranged.

  In FIG. 14, the electrode LE1 is formed in the same layer as the wiring M1 in the same process, the floating electrode FE1 is formed in the same layer as the wiring M2, and the electrode UE1 is formed in the same process as the wiring M3. The floating electrode FE2 is formed in the same layer as the wiring M4 in the same process, and the electrode LE2 is formed in the same layer as the wiring M5 in the same process. Therefore, the electrode LE1 is embedded in a groove (or opening) formed in the insulating film IL2, and the floating electrode FE1 is embedded in a groove (or opening) formed in the insulating film IL3. The electrode UE1 is embedded in a groove (or opening) formed in the insulating film IL4. The floating electrode FE2 is embedded in a groove (or opening) formed in the insulating film IL5, and the electrode LE2 is embedded in a groove (or opening) formed in the insulating film IL6.

  The bottom surface (lower surface) of the floating electrode FE1 is located in the middle of the thickness of the insulating film IL3, and the insulating film IL3 (a portion positioned below the bottom surface of the floating electrode FE1) is interposed between the electrode LE1 and the floating electrode FE1. Insulating film IL3) is interposed. Further, the bottom surface (lower surface) of the electrode UE1 is located in the middle of the thickness of the insulating film IL4, and the insulating film IL4 (a portion located below the bottom surface of the electrode UE1) is located between the floating electrode FE1 and the electrode UE1. Insulating film IL4) is interposed. Further, the bottom surface (lower surface) of the floating electrode FE2 is located in the middle of the thickness of the insulating film IL5, and the insulating film IL5 (lower than the bottom surface of the floating electrode FE2) is positioned between the electrode UE1 and the floating electrode FE2. Part of the insulating film IL5) is interposed. The bottom surface (lower surface) of the electrode LE2 is located in the middle of the thickness of the insulating film IL6, and the insulating film IL6 (a portion positioned below the bottom surface of the electrode LE2) is interposed between the floating electrode FE2 and the electrode LE2. Insulating film IL6) is interposed. The electrode LE1, the floating electrode FE1, the electrode UE1, the floating electrode FE2, and the electrode LE2 are formed in five continuous wiring layers. The wiring layer that forms the electrode LE1 is the lowermost wiring layer (that is, the wiring M1 is formed). The wiring layer is not limited.

  Both the floating electrode FE1 and the floating electrode FE2 are set to a floating potential. That is, the floating electrode FE1 and the floating electrode FE2 are electrically in a floating state (floating state). The floating electrode FE1 is not connected to any of the electrodes LE1, UE1, and LE2 by a conductor, and the floating electrode FE2 is not connected to any of the electrodes LE1, UE1, and LE2 by a conductor. That is, since the floating electrode FE1 is not connected to any of the electrodes LE1, UE1, and LE2 by a conductor, a direct current does not flow between the floating electrode FE1 and the electrodes LE1, UE1, and LE2. In addition, since the floating electrode FE2 is not connected to any of the electrodes LE1, UE1, and LE2 by a conductor, a direct current does not flow between the floating electrode FE2 and the electrodes LE1, UE1, and LE2. Further, the floating electrode FE1 and the floating electrode FE2 are not connected by a conductor.

  The electrode LE1 and the electrode UE1 are not connected by a conductor, and the electrode UE1 and the electrode LE2 are not connected by a conductor, but the electrode LE1 and the electrode LE2 are connected by a conductor. That is, the electrode LE1 and the electrode UE1 are connected through a conductor and are electrically connected to each other. For this reason, the same potential is supplied to the electrode LE1 and the electrode LE2.

  Although not shown, the electrical connection between the electrode LE1 and the electrode LE2 can be ensured as follows, for example. That is, the wiring M1 that is integrally connected to the electrode LE1, the wiring M2 that is not connected to the floating electrode FE1, the wiring M3 that is not connected to the electrode UE1, and the wiring M4 that is not connected to the floating electrode FE2. The electrode LE1 and the electrode LE2 can be electrically connected through the wiring M5 integrally connected to the electrode LE2 and via portions V2 to V5 connecting the wirings.

  In the case of the first modification in FIG. 14, the electrode LE1, the electrode LE2, the electrode UE1, the insulating films IL3 and IL4 between the electrode LE1 and the electrode UE1, and the insulating film IL5 between the electrode UE1 and the electrode LE2. , IL6 forms a capacitive element C1. The electrode UE1 is one electrode of the capacitive element C1, the electrode LE1 and the electrode LE2 are the other electrode of the capacitive element C1, and the insulating films IL3 and IL4 interposed between the electrode LE1 and the electrode UE1, The insulating films IL5 and IL6 interposed between the electrode UE1 and the electrode LE2 function as a capacitive insulating film (dielectric film) of the capacitive element C1.

  In the case of FIG. 1 and FIG. 8, a higher potential (voltage) is applied (supplied) to one of the lower electrode LE and the upper electrode UE than to the other of the lower electrode LE and the upper electrode UE. As a result, charges are accumulated in the capacitive element C1.

  On the other hand, in the case of the first modification shown in FIG. 14, a higher potential (voltage) is applied to one of the electrodes LE1, LE2 and the electrode UE1 than to the other of the electrodes LE1, LE2 and the electrode UE1. By (supplied), electric charge is accumulated in the capacitive element C1. That is, when accumulating charges in the capacitive element C1, different voltages are applied to the electrodes LE1 and LE2 and the electrode UE1 through a conductor such as a wiring. However, the electrode LE1 and the electrode LE2 are at the same potential. That is, when accumulating charges in the capacitive element C1, the electrode UE1 is set to a higher potential (high voltage) than the electrodes LE1 and LE2, or the electrodes LE1 and LE2 are set to a higher potential (high voltage) than the electrode UE1. ). However, like the floating electrode FE, the floating electrodes FE1 and FE2 are set at a floating potential, and when charges are accumulated in the capacitor C1, voltage application through a conductor such as a wiring is applied to the floating electrodes FE1 and FE2. It is not done for. For this reason, the floating electrodes FE1, FE2 can also be regarded as dummy electrodes.

  Also in the case of the first modification of FIG. 14, the electrode UE1 is formed in the wiring layer two layers above the wiring layer in which the electrode LE1 is formed, and the electrode is formed in the wiring layer two layers above the wiring layer in which the electrode UE1 is formed. Since LE2 is formed, the gap between the electrodes of the capacitor can be increased, so that the withstand voltage and the TDDB life of the capacitor C1 can be improved.

  Also in the case of the first modified example of FIG. 14, the electrode UE1 is formed in a wiring layer two layers above the wiring layer in which the electrode LE1 is formed, and the wiring layer one layer higher than the wiring layer in which the electrode LE1 is formed. The floating electrode FE1 is formed in the layer, and the floating electrode FE1 is disposed between the electrode LE1 and the electrode UE1. In addition, the electrode LE2 is formed in the wiring layer two layers above the wiring layer in which the electrode UE1 is formed, and the floating electrode FE2 is formed in the wiring layer one layer higher than the wiring layer in which the electrode UE1 is formed. The electrode FE2 is disposed between the electrode UE1 and the electrode LE2. Since the floating electrode FE1 is disposed between the electrode LE1 and the electrode UE1, and the floating electrode FE2 is disposed between the electrode UE1 and the electrode LE2, the capacitance is smaller than that in the case where the floating electrodes FE1 and FE2 are not provided. The capacitance value of the element C1 can be increased. In addition, since the capacitance value of the capacitor can be increased by reducing the effective thickness of the capacitor insulating film, the area occupied by the capacitor can be reduced. This is advantageous for miniaturization (small area) of the semiconductor device.

  As a result, the reliability of the semiconductor device having the capacitor can be improved. In addition, the performance of the semiconductor device having a capacitor can be improved. In addition, a semiconductor device having a capacitor can be reduced in size.

  Furthermore, as another modified example, in the first modified example of FIG. 14, another electrode (electrode) electrically connected to the electrode UE1 through a conductor in the wiring layer two layers above the wiring layer in which the electrode LE2 is formed. Electrode) to which the same potential as UE1 is supplied), another floating electrode is formed in the wiring layer one layer higher than the wiring layer in which electrode LE2 is formed, and the other floating electrode is connected to electrode LE2 and the other It can also arrange | position between these electrodes. In this case, the electrode UE1 and the other electrode are one electrode of the capacitive element C1, and the electrode LE1 and the electrode LE2 are the other electrode of the capacitive element C1. Similarly, the floating electrode and the electrode for the capacitive element can be further stacked.

(Embodiment 2)
<Structure of semiconductor device>
15 to 17 and FIG. 21 are cross-sectional views of main parts of the semiconductor device of the second embodiment, and FIGS. 18 to 20 are plan views of main parts of the semiconductor device of the second embodiment. FIG. 15 corresponds to FIG. 1 of the first embodiment, and shows a cross-sectional view of the MISFET formation region and the capacitor formation region in the semiconductor device of the second embodiment. 16 and 17 are other cross-sectional views of the capacitor formation region in the semiconductor device of the second embodiment. 18 to 20 are plan views of capacitor formation regions in the semiconductor device of the second embodiment.

  15 substantially corresponds to the cross section taken along the line B1-B1 in FIGS. 18 to 20, and the cross sectional view in FIG. 16 corresponds to the position along the line B2-B2 in FIGS. 17 substantially corresponds to the cross section taken along the line B3-B3 in FIGS. However, in the cross-sectional views of FIGS. 15 to 17, the illustration of the insulating film IL6 and the structure above the wiring M5 embedded in the insulating film IL6 is omitted. Further, the MISFET formation region and the capacitor formation region in FIG. 15 correspond to different planar regions in the same semiconductor device (the same semiconductor substrate SB). The MISFET formation region and the capacitor formation region in FIG. 15 may or may not be adjacent to each other. However, for the sake of easy understanding, in the cross-sectional view of FIG. A sectional view of the capacitor formation region is shown next to the figure.

  18 to 20 show the same planar region (capacitor formation region here) in the same semiconductor device (semiconductor substrate SB), but the layers shown in FIGS. 18 to 20 are different. Yes. That is, FIG. 18 shows a planar layout of a layer (that is, the wiring layer ML3) where the metal patterns MP1 and MP2 are formed in the capacitor formation region. FIG. 19 shows a planar layout of a layer in which the metal patterns MP3 and MP4 are formed in the capacitor formation region (that is, the wiring layer ML4). FIG. 20 shows a planar layout of a layer (that is, the wiring layer ML5) where the metal patterns MP5 and MP6 are formed in the capacitor formation region. 18 to 20 are all plan views, but the metal patterns MP1 to MP6 are hatched in order to make the drawings easy to see.

  In FIG. 18, the metal patterns MP1 and MP2 are hatched and indicated by solid lines, but in order to facilitate understanding of the planar positional relationship, the electrode portions MD3 and MD4 of the metal patterns MP3 and MP4 are shown. Shown in dotted lines. In FIG. 19, the metal patterns MP3 and MP4 are hatched and indicated by solid lines. In order to facilitate understanding of the planar positional relationship, the electrodes of the metal patterns MP1 and MP2 (MP5 and MP6). The parts MD1, MD2 (MD5, MD6) are indicated by dotted lines. In FIG. 20, the metal patterns MP5 and MP6 are hatched and indicated by solid lines. However, in order to facilitate understanding of the planar positional relationship, the electrode portions MD3 and MD4 of the metal patterns MP3 and MP4 are shown. Shown in dotted lines.

  FIG. 21 shows insulating films IL4, IL5, and IL6 and electrodes embedded therein (electrodes for capacitive elements) in the capacitor formation region. The insulating film IL3 and the structure below it are shown. The illustration is omitted. That is, in FIG. 15, the insulating films IL4, IL5, IL6 in the capacitor formation region and the metal patterns MP1 to MP6 (electrode portions MD1 to MD6) embedded therein are extracted and shown corresponding to FIG. Yes. 21 is a cross-sectional view, but hatching is omitted for the insulating films IL4, IL5, and IL6 in order to make the drawing easy to see. In FIG. 21, the hatching directions of the electrode parts MD1, MD3, MD5 that are electrically connected to each other are made common, and the hatching directions of the electrode parts MD2, MD4, MD6 that are electrically connected to each other. The direction is common.

  Since the configuration of the MISFET formation region in the semiconductor device of the second embodiment is the same as that of the first embodiment (FIG. 1 above), the repetitive description is omitted here.

  In the semiconductor device of the second embodiment, the MISFET is formed in the MISFET formation region, and the capacitor C2 and the capacitor C3 are formed in the capacitor formation region which is a different planar region (different planar region of the same semiconductor substrate SB) from the MISFET formation region. And are formed. A specific configuration of the capacitor formation region in the semiconductor device of the second embodiment will be described with reference to FIGS.

  As shown in FIGS. 15 to 17, the capacitor C <b> 3 is formed on the main surface of the semiconductor substrate SB in the capacitor formation region. The capacitive element C3 is a so-called MOS (Metal Oxide Semiconductor) capacitive element.

  Specifically, a well region, here a p-type well region PW2, is formed on the main surface of the semiconductor substrate SB in the capacitor formation region. The capacitive element C3 is formed on the n-type semiconductor region NS1 formed on the surface layer portion of the p-type well region PW2 in the capacitor formation region, the insulating film YZ formed on the n-type semiconductor region NS1, and the insulating film YZ. The upper electrode GD and the n-type semiconductor region NS2 formed in the p-type well region PW2 on both sides of the upper electrode GD. The upper electrode GD functions as one electrode of the capacitive element C3, the n-type semiconductor region NS1 functions as the other electrode (lower electrode) of the capacitive element C3, and is located between the upper electrode GD and the n-type semiconductor region NS1. The insulating film YZ interposed therebetween functions as a capacitive insulating film (dielectric film) of the capacitive element C3.

  The MOS type capacitive element is one in which the channel region, gate insulating film and gate electrode of the MISFET are used as the lower electrode, capacitive insulating film and upper electrode of the MOS type capacitive element, respectively. A diffusion layer (here, n-type semiconductor region NS1) is provided and used as a lower electrode. Note that the capacitor insulating film (here, the insulating film YZ) is not limited to the oxide film even when referred to as a MOS capacitor, and an insulating film other than the oxide film is used as the capacitor insulating film (here, the insulating film YZ). You can also. Therefore, the MOS type capacitive element uses a part of the semiconductor substrate SB (here, the n-type semiconductor region NS1) as a lower electrode, and an insulating film (here, the insulating film YZ) on the semiconductor substrate SB (on the n-type semiconductor region NS1). Can be regarded as a capacitive element having a conductor layer (here, the upper electrode GD) formed via the upper electrode.

  The insulating film YZ is formed together (simultaneously) when the gate insulating film GI for the MISFET Q1 is formed, and is formed of the same insulating film as the gate insulating film GI of the MISFET Q1.

  The upper electrode GD is formed on the insulating film YZ and is formed of a patterned conductive film, for example, a polycrystalline silicon film (doped polysilicon film) into which impurities are introduced. The upper electrode GD and the gate electrode GE can be formed by forming a conductive film serving both as the upper electrode GD and the gate electrode GE and then patterning the conductive film. Therefore, the upper electrode GD is formed together (simultaneously) when the gate electrode GE of the MISFET Q1 is formed, and is composed of a conductive film (conductor film) in the same layer as the gate electrode GE of the MISFET Q1.

  FIG. 15 shows a case where a MOS type capacitive element C3 is formed on the main surface of the semiconductor substrate SB in the capacitor formation region. As another form, another semiconductor element, for example, MISFET or the like can be formed on the main surface of the semiconductor substrate SB in the capacitor formation region. Alternatively, as in the case of FIG. 1, the semiconductor substrate SB in the capacitor formation region. There may be a case where no semiconductor element is formed on the main surface.

  On the semiconductor substrate SB, an insulating film IL1 is formed so as to cover a semiconductor element (for example, MISFET Q1 or capacitive element C3) formed on the main surface of the semiconductor substrate SB, and a plug PG is necessary for this insulating film IL1. It is embedded in the place according to.

  Next, the structure above the insulating film IL1 will be described. Also in the semiconductor device of the second embodiment, a plurality of wiring layers including the wirings M1 to M5, that is, a multilayer wiring structure is formed on the insulating film IL1. The semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in the multilayer wiring structure in the capacitor formation region. For this reason, here, a multilayer wiring structure in the capacitor formation region will be described.

  Similar to the first embodiment, also in the second embodiment, the insulating film IL2 is formed on the insulating film IL1 in which the plug PG is embedded. The insulating film IL2 includes a trench for wiring and its insulating film IL2. A wiring M1 embedded in the groove is formed. An insulating film IL3 is formed on the insulating film IL2 in which the wiring M1 is embedded. In the insulating film IL3, a wiring groove and a wiring M2 embedded in the groove are formed. An insulating film IL4 is formed on the insulating film IL3 in which the wiring M2 is embedded, and a wiring trench and a wiring M3 embedded in the groove are formed in the insulating film IL4. An insulating film IL5 is formed on the insulating film IL4 in which the wiring M3 is embedded. In the insulating film IL5, a wiring groove and a wiring M4 embedded in the groove are formed. An insulating film IL6 is formed on the insulating film IL5 in which the wiring M4 is embedded, and a wiring groove and a wiring M5 embedded in the groove are formed in the insulating film IL6. Each of the wirings M1 to M5 can be formed using a damascene technique, and can be a copper wiring (damascene copper wiring, embedded copper wiring) containing copper as a main component. Each of the insulating films IL2 to IL6 can be a single-layer insulating film or a stacked film of a plurality of insulating films, and the bottom surface of the wiring M2 is located in the middle of the thickness of the insulating film IL3. The bottom surface is located in the middle of the thickness of the insulating film IL4, the bottom surface of the wiring M4 is located in the middle of the thickness of the insulating film IL5, and the bottom surface of the wiring M5 is located in the middle of the thickness of the insulating film IL6. These are the same as the first embodiment in the second embodiment.

  The wiring M2 is electrically connected to the wiring M1 through the via portion V2 as necessary, and the wiring M3 is electrically connected to the wiring M2 through the via portion V3 as necessary, to the wiring M4. Is electrically connected to the wiring M3 via the via portion V4 as necessary, and the wiring M5 is electrically connected to the wiring M4 via the via portion V5 as necessary. When the wiring M2 is formed by the dual damascene technology, the via portion V2 is formed integrally with the wiring M2, the bottom surface of the via portion V2 is in contact with the wiring M1, and the wiring M2 is formed by the single damascene technology. The via portion V2 is formed separately from the wiring M2, but the upper surface of the via portion V2 is in contact with the wiring M2, and the bottom surface of the via portion V2 is in contact with the wiring M1. The same applies to the wirings M3 to M5 and the via portions V3 to V5. These are the same as the first embodiment in the second embodiment.

  However, the second embodiment is different from the first embodiment in the configuration of the electrodes of the capacitive element formed in the capacitor formation region. Hereinafter, in the second embodiment, the structure of the electrode of the capacitive element formed in the capacitor formation region will be specifically described.

  As shown in FIGS. 15 to 21, in the capacitor forming region, the metal patterns MP1 and MP2 are formed in the same layer as the wiring M3 in the same process, and the metal patterns MP3 and MP4 are formed in the same layer as the wiring M4 in the same process. The metal patterns MP5 and MP6 are formed in the same layer as the wiring M5 in the same process.

  That is, the wiring M3, the metal pattern MP1, and the metal pattern MP2 are formed in the same layer in the same process using damascene technology, and are embedded in the insulating film IL4 (specifically, a groove formed in the insulating film IL4). Yes. Therefore, the wiring M3, the metal pattern MP1, and the metal pattern MP2 are formed by damascene wiring (specifically, damascene wiring embedded in the insulating film IL4).

  Further, the wiring M4, the metal pattern MP3, and the metal pattern MP4 are formed in the same layer in the same process using the damascene technique, and are embedded in the insulating film IL5 (specifically, a groove formed in the insulating film IL5). Yes. Therefore, the wiring M4, the metal pattern MP3, and the metal pattern MP4 are formed by damascene wiring (specifically, damascene wiring embedded in the insulating film IL5).

  Further, the wiring M5, the metal pattern MP5, and the metal pattern MP6 are formed in the same layer in the same process using the damascene technique, and are embedded in the insulating film IL6 (specifically, a groove formed in the insulating film IL6). Yes. Therefore, the wiring M5, the metal pattern MP5, and the metal pattern MP6 are formed by damascene wiring (specifically, damascene wiring embedded in the insulating film IL6).

  The metal pattern MP1, the metal pattern MP2, and the wiring M3 are made of the same conductive material, the metal pattern MP3, the metal pattern MP4, and the wiring M4 are made of the same conductive material, and the metal pattern MP5, the metal pattern MP6, and the wiring M5 are the same conductive material. Made of material. The insulating film IL5 is formed on the insulating film IL4 in which the wiring M3 and the metal patterns MP1 and MP2 are embedded, and the insulating film IL6 is formed on the insulating film IL5 in which the wiring M4 and the metal patterns MP3 and MP4 are embedded. Yes. Although not shown, an insulating film (not shown) is formed on the insulating film IL6 in which the wiring M5 and the metal patterns MP5 and MP6 are embedded.

  The bottom surface of the metal pattern MP1 and the bottom surface of the metal pattern MP2 are located in the middle of the thickness of the insulating film IL4, the height position of the bottom surface of the metal pattern MP1, the height position of the bottom surface of the metal pattern MP2, and the wiring The height position of the bottom surface of M3 is substantially the same. The bottom surface of the metal pattern MP3 and the bottom surface of the metal pattern MP4 are located in the middle of the thickness of the insulating film IL5, and the height position of the bottom surface of the metal pattern MP3 and the height position of the bottom surface of the metal pattern MP4 The height position of the bottom surface of the wiring M4 is substantially the same. The bottom surface of the metal pattern MP5 and the bottom surface of the metal pattern MP6 are located in the middle of the thickness of the insulating film IL6, and the height position of the bottom surface of the metal pattern MP5 and the height position of the bottom surface of the metal pattern MP6 The height position of the bottom surface of the wiring M5 is substantially the same.

  The metal patterns MP1, MP2, MP3, MP4, MP5, and MP6 are electrodes of the capacitive element C2. That is, the metal patterns MP1, MP3, and MP5 function as one electrode of the capacitive element C2, and the metal patterns MP2, MP4, and MP6 function as the other electrode of the capacitive element C2. The planar layout of the metal patterns MP1, MP2, MP3, MP4, MP5 and MP6 will be specifically described below.

  As shown in FIG. 15 to FIG. 18 and FIG. 21, in the wiring layer ML3 in the capacitor formation region (that is, in the same layer as the wiring M3), a plurality of electrode portions (wiring portions, conductor portions) MD1 extending in the X direction. , MD2 and a connecting part (wiring part, conductor part) MC1 extending in the Y direction and connecting the end part of the electrode part MD1, and a connecting part extending in the Y direction and connecting the end part of the electrode part MD2. (Wiring portion, conductor portion) MC2 is formed. Between the connecting part MC1 and the connecting part MC2 extending in the Y direction, the electrode parts MD1 and the electrode parts MD2 extending in the X direction are alternately arranged at predetermined intervals (preferably at equal intervals) in the Y direction. Yes. The widths of the electrode parts MD1 and MD2 (the width in the Y direction) are preferably the same.

  Note that the X direction and the Y direction are directions that intersect each other, and preferably are directions that are orthogonal to each other. Further, the X direction and the Y direction are parallel to the main surface of the semiconductor substrate SB, and are also parallel to the upper surface of the insulating film IL4.

  Each electrode part MD1 is connected to the connecting part MC1 at one end part side (the end part on the side facing the connecting part MC1 and corresponding to the lower end part in FIG. 18), and the other end part side. (The end on the side facing the connecting part MC2 and corresponding to the upper end in FIG. 18) is separated from the connecting part MC2. Each electrode portion MD2 has one end side (the end on the side facing the connecting portion MC1 and corresponding to the lower end in FIG. 18) spaced from the connecting portion MC1 and the other end side. (The end on the side facing the coupling part MC2 and corresponding to the upper end in FIG. 18) is connected to the coupling part MC2.

  Accordingly, in the wiring layer ML3 in the capacitor formation region, the plurality of electrode portions MD1 and the connecting portion MC1 that connects them are integrally formed to form a comb-shaped metal pattern (conductor pattern, wiring pattern) MP1. ing. That is, the metal pattern MP1 has a comb-like pattern shape in which a plurality of electrode parts MD1 extending in the X direction and arranged in the Y direction are connected by a connecting part MC1 extending in the Y direction. . Further, the plurality of electrode parts MD2 and the connecting part MC2 that connects them are integrally formed to form a comb-shaped metal pattern (conductor pattern, wiring pattern) MP2. That is, the metal pattern MP2 has a comb-like pattern shape in which a plurality of electrode parts MD2 extending in the X direction and arranged in the Y direction are connected by a connecting part MC2 extending in the Y direction. . In the wiring layer ML3 in the capacitor formation region, the metal pattern MP1 and the metal pattern MP2 are in the plane direction (parallel to the main surface of the semiconductor substrate SB) with an insulating film (corresponding to the insulating film IL4 here) interposed therebetween. Direction). In particular, the electrode part MD1 and the electrode part MD2 face each other in the Y direction and are alternately arranged in the Y direction.

  As shown in FIGS. 15 to 17, 19, and 21, in the wiring layer ML <b> 4 in the capacitor formation region (that is, in the same layer as the wiring M <b> 4), a plurality of electrode portions (wiring portions and conductor portions) extending in the X direction. ) MD3, MD4, connecting part (wiring part, conductor part) MC3 extending in the Y direction and connecting the end part of the electrode part MD3, and extending in the Y direction, connecting the end part of the electrode part MD4 A connecting portion (wiring portion, conductor portion) MC4 is formed. Between the connecting part MC3 and the connecting part MC4 extending in the Y direction, the electrode parts MD3 and the electrode parts MD4 extending in the X direction are alternately arranged at predetermined intervals (preferably at equal intervals) in the Y direction. Yes. It is preferable that the electrode parts MD3 and MD4 have the same width (width in the Y direction).

  Each electrode part MD3 has one end side (the end on the side facing the connecting part MC3 and corresponding to the lower end in FIG. 19) connected to the connecting part MC3 and the other end side. (The end on the side facing the connecting part MC4 and corresponding to the upper end in FIG. 19) is separated from the connecting part MC4. Each electrode part MD4 has one end side (the end facing the connecting part MC3 and corresponding to the lower end in FIG. 19) spaced from the connecting part MC3 and the other end side. (It is an end portion on the side facing the connecting portion MC4 and corresponds to the upper end portion in FIG. 19) is connected to the connecting portion MC4.

  Accordingly, in the wiring layer ML4 in the capacitor formation region, the plurality of electrode parts MD3 and the connecting part MC3 connecting them are integrally formed to form a comb-shaped metal pattern (conductor pattern, wiring pattern) MP3. ing. That is, the metal pattern MP3 has a comb-like pattern shape in which a plurality of electrode parts MD3 extending in the X direction and arranged in the Y direction are connected by a connecting part MC3 extending in the Y direction. . Further, the plurality of electrode parts MD4 and the connecting part MC4 for connecting them are integrally formed to form a comb-shaped metal pattern (conductor pattern, wiring pattern) MP4. That is, the metal pattern MP4 has a comb-shaped pattern shape in which a plurality of electrode parts MD4 extending in the X direction and arranged in the Y direction are connected by a connecting part MC4 extending in the Y direction. . In the wiring layer ML4 in the capacitor formation region, the metal pattern MP3 and the metal pattern MP4 are arranged in a plane direction (parallel to the main surface of the semiconductor substrate SB) with an insulating film (corresponding to the insulating film IL5 here) interposed therebetween. Direction). In particular, the electrode part MD3 and the electrode part MD4 face each other in the Y direction and are alternately arranged in the Y direction.

  As shown in FIGS. 15 to 17, 20, and 21, in the wiring layer ML <b> 5 in the capacitor formation region (that is, in the same layer as the wiring M <b> 5), a plurality of electrode portions (wiring portions, conductor portions) extending in the X direction. ) MD5, MD6, a connecting part (wiring part, conductor part) MC5 extending in the Y direction and connecting the end part of the electrode part MD5, and an end part of the electrode part MD6 extending in the Y direction A connecting part (wiring part, conductor part) MC6 is formed. Between the connecting portion MC5 and the connecting portion MC6 extending in the Y direction, the electrode portions MD5 and the electrode portions MD6 extending in the X direction are alternately arranged at predetermined intervals (preferably at equal intervals) in the Y direction. Yes. It is preferable that the electrode parts MD5 and MD6 have the same width (width in the Y direction). In addition, the electrode parts MD1, MD2, MD3, MD4, MD5, and MD6 preferably have the same width (the width in the Y direction), thereby efficiently increasing the capacitance value of the capacitive element C2. be able to. The lengths of the electrode parts MD1, MD2, MD3, MD4, MD5, and MD6 (the length in the X direction) are more preferably the same, whereby the capacitance value of the capacitive element C2 can be efficiently increased. Can be bigger.

  Each electrode part MD5 is connected to the connecting part MC5 at one end part side (the end part on the side facing the connecting part MC5 and corresponding to the lower end part in FIG. 20), and the other end part side. (The end on the side facing the connecting part MC6 and corresponding to the upper end in FIG. 20) is separated from the connecting part MC6. Each electrode part MD6 has one end side (the end on the side facing the connecting part MC5 and corresponding to the lower end in FIG. 20) spaced from the connecting part MC5 and the other end side. (The end on the side facing the coupling part MC6, which corresponds to the upper end in FIG. 20) is connected to the coupling part MC6.

  Accordingly, in the wiring layer ML5 in the capacitor formation region, the plurality of electrode parts MD5 and the connecting part MC5 that connects them are integrally formed to form a comb-shaped metal pattern (conductor pattern, wiring pattern) MP5. ing. That is, the metal pattern MP5 has a comb-like pattern shape in which a plurality of electrode parts MD5 extending in the X direction and arranged in the Y direction are connected by a connecting part MC5 extending in the Y direction. . Further, the plurality of electrode parts MD6 and the connecting part MC6 connecting them are integrally formed to form a comb-shaped metal pattern (conductor pattern, wiring pattern) MP6. That is, the metal pattern MP6 has a comb-like pattern shape in which a plurality of electrode parts MD6 extending in the X direction and arranged in the Y direction are connected by a connecting part MC6 extending in the Y direction. . In the wiring layer ML5 in the capacitor formation region, the metal pattern MP5 and the metal pattern MP6 are in the plane direction (parallel to the main surface of the semiconductor substrate SB) with an insulating film (corresponding to the insulating film IL6 here) interposed therebetween. Direction). In particular, the electrode part MD5 and the electrode part MD6 face each other in the Y direction and are alternately arranged in the Y direction.

  The planar layout of the metal pattern MP1 and the planar layout of the metal pattern MP5 are the same, and the planar layout of the metal pattern MP2 and the planar layout of the metal pattern MP6 are the same. That is, the metal pattern MP1 and the metal pattern MP5 are arranged in different positions (preferably the same) in a plan view (preferably with the same plane dimensions and shape), although the formed layers are different. Further, the metal pattern MP2 and the metal pattern MP6 are arranged in different positions (preferably the same) in a plan view (preferably with the same plane dimensions and plane shape), although the formed layers are different.

  For this reason, the electrode part MD1 formed in the wiring layer ML3 and the electrode part MD5 formed in the wiring layer ML5 are arranged (preferably with the same plane dimensions) at positions that overlap (preferably the same) in plan view. In addition, the electrode part MD2 formed in the wiring layer ML3 and the electrode part MD6 formed in the wiring layer ML5 are arranged (preferably with the same plane dimensions) at positions that overlap (preferably the same) in plan view. .

  However, the electrode part MD3 of the metal pattern MP3 formed on the wiring layer ML4 is seen in plan view on both the metal patterns MP1 and MP2 formed on the wiring layer ML3 and the metal patterns MP5 and MP6 formed on the wiring layer ML5. There is no overlap. Further, the electrode part MD4 of the metal pattern MP4 formed on the wiring layer ML4 has a plan view on both the metal patterns MP1 and MP2 formed on the wiring layer ML3 and the metal patterns MP5 and MP6 formed on the wiring layer ML5. There is no overlap.

  In the capacitor formation region, attention is paid to the wiring layer ML3 and the wiring layer ML4 as follows.

  That is, in plan view, the electrode part MD3 formed in the wiring layer ML4 is disposed between the electrode part MD1 and the electrode part MD2 that are formed in the wiring layer ML3 and are adjacent to each other in the Y direction. The formed electrode part MD4 is disposed between the electrode part MD1 and the electrode part MD2 which are formed in the wiring layer ML3 and adjacent to each other in the Y direction. That is, in the plan view, the electrode part MD3 does not overlap the electrode part MD1 and the electrode part MD2, and is disposed between the electrode part MD1 and the electrode part MD2 adjacent in the Y direction. MD4 does not overlap with electrode part MD1 and electrode part MD2, and is disposed between electrode part MD1 and electrode part MD2 adjacent in the Y direction. In other words, the position of the electrode part MD3 is shifted in the Y direction from the position directly above the electrode part MD1, and is also shifted in the Y direction from the position directly above the electrode part MD2, and the electrode part MD4. Is shifted in the Y direction from a position immediately above the electrode part MD1, and is also shifted in the Y direction from a position immediately above the electrode part MD2. For example, in plan view, the electrode part MD1, the electrode part MD3, the electrode part MD2, and the electrode part MD4 are arranged in this order in the Y direction, and this arrangement is repeated in the Y direction. The electrode part MD4, the electrode part MD2, and the electrode part MD3 may be arranged in this order in the Y direction, and this arrangement may be repeated in the Y direction.

  As an example, the electrode part MD3 can be arranged at a substantially central position between the electrode part MD1 and the electrode part MD2 adjacent in the Y direction in plan view, and the electrode part MD4 is shown in plan view. In FIG. 5, the electrode portion MD1 and the electrode portion MD2 adjacent in the Y direction can be disposed at a substantially central position.

  In the capacitor formation region, attention is paid to the wiring layer ML4 and the wiring layer ML5 as follows.

  That is, in a plan view, the electrode part MD3 formed in the wiring layer ML4 is disposed between the electrode part MD5 and the electrode part MD6 that are formed in the wiring layer ML5 and are adjacent in the Y direction. The formed electrode part MD4 is disposed between the electrode part MD5 and the electrode part MD6 which are formed in the wiring layer ML5 and adjacent to each other in the Y direction. That is, in the plan view, the electrode part MD3 does not overlap the electrode part MD5 and the electrode part MD6, and is disposed between the electrode part MD5 and the electrode part MD6 adjacent in the Y direction. MD4 does not overlap electrode part MD5 and electrode part MD6, and is arranged between electrode part MD5 and electrode part MD6 adjacent in the Y direction. In other words, the position of the electrode part MD3 is shifted in the Y direction from the position immediately below the electrode part MD5, and is also shifted in the Y direction from the position immediately below the electrode part MD6, and the electrode part MD4. Is shifted in the Y direction from a position immediately below the electrode part MD5, and is also shifted in the Y direction from a position immediately below the electrode part MD6. For example, in plan view, the electrode part MD5, the electrode part MD3, the electrode part MD6, and the electrode part MD4 are arranged in this order in the Y direction, and this arrangement is repeated in the Y direction. The electrode part MD4, the electrode part MD6, and the electrode part MD3 may be arranged in this order in the Y direction, and this arrangement may be repeated in the Y direction. As described above, in a plan view, the electrode part MD1 and the electrode part MD5 are arranged at a position where they overlap (preferably the same), and the electrode part MD2 and the electrode part MD6 are arranged at a position where they overlap (preferably the same). ing.

  For example, the electrode part MD3 can be disposed at a substantially central position between the electrode part MD5 and the electrode part MD6 adjacent in the Y direction in plan view, and the electrode part MD4 is shown in plan view. In FIG. 5, the electrode portion MD5 and the electrode portion MD6 adjacent in the Y direction can be disposed at a substantially central position.

  When attention is paid to the connecting portions MC1 to MC6 of the metal patterns MP1 to MP6, it is as follows.

  The side connected to the connecting part MC1 of the electrode part MD1 and the side connected to the connecting part MC2 of the electrode part MD2 are opposite to each other, the side connected to the connecting part MC3 of the electrode part MD3, and the electrode The side connected to the connecting part MC4 of the part MD4 is opposite to each other, and the side connected to the connecting part MC5 of the electrode part MD5 and the side connected to the connecting part MC6 of the electrode part MD6 are mutually On the other side. The side connected to the connecting part MC1 of the electrode part MD1, the side connected to the connecting part MC3 of the electrode part MD3, and the side connected to the connecting part MC5 of the electrode part MD5 are the same side. . In addition, the side connected to the connecting part MC2 of the electrode part MD2, the side connected to the connecting part MC4 of the electrode part MD4, and the side connected to the connecting part MC6 of the electrode part MD6 are the same side. . And it is preferable that the connection part MC1, the connection part MC3, and the connection part MC5 are arranged at positions that overlap (preferably the same) in plan view, and the connection part MC2, the connection part MC4, and the connection part MC6 are It is preferable that they are arranged at positions that overlap (preferably the same) in plan view. However, the connection parts MC1, MC3, MC5 do not overlap with the connection parts MC2, MC4, MC6 in plan view.

  Thus, the metal pattern MP1, the metal pattern MP3, and the metal pattern MP5 have substantially the same planar shape, and the metal pattern MP2, the metal pattern MP4, and the metal pattern MP6 have substantially the same planar shape. is there. The metal pattern MP1 and the metal pattern MP5 are arranged at positions where they overlap (preferably coincide) in plan view, but the metal pattern MP3 is shifted in the Y direction in plan view with respect to the metal patterns MP1 and MP5. It is arranged at the position. The metal pattern MP2 and the metal pattern MP6 overlap (preferably match) in plan view, but the metal pattern MP4 is shifted in the Y direction in plan view with respect to the metal patterns MP2 and MP6. Is arranged. Therefore, in plan view, each electrode part MD3 of the metal pattern MP3 does not overlap with the metal patterns MP1, MP2, MP5, and MP6 in plan view, and each electrode part MD4 of the metal pattern MP4 is not in the metal pattern MP1. , MP2, MP5, and MP6 do not overlap in plan view.

  As can be seen from FIG. 16, the connecting portion MC5 of the metal pattern MP5 is electrically connected to the connecting portion MC3 of the metal pattern MP3 through a via portion V5 formed integrally with the connecting portion MC5. Further, the connecting part MC3 of the metal pattern MP3 is electrically connected to the connecting part MC1 of the metal pattern MP1 through a via part V4 formed integrally with the connecting part MC3. That is, the connecting part MC5 and the connecting part MC3 are electrically connected via the via part V5 disposed between the connecting part MC5 and the connecting part MC3, and the connecting part MC3 and the connecting part MC1 are It is electrically connected via a via part V4 arranged between the connecting part MC3 and the connecting part MC1. For this reason, the metal pattern MP1, the metal pattern MP3, and the metal pattern MP5 are electrically connected to each other through a conductor, and are supplied with the same potential (voltage).

  As can be seen from FIG. 17, the connecting portion MC6 of the metal pattern MP6 is electrically connected to the connecting portion MC4 of the metal pattern MP4 through a via portion V5 formed integrally with the connecting portion MC6. In addition, the connecting part MC4 of the metal pattern MP4 is electrically connected to the connecting part MC2 of the metal pattern MP2 through a via part V4 formed integrally with the connecting part MC4. That is, the connecting part MC6 and the connecting part MC4 are electrically connected via the via part V5 disposed between the connecting part MC6 and the connecting part MC4, and the connecting part MC4 and the connecting part MC2 are It is electrically connected via a via portion V4 disposed between the connecting portion MC4 and the connecting portion MC2. For this reason, the metal pattern MP2, the metal pattern MP4, and the metal pattern MP6 are electrically connected to each other through a conductor, and are supplied with the same potential (voltage).

  However, the metal patterns MP1, MP3, and MP5 are not connected to the metal patterns MP2, MP4, and MP6 by conductors. For this reason, the potential (voltage) supplied to the metal patterns MP1, MP3, and MP5 can be different from the potential (voltage) supplied to the metal patterns MP2, MP4, and MP6.

  Therefore, the metal pattern MP1, the metal pattern MP3, and the metal pattern MP5 are electrically connected to each other to form the first electrode (one electrode) of the capacitor C2, and the metal pattern MP2, the metal pattern MP4, and the metal The pattern MP6 is electrically connected to each other to form the second electrode (the other electrode) of the capacitive element C2. The insulating film between the first electrode and the second electrode becomes a capacitive insulating film (dielectric film) of the capacitive element C2. A capacitive element C2, which is a MIM (Metal Insulator Metal) type capacitive element, is formed by the metal patterns MP1 to MP6 (the first electrode and the second electrode) and the insulating film between the metal patterns MP1 to MP6. Yes. Accordingly, the metal patterns MP1, MP3, and MP5 each form at least a part of the first electrode of the capacitive element C2, and the metal patterns MP2, MP4, and MP6 each form at least a part of the second electrode of the capacitive element C2. To do.

  By applying (supplying) a higher potential (voltage) to the one of the metal patterns MP1, MP3, MP5 and the metal patterns MP2, MP4, MP6 than the other, it is possible to accumulate charges in the capacitive element C2. . That is, when the electric charge is accumulated in the capacitive element C2, the metal patterns MP2, MP4, MP6 are set to a higher potential (high voltage) than the metal patterns MP1, MP3, MP5, or the metal patterns MP2, MP4, The metal patterns MP1, MP3, and MP5 are set to a higher potential (high voltage) than MP6.

  Since the capacitive element C2 is formed of the metal patterns MP1 to MP6 and the entire insulating film between them, the reference numeral C2 is omitted except for FIG.

  If a wiring is connected to at least one of the metal patterns MP1, MP3, and MP5, a desired potential can be supplied to the metal patterns MP1, MP3, and MP5 through the wiring. For example, if a wiring (M5) integrally connected to the metal pattern MP5 is provided in the wiring layer ML5, a desired potential can be supplied to the metal patterns MP5, MP3, and MP1 through the wiring (M5). it can. Further, if a wiring is connected to at least one of the metal patterns MP2, MP4, and MP6, a desired potential can be supplied to the metal patterns MP2, MP4, and MP6 through this wiring. For example, if a wiring (M5) integrally connected to the metal pattern MP6 is provided in the wiring layer ML5, a desired potential can be supplied to the metal patterns MP6, MP4, and MP2 through this wiring (M5). it can.

  The total capacitance of the capacitive element C2 is the sum of the following first to seventh capacitances. That is, the first capacitor formed between the metal pattern MP1 of the wiring layer ML3 and the metal pattern MP2 of the wiring layer ML3. A second capacitor formed between the metal pattern MP3 of the wiring layer ML4 and the metal pattern MP4 of the wiring layer ML4. A third capacitor formed between the metal pattern MP5 of the wiring layer ML5 and the metal pattern MP6 of the wiring layer ML5. A fourth capacitor formed between the metal pattern MP3 of the wiring layer ML4 and the metal pattern MP2 of the wiring layer ML3. A fifth capacitor formed between the metal pattern MP3 of the wiring layer ML4 and the metal pattern MP6 of the wiring layer ML5. A sixth capacitor formed between the metal pattern MP4 of the wiring layer ML4 and the metal pattern MP1 of the wiring layer ML3. A seventh capacitor formed between the metal pattern MP4 of the wiring layer ML4 and the metal pattern MP5 of the wiring layer ML5. Since the total capacitance of the capacitive element C2 can be the sum of the first to seventh capacitances, the capacitive element C2 can be increased in capacity.

  Among the first to seventh capacitors constituting the total capacitance of the capacitive element C2, the first to third capacitors are between the metal patterns in the same layer (here, between the metal patterns MP1, MP2, between the metal patterns MP3, MP4, And between metal patterns MP5 and MP6). Among the first to seventh capacitors constituting the total capacitance of the capacitive element C2, the fourth to seventh capacitors are between metal patterns of different layers (here, between metal patterns MP2 and MP3, between metal patterns MP3 and MP6, Capacity between the metal patterns MP1 and MP4 and between the metal patterns MP4 and MP5). The capacitive element C2 can also be regarded as a capacitive element that uses the fringe capacitance of the metal patterns MP1 to MP6 formed in the wiring layer.

  About the pattern shape (planar shape) of each metal pattern MP1-MP6, it is a comb-shaped pattern shape as mentioned above. That is, each metal pattern MP1 to MP6 extends in the X direction, and a plurality of electrode portions (any one of the electrode portions MD1 to MD6) arranged in the Y direction are connected to each other in the Y direction (connecting portion MC1). To any one of MC6). By making the metal patterns MP1 to MP6 into a comb-like pattern shape, the capacitance value per unit area of the capacitive element C2 can be efficiently increased. In addition, the width (the width in the Y direction) of the electrode portions MD1 to MD6 of the metal patterns MP1 to MP6 is the wiring M3 of the wiring layer (here, the wiring layers ML3 to ML5) in which the metal patterns MP1 to MP6 are formed. More preferably, it is the same as the minimum wiring width of .about.M5, whereby the capacitance value per unit area of the capacitive element C2 can be increased more efficiently.

  Moreover, although the case where the number of the electrode parts (MD1-MD6) extended in the X direction which each metal pattern MP1-MP6 has is four is shown by FIGS. 18-20, it is not limited to this. Various modifications are possible.

  In the second embodiment, the capacitive element C2 is formed using three continuous wiring layers. That is, the metal patterns MP1 and MP2 are formed in any one of the plurality of wiring layers formed on the semiconductor substrate SB, and one wiring layer higher than the wiring layer in which the metal patterns MP1 and MP2 are formed. Metal patterns MP3 and MP4 are formed on the layers, and metal patterns MP5 and MP6 are formed on the wiring layer one layer higher than the wiring layer on which the metal patterns MP3 and MP4 are formed. Although the case where the metal patterns MP1 to MP6 are formed in the wiring layers ML3 to ML5 has been described as an example, the invention is not limited thereto. For example, the metal patterns MP1 to MP6 can be formed in the wiring layers ML1 to ML3, or can be formed in the wiring layers ML2 to ML4, or one of the wiring layers ML4 and ML5 and the wiring layer ML5. It can also be formed on the upper wiring layer.

  As another form, the formation of the metal patterns MP5 and MP6 can be omitted. In this case, the metal pattern MP1 and the metal pattern MP3 become one electrode (first electrode) of the capacitive element C2, and the metal pattern MP2 and the metal pattern MP4 becomes the other electrode (second electrode) of the capacitive element C2. Alternatively, the formation of the metal patterns MP1 and MP2 can be omitted. In this case, the metal pattern MP3 and the metal pattern MP5 serve as one electrode (first electrode) of the capacitor C2, and the metal pattern MP4 and the metal pattern MP6 have a capacitance. This is the other electrode (second electrode) of the element C2.

  As another form, the number of wiring layers for forming the comb-shaped metal pattern for the electrode of the capacitive element C2 may be four or more. In the case of four layers, the wiring layer one layer higher than the wiring layer on which the metal patterns MP5 and MP6 are formed has the same planar shape (pattern shape) as the metal pattern MP3, and the metal pattern MP3 and the planar view And a metal pattern that has the same planar shape (pattern shape) as the metal pattern MP4 and overlaps (matches) the metal pattern MP4 in plan view. In this case, the metal pattern provided in the wiring layer one layer higher than the metal patterns MP5 and MP6 and having the same pattern shape as the metal pattern MP3 is electrically connected by being connected to the metal pattern MP3 through a conductor. Is done. Further, a metal pattern provided in the wiring layer one layer higher than the metal patterns MP5 and MP6 and having the same pattern shape as the metal pattern MP4 is electrically connected by being connected to the metal pattern MP4 through a conductor. The

  That is, the capacitive element C2 of the second embodiment is basically based on a laminated structure of comb-shaped metal patterns MP1 and MP2 and comb-shaped metal patterns MP3 and MP4 formed in the wiring layer one layer above it. . When the number of wiring layers on which the comb-shaped metal pattern for the capacitive element C2 is provided is increased, the metal has the same planar shape as the metal patterns MP1 and MP2 and overlaps (coincides with) the metal patterns MP1 and MP2 in plan view. The patterns and the metal patterns that have the same planar shape as the metal patterns MP3 and MP4 and overlap (coincide with) the metal patterns MP3 and MP4 in plan view may be alternately stacked.

  In the case of FIG. 15, in the capacitor formation region, a wiring M1 is formed in the wiring layer ML1, and the wiring M1 is formed on the main surface of the semiconductor substrate SB as needed (FIG. 15). In this case, the capacitor C2) can be electrically connected via the plug PG. In the case of FIG. 15, the dummy wiring DM is formed in the wiring layer ML2 in the capacitor formation region. The dummy wiring DM is formed in the same layer and in the same process as the wiring M2, and is embedded in the insulating film IL3. The bottom surface of the dummy wiring DM is located in the middle of the thickness of the insulating film IL3. The dummy wiring DM is set to a floating potential. The reason for providing the dummy wiring DM is to prevent dishing from occurring in the CMP process when forming the wiring M2. Further, by setting the dummy wiring DM to a floating potential, it is possible to avoid dielectric breakdown between the metal patterns MP1 and MP2 constituting the capacitive element C2 and the dummy wiring DM. If unnecessary, the formation of the dummy wiring DM can be omitted. Further, the metal pattern constituting the capacitive element C2 can be formed in the wiring layer ML2 without providing the dummy wiring DM.

<About study example>
Next, a study example studied by the present inventors will be described.

  FIG. 22 is a cross-sectional view of the main part of the semiconductor device of the third study example studied by the present inventor, and FIG. Each corresponds to FIG. 21 of the second embodiment.

  The third study example shown in FIG. 22 and the fourth study example shown in FIG. 23 differ from the second embodiment (FIG. 21) in the planar layout of the electrode parts MD3 and MD4.

  That is, in the third study example shown in FIG. 22, unlike the second embodiment, each electrode part MD3 of the wiring layer ML4 is in a position coincident with each electrode part MD1 of the wiring layer ML3 in plan view, and The electrode layer MD5 of the wiring layer ML5 is arranged at a position that coincides in plan view. Further, in the third study example shown in FIG. 22, unlike the second embodiment, each electrode part MD4 of the wiring layer ML4 is in a position coincident with each electrode part MD2 of the wiring layer ML3 in plan view, and The electrode layer MD6 of the wiring layer ML5 is disposed at a position that coincides in plan view. That is, in the third study example shown in FIG. 22, the electrode part MD1, the electrode part MD3, and the electrode part MD5 are arranged at positions that coincide with each other in plan view, and the electrode part MD2, the electrode part MD4, and the electrode part MD6 Are arranged at positions that coincide with each other in plan view.

  In the fourth study example shown in FIG. 23, unlike the second embodiment, each electrode part MD3 of the wiring layer ML4 is in a position coincident with each electrode part MD2 of the wiring layer ML3 in a plan view, and The electrode layer MD6 of the wiring layer ML5 is disposed at a position coinciding with the plane view. In the fourth study example shown in FIG. 23, unlike the second embodiment, each electrode part MD4 of the wiring layer ML4 is in a position coincident with each electrode part MD1 of the wiring layer ML3 in plan view, and The electrode layer MD5 of the wiring layer ML5 is arranged at a position that coincides in plan view. That is, in the fourth study example shown in FIG. 23, the electrode part MD1, the electrode part MD4, and the electrode part MD5 are arranged at positions that coincide with each other in plan view, and the electrode part MD2, the electrode part MD3, and the electrode part MD6 Are arranged at positions that coincide with each other in plan view.

  In the case of the third study example of FIG. 22, the electrode part MD1 is disposed immediately below the electrode part MD3, the electrode part MD5 is disposed immediately above the electrode part MD3, the electrode part MD2 is disposed immediately below the electrode part MD4, and the electrode The electrode part MD6 is arranged immediately above the part MD4. Therefore, the distance between the electrode part MD3 of the wiring layer ML4 and the electrode part MD2 of the wiring layer ML3, the distance between the electrode part MD3 of the wiring layer ML4 and the electrode part MD6 of the wiring layer ML5, the electrode of the wiring layer ML4 The distance between the part MD4 and the electrode part MD1 of the wiring layer ML3 and the distance between the electrode part MD4 of the wiring layer ML4 and the electrode part MD5 of the wiring layer ML5 are respectively large values. Accordingly, in the case of the third study example in FIG. 22, the fourth to seventh capacitances are reduced, so that the capacitance value of the capacitive element C2 is reduced. In this case, in order to secure the capacitance value of the capacitive element C2, it is necessary to increase the areas of the metal patterns MP1 to MP6. Therefore, in the semiconductor device, an increase in the area necessary for forming the capacitive element C2 is required. Will increase the area of the semiconductor device. This is disadvantageous for miniaturization (area reduction) of the semiconductor device.

  On the other hand, in the case of the fourth study example in FIG. 23, the electrode part MD2 is disposed immediately below the electrode part MD3, the electrode part MD6 is disposed immediately above the electrode part MD3, and the electrode part MD1 is disposed directly below the electrode part MD4. The electrode part MD5 is arranged immediately above the electrode part MD4. Therefore, the distance between the electrode part MD3 of the wiring layer ML4 and the electrode part MD2 of the wiring layer ML3, the distance between the electrode part MD3 of the wiring layer ML4 and the electrode part MD6 of the wiring layer ML5, the electrode of the wiring layer ML4 The distance between the part MD4 and the electrode part MD1 of the wiring layer ML3 and the distance between the electrode part MD4 of the wiring layer ML4 and the electrode part MD5 of the wiring layer ML5 become small values, and the withstand voltage and the TDDB life are reduced. It will be a concern.

  In a capacitor element, by applying different potentials to one electrode and the other electrode, a potential difference is generated between one electrode and the other electrode, and electric charge is accumulated in the capacitor element. That is, when accumulating charges in the capacitive element C2, one of the metal patterns MP1, MP3, MP5 and the metal patterns MP2, MP4, MP6 has a low potential (low voltage) and the other has a higher potential. (High voltage) is applied.

  Therefore, the electrode parts MD1, MD3, MD5 are at the same potential, and the electrode parts MD2, MD4, MD6 are at the same potential, but between the electrode parts MD1, MD3, MD5 and the electrode parts MD2, MD4, MD6. Causes a predetermined potential difference. In recent years, semiconductor devices have been made smaller and thinner, and accordingly, the thickness of an interlayer insulating film for forming a multilayer wiring structure has been reduced. The reduction in the thickness of the interlayer insulating film corresponds to the reduction in the thickness of the insulating films IL5 and IL6 in the case of FIGS.

  In the case of the fourth study example of FIG. 23, an electrode part MD6 having a different potential from the electrode part MD3 is arranged immediately above the electrode part MD3, and an electrode part MD2 having a different potential from the electrode part MD3 is directly below the electrode part MD3. The electrode part MD5 having a different potential from the electrode part MD4 is disposed immediately above the electrode part MD4, and the electrode part MD1 having a different potential from the electrode part MD4 is disposed immediately below the electrode part MD4. In this case, when the thickness of the insulating films IL5 and IL6 is reduced, the thickness of the insulating film IL5 interposed between the electrode part MD3 and the electrode part MD2 or between the electrode part MD4 and the electrode part MD1, the electrode part MD3 and the electrode This leads to a reduction in the thickness of the insulating film IL6 interposed between the part MD6 and between the electrode part MD4 and the electrode part MD5. This leads to a decrease in the breakdown voltage and the TDDB life of the capacitive element C2.

  In addition, when the voltage applied between the electrodes of the capacitive element is high, for example, when the voltage is 12 V or more, it is difficult to ensure the withstand voltage and the TDDB life if the insulating film interposed between the electrodes is thin. It is desirable in design to avoid the layout as in the fourth study example. Further, since the thickness of the interlayer insulating film may change when the product type changes (that is, the interlayer insulating film may be thin), it is desirable to avoid the layout as in the fourth study example of FIG. 23 as a design rule. .

<Main features and effects>
The semiconductor device according to the second embodiment includes a semiconductor substrate SB, a wiring structure (multilayer wiring structure) formed on the semiconductor substrate SB and including a plurality of wiring layers, and a capacitor element (C2) formed in the wiring structure. A semiconductor device having Then, the first metal pattern and the second metal pattern formed in the first wiring layer among the plurality of wiring layers of the wiring structure (multilayer wiring structure), and the second one layer higher than the first wiring layer. A third metal pattern and a fourth metal pattern formed in the wiring layer. The metal pattern MP1 corresponds to the first metal pattern, the metal pattern MP2 corresponds to the second metal pattern, the metal pattern MP3 corresponds to the third metal pattern, and the metal pattern MP4 corresponds to the fourth metal pattern. doing.

  The first metal pattern (MP1) extends in the X direction (first direction) and has a plurality of first electrode portions (second direction) arranged in the Y direction (second direction) intersecting the X direction in plan view. Corresponding to the electrode part MD1). The second metal pattern (MP2) includes a plurality of second electrode portions (corresponding to the electrode portions MD2) extending in the X direction and arranged in the Y direction in plan view. The first electrode part (MD1) and the second electrode part (MD2) are alternately arranged in the Y direction. The third metal pattern (MP3) includes a plurality of third electrode portions (corresponding to the electrode portions MD3) extending in the X direction and arranged in the Y direction in plan view. The fourth metal pattern (MP4) includes a plurality of fourth electrode portions (corresponding to the electrode portions MD4) extending in the X direction and arranged in the Y direction in plan view. The third electrode part (MD3) and the fourth electrode part (MD4) are alternately arranged in the Y direction. The first metal pattern (MP1) and the third metal pattern (MP3) are electrically connected to form one electrode of the capacitive element (C2), and the second metal pattern (MP2) and the fourth metal pattern (MP4) is electrically connected to form the other electrode of the capacitor (C2).

  The metal pattern MP3 corresponds to the first metal pattern, the metal pattern MP4 corresponds to the second metal pattern, the metal pattern MP5 corresponds to the third metal pattern, and the metal pattern MP6 is the fourth metal pattern. It can be considered that it corresponds to. In that case, the first electrode portion corresponds to the electrode portion MD3, the second electrode portion corresponds to the electrode portion MD4, the third electrode portion corresponds to the electrode portion MD5, and the fourth electrode portion is an electrode. This corresponds to the part MD6.

  Further, by applying (supplying) a potential (voltage) higher than the other to one of the first and third metal patterns (MP1, MP3) and the second and fourth metal patterns (MP2, MP4). Charge is accumulated in the capacitor element (C2).

  One of the main features of the second embodiment is that each of the plurality of first electrode parts (MD1) is adjacent to the third electrode part (MD3) and the fourth electrode part in the Y direction in plan view. (MD4), and each of the plurality of second electrode parts (MD2) includes a third electrode part (MD3) and a fourth electrode part (MD4) that are adjacent to each other in the Y direction in plan view. It is arranged between. Thereby, each of the plurality of first electrode parts (MD1) does not overlap with the plurality of third electrode parts (MD3) and the plurality of fourth electrode parts (MD4) in plan view, and the plurality of first electrode parts (MD1) Each of the two electrode parts (MD2) does not overlap with the plurality of third electrode parts (MD3) and the plurality of fourth electrode parts (MD4) in plan view.

  Unlike the second embodiment, the third electrode portion (MD3) in which each first electrode portion (MD1) has the same potential as the first electrode portion (MD1) as in the third study example of FIG. When each second electrode part (MD2) is arranged at a position immediately below the fourth electrode part (MD4) having the same potential as the second electrode part (MD2), The capacitance value of the element (C2) becomes small. Further, unlike the second embodiment, as in the fourth study example of FIG. 23 described above, each first electrode part (MD1) is supplied with a different potential from the first electrode part (MD1). It is arranged at a position immediately below the electrode part (MD4), and each second electrode part (MD2) is at a position directly below the third electrode part (MD3) to which a potential different from that of the second electrode part (MD2) is supplied. In the case of being arranged, the withstand voltage and the TDDB life of the capacitor (C2) may be reduced.

  On the other hand, in the second embodiment, each first electrode portion (MD1) includes a third electrode portion (MD3) having the same potential as the first electrode portion (MD1), a first electrode portion (MD1), and Are arranged at positions between the fourth electrode part (MD4) to which different potentials are supplied. Each second electrode part (MD2) is supplied with a fourth electrode part (MD4) having the same potential as the second electrode part (MD2) and a third electrode supplied with a different potential from the second electrode part (MD2). It arrange | positions in the position between electrode parts (MD3).

  For this reason, in this Embodiment 2, compared with the case of the 3rd examination example of the above-mentioned Drawing 22, the interval between the 1st electrode part (MD1) and the 4th electrode part (MD4), and the 2nd electrode part Since the distance between (MD2) and the third electrode part (MD3) can be reduced, the capacitance value of the capacitive element C2 can be increased. Specifically, in the case of the second embodiment in FIG. 21, the fourth to seventh capacitances can be increased in comparison with the case of the third study example in FIG. 22, and thus the capacitance of the capacitive element C2 The value can be increased. Further, since the capacitance value of the capacitive element C2 can be increased, the area necessary for forming the capacitive element C2 can be reduced, so that the semiconductor device can be reduced in size (reduced area). .

  In the second embodiment, as compared with the case of the fourth study example in FIG. 23, the distance between the first electrode portion (MD1) and the fourth electrode portion (MD4) and the second electrode portion ( Since the distance between MD2) and the third electrode part (MD3) can be increased, the withstand voltage and the TDDB life of the capacitive element C2 can be improved. For this reason, the reliability of the semiconductor device having a capacitor can be improved.

  That is, in the second embodiment, the first electrode part (MD1) constituting a part of one electrode of the capacitive element (C2) and the fourth part constituting a part of the other electrode of the capacitive element (C2). The distance between the electrode portions (MD4) can be made smaller than that in the third study example in FIG. 22 and larger than in the fourth study example in FIG. In the second embodiment, the second electrode part (MD2) that constitutes a part of the other electrode of the capacitor element (C2) and the third electrode that constitutes a part of one electrode of the capacitor element (C2). The distance between the electrodes (MD3) can be made smaller than in the case of the third study example in FIG. 22 and larger than in the case of the fourth study example in FIG. For this reason, in the second embodiment, the capacitance value between the first electrode part (MD1) and the fourth electrode part (MD4) is made larger than in the case of the third study example in FIG. The capacitance value between the electrode part (MD2) and the third electrode part (MD3) can be increased. In the second embodiment, the breakdown voltage and the TDDB life between the first electrode part (MD1) and the fourth electrode part (MD4) can be improved as compared with the case of the third study example in FIG. The breakdown voltage and the TDDB life between the two-electrode part (MD2) and the third electrode part (MD3) can be improved.

  Therefore, in the second embodiment, the first electrode part (MD1), the second electrode part (MD2), the third electrode part (MD3), and the fourth electrode part (MD4) constituting the electrode of the capacitive element (C2). By devising the arrangement position, it is possible to balance the enhancement of the capacitance value of the capacitive element with the enhancement of the reliability by improving the breakdown voltage and the TDDB lifetime, and to achieve both.

  As described above, in the second embodiment, the breakdown voltage of the capacitor can be increased. In addition, the TDDB life of the capacitor can be extended. In addition, the capacitance value of the capacitor can be increased. As a result, the reliability of the semiconductor device having the capacitor can be improved. In addition, the performance of the semiconductor device having a capacitor can be improved. In addition, a semiconductor device having a capacitor can be reduced in size.

  The second embodiment is applied when the voltage (potential difference) applied between the electrodes of the capacitive element C2 (here, between the metal patterns MP1, MP3, MP5 and the metal patterns MP2, MP4, MP6) is high. For example, if applied to a case where a voltage of 12 V or higher is applied between the electrodes of the capacitive element C2, the effect is extremely large.

(Embodiment 3)
<Structure of semiconductor device>
24 to 26 are main part plan views of the semiconductor device according to the third embodiment, and FIG. 27 is a main part sectional view of the semiconductor device according to the third embodiment. 24 to 26 correspond to FIGS. 18 to 20 of the second embodiment, respectively, and show plan views of capacitor formation regions in the semiconductor device of the third embodiment. FIG. 27 corresponds to FIG. 21 of the second embodiment, and shows a cross-sectional view of a capacitor formation region in the semiconductor device of the third embodiment.

  The cross-sectional view of FIG. 27 substantially corresponds to the cross-section at the position of line B4-B4 of FIGS. However, the cross-sectional view of FIG. 27 shows the insulating films IL4, IL5, and IL6 and electrodes embedded therein (electrodes for capacitive elements) in the capacitor formation region, as in FIG. 21, and the insulating film IL3. Further, the illustration of the structure below and the structure above the insulating film IL6 is omitted. In FIG. 27, the insulating films IL4, IL5, and IL6 are not hatched.

  24 to 26 show the same plane region (capacitor formation region here) in the same semiconductor device (semiconductor substrate SB), but the layers shown in FIGS. 24 to 26 are different. Yes. That is, FIG. 24 shows a planar layout of a layer in which the metal patterns MP1 and MP2 are formed (that is, the wiring layer ML3) in the capacitor formation region. FIG. 25 shows a planar layout of a layer in which the metal patterns MP3 and MP4 are formed in the capacitor formation region (that is, the wiring layer ML4). FIG. 26 shows a planar layout of a layer (that is, the wiring layer ML5) on which the metal patterns MP5 and MP6 are formed in the capacitor formation region. 24 to 26 are all plan views, but the metal patterns MP1 to MP6 and the floating electrodes FE3 to FE5 are hatched for easy viewing of the drawings.

  The configuration of the MISFET formation region in the semiconductor device of the third embodiment is the same as that of the first embodiment (FIG. 1) and the second embodiment (FIG. 15). Is omitted.

  In the semiconductor device according to the third embodiment, the MISFET is formed in the MISFET formation region, and the capacitive element C2 is formed in the capacitor formation region which is a different planar region (different planar region of the same semiconductor substrate SB) from the MISFET formation region. Yes. A specific configuration of the capacitor formation region in the semiconductor device according to the third embodiment will be described with reference to FIGS.

  Also in the semiconductor device of the third embodiment, the metal patterns MP1, MP2, MP3, MP4, MP5, and MP6 as described in the second embodiment are formed, but the electrode part MD3 of the metal patterns MP3 and MP4. , MD4 is different between the third embodiment and the second embodiment.

  That is, in the second embodiment, each electrode part MD3 of the metal pattern MP3 is formed in a wiring layer one layer lower than the metal pattern MP3 and is adjacent to the Y direction in the plan view. Between the electrode part MD5 and the electrode part MD6 that are formed in the wiring layer one layer higher than the metal pattern MP3 and adjacent in the Y direction. In the second embodiment, each of the electrode parts MD4 of the metal pattern MP4 is formed in the wiring layer one lower than the metal pattern MP3 and is adjacent to the Y direction in the plan view. Between the electrode part MD5 and the electrode part MD6 that are formed in the wiring layer one layer higher than the metal pattern MP4 and adjacent in the Y direction.

  On the other hand, in the third embodiment, the planar layout of the metal pattern MP1, the planar layout of the metal pattern MP3, and the planar layout of the metal pattern MP5 are the same, and the planar layout of the metal pattern MP2 and the metal pattern MP4. The plane layout of the metal pattern MP6 is the same as the plane layout of the metal pattern MP6. Therefore, in the third embodiment, the electrode part MD1 formed in the wiring layer ML3, the electrode part MD3 formed in the wiring layer ML4, and the electrode part MD5 formed in the wiring layer ML5 overlap in plan view ( (Preferably the same) position (preferably with the same planar dimensions). Further, the electrode part MD2 formed on the wiring layer ML3, the electrode part MD4 formed on the wiring layer ML4, and the electrode part MD6 formed on the wiring layer ML5 overlap (preferably the same) in a plan view (preferably the same). Are arranged in the same plane dimensions). That is, in the third embodiment, each electrode part MD3 of the wiring layer ML4 is in a position that coincides with each electrode part MD1 of the wiring layer ML3 in plan view, and in plan view with each electrode part MD5 of the wiring layer ML5. The electrode portions MD4 of the wiring layer ML4 are arranged at positions that coincide with each electrode portion MD2 of the wiring layer ML3 in plan view, and in plan view with the electrode portions MD6 of the wiring layer ML5. It is arranged at the position that matches.

  In addition, the connecting part MC1 formed in the wiring layer ML3, the connecting part MC3 formed in the wiring layer ML4, and the connecting part MC5 formed in the wiring layer ML5 overlap (preferably the same) in a plan view (preferably the same). The third embodiment is the same as the second embodiment in that they are arranged with the same plane dimensions. Further, the connecting portion MC2 formed in the wiring layer ML3, the connecting portion MC4 formed in the wiring layer ML4, and the connecting portion MC6 formed in the wiring layer ML5 overlap (preferably the same) in a plan view (preferably the same). The third embodiment is the same as the second embodiment in that they are arranged with the same plane dimensions.

  Therefore, in the third embodiment, the metal pattern MP1, the metal pattern MP3, and the metal pattern MP5 are formed in different layers, but overlap (preferably the same) in a plan view (preferably with the same plane size and plane). (In shape). Further, the metal pattern MP2, the metal pattern MP4, and the metal pattern MP6 are arranged at different positions (preferably the same) in a plan view (preferably with the same plane dimensions and shape), although the formed layers are different. It will be.

  In the third embodiment, in the wiring layer (here, the wiring layer ML3) in which the metal patterns MP1 and MP2 are formed, it extends in the X direction between the electrode part MD1 and the electrode part MD2 adjacent in the Y direction. The existing floating electrode FE3 is formed. In addition, in the wiring layer (here, the wiring layer ML4) in which the metal patterns MP3 and MP4 are formed, the floating electrode FE4 extending in the X direction is formed between the electrode part MD3 and the electrode part MD4 adjacent in the Y direction. Has been. Further, in the wiring layer (here, the wiring layer ML5) in which the metal patterns MP5 and MP6 are formed, the floating electrode FE5 extending in the X direction is formed between the electrode part MD5 and the electrode part MD6 adjacent in the Y direction. Has been.

  For this reason, in the wiring layer ML3 in the capacitor formation region, the electrode part MD1 extending in the X direction between the connecting part MC1 extending in the Y direction and the connecting part MC2 extending in the Y direction, and the X direction. The extending floating electrode FE3, the electrode part MD2 extending in the X direction, and the floating electrode FE3 extending in the X direction are repeatedly arranged in this order at predetermined intervals (preferably at equal intervals). Yes. Further, in the wiring layer ML4 in the capacitor formation region, the electrode part MD3 extending in the X direction and the electrode part MD3 extending in the X direction are connected between the connecting part MC3 extending in the Y direction and the connecting part MC4 extending in the Y direction. The existing floating electrode FE4, the electrode part MD4 extending in the X direction, and the floating electrode FE4 extending in the X direction are repeatedly arranged in this order at a predetermined interval (preferably at equal intervals). . Further, in the wiring layer ML5 in the capacitor formation region, the electrode part MD5 extending in the X direction and the electrode part MD5 extending in the X direction between the connecting part MC5 extending in the Y direction and the connecting part MC6 extending in the Y direction. The existing floating electrode FE5, the electrode part MD6 extending in the X direction, and the floating electrode FE5 extending in the X direction are repeatedly arranged in this order at a predetermined interval (preferably at equal intervals). .

  The floating electrode FE3 is formed in the same step as the metal patterns MP1 and MP2, the floating electrode FE4 is formed in the same layer as the metal patterns MP3 and MP4, and the floating electrode FE5 is formed in the metal patterns MP5 and MP6. And in the same layer and in the same process.

  That is, the wiring M3, the metal pattern MP1, the metal pattern MP2, and the floating electrode FE3 are formed in the same layer in the same process using the damascene technique, and the insulating film IL4 (specifically, a groove formed in the insulating film IL4). Embedded in. Therefore, the wiring M3, the metal pattern MP1, the metal pattern MP2, and the floating electrode FE3 are formed by damascene wiring (specifically, damascene wiring embedded in the insulating film IL4).

  Further, the wiring M4, the metal pattern MP3, the metal pattern MP4, and the floating electrode FE4 are formed in the same layer in the same process using the damascene technique, and the insulating film IL5 (specifically, a groove formed in the insulating film IL5). Embedded in. Therefore, the wiring M4, the metal pattern MP3, the metal pattern MP4, and the floating electrode FE4 are formed by damascene wiring (specifically, damascene wiring embedded in the insulating film IL5).

  Further, the wiring M5, the metal pattern MP5, the metal pattern MP6, and the floating electrode FE5 are formed in the same layer in the same process using the damascene technique, and the insulating film IL6 (specifically, a groove formed in the insulating film IL6). Embedded in. Therefore, the wiring M5, the metal pattern MP5, the metal pattern MP6, and the floating electrode FE5 are formed by damascene wiring (specifically, damascene wiring embedded in the insulating film IL6).

  For this reason, the floating electrode FE3, the metal pattern MP1, the metal pattern MP2, and the wiring M3 are made of the same conductive material, and the floating electrode FE4, the metal pattern MP3, the metal pattern MP4, and the wiring M4 are made of the same conductive material, and the floating electrode FE5. The metal pattern MP5, the metal pattern MP6, and the wiring M5 are made of the same conductive material.

  The bottom surface of the floating electrode FE3 is located in the middle of the thickness of the insulating film IL4, and the height position of the bottom surface of the floating electrode FE3 and the height position of the bottom surfaces of the metal patterns MP1 and MP2 are substantially the same. The bottom surface of the floating electrode FE4 is located in the middle of the thickness of the insulating film IL5. The height position of the bottom surface of the floating electrode FE4 and the height position of the bottom surfaces of the metal patterns MP3 and MP4 are substantially the same. is there. Further, the bottom surface of the floating electrode FE5 is located in the middle of the thickness of the insulating film IL6, and the height position of the bottom surface of the floating electrode FE5 and the height position of the bottom surfaces of the metal patterns MP5 and MP6 are substantially the same. is there.

  The floating electrode FE3 is formed in the same layer as the metal patterns MP1 and MP2, but is not connected to any of the metal patterns MP1 and MP2. The floating electrode FE4 is formed in the same layer as the metal patterns MP3 and MP4, but is not connected to any of the metal patterns MP3 and MP4. The floating electrode FE5 is formed in the same layer as the metal patterns MP5 and MP6, but is not connected to any of the metal patterns MP5 and MP6. Therefore, the floating electrode FE3 is not connected to any of the metal patterns MP1, MP2, MP3, MP4, MP5, and MP6 by a conductor, and the floating electrode FE4 is formed of the metal patterns MP1, MP2, MP3, MP4, MP5, and MP6. None of them are connected by a conductor, and the floating electrode FE5 is not connected by a conductor to any of the metal patterns MP1, MP2, MP3, MP4, MP5, and MP6. That is, each floating electrode FE3 is an isolated pattern extending in the X direction, each floating electrode FE4 is an isolated pattern extending in the X direction, and each floating electrode FE5 extends in the X direction. It is an isolated pattern. Further, the floating electrode FE3, the floating electrode FE4, and the floating electrode FE5 are not connected by a conductor.

  Each of the floating electrodes FE3, FE4, and FE5 is set to a floating potential. That is, each of the floating electrodes FE3, FE4, and FE5 is in an electrically floating state (floating state).

  The other configuration of the semiconductor device according to the third embodiment is substantially the same as that of the second embodiment, and thus the repeated description thereof is omitted here.

  Therefore, also in the third embodiment, the metal patterns MP1, MP3, and MP5 function as one electrode of the capacitive element C2, and the metal patterns MP2, MP4, and MP6 function as the other electrode of the capacitive element C2. The point that the insulating films (IL4, IL5, IL6) between the MP1, MP3, MP5 and the metal patterns MP2, MP4, MP6 function as capacitive insulating films is the same as in the second embodiment.

  However, the third embodiment is different from the second embodiment in that floating electrodes FE3, FE4, and FE5 are formed. In the third embodiment, the floating electrodes FE3 are formed in the same layer as the metal patterns MP1 and MP2 between the electrode portions MD1 of the metal pattern MP1 and the electrode portions MD2 of the metal pattern MP2. Further, in the same layer as the metal patterns MP3 and MP4, floating electrodes FE4 are formed between the electrode parts MD3 of the metal pattern MP3 and the electrode parts MD4 of the metal pattern MP4, respectively. Further, in the same layer as the metal patterns MP5 and MP6, floating electrodes FE5 are formed between the electrode parts MD5 of the metal pattern MP5 and the electrode parts MD6 of the metal pattern MP6, respectively.

<Main features and effects>
The semiconductor device according to the third embodiment is formed in a semiconductor substrate SB, a wiring structure (multilayer wiring structure) formed on the semiconductor substrate SB and including a plurality of wiring layers, and the wiring structure (multilayer wiring structure). A semiconductor device having a capacitor (C2). And it has the 1st metal pattern and 2nd metal pattern which were formed in the 1st wiring layer among the several wiring layers of a wiring structure (multilayer wiring structure). The metal pattern MP1 corresponds to the first metal pattern, and the metal pattern MP2 corresponds to the second metal pattern.

  The first metal pattern (MP1) extends in the X direction (first direction) and has a plurality of first electrode portions (second direction) arranged in the Y direction (second direction) intersecting the X direction in plan view. Corresponding to the electrode part MD1). The second metal pattern (MP2) includes a plurality of second electrode portions (corresponding to the electrode portions MD2) extending in the X direction and arranged in the Y direction in plan view. The first electrode part (MD1) and the second electrode part (MD2) are alternately arranged in the Y direction. The first metal pattern (MP1) forms one electrode of the capacitive element (C2), and the second metal pattern (MP2) forms the other electrode of the capacitive element (C2).

  The metal pattern MP3 may correspond to the first metal pattern, and the metal pattern MP4 may correspond to the second metal pattern. In this case, the first electrode portion corresponds to the electrode portion MD3. The second electrode portion corresponds to the electrode portion MD4. Alternatively, it can be considered that the metal pattern MP5 corresponds to the first metal pattern and the metal pattern MP6 corresponds to the second metal pattern, in which case the first electrode portion corresponds to the electrode portion MD5. The second electrode portion corresponds to the electrode portion MD6.

  One of the main features of the third embodiment is that in the wiring layer in which the first metal pattern (MP1) and the second metal pattern (MP2) are formed, the first electrode portion (MD1) adjacent in the Y direction. ) And the second electrode part (MD2), the floating electrode (FE3) is formed.

  Unlike the third embodiment, it is assumed that the formation of the floating electrodes FE3, FE4, and FE5 is omitted. In this case, since different potentials are applied to the electrode part MD1 of the metal pattern MP1 and the electrode part MD2 of the metal pattern MP2, the distance between the electrode part MD1 of the metal pattern MP1 and the electrode part MD2 of the metal pattern MP2 Is small, the withstand voltage and the TDDB life between the electrode part MD1 of the metal pattern MP1 and the electrode part MD2 of the metal pattern MP2 are reduced. For this reason, in order to improve the withstand voltage and the TDDB life between the metal pattern MP1 and the metal pattern MP1, the interval between the electrode part MD1 of the metal pattern MP1 and the electrode part MD2 of the metal pattern MP2 is increased, It is effective to increase the thickness of the insulating film in the part interposed between the electrode part MD1 and the electrode part MD2. However, increasing the distance between the electrode part MD1 and the electrode part MD2 without forming the floating electrode FE3 adversely affects the accurate formation of the metal patterns MP1 and MP2. This is because the accuracy of photolithography (the accuracy with which a photoresist pattern is formed as designed by exposure / development) decreases when the interval (pitch) between the repeated patterns increases when photolithography technology is used to form the repeated patterns. It is because it is easy to do.

  In order to form the metal patterns MP1 and MP2, after forming the insulating film IL4, a photoresist pattern is formed on the insulating film IL4 by using a photolithography technique, and this photoresist pattern is used as an etching mask. By etching the insulating film IL4, grooves for embedding the metal patterns MP1 and MP2 are formed in the insulating film IL4. Then, after forming a conductive film (conductive film for forming the wiring M3 and the metal patterns MP1 and MP2) on the insulating film IL4 so as to fill the groove, the conductive film outside the groove is removed, thereby forming the groove. Metal patterns MP1 and MP2 made of an embedded conductive film can be formed.

  When the metal patterns MP1 and MP2 are formed, the electrode portions MD1 and the electrode portions MD2 are alternately arranged. If the arrangement interval (arrangement pitch) between the electrode portions MD1 and the electrode portions MD2 is large, the metal patterns MP1 and MP2 are arranged. There is a possibility that the accuracy of photolithography when forming a trench for embedding in the insulating film IL4 is lowered. This makes it difficult to manage the manufacturing process of the semiconductor device having the capacitive element, and may reduce the reliability of the semiconductor device having the capacitive element.

  On the other hand, in the third embodiment, the floating electrodes FE3 are formed in the same layer as the metal patterns MP1 and MP2 between the electrode portions MD1 of the metal pattern MP1 and the electrode portions MD2 of the metal pattern MP2. ing. Since the floating electrode FE3 is arranged between the electrode part MD1 and the electrode part MD2, the electrode parts (electrode parts MD1, MD1 extending in the X direction and arranged in the Y direction are compared to the case where the floating electrode FE3 is not arranged. The arrangement interval (arrangement pitch) of the electrode part MD2 and the floating electrode FE3) can be reduced. Therefore, it is possible to improve the accuracy of photolithography when forming the trench for embedding the metal patterns MP1 and MP2 and the floating electrode FE3 in the insulating film IL4. This facilitates management of the manufacturing process of the semiconductor device having the capacitive element. In addition, the reliability of the semiconductor device having a capacitor can be improved.

  For example, in the case where the floating electrode FE3 is formed (corresponding to the third embodiment) and the case where the floating electrode FE3 is not formed, an effective portion of the insulating film interposed between the electrode part MD1 and the electrode part MD2 is effective. It is assumed that the thicknesses are the same (thus, the capacitance values between the metal pattern MP1 and the metal pattern MP2 are the same). At this time, when the floating electrode FE3 is formed (corresponding to the third embodiment), the distance between the electrode part MD1 and the floating electrode FE3 and the distance between the electrode part MD2 and the floating electrode FE3 are totaled. This is the same as the distance between the electrode part MD1 and the electrode part MD2 when the floating electrode FE3 is not formed. That is, when it is assumed that the effective thickness of the insulating film in the portion interposed between the electrode part MD1 and the electrode part MD2 is the same, the floating electrode FE3 is formed compared to the case where the floating electrode FE3 is not formed. In the case (corresponding to the third embodiment), the arrangement interval of the repetitive patterns (corresponding to the electrode part MD1, the electrode part MD2, and the floating electrode FE3) can be reduced. For example, the arrangement interval can be halved. For this reason, in the case of the third embodiment in which the floating electrode FE3 is formed, it is possible to improve the accuracy of photolithography when the trenches for embedding the metal patterns MP1 and MP2 and the floating electrode FE3 are formed in the insulating film IL4. it can.

  The same can be said for the metal patterns MP3 and MP4 and the floating electrode FE4, and also for the metal patterns MP5 and MP6 and the floating electrode FE5.

  As described above, in the third embodiment, even if the interval between the electrode part MD1 and the electrode part MD2 is increased in order to improve the breakdown voltage and the TDDB life, the floating electrode FE3 is interposed between the electrode part MD1 and the electrode part MD2. It becomes easy to form the metal patterns MP1 and MP2 accurately. Similarly, even if the gap between the electrode part MD3 and the electrode part MD4 is increased in order to improve the breakdown voltage and the TDDB life, the floating electrode FE4 is provided between the electrode part MD3 and the electrode part MD4. It becomes easy to form MP3 and MP4 accurately. Even if the gap between the electrode part MD5 and the electrode part MD6 is increased in order to improve the withstand voltage and the TDDB life, the metal pattern MP5 is obtained by providing the floating electrode FE5 between the electrode part MD5 and the electrode part MD6. , MP6 can be easily formed accurately.

  Therefore, in the third embodiment, the reliability of the semiconductor device is improved by improving the withstand voltage and the TDDB life, the semiconductor device is easily manufactured accurately, and the manufacturing process of the semiconductor device having the capacitor element is managed. Can be easily.

  In the third embodiment, the capacitive element C2 is formed using three continuous wiring layers. That is, the metal patterns MP1 and MP2 are formed in any one of the plurality of wiring layers of the multilayer wiring structure formed on the semiconductor substrate SB, and the metal patterns MP1 and MP2 are formed in the wiring pattern 1 in the wiring layer. Metal patterns MP3 and MP4 are formed in the upper wiring layer, and metal patterns MP5 and MP6 are formed in the wiring layer one layer higher than the wiring layer in which the metal patterns MP3 and MP4 are formed. The metal patterns MP1 to MP6 are not limited to being formed on the wiring layers ML3 to ML5, and the metal patterns MP1 to MP6 can be formed on the other three consecutive wiring layers.

  As another form, the formation of the metal patterns MP5 and MP6 can be omitted, and the capacitive element C2 can be formed by the metal patterns MP1, MP2, MP3 and MP4, or the formation of the metal patterns MP1 and MP2 can be omitted. The capacitive element C2 can also be formed by the metal patterns MP3, MP4, MP5, and MP6. Alternatively, the formation of the metal patterns MP3, MP4, MP5, and MP6 can be omitted, and the capacitor element C2 can be formed by the metal patterns MP1 and MP2, or the formation of the metal patterns MP1, MP2, MP5, and MP6 can be omitted. Thus, the capacitive element C2 can be formed by the metal patterns MP3 and MP4. Alternatively, the formation of the metal patterns MP1, MP2, MP3, and MP4 can be omitted, and the capacitive element C2 can be formed of the metal patterns MP5 and MP6.

  As another form, the number of wiring layers for forming the comb-shaped metal pattern for the electrode of the capacitive element C2 may be four or more. In the case of four layers, the same pattern as the metal patterns MP5 and MP6 and the floating electrode FE5 may be provided in the wiring layer one layer higher than the wiring layer in which the metal patterns MP5 and MP6 and the floating electrode FE5 are formed.

  That is, the capacitive element C2 of the third embodiment has a basic structure of comb-shaped metal patterns MP1 and MP2 and a floating electrode FE3, and the basic structure may be stacked.

(Embodiment 4)
The fourth embodiment corresponds to the case where the third embodiment is applied to the semiconductor device of the second embodiment.

  28 to 30 are main part plan views of the semiconductor device according to the fourth embodiment, and FIG. 31 is a main part sectional view of the semiconductor device according to the fourth embodiment. 28 to 30 correspond to FIGS. 18 to 20 of the second embodiment, respectively, and show plan views of capacitor formation regions in the semiconductor device of the fourth embodiment. FIG. 31 corresponds to FIG. 21 of the second embodiment, and shows a cross-sectional view of a capacitor formation region in the semiconductor device of the fourth embodiment. 31 substantially corresponds to the cross section taken along the line B5-B5 in FIGS. In FIG. 31, hatching is omitted for the insulating films IL4, IL5, and IL6, and FIGS. 28 to 30 are all plan views, but in order to make the drawing easy to see, metal patterns MP1 to MP6 and The floating electrodes FE3 to FE5 are hatched.

  The semiconductor device according to the fourth embodiment is substantially the same as the semiconductor device according to the second embodiment except that floating electrodes FE3, FE4, and FE5 are added. Here, the difference from the second embodiment is described here. The explanation is centered.

  In the fourth embodiment, in the semiconductor device in the third embodiment, the floating electrode FE3 is added to the wiring layer (here, the wiring layer ML3) on which the metal patterns MP1 and MP2 are formed, and the metal patterns MP3 and MP4 are formed. The floating electrode FE4 is added to the wiring layer (here, the wiring layer ML4), and the floating electrode FE5 is added to the wiring layer (here, the wiring layer ML5) on which the metal patterns MP5 and MP6 are formed. Since the floating electrodes FE3, FE4, and FE5 are the same as those described in the third embodiment, repeated description thereof is omitted here.

  Briefly, in the wiring layer in which the metal patterns MP1 and MP2 are formed, the floating electrode FE3 extending in the X direction is formed between the electrode part MD1 and the electrode part MD2 adjacent in the Y direction. Further, in the wiring layer in which the metal patterns MP3 and MP4 are formed, the floating electrode FE4 extending in the X direction is formed between the electrode part MD3 and the electrode part MD4 adjacent in the Y direction. Further, in the wiring layer in which the metal patterns MP5 and MP6 are formed, the floating electrode FE5 extending in the X direction is formed between the electrode part MD5 and the electrode part MD6 adjacent in the Y direction.

  In the fourth embodiment, in addition to the effects obtained in the second embodiment, the effects described in the third embodiment can also be obtained.

(Embodiment 5)
In the fifth embodiment, an example of the manufacturing process of the semiconductor device of the first to fourth embodiments will be described.

  32 to 47 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the fifth embodiment. 32 to 47 show cross-sectional views of regions corresponding to the MISFET formation regions shown in FIG. 1 and FIG.

  First, as shown in FIG. 32, a semiconductor substrate (semiconductor wafer) SB made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared.

  Next, the element isolation region ST is formed in the semiconductor substrate SB. The element isolation region ST can be formed by an STI (Shallow Trench Isolation) method.

  Next, as shown in FIG. 33, a semiconductor element such as MISFET Q1 is formed on the semiconductor substrate SB. The MISFET Q1 can be formed as follows, for example.

  That is, the p-type well region PW is formed in the semiconductor substrate SB using an ion implantation method or the like. Then, the gate electrode GE is formed on the p-type well region PW via the gate insulating film GI. For example, the gate electrode GE and the gate insulating film GI are formed by sequentially forming an insulating film for the gate insulating film GI and a conductive film for the gate electrode GE on the main surface of the semiconductor substrate SB and then patterning them. be able to. Then, an n-type semiconductor region SD for source / drain formed in the p-type well region PW is formed by ion implantation. In this way, the MISFET Q1 is formed. By forming a sidewall spacer on the sidewall of the gate electrode GE, the n-type semiconductor region SD can also have an LDD structure. In addition, metal silicide layers (not shown) can be formed on the surfaces (surface layer portions) of the gate electrode GE and the n-type semiconductor region SD by salicide technology or the like.

  Next, as shown in FIG. 34, over the entire main surface of the semiconductor substrate SB, an insulating film (interlayer insulating film) IL1 is formed by CVD (Chemical Vapor Deposition) so as to cover the gate electrode GE. It is formed using a method or the like. After the insulating film IL1 is formed, the upper surface (front surface) of the insulating film IL1 can be planarized by polishing the upper surface (surface) of the insulating film IL1 by a CMP method.

  Next, as shown in FIG. 35, a photoresist pattern (not shown) is formed on the insulating film IL1 using a photolithography method, and the insulating film IL1 is etched using the photoresist pattern as an etching mask. Then, a contact hole CT is formed in the insulating film IL1.

  Next, a plug PG is formed in the contact hole CT. To form the plug PG, first, a conductive barrier film (for example, a titanium film, a titanium nitride film, or a laminated film thereof) is sputtered on the insulating film IL1 including the inside (on the bottom and side walls) of the contact hole CT. Then, a main conductor made of a tungsten (W) film or the like is formed so as to fill the contact hole CT on the conductive barrier film by a CVD method or the like. Then, the unnecessary main conductor film and conductive barrier film outside the contact hole CT are removed by a CMP method or an etch back method. As a result, the plug PG composed of the main conductor film and the conductive barrier film embedded and remaining in the contact hole CT can be formed. For simplification of the drawing, in FIG. 35, the barrier conductor film and the main conductor film constituting the plug PG are shown integrally.

  Next, as illustrated in FIG. 36, the insulating film IL2 is formed over the insulating film IL1 in which the plug PG is embedded.

  Next, a first layer wiring is formed by a single damascene method. First, as shown in FIG. 37, a photoresist pattern PR1 is formed on the insulating film IL2 by using a photolithography method, and then the insulating film IL2 is etched by using the photoresist pattern PR1 as an etching mask. A trench (opening) TR1 is formed in the film IL2. Then, a barrier conductor film (barrier metal film) is formed on the main surface of the semiconductor substrate SB (that is, on the insulating film IL2 including the bottom and side walls of the trench TR1). As the barrier conductor film, for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like can be used. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film (main conductor film) is further formed on the seed layer by using an electrolytic plating method. The trench TR1 is filled with a film. In FIG. 38, the copper plating film, the seed layer, and the barrier conductor film are shown together as a conductive film CD1, and the conductive film CD1 is formed on the insulating film IL2 so as to fill the trench TR1. Then, the copper plating film, the seed layer, and the barrier conductor film (that is, the conductive film CD1) in the region other than the trench TR1 are removed by the CMP method, and the copper plating film, the seed layer, and the barrier conductor film (that is, the conductive film) in the trench TR1. By leaving CD1), as shown in FIG. 39, the first layer wiring M1 having copper as the main conductive material is formed in the trench TR1. For simplification of the drawing, in FIG. 39, the copper plating film, the seed layer, and the barrier conductor film constituting the wiring M1 are shown in an integrated manner.

  Next, as shown in FIG. 40, an insulating film (interlayer insulating film) IL3 is formed over the insulating film IL2 in which the wiring M1 is embedded.

  Next, a second layer wiring M2 and a via portion V2 are formed by a dual damascene method. The wiring formation process by the dual damascene method can be performed as follows, for example.

  The insulating film IL3 can be formed, for example, as a stacked film of a barrier insulating film IL3a, an insulating film (interlayer insulating film) IL3b on the barrier insulating film IL3a, and an insulating film (CMP protective film) IL3c on the insulating film IL3b. .

  The barrier insulating film IL3a is made of, for example, a SiCN film, a SiCO film, or a laminated film thereof, and can be formed by, for example, a CVD method. The barrier insulating film (for example, the barrier insulating film IL3a) is formed between a wiring mainly composed of copper (for example, the wiring M1) and an interlayer insulating film (for example, the insulating film IL3b), and metal ions (particularly copper ions) in the wiring are formed. ) Is a film having a function of preventing diffusion into the interlayer insulating film.

  The insulating film IL3b is an interlayer insulating film, and can be, for example, a low dielectric constant insulating film (so-called Low-k insulating film or Low-k film) made of a low dielectric constant material (so-called Low-k material). The film thickness of the insulating film IL3b is thicker than each film thickness of the barrier insulating film IL3a and the insulating film IL3c.

  The insulating film IL3c functions as a CMP protective film, and can be a silicon oxide film, for example. The formation of the insulating film IL3c can be omitted if unnecessary.

  Note that examples of the low dielectric constant insulating film (Low-k insulating film, Low-k film) include an insulating film having a dielectric constant lower than that of a silicon oxide film (eg, TEOS (Tetraethoxysilane) oxide film).

  After the formation of the insulating film IL3, as shown in FIG. 41, a photoresist pattern PR2 is formed on the insulating film IL3 by using a photolithography method. The photoresist pattern PR2 has an opening in a region where the via portion V2 is to be formed. Then, the via holes (openings) VH1 are formed in the insulating films IL3c and IL3b by etching the insulating films IL3c and IL3b using the photoresist pattern PR2 as an etching mask. The via hole VH1 penetrates the insulating films IL3c and 3b, but it is preferable that the barrier insulating film IL3a is exposed at the bottom of the via hole VH1 without penetrating the barrier insulating film IL3a.

  Next, after removing the photoresist pattern PR2, as shown in FIG. 42, a photoresist pattern PR3 is formed on the insulating film IL3 by using a photolithography method. The photoresist pattern PR3 has an opening in a region where the wiring M2 is to be formed. Then, using the photoresist pattern PR3 as an etching mask, the insulating film IL3c is etched to pattern the insulating film IL3c into the same pattern (planar shape) as the photoresist pattern PR3. Thereafter, the photoresist pattern PR3 is removed, and this stage is shown in FIG.

  Next, as shown in FIG. 44, the upper surface of the wiring M1 is exposed at the bottom of the via hole VH1 by removing the barrier insulating film IL3a exposed at the bottom of the via hole VH1 by an etch back method (anisotropic etching). Let In the etch back process at this time, since the patterned insulating film IL3c functions as an etching mask (hard mask), a part of the insulating film IL3b exposed from the patterned insulating film IL3c is also etched to form the trench TR2. Is formed. The bottom of the trench TR2 is located in the middle of the thickness of the insulating film IL3b. The via hole VH1 is formed at a position included in the trench TR2 in plan view. When the insulating film IL3c is not formed, the photoresist pattern PR3 can also be used as an etching mask in this etch back process.

  Next, a barrier conductor film (barrier metal film) is formed on the main surface of the semiconductor substrate SB (that is, on the insulating film IL3 including the trench TR2 and the bottom and side walls of the via hole VH1). As the barrier conductor film, for example, a titanium nitride film, a tantalum film, a tantalum nitride film, or the like can be used. Subsequently, a copper seed layer is formed on the barrier conductor film by a CVD method or a sputtering method, and a copper plating film (main conductor film) is further formed on the seed layer by using an electrolytic plating method. The trench TR2 and the via hole VH1 are filled with the film. In FIG. 45, the copper plating film, the seed layer, and the barrier conductor film are shown together as a conductive film CD2, and the conductive film CD2 is formed on the insulating film IL3c so as to fill the trench TR2 and the via hole VH1. . Then, the copper plating film, the seed layer, and the barrier conductor film (that is, the conductive film CD2) in the region other than the trench TR2 and the via hole VH1 are removed by CMP, and the copper plating film, the seed layer, and the barrier are disposed in the trench TR2 and the via hole VH1. The conductor film (namely, conductive film CD2) is left. As a result, as shown in FIG. 46, the insulating film IL3 is exposed, the copper plating film, the seed layer, and the barrier conductor film are buried in the trench TR2 to form the wiring M2, and the via hole VH1 is plated with copper. The via, V2 is formed by embedding the film, seed layer and barrier conductor film. The via portion V2 is formed integrally with the wiring M2. For simplification of the drawing, in FIG. 46, the copper plating film, the seed layer, and the barrier conductor film constituting the wiring M2 and the via portion V2 are shown in an integrated manner. The insulating film IL3c is provided to protect the semiconductor device during the manufacturing process from the polishing pressure or scratch damage by the CMP method at this time, and is removed in the CMP process at this time. For this reason, when the wiring M2 and the via portion V2 are formed, the upper surface of the insulating film IL3b is exposed, and the wiring M2 and the via portion V2 are formed on the insulating film IL3 formed of the laminated film of the barrier insulating film IL3a and the insulating film IL3b thereon. It becomes an embedded state.

  Here, the case of the via first manufacturing method in which the trench TR2 is formed after the via hole VH1 is formed in the insulating film IL3 has been described. As another form, a trench-first manufacturing method in which the via hole VH1 is formed after the trench TR2 is formed in the insulating film IL3 can also be used.

  Next, as shown in FIG. 47, after an insulating film (interlayer insulating film) IL4 is formed on the insulating film IL3 in which the wiring M2 is embedded, a third layer is formed on the insulating film IL4 by a dual damascene method. An eye wiring M3 and a via portion V3 are formed. Then, after an insulating film (interlayer insulating film) IL5 is formed on the insulating film IL4 in which the wiring M3 is embedded, the fourth layer wiring M4 and the via portion V4 are formed on the insulating film IL5 by a dual damascene method. Form. Then, after an insulating film (interlayer insulating film) IL6 is formed on the insulating film IL5 in which the wiring M4 is embedded, the fifth-layer wiring M5 and the via portion V5 are formed on the insulating film IL6 by a dual damascene method. Form. The formation method of the wiring M3 and the via portion V3, the formation method of the wiring M4 and the via portion V4, and the formation method of the wiring M5 and the via portion V5 are basically the same as the above-described formation method of the wiring M2 and the via portion V2, respectively. Since they are the same, repeated description thereof is omitted here.

  On the insulating film IL6 in which the wiring M5 is embedded, an upper insulating film, wiring, bonding pad, uppermost protective film, and the like are further formed as necessary, but illustration and description thereof are omitted here.

  In this way, the semiconductor devices of the first to fourth embodiments can be manufactured.

  In the case of the first embodiment, when the lower electrode LE is formed in the same layer as the wiring M1, the lower electrode LE is also formed in the process of forming the wiring M1. That is, when the trench TR1 is formed in the insulating film IL2, the trench TR1 for the wiring M1 and the trench TR1 (or opening) for the lower electrode LE are formed, and the barrier conductor film, the seed layer, and the copper are formed in the trench TR1. By embedding the plating film (that is, the conductive film CD1), the wiring M1 and the lower electrode LE can be formed. Further, when the floating electrode FE is formed in the same layer as the wiring M2, the floating electrode FE is also formed together in the process of forming the wiring M2. That is, when forming the trench TR2 in the insulating film IL3, the trench TR2 for the wiring M2 and the trench TR2 (or opening) for the floating electrode FE are formed, and the barrier conductor film, the seed layer, and the copper are formed in the trench TR2. By embedding the plating film (that is, the conductive film CD2), the wiring M2 and the floating electrode FE can be formed. Further, when the upper electrode UE is formed in the same layer as the wiring M3, the upper electrode UE is also formed together in the step of forming the wiring M3. That is, when forming a groove in the insulating film IL4, a groove for the wiring M3 and a groove (or opening) for the upper electrode UE are formed, and a barrier conductor film, a seed layer, and a copper plating film (that is, a groove) By embedding the conductive film CD2), the wiring M3 and the upper electrode UE can be formed.

  In the case of the second embodiment, when the metal patterns MP1 and MP2 are formed in the same layer as the wiring M3, the metal patterns MP1 and MP2 are also formed together in the process of forming the wiring M3. That is, when the groove is formed in the insulating film IL4, a groove for the wiring M3, a groove for the metal pattern MP1, and a groove for the metal pattern MP2 are formed, and a barrier conductor film, a seed layer, and a copper plating film are formed in the groove. By embedding (that is, the conductive film CD2), the wiring M3, the metal pattern MP1, and the metal pattern MP2 can be formed. Similarly, in the process of forming the wiring M4, the metal patterns MP3 and MP4 can be formed together, and in the process of forming the wiring M5, the metal patterns MP5 and MP6 can be formed together.

  In the case of the third and fourth embodiments, when the metal patterns MP1 and MP2 and the floating electrode FE3 are formed in the same layer as the wiring M3, the metal patterns MP1 and MP2 and the floating electrode FE3 are together in the process of forming the wiring M3. To form. That is, when the groove is formed in the insulating film IL4, a groove for the wiring M3, a groove for the metal pattern MP1, a groove for the metal pattern MP2, and a groove for the floating electrode FE3 are formed, and the barrier conductor film is formed in the groove. By embedding the seed layer and the copper plating film (that is, the conductive film CD2), the wiring M3, the metal pattern MP1, the metal pattern MP2, and the floating electrode FE3 can be formed. Similarly, in the process of forming the wiring M4, the metal patterns MP3 and MP4 and the floating electrode FE4 are formed together, and in the process of forming the wiring M5, the metal patterns MP5 and MP6 and the floating electrode FE5 are formed together. Can do.

(Embodiment 6)
The sixth embodiment corresponds to a preferred configuration example of the insulating film in the wiring layer in which the capacitive elements C1 and C2 are formed in the semiconductor devices of the first to fourth embodiments.

  FIG. 48 is a main-portion cross-sectional view showing the wiring layer in which the wiring MM is formed, and shows the wiring MM and the via portion VV embedded in the insulating film IL. The wiring MM and the via portion VV are formed using a damascene method. For this reason, the wiring MM is a damascene wiring, which is a buried wiring embedded in an insulating film. Further, since the wiring MM is mainly made of copper, it is a damascene copper wiring, which is a buried copper wiring embedded in an insulating film. When the dual damascene method is used, the wiring MM and the via portion VV are integrally formed, and when the single damascene method is used, the wiring MM and the via portion VV are formed separately. The via portion VV is a connecting conductor portion that is located between the wiring MM and a wiring (not shown here) lower than the wiring MM and electrically connects them.

  When the wiring MM corresponds to the wiring M2, the via portion VV corresponds to the via portion V2, and the insulating film IL corresponds to the insulating film IL3. When the wiring MM corresponds to the wiring M3, the via portion VV corresponds to the via portion V3, and the insulating film IL corresponds to the insulating film IL4. When the wiring MM corresponds to the wiring M4, the via portion VV corresponds to the via portion V4, and the insulating film IL corresponds to the insulating film IL5. When the wiring MM corresponds to the wiring M5, the via portion VV corresponds to the via portion V5, and the insulating film IL corresponds to the insulating film IL6.

  The insulating film IL is a laminated film of a barrier insulating film BR corresponding to the barrier insulating film IL3a and an interlayer insulating film SZ formed on the barrier insulating film BR. The interlayer insulating film SZ corresponds to the insulating film IL3b. The interlayer insulating film SZ has a two-layer structure (laminated structure) including a lower insulating layer SZ1 and an upper insulating layer SZ2 on the lower insulating layer SZ1.

  The via part VV is formed in the barrier insulating film BR and the lower insulating layer SZ1. That is, a via hole (through hole, opening) VH is formed so as to penetrate the barrier insulating film BR and the lower insulating layer SZ1 on the barrier insulating film BR, and the via portion VV is embedded in the via hole VH. Yes. That is, the barrier insulating film BR and the lower insulating layer SZ1 are formed in a region having the same height as the via portion VV. In other words, the lower insulating layer SZ1 is formed between a plurality of adjacent via portions VV.

  The wiring MM is formed in the upper insulating layer SZ2. That is, a trench (a trench for wiring, an opening) TR is formed in the upper insulating layer SZ2, and the wiring MM is embedded in the trench TR. That is, the upper insulating layer SZ2 is formed in a region having the same height as the wiring MM. In other words, the upper insulating layer SZ2 is formed between a plurality of adjacent wirings MM.

  Accordingly, the upper insulating layer SZ2 is formed on the lower insulating layer SZ1, the upper insulating layer SZ2 is formed above the lower surface of the wiring MM, and the lower insulating layer SZ1 is formed below the lower surface of the wiring MM.

  When a multilayer wiring structure is formed, the parasitic capacitance between wirings becomes a problem not only between wirings in different layers but mainly between wirings in the same layer. For this reason, it is preferable that the wiring is embedded in an insulating film having a low dielectric constant among the wiring and the via portion, whereby parasitic capacitance between wirings in the same layer can be reduced. For this reason, it is preferable that the dielectric constant of the upper insulating layer SZ2 in which the wiring MM is embedded is low, thereby reducing the parasitic capacitance between the adjacent wirings MM in the same layer.

  On the other hand, even if the insulating film in which the via portion is embedded has a high dielectric constant, it does not contribute much to the parasitic capacitance between the wirings, and does not increase the parasitic capacitance. For this reason, even if the dielectric constant of the lower insulating layer SZ1 and the barrier insulating film BR in which the via portion VV is embedded is not likely to increase the parasitic capacitance between the wirings.

  Therefore, in the sixth embodiment, in the insulating film (here, the insulating film IL) in which the wiring MM and the via portion VV are embedded, the lower insulating layer (here, the lower insulating layer SZ1 and the insulating layer IL) in which the via portion VV is embedded. The dielectric constant of the upper insulating layer (here, the upper insulating layer SZ2) in which the wiring MM is embedded is made lower than the dielectric constant of the barrier insulating film BR). That is, the dielectric constant of the upper insulating layer SZ2 that is the insulating layer in which the wiring MM is embedded is made lower than the dielectric constant of the lower insulating layer SZ1 that is the insulating layer in which the via portion VV is embedded and the barrier insulating film BR. In other words, the dielectric constants of the lower insulating layer SZ1 and the barrier insulating film BR, which are the insulating layers in which the via portions VV are embedded, than the dielectric constant of the upper insulating layer SZ2, which is the insulating layer in which the wiring MM is embedded. To increase.

  By reducing the dielectric constant of the upper insulating layer SZ2, which is an insulating layer in which the wiring MM is embedded, it is possible to reduce the parasitic capacitance between the adjacent wirings MM in the same layer. Thereby, the performance of the semiconductor device can be improved.

  Increasing the dielectric constant of the insulating layer (here, the lower insulating layer SZ1 and the barrier insulating film BR) in which the via portion VV is embedded means that the insulating layer (here, the lower insulating layer SZ1 and the barrier insulating layer) in which the via portion VV is embedded is used. When a capacitor element using the film BR) as a capacitor insulating film is formed, the capacitor element acts to increase the capacitance value of the capacitor element. In the first to fourth embodiments (particularly, the first, second, and fourth embodiments), an insulating layer in which a via portion is embedded is used as a capacitive insulating film of a capacitive element. Therefore, it is more preferable to apply the wiring layer of the sixth embodiment (FIG. 48) to the first to fourth embodiments (particularly, the first, second, and fourth embodiments).

  That is, in the first to fourth embodiments (particularly, the first, second, and fourth embodiments), the dielectric of the interlayer insulating film in which the wiring and via portions are embedded in the wiring layer that forms the capacitive element (C1, C2). It is preferable that the rate is different between the upper layer side where the wiring is formed and the lower layer side where the via portion is formed, and the upper layer side has a lower dielectric constant than the lower layer side. Thereby, the capacitance value of the capacitive elements (C1, C2) can be increased while suppressing the parasitic capacitance between the wirings. In addition, since the area occupied by the capacitor element can be reduced, it is advantageous for downsizing (smaller area) of the semiconductor device.

  That is, when the sixth embodiment (FIG. 48) is applied to the first embodiment (FIGS. 1 and 8), the wiring layer in which the floating electrode FE is formed and the wiring layer in which the upper electrode UE is formed. In addition, it is preferable to apply the wiring layer of the sixth embodiment (FIG. 48). That is, in FIGS. 1 and 8, the insulating film IL3 of the sixth embodiment is applied to the insulating film IL3 in which the floating electrode FE is embedded, and the insulating film IL4 in which the upper electrode UE is embedded is applied to the insulating film IL4. It is preferable to apply the insulating film IL of the sixth embodiment. Thereby, in each of the insulating films IL3 and IL4 in FIG. 1 and FIG. 8, the dielectric constant of the layer (here, the upper insulating layer SZ2) in which the damascene wiring (the wiring M1 or the wiring M2) is embedded is the damascene wiring. The dielectric constant of the layer (here, the lower insulating layer SZ1 and the barrier insulating film BR) in which the via portion (the via portion V2 or the via portion V3) connected to is buried is lower.

  In this case, the floating electrode FE is embedded in the upper insulating layer SZ2 in the insulating film IL applied to the insulating film IL3, and the upper electrode UE is in the upper insulating layer SZ2 in the insulating film IL applied to the insulating film IL4. Embedded state. Therefore, it is the barrier insulating film BR and the lower insulating layer SZ1 that functions as a capacitive insulating film by interposing between the lower electrode LE and the floating electrode FE, and between the floating electrode FE and the upper electrode UE. It is the barrier insulating film BR and the lower insulating layer SZ1 that function as a capacitive insulating film by interposing them. Thereby, since the dielectric constant of the capacitive insulating film is increased, the capacitance value of the capacitive element (C1) can be further increased.

  Further, when the sixth embodiment is applied to the first modification of the first embodiment (FIG. 14), the wiring layer in which the floating electrode FE1 is formed, the wiring layer in which the electrode UE1 is formed, and the floating layer It is preferable to apply the wiring layer of the sixth embodiment (FIG. 48) to the wiring layer in which the electrode FE2 is formed and the wiring layer in which the electrode LE2 is formed. That is, in FIG. 14, the insulating film IL3 in which the floating electrode FE1 is embedded, the insulating film IL4 in which the electrode UE1 is embedded, the insulating film IL5 in which the floating electrode FE2 is embedded, and the electrode LE2 are embedded. It is preferable to apply the insulating film IL of the sixth embodiment to the insulating film IL6.

  When the sixth embodiment is applied to the second to fourth embodiments (FIGS. 21, 27, and 31), the wiring layer on which the metal patterns MP3 and MP4 are formed and the metal patterns MP5 and MP6 are provided. It is preferable to apply the wiring layer of the sixth embodiment (FIG. 48) to the formed wiring layer. That is, in FIGS. 21, 27 and 31, the insulating film IL5 of the sixth embodiment is applied to the insulating film IL5 in which the metal patterns MP3 and MP4 are embedded, and the metal patterns MP5 and MP6 are embedded. It is preferable to apply the insulating film IL of the sixth embodiment to the insulating film IL6. Thereby, in each of the insulating films IL5 and IL6 in FIGS. 15 to 17, 21, 27, and 31, the layer (here, the upper insulating layer SZ2) in which the damascene wiring (the wiring M4 or the wiring M5) is embedded. ) Is lower than the dielectric constant of the layer (here, lower insulating layer SZ1 and barrier insulating film BR) in which the via portion (via portion V4 or via portion V5) connected to the damascene wiring is embedded. . By doing so, since the dielectric constant of the insulating film (insulating layer in which the via portion is buried) contributing to the fourth to seventh capacitors is increased, the capacitance value of the capacitor element (C2) can be further increased. .

  That is, in the first to fourth embodiments, when the capacitor elements (C1, C2) are formed using a plurality of continuous wiring layers in the multilayer wiring structure, the lowest of the plurality of continuous wiring layers. It is preferable to apply the wiring layer (FIG. 48) of the sixth embodiment to a wiring layer other than the wiring layer (the lower electrode LE or the electrode LE1 or the wiring layer forming the metal patterns MP1 and MP2). Thereby, the capacitance value of the capacitive elements (C1, C2) can be further increased.

  The lowermost wiring layer (the wiring layer forming the lower electrode LE or the electrode LE1 or the metal patterns MP1 and MP2) among the plurality of continuous wiring layers that form the capacitive elements (C1 and C2) includes: The wiring layer of the sixth embodiment (FIG. 48) may or may not be applied. This is because, in the lowermost wiring layer among the plurality of continuous wiring layers forming the capacitive elements (C1, C2), the insulating layer in which the via portion is embedded functions almost as a capacitive insulating film of the capacitive element. It is because it does not.

  The interlayer insulating film SZ has a two-layer structure (laminated structure) including a lower insulating layer SZ1 and an upper insulating layer SZ2 having a lower dielectric constant than the lower insulating layer SZ1. An example of the formation process of SZ will be described. FIG. 49 is a cross-sectional view showing the step of forming the interlayer insulating film SZ, and shows the region corresponding to FIG.

  As shown in FIG. 49, after forming the barrier insulating film BR, the interlayer insulating film SZ is formed on the barrier insulating film BR. Here, in the case where the interlayer insulating film SZ is a porous SiOC film having a plurality of vacancies formed using a porogen described later, a method of forming the interlayer insulating film SZ will be described below. Note that the SiOC film is an insulating film containing carbon (C), oxygen (O), and silicon (Si) as constituent elements, and can also be regarded as a silicon oxide film containing carbon (C).

  The interlayer insulating film SZ is formed by depositing a SiOC film in a plasma CVD apparatus. This SiOC film is a porous Low-k film (porous low dielectric constant film) having a plurality of vacancies inside, and after forming an insulating film containing porogen by plasma CVD, the porogen is desorbed from the insulating film. Can be formed.

  The porogen is a hole forming agent for forming a large number of holes in the interlayer insulating film SZ. After forming an insulating film having a plurality of holes containing porogen gas, the porogen is formed in the insulating film. By performing a curing step for desorption (discharge) from the substrate, a plurality of vacancies not containing porogen are formed, and an interlayer insulating film SZ is formed.

Specifically, O ₂ (oxygen), He (helium), and C ₅ H ₁₄ O ₂ Si (methyldiethoxysilane), which are source gases for forming an interlayer insulating film SZ containing porogen in a plasma CVD apparatus. ) And porogen to form an interlayer insulating film SZ.

  Here, the flow rate of the porogen supplied during the formation of the interlayer insulating film SZ is initially reduced and increased later. That is, the flow rate of the porogen while the portion corresponding to the upper insulating layer SZ2 is formed is larger than the flow rate of the porogen while the portion corresponding to the lower insulating layer SZ1 is formed. That is, the flow rate of the porogen is changed while forming the interlayer insulating film SZ. For this reason, the lower insulating layer SZ1 and the upper insulating layer SZ2 are continuously formed so that an oxide film or the like is not formed between the lower insulating layer SZ1 and the upper insulating layer SZ2.

The porogen material is C _X H _Y (hydrocarbon) having a molecular weight of 80 to 150, and for example, α-terpinene (C ₁₀ H ₁₆ ), limonene (C ₁₀ H ₁₆ ), cycloocta, or the like is used. it can.

  Further, as a curing process for detaching the porogen from the interlayer insulating film SZ, there is a curing method using UV (Ultraviolet) irradiation, EB (Electron Beam) irradiation, heat treatment using a lamp, plasma, or the like. Here, the term “cure” refers to a step of discharging porogen out of the interlayer insulating film by applying energy to the porogen in the interlayer insulating film by UV irradiation or EB irradiation described above. The curing process also has a role of increasing the strength of the interlayer insulating film SZ.

  That is, the interlayer insulating film SZ including a large number of vacancies filled with the porogen gas is formed on the barrier insulating film BR by the film forming process using the plasma CVD method. Thereafter, for example, the main surface of the semiconductor substrate SB is irradiated with an electron beam (EB), and the porogen is discharged (cured) from the interlayer insulating film SZ, so that the porogen is filled as shown in FIG. The plurality of vacancies become vacancies (voids) VC that do not contain porogen, and a porous interlayer insulating film SZ having vacancies VC can be formed.

  Here, in the film forming process of the interlayer insulating film SZ, as described above, the flow rate of the porogen is increased during the film forming process. Therefore, the interlayer insulating film formed at an early stage in the film forming process. The lower region in SZ, that is, the lower insulating layer SZ1, and the upper region in the interlayer insulating film SZ formed thereafter, that is, the upper insulating layer SZ2, have different amounts of porogen contained therein (volume of porogen gas). . That is, the amount of porogen (volume of porogen gas) is larger in the upper insulating layer SZ2 of the interlayer insulating film SZ than in the lower insulating layer SZ1 of the interlayer insulating film SZ.

  For this reason, if the porogen desorption step is performed by the above-described curing method after the plasma CVD method, the porogen is desorbed from the lower insulating layer SZ1 and the upper insulating layer SZ2, and in the lower insulating layer SZ1. A plurality of holes VC having a relatively small average diameter are formed, and a plurality of holes VC having a relatively large average diameter are formed in the upper insulating layer SZ2. As described above, the flow rate of the porogen is increased during the process of forming the interlayer insulating film SZ, and a small hole VC is formed in the lower region (that is, the lower insulating layer SZ1) in the interlayer insulating film SZ. A large hole VC can be formed in the upper region (that is, the upper insulating layer SZ2). As a result, the upper insulating layer SZ2 of the interlayer insulating film SZ has a higher hole occupancy (hole density) than the lower insulating layer SZ1 of the interlayer insulating film SZ, and therefore the dielectric constant of the lower insulating layer SZ1. Also, the dielectric constant of the upper insulating layer SZ2 can be lowered. Here, the vacancy occupation ratio is a ratio (volume ratio) occupied by vacancies in the insulating film in the insulating film in which a plurality of vacancies are formed. Corresponds to the percentage of the total volume. In the insulating film in which a plurality of holes are formed, the dielectric constant can be lowered as the hole occupation ratio is increased. Further, since the lower insulating layer SZ1 has a lower occupancy rate than the upper insulating layer SZ2, the lower insulating layer SZ1 can be said to be a denser film than the upper insulating layer SZ2.

  In this manner, the interlayer insulating film SZ having a two-layer structure (laminated structure) including the lower insulating layer SZ1 and the upper insulating layer SZ2 having a dielectric constant lower than that of the lower insulating layer SZ1 can be formed. Note that the description of the process of forming the wiring MM and the via portion VV by the damascene method is omitted here, but can be performed, for example, as described in the fifth embodiment.

  Here, in order to make the dielectric constant of the upper insulating layer SZ2 lower than the dielectric constant of the lower insulating layer SZ1, the vacancy occupation ratio of the upper insulating layer SZ2 is made larger than the vacancy occupation ratio of the lower insulating layer SZ1. ing. As another form, the upper insulating layer SZ2 and the lower insulating layer SZ1 are formed of different materials, and the dielectric constant of the material constituting the upper insulating layer SZ2 is made lower than the dielectric constant of the material constituting the lower insulating layer SZ1. Thus, the dielectric constant of the upper insulating layer SZ2 can be made lower than the dielectric constant of the lower insulating layer SZ1.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

BR Barrier insulating film C1, C2, C3, C101, C201 Capacitance element CD1, CD2 Conductive film CT Contact hole DE1, DE2, DE3 Electrode FE, FE1, FE2, FE3, FE4, FE5 Floating electrode GD Upper electrode GE Gate electrode GI Gate Insulating film IL, IL1, IL2, IL3, IL3b, IL3c Insulating film IL3a Barrier insulating film IL4, IL5, IL6 Insulating films L1, L2, L3, L101, L102, L201 Distance LE Lower electrode M1, M2, M3, M4, M5 , MM wiring MC1, MC2, MC3, MC4, MC5, MC6 connecting part MD1, MD2, MD3, MD4, MD5, MD6 electrode part ML1, ML2, ML3, ML4, ML5 wiring layer MP1, MP2, MP3, MP4, MP5 MP6 metal pattern NS1, NS2 n-type semiconductor Frequency PG plug PR1, PR2, PR3 photoresist pattern PW p-type well region Q1 MISFET
SB semiconductor substrate SD n-type semiconductor region ST element isolation region SZ interlayer insulating film SZ1 lower insulating layer SZ2 upper insulating layer T1, T2 thickness TR, TR1, TR2 groove UE upper electrode YZ insulating films V2, V3, V4, V5, VV via Part VC Hole VH, VH1 Via hole

Claims (18)

A semiconductor device comprising: a semiconductor substrate; a wiring structure formed on the semiconductor substrate and including a plurality of wiring layers; and a capacitor element formed in the wiring structure,
The plurality of wiring layers include a first wiring layer, a second wiring layer that is one layer above the first wiring layer, and a third wiring layer that is one layer above the second wiring layer. And including
A first electrode of the capacitive element is formed on the first wiring layer;
A second electrode of the capacitive element is formed on the third wiring layer;
The second electrode is disposed above the first electrode;
A semiconductor device, wherein a floating electrode located between the first electrode and the second electrode is formed on the second wiring layer. The semiconductor device according to claim 1,
A semiconductor in which electric charge is accumulated in the capacitive element by applying a higher potential to one of the first electrode and the second electrode than the other of the first electrode and the second electrode. apparatus. The semiconductor device according to claim 2,
The first wiring layer, the second wiring layer, and the third wiring layer are wiring layers in which damascene wiring is formed,
The first electrode is embedded in a first insulating film formed above the semiconductor substrate;
The floating electrode is embedded in a second insulating film formed on the first insulating film in which the first electrode is embedded;
The semiconductor device, wherein the second electrode is embedded in a third insulating film formed on the second insulating film in which the floating electrode is embedded. The semiconductor device according to claim 3.
The semiconductor device, wherein the second insulating film and the third insulating film interposed between the first electrode and the second electrode function as a capacitive insulating film of the capacitive element. The semiconductor device according to claim 3.
In each of the second insulating film and the third insulating film, the dielectric constant of the layer in which the damascene wiring is embedded is lower than the dielectric constant of the layer in which the via portion connected to the damascene wiring is embedded. , Semiconductor devices. The semiconductor device according to claim 1,
The planar size of the floating electrode is the same as that of the first electrode and the second electrode. The semiconductor device according to claim 1,
The semiconductor device, wherein the floating electrode has a planar dimension larger than that of the first electrode and the second electrode. The semiconductor device according to claim 1,
The planar size of the floating electrode is a semiconductor device smaller than the first electrode and the second electrode. A semiconductor device comprising: a semiconductor substrate; a wiring structure formed on the semiconductor substrate and including a plurality of wiring layers; and a capacitor element formed in the wiring structure,
A first metal pattern and a second metal pattern formed in a first wiring layer of the plurality of wiring layers;
A third metal pattern and a fourth metal pattern formed in a second wiring layer that is one layer above the first wiring layer of the plurality of wiring layers;
Have
The first metal pattern includes a plurality of first electrode portions extending in a first direction and arranged in a second direction intersecting the first direction in a plan view,
The second metal pattern includes a plurality of second electrode portions extending in the first direction and arranged in the second direction in a plan view,
The first electrode portion and the second electrode portion are alternately arranged in the second direction,
The third metal pattern includes a plurality of third electrode portions extending in the first direction and arranged in the second direction in a plan view;
The fourth metal pattern includes a plurality of fourth electrode portions extending in the first direction and arranged in the second direction in plan view,
The third electrode portion and the fourth electrode portion are alternately arranged in the second direction,
The first metal pattern and the third metal pattern are electrically connected to each other to form one electrode of the capacitive element;
The second metal pattern and the fourth metal pattern are electrically connected to each other to form the other electrode of the capacitive element;
Each of the plurality of first electrode portions is disposed between the third electrode portion and the fourth electrode portion adjacent in the second direction in a plan view,
Each of the plurality of second electrode portions is a semiconductor device disposed between the third electrode portion and the fourth electrode portion adjacent in the second direction in plan view. The semiconductor device according to claim 9.
A semiconductor device in which a charge is accumulated in the capacitive element by applying a higher potential to one of the first and third metal patterns and the second and fourth metal patterns than the other. The semiconductor device according to claim 9.
The first metal pattern includes a first connection part extending in the second direction and connecting ends of the plurality of first electrode parts in a plan view,
The second metal pattern includes a second connection portion that extends in the second direction and connects ends of the plurality of second electrode portions in a plan view,
The third metal pattern includes a third connection portion that extends in the second direction and connects the ends of the plurality of third electrode portions in plan view,
The fourth metal pattern includes a fourth connection portion that extends in the second direction and connects ends of the plurality of fourth electrode portions in a plan view,
The side connected to the first connecting part of the first electrode part and the side connected to the second connecting part of the second electrode part are opposite to each other,
The side connected to the third connecting part of the third electrode part and the side connected to the fourth connecting part of the fourth electrode part are opposite to each other,
The side connected to the first connection part of the first electrode part and the side connected to the third connection part of the third electrode part are the same side.
The side of the second electrode part connected to the second connecting part and the side of the fourth electrode part connected to the fourth connecting part are the same side. The semiconductor device according to claim 9.
The semiconductor device, wherein the first metal pattern, the second metal pattern, the third metal pattern, and the fourth metal pattern are formed by damascene wiring. The semiconductor device according to claim 12, wherein
The first metal pattern and the second metal pattern are embedded in a first insulating film formed above the semiconductor substrate,
The third metal pattern and the fourth metal pattern are embedded in a second insulating film formed on the first insulating film in which the first metal pattern and the second metal pattern are embedded;
In the second insulating film, the dielectric constant of the layer in which the damascene wiring is embedded is lower than the dielectric constant of the layer in which the via portion connected to the damascene wiring is embedded. The semiconductor device according to claim 12, wherein
In the first wiring layer, a first floating electrode is formed between the first electrode portion and the second electrode portion adjacent in the second direction,
A semiconductor device, wherein a second floating electrode is formed between the third electrode portion and the fourth electrode portion adjacent to each other in the second direction in the second wiring layer. A semiconductor device comprising: a semiconductor substrate; a wiring structure formed on the semiconductor substrate and including a plurality of wiring layers; and a capacitor element formed in the wiring structure,
Having a first metal pattern and a second metal pattern formed in a first wiring layer of the plurality of wiring layers;
The first metal pattern includes a plurality of first electrode portions extending in a first direction and arranged in a second direction intersecting the first direction in a plan view,
The second metal pattern includes a plurality of second electrode portions extending in the first direction and arranged in the second direction in a plan view,
The first electrode portion and the second electrode portion are alternately arranged in the second direction,
The first metal pattern forms one electrode of the capacitive element,
The second metal pattern forms the other electrode of the capacitive element;
A semiconductor device, wherein a floating electrode is formed between the first electrode portion and the second electrode portion adjacent to each other in the second direction in the first wiring layer. The semiconductor device according to claim 15, wherein
A semiconductor device in which a charge is accumulated in the capacitive element by applying a higher potential to one of the first metal pattern and the second metal pattern than the other. The semiconductor device according to claim 15, wherein
The first metal pattern includes a first connection part extending in the second direction and connecting ends of the plurality of first electrode parts in a plan view,
The second metal pattern includes a second connection portion that extends in the second direction and connects ends of the plurality of second electrode portions in a plan view,
The semiconductor device, wherein a side of the first electrode part connected to the first connection part and a side of the second electrode part connected to the second connection part are opposite to each other. The semiconductor device according to claim 15, wherein
The semiconductor device, wherein the first metal pattern, the second metal pattern, and the floating electrode are formed by damascene wiring.

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