JP2014225267A - Voltage detecting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a voltage detecting circuit capable of highly sensitively detecting voltage fluctuation.SOLUTION: A voltage detecting circuit 10 for detecting voltage between a VPP and a VSS, comprises at least transistors 12 and 13 connected in series between the VPP and the VSS. Reference voltage Vref is supplied to a gate of the transistor 13, a gate of the transistor 12 is short-circuited with a drain thereof, and a detection signal Vdiff is output from a connection point between a drain of the transistor 13 and a source of the transistor 12. Voltage fluctuation between the VPP and the VSS is thereby reflected to the detection signal Vdiff, and thereby the voltage is monitored highly sensitively compared with a background technique.

Description

  The present invention relates to a voltage detection circuit, and more particularly to a voltage detection circuit that detects fluctuations in internal voltage generated inside a semiconductor device. The present invention also relates to a semiconductor device including such a voltage detection circuit.

  The power supply voltage used in a semiconductor device such as a DRAM (Dynamic Random Access Memory) has been decreasing year by year, thereby reducing power consumption. The power supply voltage in the past was generally 5V, but then decreased to 3.3V, and a voltage of about 1.2V may be used at present.

  However, depending on the type of semiconductor device, there is an internal circuit that requires a voltage higher than the power supply voltage. For example, in a DRAM, a selected word line may be set to a voltage higher than a power supply voltage. In this case, a boosted internal voltage is required for the word line driving circuit.

  However, there is a problem that the internal voltage generated inside the semiconductor device is likely to fluctuate as compared with the voltage supplied from the outside. For this reason, in order to further stabilize the internal voltage, it is necessary to use a voltage detection circuit that monitors the internal voltage and feed back the output to the internal voltage generation circuit (see Patent Documents 1 to 3).

  FIG. 13 is a circuit diagram of a conventional voltage detection circuit.

  A voltage detection circuit 1 shown in FIG. 13 is a circuit that detects fluctuations in the internal voltage VPP boosted inside the semiconductor device. The voltage detection circuit 1 includes a power supply wiring to which a higher potential VPP is supplied and a lower potential VSS (usually Three resistors 2 to 4 are connected in series with a power supply wiring to which a ground potential is supplied. The detection signal Vdiff is output from a connection point between the resistors 3 and 4 and is supplied to the comparator 5. The comparator 5 compares the reference voltage Vref and the detection signal Vdiff, and generates the determination signal S based on the comparison. The determination signal S is supplied to an internal voltage generation circuit (not shown), whereby the boosting operation by the internal voltage generation circuit is controlled.

However, since the voltage detection circuit 1 shown in FIG. 13 generates the detection signal Vdiff by resistance-dividing the internal voltage VPP, even if the internal voltage VPP fluctuates, the amount of fluctuation that appears in the detection signal Vdiff is Get smaller. In particular,
Vdiff = VPP / 3
Thus, the fluctuation amount of the detection signal Vdiff is also 1/3 of the fluctuation amount of the internal voltage VPP. For this reason, the sensitivity to voltage fluctuation is low, and it is difficult to sufficiently stabilize the internal voltage.

JP-A-10-134574 JP 2000-014134 A JP 2001-067132 A

  Accordingly, an object of the present invention is to provide a voltage detection circuit capable of detecting a fluctuation in voltage with higher sensitivity and a semiconductor device including the same.

  A voltage detection circuit according to the present invention is a voltage detection circuit that detects a voltage between first and second wirings, and includes at least first and second transistors connected in series between the first and second wirings. A first reference voltage is supplied to the gate of the first transistor, the gate and drain of the second transistor are short-circuited, and a detection signal is output from a connection point between the drain of the first transistor and the source of the second transistor. It is output.

  A semiconductor device according to the present invention includes the voltage detection circuit, an internal voltage generation circuit that generates a potential to be applied to the first or second wiring, and a comparator that compares the detection signal with the second reference voltage. The internal voltage generation circuit is controlled based on the output of the comparator.

  According to the present invention, since the gate-source voltage of the first transistor matches the source-drain voltage of the second transistor, the amount of voltage drop due to the second transistor is the gate-source of the first transistor. It is uniquely determined by the inter-voltage. For this reason, the voltage fluctuation is reflected as it is in the detection signal, and as a result, it becomes possible to monitor the voltage with higher sensitivity than in the past.

  Both the first and second transistors may be N-channel MOS transistors, or both may be P-channel MOS transistors. In the former case, the source of the first transistor may be connected to the lower wiring. Conversely, in the latter case, the source of the first transistor may be connected to the higher-level wiring.

  The “source” of the transistor refers to a node connected to the low potential side in the N-channel MOS transistor, and refers to a node connected to the high potential side in the P-channel MOS transistor. Similarly, the “drain” of the transistor refers to a node connected to the high potential side in the N-channel MOS transistor, and refers to a node connected to the low potential side in the P-channel MOS transistor.

  Thus, according to the present invention, it is possible to detect voltage fluctuation with higher sensitivity. For this reason, it is possible to stabilize the internal voltage of the semiconductor device with higher accuracy.

It is a block diagram which shows the structure of the principal part of the semiconductor device concerning Embodiment 1 of this invention. It is a circuit diagram of the voltage detection circuit concerning Embodiment 1 of this invention. (A) is a figure which shows an example of the specific circuit structure of the internal voltage generation circuit concerning Embodiment 1 of this invention. (B) is the operation | movement waveform diagram. (A) is a figure which shows another example of the specific circuit structure of the internal voltage generation circuit concerning Embodiment 1 of this invention. (B) is the operation | movement waveform diagram. It is a circuit diagram of the voltage detection circuit concerning the modification of Embodiment 1 of this invention. It is a block diagram which shows the structure of the principal part of the semiconductor device concerning Embodiment 2 of this invention. It is a circuit diagram of the voltage detection circuit concerning Embodiment 2 of this invention. It is a circuit diagram of the voltage detection circuit concerning the modification of Embodiment 2 of this invention. FIG. 6 is a circuit diagram of an internal step-down power supply generation circuit according to Embodiment 3 of the present invention. It is a circuit diagram of the internal step-down power supply generation circuit concerning the modification of Embodiment 3 of this invention. It is a circuit diagram of the internal step-down power supply generation circuit concerning the other modification of Embodiment 3 of this invention. FIG. 10 is a circuit diagram of an internal step-down power generation circuit according to still another modification of Embodiment 3 of the present invention. It is a circuit diagram of the voltage detection circuit concerning the background art of this invention. It is a circuit diagram of an internal step-down power supply generation circuit according to the background art of the present invention. It is a circuit diagram of an internal step-down power supply generation circuit according to the background art of the present invention.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram showing the configuration of the main part of the semiconductor device according to the first embodiment of the present invention.

  A semiconductor device 100 illustrated in FIG. 1 is a semiconductor device that operates with an externally supplied power supply voltage VDD, and an internal voltage generation circuit 110 that generates a boosted internal voltage VPP, and an internal circuit 121 that operates with the power supply voltage VDD. And an internal circuit 122 that operates with the internal voltage VPP. The type of the semiconductor device 100 is not particularly limited, and may be a memory semiconductor device such as a DRAM or a flash memory, or a processor semiconductor device such as a CPU or DSP.

  The internal voltage VPP generated by the internal voltage generation circuit 110 is higher than the power supply voltage VDD. Both the power supply voltage and the internal voltage are defined by the potential difference between the high potential and the low potential, and the low potential (VSS) is a ground potential. Therefore, in the present embodiment, the higher potential of the internal voltage VPP is higher than the higher potential of the power supply voltage VDD. In the present specification, the potential difference between the power supply voltage and the lower potential VSS is sometimes simply referred to as “voltage”. For example, a power supply voltage that is a potential difference between the higher potential VDD and the lower potential VSS may be simply expressed as VDD. The same applies to an internal voltage VPP, a reference voltage Vref, and the like described later.

  The internal circuit 121 that operates with the power supply voltage VDD is a circuit block that can operate with a relatively low voltage. On the other hand, the internal circuit 122 operated by the internal voltage VPP is a circuit block that needs to be operated at a relatively high voltage. As an example, when the semiconductor device 100 according to the present embodiment is a DRAM, various control circuits such as an address counter and a command decoder correspond to the internal circuit 121, and a word line drive circuit that activates a word line is the internal circuit 122. Equivalent to.

  As shown in FIG. 1, the semiconductor device 100 according to the present embodiment further includes a reference voltage generation circuit 130 that generates a stabilized reference voltage Vref, and a voltage detection circuit 10 that monitors the internal voltage VPP. The voltage detection circuit 10 generates the determination signal S by monitoring the internal voltage VPP. The determination signal S is supplied to the internal voltage generation circuit 110, whereby the boosting operation by the internal voltage generation circuit 110 is controlled. The reference voltage Vref generated by the reference voltage generation circuit 130 may be a single potential, or may be constituted by a plurality of reference voltages Vref1, Vref2,.

  FIG. 2 is a circuit diagram of the voltage detection circuit 10.

  The voltage detection circuit 10 shown in FIG. 2 is connected in series in this order between a power supply wiring to which a higher potential VPP is supplied and a power supply wiring to which a lower potential VSS (usually a ground potential) is supplied. Three N-channel MOS transistors 11 to 13 are provided. These three transistors 11 to 13 have the same transistor size.

  Of these, the two transistors 11 and 12 are so-called diode-connected with the gate and drain short-circuited. For the remaining transistor 13, the reference voltage Vref1 is supplied to the gate. The detection signal Vdiff is output from the connection point between the transistor 12 and the transistor 13, in other words, from the connection point between the source of the transistor 12 and the drain of the transistor 13.

  The detection signal Vdiff is supplied to the comparator 14. The comparator 14 compares the reference voltage Vref2 and the detection signal Vdiff, and generates a determination signal S based on the comparison. The determination signal S is supplied to the internal voltage generation circuit 110 shown in FIG. 1, thereby controlling the boosting operation by the internal voltage generation circuit. The circuit configuration and operation of the internal voltage generation circuit 110 will be described later. The reference voltages Vref1 and Vref2 may be the same potential or different potentials.

  As shown in FIG. 2, since the transistors 11 to 13 are connected in series, equal currents flow through these transistors. In this embodiment, since the reference voltage Vref1 is supplied to the gate of the transistor 13, the gate-source voltage Vgs of the transistor 13 matches Vref1.

  As described above, the transistor sizes of the transistors 11 to 13 are equal to each other. Therefore, if the amount of flowing current is equal, the gate-source voltages Vgs should be equal to each other. Since the transistors 11 and 12 are diode-connected, the source-drain voltages of these transistors also coincide with Vref1.

As a result, the level of the connection point (contact point a1) between the transistors 11 and 12 is VPP-Vref1.
The level of the connection point (contact b1) between the transistors 12 and 13, that is, the level of the detection signal Vdiff is VPP-2 × Vref1 (1)
Will be given.

  As is apparent from the equation (1), the detection signal Vdiff reflects the fluctuation of the internal voltage VPP as it is. That is, in the conventional voltage detection circuit shown in FIG. 13, the fluctuation amount of the detection signal Vdiff is attenuated to 1/3 with respect to the fluctuation amount of the internal voltage VPP. The fluctuation amount of the voltage VPP becomes the fluctuation amount of the detection signal Vdiff as it is.

  In addition, since the transistors 11 to 13 are N-channel MOS transistors and the gates of the transistors 11 and 12 are connected to the internal voltage VPP side to be detected, the presence of the gate-source capacitance causes the internal voltage VPP to be reduced. Variation is transmitted with high sensitivity. That is, the fluctuation of the internal voltage VPP is directly transmitted to the gate of the transistor 11 and is also transmitted to the source via the gate-source capacitance of the transistor 11. The same applies to the transistor 12. As a result of such capacitive coupling, fluctuations in the internal voltage VPP are transmitted with high sensitivity, and the responsiveness of the detection signal Vdiff is enhanced.

  The fluctuation of the detection signal Vdiff is compared with the reference voltage Vref2 by the comparator 14, and the logical level of the determination signal S is determined according to the result. For this reason, the comparator 14 can monitor the voltage with higher sensitivity than before.

  The comparator 14 sets the determination signal S to a low level if the level of the detection signal Vdiff is higher than the reference voltage Vref2, and conversely sets the determination signal S to a high level if the level of the detection signal Vdiff is lower than the reference voltage Vref2. The determination signal S generated in this way is fed back to the internal voltage generation circuit 110 shown in FIG.

  FIG. 3A is a diagram showing an example of a specific circuit configuration of the internal voltage generation circuit 110, and FIG. 3B is an operation waveform diagram thereof.

  The internal voltage generation circuit 110 according to the example shown in FIG. 3A is a circuit for generating an internal voltage VPP that is twice the power supply voltage VDD, and controls the N-channel MOS transistors t1 to t3 and the operation of these transistors. It is comprised by the control circuit s1 to perform.

  The transistor t1 is connected between the power supply line to which the power supply voltage VDD is supplied and the contact C, and the control voltage N1 is supplied to the gate of the transistor t1 from the control circuit s1. The transistor t2 has a shorted source and drain and functions as a capacitor. The gate of the transistor t2 is connected to the contact C, and the control voltage B is supplied from the control circuit s1 to the source / drain. The transistor t3 is connected between the contact C and the output end, and a control voltage N2 is supplied to the gate of the transistor t3 from the control circuit s1. The threshold voltage of the transistor t1 is set to an intermediate voltage between 2VDD and VDD, and the threshold voltage of the transistor t3 is set to an intermediate voltage between VDD + VPP and VDD.

  As shown in FIG. 3B, the internal voltage generation circuit 110 having such a configuration generates an internal voltage VPP as an output by alternately repeating a charge operation and a pumping operation.

  The charging operation is performed by setting the control voltages N1, B, and N2 to 2VDD, VSS, and VDD, respectively. As a result, since the transistor t1 is turned on and the transistor t3 is turned off, charging of the transistor t2 is started, and the voltage at the contact C is charged to VDD as shown in FIG.

  The pumping operation is performed by setting the control voltages N1, B, and N2 to VDD, VDD, and VDD + VPP, respectively. As a result, the transistor t1 is turned off and the transistor t3 is turned on, so that the total voltage 2VDD of the charging voltage of the transistor t2 and the voltage B is output to the output terminal of the internal voltage generation circuit 110.

  By repeating such an operation alternately, the internal voltage VPP, which is the output of the internal voltage generation circuit 110, is boosted to twice the power supply voltage VDD. However, since the generated internal voltage VPP varies depending on the load, it is necessary to change the duty of the control voltage in order to stabilize it. Such control is performed by the control circuit s1 based on the logic level of the determination signal S. As a result, the internal voltage VPP that is the output of the internal voltage generation circuit 110 is stabilized.

  FIG. 4A is a diagram showing another example of a specific circuit configuration of the internal voltage generation circuit 110, and FIG. 4B is an operation waveform diagram thereof.

  The internal voltage generation circuit 110 according to the example shown in FIG. 4A is a circuit for generating an internal voltage VPP that is three times the power supply voltage VDD, and controls the N-channel MOS transistors t4 to t10 and the operation of these transistors. It is comprised by the control circuit s2 to perform.

  The transistors t4, t6, and t7 are connected in series between VDD and VSS, and control voltages N1, P1, and N2 are supplied to the gates from the control circuit s2. The source and drain of the transistor t5 are short-circuited and function as a capacitor. The gate of the transistor t5 is connected to the contact D, and the control voltage A is supplied from the control circuit s2 to the source / drain. The transistors t8 to t10 correspond to the transistors t1 to t3 shown in FIG.

  The control circuit s2 controls the voltages N1, N2, N3, N4, P1, A, B, and C in the same manner as the control circuit s1 described with reference to FIG. 3, and VPP = 3VDD is applied to the output terminal of the internal voltage generation circuit 110. Is output. Also in the example shown in FIG. 4, the control circuit s2 changes the duty of each control voltage based on the logic level of the determination signal S, thereby stabilizing the internal voltage VPP.

  The circuits shown in FIGS. 3 and 4 are merely examples of the internal voltage generation circuit 110, and circuit configurations different from these may be used.

  As described above, according to the present embodiment, since the fluctuation of the internal voltage VPP is directly reflected in the detection signal Vdiff, the voltage determination by the comparator 14 can be performed with high sensitivity. As a result, the level of the internal voltage VPP generated by the internal voltage generation circuit 110 can be further stabilized.

  FIG. 5 is a circuit diagram of a voltage detection circuit 20 according to a modification.

  A voltage detection circuit 20 shown in FIG. 5 is a circuit that can be used in place of the voltage detection circuit 10 shown in FIG. 2, and includes three P-channel MOS transistors 21 to 23 connected in series between a pair of power supply wires. I have. These three transistors 21 to 23 have the same transistor size.

  Among these, the two transistors 22 and 23 are so-called diode-connected with their gates and drains short-circuited. For the remaining transistors 21, the reference voltage Vref1 is supplied to the gates. The detection signal Vdiff is output from the connection point between the transistor 21 and the transistor 22, in other words, from the connection point between the drain of the transistor 21 and the source of the transistor 22. The detection signal Vdiff is supplied to the comparator 24 and compared with the reference voltage Vref2.

  As shown in FIG. 5, since the transistors 21 to 23 are connected in series, equal currents flow through these transistors. In this embodiment, since the reference voltage Vref1 is supplied to the gate of the transistor 21, the gate-source voltage Vgs of the transistor 21 is given by VPP-Vref1.

  As described above, since the transistor sizes of the transistors 21 to 23 are equal to each other, the gate-source voltages Vgs should be equal to each other if the flowing current amount is equal. Since the transistors 22 and 23 are diode-connected, the source-drain voltage of these transistors is also given by VPP-Vref1.

As a result, the level of the connection point (contact b2) between the transistors 22 and 23 is VPP-Vref1.
And the level of the connection point (contact point a2) of the transistors 21 and 22, that is, the level of the detection signal Vdiff is 2 × VPP-2 × Vref1 (2)
Will be given.

  As is clear from the equation (2), it can be seen that the fluctuation of the internal voltage VPP appears in the detection signal Vdiff after being amplified twice. For this reason, the comparator 24 can monitor the voltage with higher sensitivity. The amplification degree of the fluctuation is equal to the number of transistors diode-connected between the contact point a2 and the VSS potential. Therefore, if the number of transistors between the contact point a2 and the VSS potential is one, the amplification factor is one, and if the number of transistors between the contact point a2 and the VSS potential is three, the amplification factor is three times.

  As described above, when the source of the transistor is connected to the power supply wiring to which the voltage to be detected (in this embodiment, the internal voltage VPP) is applied, it is possible to obtain the amplified detection signal Vdiff. .

  Next, a second embodiment of the present invention will be described.

  FIG. 6 is a block diagram showing the configuration of the main part of the semiconductor device according to the preferred second embodiment of the present invention. In the figure, the same circuit elements as those of the semiconductor device 100 are denoted by the same reference numerals.

  Similarly to the semiconductor device 100, the semiconductor device 101 illustrated in FIG. 6 is a semiconductor device that operates with a power supply voltage supplied from the outside. The semiconductor device 101 includes a reference voltage generation circuit 131 that generates a stabilized reference voltage Vref, a voltage detection circuit 30 that monitors the internal voltage VPP, and an internal voltage generation circuit 111 that generates an internal voltage VBB lower than VSS. And an internal circuit 123 that operates with the internal voltage VBB.

  The internal circuit 123 that operates with the internal voltage VBB is a circuit block that needs to supply a negative voltage.

  The voltage detection circuit 30 generates the determination signal S by monitoring the internal voltage VBB. The determination signal S is supplied to the internal voltage generation circuit 111, whereby the VBB generation operation by the internal voltage generation circuit 111 is controlled.

  The reference voltage Vref generated by the reference voltage generation circuit 131 is composed of two reference voltages Vref3 and Vref4.

  FIG. 7 is a circuit diagram of the voltage detection circuit 30.

  The voltage detection circuit 30 shown in FIG. 7 is connected between the wiring (second wiring) supplied with the potential Vref3 from the reference voltage generation circuit 131 and the power supply wiring (first wiring) supplied with the voltage VBB. Three N-channel MOS transistors 31 (third transistor), 32 (second transistor), and 33 (first transistor) are connected in series. These three transistors 31 to 33 have the same transistor size.

  Of these, the two transistors 31 and 32 are so-called diode-connected with their gates and drains short-circuited. For the remaining transistors 33, the reference voltage Vref4 (first reference voltage) is supplied to the gate. The detection signal Vdiff is output from the connection point between the transistor 32 and the transistor 33, in other words, from the connection point between the source of the transistor 32 and the drain of the transistor 33.

  The detection signal Vdiff is supplied to the comparator 34. The comparator 14 compares the reference voltage Vref4 and the detection signal Vdiff, and generates a determination signal S based on the comparison. The determination signal S is supplied to the internal voltage generation circuit 111 shown in FIG. 6, thereby controlling the VBB generation operation by the internal voltage generation circuit 111.

  As shown in FIG. 7, since the transistors 31 to 33 are connected in series, equal currents flow through these transistors. In this embodiment, since the reference voltage Vref4 is supplied to the gate of the transistor 33, the gate-source voltage Vgs of the transistor 33 matches Vref4-VBB.

  As described above, the transistor sizes of the transistors 31 to 33 are equal to each other. Therefore, if the amount of flowing current is equal, the gate-source voltages Vgs should be equal to each other. Since the transistors 31 and 32 are diode-connected, the source-drain voltages of these transistors also coincide with Vref4-VBB.

As a result, the level of the connection point (contact point a3) between the transistors 31 and 32 is Vref3- (Vref4-VBB).
The level of the connection point (contact point b3) between the transistors 32 and 33, that is, the level of the detection signal Vdiff is Vref3−2 × (Vref4−VBB) (3)
Will be given.

  As is clear from the equation (3), it can be seen that the fluctuation of the internal voltage VBB is amplified twice in the detection signal Vdiff. For this reason, the comparator 34 can monitor the voltage with higher sensitivity. The amplification degree of the variation is equal to the number of transistors diode-connected between the contact b3 and the Vref3 potential. Therefore, if the number of transistors between the contact b3 and the Vref3 potential is one, the amplification factor is one, and if the number of transistors between the contact b3 and the Vref3 potential is three, the amplification factor is three times.

  The fluctuation of the detection signal Vdiff is compared with the reference voltage Vref4 by the comparator 34, and the logical level of the determination signal S is determined according to the result. For this reason, the comparator 34 can monitor the voltage with higher sensitivity than before.

  The comparator 34 sets the determination signal S to a low level if the level of the detection signal Vdiff is lower than the reference voltage Vref4, and conversely sets the determination signal S to a high level if the level of the detection signal Vdiff is higher than the reference voltage Vref2. The determination signal S generated in this way is fed back to the internal voltage generation circuit 111 shown in FIG.

  As described above, according to the present embodiment, the fluctuation of the internal voltage VBB is doubled and reflected in the detection signal Vdiff, so that the voltage determination by the comparator 34 can be performed with high sensitivity. As a result, the level of the internal voltage VPP generated by the internal voltage generation circuit 111 can be further stabilized.

  FIG. 8 is a circuit diagram of a voltage detection circuit 40 according to a modification.

  A voltage detection circuit 40 shown in FIG. 8 is a circuit that can be used in place of the voltage detection circuit 30 shown in FIG. 7, and is connected in series between a wiring to which the potential Vref3 is supplied and a power supply wiring to which the voltage VBB is supplied. Three P-channel MOS transistors 41 to 43 are connected. These three transistors 41 to 43 have the same transistor size.

  Of these, the two transistors 42 and 43 are so-called diode-connected with their gates and drains short-circuited. For the remaining transistors 41, the reference voltage Vref4 is supplied to the gates. The detection signal Vdiff is output from the connection point between the transistor 41 and the transistor 42, in other words, the connection point between the drain of the transistor 41 and the source of the transistor 42. The detection signal Vdiff is supplied to the comparator 44 and compared with the reference voltage Vref4.

  As shown in FIG. 8, since the transistors 41 to 43 are connected in series, equal currents flow through these transistors. In this embodiment, since the reference voltage Vref4 is supplied to the gate of the transistor 41, the gate-source voltage Vgs of the transistor 41 is given by Vref3-Vref4.

  As described above, the transistor sizes of the transistors 41 to 43 are equal to each other. Therefore, if the amount of flowing current is equal, the gate-source voltages Vgs should be equal to each other. Since the transistors 42 and 43 are diode-connected, the source-drain voltages of these transistors are also given by Vref3-Vref4.

As a result, the level of the connection point (contact point b4) between the transistors 42 and 43 is VBB + Vref3−Vref4.
The level of the connection point (contact point a4) of the transistors 41 and 42, that is, the level of the detection signal Vdiff is VBB + 2 × (Vref3−Vref4) (4)
Will be given.

  As apparent from the equation (4), it can be seen that the detection signal Vdiff reflects the fluctuation of the internal voltage VBB as it is. For this reason, the comparator 44 can monitor the voltage with high sensitivity.

  Next, a third embodiment of the present invention will be described.

  FIG. 9 is a circuit diagram of an internal step-down power supply generation circuit according to a preferred third embodiment of the present invention.

  An internal step-down power supply generation circuit 200 shown in FIG. 9 is a circuit that generates a voltage Vout by stepping down a power supply voltage supplied from the outside, and also has a function as a voltage detection circuit. The semiconductor device 200 is also provided inside a memory semiconductor device such as a DRAM or flash memory or a processor semiconductor device such as a CPU or DSP.

  Here, for explanation, first, two examples of the internal step-down power generation circuit according to the background art of the present invention will be described. Thereafter, the semiconductor device 200 will be described in detail.

  FIG. 14 is a circuit diagram of an internal step-down power supply generation circuit 1000 according to the first background art. The internal step-down power supply generation circuit 1000 includes a comparator 1001, a P-channel MOS transistor 1002, and resistors 1003 and 1004. The transistor 1002 and the resistors 1003 and 1004 are connected to a power supply line to which a high potential VDD is supplied. Are connected in series in this order with the power supply wiring to which the potential VSS on the side is supplied. The reference voltage Vref5 is supplied to the inverting input terminal of the comparator 1001, and the non-inverting input terminal is connected to the connection point of the resistors 1003 and 1004. The voltage Vout is extracted from the connection point between the transistor 1002 and the resistor 1003.

  The resistance values of the resistors 1003 and 1004 are set to be the same. As a result, the detection signal Vdiff = (1/2) Vout is input to the non-inverting input terminal of the comparator 1001. Thus, the comparator 1001 compares (1/2) Vout with Vref5. The comparator 1001 generates a determination signal S reflecting the comparison result and outputs it to the gate of the transistor 1002, thereby adjusting Vout.

  Here, since the half value of Vout is input to the comparator 1001, the variation amount of Vout is also halved. For this reason, in the internal step-down power generation circuit 1000, the sensitivity of the comparator 1001 with respect to voltage fluctuation is low, and it is difficult to sufficiently stabilize the internal voltage.

  FIG. 15 is a circuit diagram of an internal step-down power supply generation circuit 1010 according to the second background art. The internal step-down power generation circuit 1010 includes N-channel MOS transistors 1013 and 1014 in place of the resistors 1003 and 1004 of the internal step-down power generation circuit 1000. The transistors 1013 and 1014 are all diode-connected. The non-inverting input terminal of the comparator 1001 is connected to the connection point of the transistors 1013 and 1014. The voltage Vout is extracted from a connection point between the transistor 1002 and the transistor 1013.

  The transistor sizes of the transistor 1013 and the transistor 1014 are set to be the same. As a result, the detection signal Vdiff = (1/2) Vout is input to the non-inverting input terminal of the comparator 1001. Therefore, similarly to the internal step-down power generation circuit 1000, the internal step-down power generation circuit 1010 has a low sensitivity of the comparator 1001 with respect to voltage fluctuations, and it is difficult to sufficiently stabilize the internal voltage.

  Now, the semiconductor device 200 according to the present embodiment will be described. As shown in FIG. 9, the internal step-down power generation circuit 200 includes a comparator 201, a P-channel MOS transistor 202 (third transistor), N-channel MOS transistors 203 (second transistors), and 204 (first transistors). The transistors 202, 203, and 204 include a power supply wiring (second wiring) to which a higher potential VDD is supplied and a power supply wiring (first wiring) to which a lower potential VSS is supplied. Are connected in series in this order. The transistor 203 is diode-connected. Further, the reference voltage Vref5 is supplied to the inverting input terminal of the comparator 201, and the non-inverting input terminal is connected to the connection point of the transistors 203 and 204. The reference voltage Vref5 is also supplied to the gate of the transistor 204. The voltage Vout is extracted from the connection point between the transistor 202 and the transistor 203. Further, the transistors 203 and 204 have the same transistor size.

  In this case, the gate-source voltage Vgs of the transistor 204 is Vref5. Since the transistor sizes of the transistors 203 and 204 are equal to each other as described above, the gate-source voltages Vgs should be equal to each other if the flowing current amount is equal. Since the transistor 203 is diode-connected, the source-drain voltage of the transistor 203 is also given by Vref5.

As a result, the level of the connection point (contact c1) between the transistors 203 and 204, that is, the level of the detection signal Vdiff input to the non-inverting input terminal of the comparator 201 is Vout−Vref5 (5)
Will be given.

  As apparent from the equation (5), the fluctuation of the voltage Vout is directly reflected in the detection signal Vdiff. That is, in the internal step-down power supply generation circuit shown in FIG. 14 or FIG. 15, the fluctuation amount of the signal input to the non-inverting input terminal of the comparator 31 is attenuated to ½ with respect to the fluctuation amount of the voltage Vout. In the internal step-down power supply generation circuit 200 according to the present embodiment, the fluctuation amount of the voltage Vout is directly reflected on the input to the non-inverting input terminal of the comparator 201.

  The fluctuation of the detection signal Vdiff is compared with the reference voltage Vref5 by the comparator 201, and the logic level of the output signal of the comparator 201 is determined according to the result. Therefore, the comparator 201 can monitor the voltage with higher sensitivity than before.

  The comparator 201 sets the determination signal S to a low level if the level of the detection signal Vdiff is higher than the reference voltage Vref2, and conversely sets the determination signal S to a high level if the level of the detection signal Vdiff is lower than the reference voltage Vref2. By controlling on / off of the transistor 202 by the determination signal S generated in this manner, the determination result of the comparator 201 is fed back to the voltage Vout.

  As described above, according to the present embodiment, since the fluctuation of the internal voltage Vout is directly reflected in the detection signal Vdiff, the voltage determination by the comparator 201 can be performed with high sensitivity. As a result, the level of voltage Vout generated by internal step-down power supply generation circuit 200 can be further stabilized.

  In the internal step-down power supply generation circuit 200 shown in FIG. 9, the same reference voltage Vref5 is supplied to the comparator 201 and the transistor 204, but different reference voltages may be supplied as shown in FIG.

  In the example illustrated in FIG. 10, the reference voltage Vref6 is supplied to the comparator 201, and the reference voltage Vref7 is supplied to the transistor 204. In this case, the voltage Vout is adjusted to Vref6 + Vref7. The relationship between the reference voltages Vref6 and Vref7 is not particularly limited, but it is preferable to set Vref7 to a higher potential than Vref6. According to this, the gate-source voltage Vgs = Vref7 of the transistor 204 can be sufficiently secured, and the operation under a low voltage can be stabilized.

  FIG. 11 is a circuit diagram of an internal step-down power generation circuit according to a modification.

  An internal step-down power supply generation circuit 210 shown in FIG. 11 is a circuit that can be used in place of the internal step-down power supply generation circuit 200 shown in FIG. , 214.

  In the internal step-down power generation circuit 210, the transistors 202 (third transistor), 213 (first transistor), and 214 (second transistor) are connected to the power supply wiring (first transistor) to which the higher potential VDD is supplied. Wiring) and a power supply wiring (second wiring) to which the lower potential VSS is supplied in series in this order. The transistor 214 is diode-connected. Further, the reference voltage Vref5 is supplied to the inverting input terminal of the comparator 201, and the non-inverting input terminal is connected to the connection point of the transistors 213 and 214. The reference voltage Vref5 is also supplied to the gate of the transistor 213. The voltage Vout is extracted from the connection point between the transistor 202 and the transistor 213. Further, the transistors 213 and 214 have the same transistor size.

  In this case, the gate-source voltage Vgs of the transistor 204 is Vout−Vref5. As described above, the transistor sizes of the transistors 213 and 214 are equal to each other. Therefore, if the amount of flowing current is equal, the gate-source voltages Vgs should be equal to each other. Since the transistor 214 is diode-connected, the source-drain voltage of the transistor 214 is also given by Vout-Vref5.

As a result, the level of the connection point (contact c2) of the transistors 213 and 214, that is, the level of the detection signal Vdiff input to the non-inverting input terminal of the comparator 201 is Vout−Vref5 (6)
Will be given.

  As is clear from the equation (6), also in this modification, the fluctuation of the voltage Vout is directly reflected in the detection signal Vdiff. Therefore, the voltage determination by the comparator 201 can be performed with high sensitivity. As a result, the level of voltage Vout generated by internal step-down power supply generation circuit 210 can be further stabilized.

  In the internal step-down power generation circuit 210 shown in FIG. 11, the same reference voltage Vref5 is supplied to the comparator 201 and the transistor 214, but different reference voltages may be supplied as shown in FIG.

  In the example illustrated in FIG. 12, the reference voltage Vref6 is supplied to the comparator 201, and the reference voltage Vref7 is supplied to the transistor 214. In this case, the voltage Vout is adjusted to Vref6 + Vref7. The relationship between the reference voltages Vref6 and Vref7 is not particularly limited, but it is preferable to set Vref7 to a potential lower than Vref6. According to this, the gate-source voltage Vgs = Vref7 of the transistor 214 can be sufficiently secured, and the operation under a low voltage can be stabilized.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

10, 20, 30, 40 Voltage detection circuit 11, 12, 13, 31, 32, 33, 203, 204 N-channel MOS transistors 14, 24, 34, 44, 201 Comparators 21, 22, 23, 41, 42, 43, 202, 213, 214 P-channel MOS transistor 100, 101 Semiconductor device 110, 111 Internal voltage generation circuit 121, 122, 123 Internal circuit 130, 131 Reference voltage generation circuit 200, 210 Internal step-down power supply generation circuit

Claims (1)

A voltage detection circuit for detecting a voltage between the first and second wirings, comprising at least first and second transistors connected in series between the first and second wirings;
A first reference voltage is supplied to the gate of the first transistor, a gate and a drain of the second transistor are short-circuited, and detection is performed from a connection point between the drain of the first transistor and the source of the second transistor. A voltage detection circuit which outputs a signal.

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