JP2014222203A - Signal processor and signal processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal processor and a signal processing method capable of improving signal to noise ratio even if a phase of a signal has secondary-changed.SOLUTION: Within an assumption range of secondary change of a phase shown by secondary change information outputted from secondary a change information output circuit 2, a coherent integration point setting circuit 3 calculates an improvement ratio of an SN ratio when coherent integration of a signal acquired by an acquisition of signal circuit 1 is carried out by each integration point. The integration point of coherent integration is established based on the improvement ratio.

Description

  The present invention relates to a signal processing apparatus and a signal for setting the number of integration points of coherent integration that can improve the signal-to-noise ratio by reducing the influence of unnecessary signals such as noise included in the signal to be analyzed. It relates to a processing method.

In a signal processing apparatus, a signal to be analyzed may be coherently integrated for the purpose of improving a signal-to-noise ratio (hereinafter referred to as “SN ratio”).
Coherent integration is a process in which phase information of a signal given as a complex number including amplitude and phase information is accumulated without erasing, and includes simple summation (average) processing of a plurality of signals and general Fourier transform processing.
Hereinafter, for convenience of explanation, it is assumed that the signal sequence to be processed is a time-series signal and the distribution obtained by Fourier transforming the signal sequence of the time distribution is a frequency distribution, but in particular, the axis is limited to time. For example, the axis is not limited to the time distribution and the frequency distribution as long as the axes are related through Fourier transform, such as a spatial distribution and a spatial frequency distribution.
Here, the amplitude of the complex signal is called voltage, and the square of this voltage is called power.

In the case of a signal that is uncorrelated in the time axis direction, such as noise (receiver noise) generated in a receiver mounted on a communication device or radar device, the signal is obtained by performing coherent integration with N integration points. Can be understood from the general property that a variable given by the sum of N uncorrelated variables that follow a normal distribution with the same variance follows a normal distribution with N times the variance of the original distribution. Possible).
Hereinafter, a signal having no correlation or low correlation in the time direction as described above is assumed as the unnecessary signal.

On the other hand, in the case of a signal having a uniform phase (a signal whose change with respect to time is only a primary component (including a case where the primary component is 0)), when coherent integration is performed with N integration points, the voltage of the signal Is N times, so the power is N ² times.
For signals with the same phase, coherent integration is performed to accumulate the frequency position according to the primary component of the phase.
For example, the received signal of the radar device (reflected signal reflected back to the target) is received when there is no relative motion between the target and the radar device, or when the distance changes less than the first order with respect to time. By performing coherent integration of the signal, the signal is accumulated at a frequency position corresponding to the primary component of the phase.

Therefore, in such a case, by performing coherent integration with N integration points, the S / N ratio that is the ratio of the power of the desired signal to the power of the unnecessary signal (the power of the desired signal / the power of the unnecessary signal) is obtained. It can be N times the original signal (= N ² / N).
This improves the performance of detecting a desired signal buried in noise and extracting information included in the signal.

On the other hand, when the phases of the desired signals are not aligned, the signal power does not increase even when coherent integration with N integration points is performed.
For example, when the desired signal is a signal that is uncorrelated in the time axis direction, such as receiver noise, the power of the desired signal is the same as the power of the unnecessary signal even if N-point coherent integration is performed. Since it is only N times, the SN ratio is not improved.

In addition, when the change with respect to time includes not only the primary component but also the secondary component, a phenomenon occurs in which the frequency at which the signal accumulates moves with the passage of time due to the influence of the secondary component.
When such a phenomenon occurs, the time during which the signal stays in one frequency resolution cell (the number of integration points to be coherently integrated) is limited. As a result, after a certain number of points, the power of the desired signal does not increase (roughly). Is a constant value).
For this reason, when the coherent integration point number is larger than a certain point, only the power of the unnecessary signal is accumulated, the power of the desired signal is not accumulated, and the SN ratio is deteriorated as the number of coherent integration points is increased.
Therefore, the larger the number of coherent integration points, the better. There is some optimum value.
Since the change speed of the frequency (speed of moving the frequency resolution cell) also changes depending on the magnitude of the secondary component, the optimum value also changes according to the magnitude of the secondary component.

Here, various factors can be considered as the generation component of the secondary component. In particular, in the example of the radar device, the change in the distance between the target and the radar device significantly occurs when the secondary component has a secondary component.
Examples of the secondary component include an acceleration component included in a target motion based on the radar device.
Further, when a component orthogonal to the line-of-sight direction of the radar apparatus is included among the components included in the target motion, the distance change of this component is approximately regarded as a secondary component.

Signal detection and extraction of information contained in the signal under an environment where the S / N ratio is low is performed by expanding the service area under a condition where the power used is constant (for example, in the case of a radar device, expanding the maximum distance at which the target can be monitored). Etc.) and reduction of power used by the radar device under a condition where the service area is constant (for example, power saving of communication equipment) is an important problem.
Therefore, in order to realize signal detection and extraction of information included in the signal in an environment where the S / N ratio is low, it is necessary to realize a technique for setting the number of coherent integration points in consideration of the influence of the secondary component. Yes.

Patent Document 1 below discloses a signal processing device that adjusts the number of integration points of coherent integration according to the situation.
In this signal processing apparatus, in order to cope with the fact that the received power of the desired signal decreases as the distance to the target increases, adjustment is performed so that the number of integration points of coherent integration increases as the distance to the target increases. Yes.
In Patent Document 1, a secondary change in phase such as acceleration is not focused, and even if a secondary change occurs, the number of integration points of coherent integration is not adjusted.

From the viewpoint of optimizing the tracking performance, the following Patent Document 2 is based on the trade-off relationship that the observation period increases if the number of integration points of coherent integration is increased, but the angle observation error decreases. A signal processing apparatus for setting the number of integration points for coherent integration is disclosed.
This signal processing apparatus does not pay attention to the secondary change of the phase such as acceleration, and the number of integration points of the coherent integration is not adjusted even if the secondary change occurs.

Patent Document 3 below describes that even when coherent integration of a target signal having a wide Doppler spectrum bandwidth is performed, the improvement of the S / N ratio is saturated (converged) above a certain number of integration points.
However, as a cause of the bandwidth expansion of the Doppler spectrum, “signal fluctuation” is exemplified, but it is unclear whether the signal fluctuation refers to acceleration (secondary component), The tendency of the S / N ratio to saturate as the number of coherent integration points increases does not coincide with the tendency due to the acceleration of the S / N ratio to deteriorate after a certain number of integration points. Understood.
Further, in the signal processing device disclosed in Patent Document 3, since coherent integration processing is performed in parallel with a plurality of types of integration points, even if this signal processing device considers acceleration, the processing is performed. The increase in load becomes a problem.

In Patent Document 4 below, when coherent integration processing is performed in parallel with a plurality of integration points, and the spread of the target Doppler spectrum is large, a coherent integration result with a small integration point is selected, and the spread of the target Doppler spectrum is performed. Discloses a signal processing device that selects a coherent integration result with a large number of integration points.
In Patent Document 4, the relationship between the target Doppler spectrum spread and acceleration (secondary component) is not described. For this reason, in this signal processing device, the number of integration points of coherent integration is not adjusted even if a secondary change occurs.

JP 7-43449 A (paragraph number [0008]) JP-A-2-195287 (Example column) JP-A-5-45449 (paragraph numbers [0012] to [0017]) JP 2012-225688 A (paragraph number [0305])

  Since the conventional signal processing apparatus is configured as described above, the number of integration points for coherent integration cannot be optimized in accordance with the secondary change even if the phase of the signal changes secondary. For this reason, when the phase of the signal is secondarily changed, there is a problem that the signal-to-noise ratio cannot be sufficiently improved.

  The present invention has been made to solve the above-described problems, and provides a signal processing device and a signal processing method capable of improving a signal-to-noise ratio even when the phase of the signal is second-order changed. With the goal.

  A signal processing apparatus according to the present invention outputs a signal acquisition circuit that acquires a signal for performing coherent integration, and secondary change information that indicates an assumed range of a secondary change in phase in the signal acquired by the signal acquisition circuit. The coherent integration of the signal acquired by the signal acquisition circuit is performed at each integration point within the assumed range of the secondary change of the phase indicated by the change information output circuit and the secondary change information output from the secondary change information output circuit. A coherent integration point setting circuit that calculates an improvement ratio of the signal-to-noise ratio when it is performed and sets the integration point number of the coherent integration based on the improvement ratio, and the coherent integration circuit is configured by the coherent integration point setting circuit The coherent integration of the signal acquired by the signal acquisition circuit is performed with the set number of integration points.

  According to the present invention, the coherent integration point number setting circuit is capable of coherently acquiring the signal acquired by the signal acquisition circuit within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit. Since the improvement ratio of the signal-to-noise ratio when integration is performed at each integration point is calculated, and the integration point number of coherent integration is set based on the improvement ratio, the phase of the signal changes secondarily. Even if it does, there exists an effect which can improve a signal to noise ratio.

BRIEF DESCRIPTION OF THE DRAWINGS It is a block diagram which shows the signal processing apparatus by Embodiment 1 of this invention. It is a block diagram which shows the coherent integration point number setting circuit 3 of the signal processing apparatus by Embodiment 1 of this invention. 4 is a flowchart showing processing contents of a coherent integration point number setting circuit 3; It is explanatory drawing which shows an example of the secondary change characteristic of the phase in a signal. It is explanatory drawing which shows an example of the power improvement ratio characteristic of an unnecessary signal and a desired signal. It is explanatory drawing which shows an example of a S / N improvement ratio characteristic. It is explanatory drawing which shows an example of the achievement probability in the achievement limit contour and the achievement limit of each S / N improvement ratio for every S / N improvement ratio. It is a block diagram which shows the coherent integration point number setting circuit 3 of the signal processing apparatus by Embodiment 3 of this invention.

Embodiment 1 FIG.
1 is a block diagram showing a signal processing apparatus according to Embodiment 1 of the present invention.
In FIG. 1, a signal acquisition circuit 1 is a circuit for acquiring a signal for performing coherent integration.
The secondary change information output circuit 2 is a circuit that outputs secondary change information indicating an assumed range of a secondary change in phase in the signal acquired by the signal acquisition circuit 1.
The coherent integration point number setting circuit 3 performs coherent integration of the signal acquired by the signal acquisition circuit 1 within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit 2. This is a circuit that calculates an improvement ratio of the signal-to-noise ratio (signal-to-noise ratio) when it is performed with the number of integration points, and sets the number of integration points for coherent integration based on the improvement ratio.

The coherent integration circuit 4 is a circuit that performs coherent integration of the signal acquired by the signal acquisition circuit 1 with the number of integration points set by the coherent integration point setting circuit 3.
The signal analysis circuit 5 is a circuit that analyzes the signal after the coherent integration by the coherent integration circuit 4. For example, when the signal processing device is mounted on a radar device, a process for detecting a target from the signal after the coherent integration, A process for estimating motion, a process for generating a radar image, and the like are performed. In addition, motion estimation processing for compensating for unnecessary motion components that blur the radar image is also performed.

In the example of FIG. 1, each of the signal acquisition circuit 1, the secondary change information output circuit 2, the coherent integration point number setting circuit 3, the coherent integration circuit 4, and the signal analysis circuit 5 that are components of the signal processing device is dedicated hardware. (For example, a semiconductor integrated circuit on which a CPU is mounted, or a one-chip microcomputer, etc.) is assumed. However, the signal processing apparatus may be configured with a computer.
When the signal processing device is configured by a computer, a program describing the processing contents of the signal acquisition circuit 1, the secondary change information output circuit 2, the coherent integration point setting circuit 3, the coherent integration circuit 4, and the signal analysis circuit 5 May be stored in the memory of the computer, and the CPU of the computer may execute the program stored in the memory.

FIG. 2 is a block diagram showing a coherent integration point number setting circuit 3 of the signal processing apparatus according to Embodiment 1 of the present invention.
In FIG. 2, the secondary change characteristic setting circuit 11 uses the secondary change information output from the secondary change information output circuit 2 as a secondary change characteristic of a signal (for example, a discrete secondary change amount within an assumed range). Is a circuit for setting.
The desired signal power improvement ratio calculation circuit 12 performs the case where the coherent integration of the signal acquired by the signal acquisition circuit 1 is performed at each integration point for each secondary change amount set by the secondary change characteristic setting circuit 11. Each of the circuits calculates a power improvement ratio of a desired signal included in the signal.
The unnecessary signal power improvement ratio calculation circuit 13 includes unnecessary signals (for example, components such as receiver noise) included in the signal when the coherent integration of the signal acquired by the signal acquisition circuit 1 is performed at each integration point. ) To calculate the power improvement ratio of each.
The desired signal power improvement ratio calculation circuit 12 and the unnecessary signal power improvement ratio calculation circuit 13 constitute a power improvement ratio calculation means.

The S / N improvement ratio calculation circuit 14 increases the desired signal power improvement ratio and unnecessary signal power improvement calculated by the desired signal power improvement ratio calculation circuit 12 for each secondary change amount set by the secondary change characteristic setting circuit 11. This is a circuit for calculating the improvement ratio of the SN ratio from the power improvement ratio of the unnecessary signal calculated by the ratio calculation circuit 13. The S / N improvement ratio calculation circuit 14 constitutes an S / N improvement ratio calculation means.
The achievement probability calculation circuit 15 is a circuit that calculates the achievement probability of the improvement ratio of the SN ratio calculated by the S / N improvement ratio calculation circuit 14 for each secondary change amount set by the secondary change characteristic setting circuit 11. is there. The achievement probability calculation circuit 15 constitutes an achievement probability calculation means.

  The achievement probability optimization index setting circuit 16 is an optimization index used when the coherent integration point selection circuit 17 selects an optimum integration point (for example, the improvement ratio of the S / N ratio under the condition that the achievement probability is equal to or higher than a predetermined value). An index indicating that the highest integration point is selected, an index indicating that the integration point with the highest achievement probability is selected under the condition that the improvement ratio of the SN ratio is equal to or higher than a predetermined value, and the improvement ratio of the SN ratio And an index indicating that the number of integration points with the highest index calculated from the achievement probability is selected.

The coherent integration point number selection circuit 17 is the number of integration points at which the improvement ratio of the S / N ratio is the highest under the condition that the optimization index set by the achievement probability optimization index setting circuit 16 is, for example, the achievement probability is a predetermined value or more Is selected by the S / N improvement ratio calculation circuit 14 under the condition that the achievement probability calculated by the achievement probability calculation circuit 15 is equal to or greater than a predetermined value from among a plurality of integration points. The number of integration points at which the improved S / N ratio improvement ratio is the highest is selected.
In addition, the coherent integration point selection circuit 17 has the highest achievement probability under the condition that the optimization index set by the achievement probability optimization index setting circuit 16 is, for example, the improvement ratio of the SN ratio is equal to or greater than a predetermined value. In the case of indicating that the number of integration points is to be selected, the achievement probability is obtained under the condition that the improvement ratio of the S / N ratio calculated by the S / N improvement ratio calculation circuit 14 is a predetermined value or more from among a plurality of integration points. The number of integration points with the highest achievement probability calculated by the calculation circuit 15 is selected.
Further, the coherent integration point selection circuit 17 selects the integration point at which the optimization index set by the achievement probability optimization index setting circuit 16 has the highest index calculated from the improvement ratio of the SN ratio and the achievement probability, for example. In the case of indicating that, the index F is calculated from the improvement ratio of the S / N ratio calculated by the S / N improvement ratio calculation circuit 14 and the achievement probability calculated by the achievement probability calculation circuit 15, and from among a plurality of integration points. , The number of integration points with the highest index F is selected.
The achievement probability optimization index setting circuit 16 and the coherent integration point number selection circuit 17 constitute an integration point number selection means.
FIG. 3 is a flowchart showing the processing contents of the coherent integration point number setting circuit 3.

Next, the operation will be described.
Here, an example will be described in which the signal processing apparatus is applied to a radar apparatus including an image radar such as SAR (Synthetic Aperture Radar) or ISAR (Inverse SAR).
When the signal processing device is applied to a radar device, the signal acquisition circuit 1 of the signal processing device is configured by, for example, a circuit that performs the following processing.

(1) Generate a high-frequency signal to irradiate the target and output the high-frequency signal to the transmitting antenna Transmitter (2) Transmitting antenna that radiates the high-frequency signal output from the transmitter to space (3) Radiate from the transmitting antenna After that, a receiving antenna that receives a high-frequency signal reflected / scattered by the target (using a transmission / reception switching device, the transmitting antenna and the receiving antenna are
(It can also be shared by two antennas)
(4) A receiver that detects and demodulates the high-frequency signal received by the receiving antenna. (5) Performs a correlation operation between the received signal of the receiver and the high-frequency signal generated by the transmitter to reduce the resolution in the range direction. Improved pulse compressor

The signal acquisition circuit 1 irradiates a target with a high-frequency signal in a process for obtaining a reception signal with improved resolution in the range direction (received signal, which is referred to as a “range profile” because it gives a target waveform in the range direction). It is possible to obtain a range history, which is a time history of the range profile, by repeating while shifting the time to be performed.
This series of processing is generally well used in a radar apparatus including an image radar, and its operation, configuration, and the like are well known, so detailed description thereof is omitted here.

The range history obtained by the signal acquisition circuit 1 may cause a signal distortion (for example, movement of a reflection point or a higher-order phase change due to relative motion), and this distortion may affect the performance of coherent integration. There is a possibility of deteriorating.
When the magnitude of some disturbance (for example, the magnitude of relative motion) that causes the distortion of the signal is known, the signal acquisition circuit 1 may compensate for the distortion of the signal in advance. .
This applies not only to the range history but also to communication and other possible signals.

In the radar apparatus, the second-order time-varying component included in the range change between the target and the radar apparatus is a main factor that degrades the SN ratio improvement ratio by coherent integration. Hereinafter, the reason why the secondary time change component is the main factor will be described in detail.
Here, at time t [s], a component that changes with time in the target range based on the radar device is d (t) [m].
At this time, it is assumed that the component d (t) is given by the second order or lower, and the coefficient of primary change (radial velocity) is v [m / s], and the coefficient of secondary change (radial acceleration) is a [m / s. ² ], the component d (t) is represented by the following formula (1).

In the above description, monostatic observation is assumed in which the transmission position and reception position of the high-frequency signal are the same, but the sum of “distance from transmission position to target” and “distance from target to reception position” is 2 If the distance that is a fraction is defined as a range, it can be extended to bistatic observation with different transmission and reception positions.
In the following, we will extend to bistatic observation.

したがって、瞬時ドップラー周波数γ（ｔ）［Ｈｚ］は、下記の式（３）で与えられる。

When the wavelength corresponding to the center frequency is λ [m], the phase change φ (t) [rad] of the received signal corresponding to the component d (t) is given by the following equation (2).

Therefore, the instantaneous Doppler frequency γ (t) [Hz] is given by the following equation (3).

From equation (3), it can be seen that the instantaneous Doppler frequency γ (t) changes due to the influence of the radial acceleration a.
Thus, since the target signal moves through the Doppler cell, the radial acceleration a, which is the component of the secondary change, becomes a factor that degrades the improvement ratio of the SN ratio by coherent integration.

また、時間幅Ｔに対応するドップラー周波数セル幅Δ（Ｔ）［Ｈｚ］は、下記の式（５）で与えられる。

よって、時間幅Ｔの間に移動するドップラーセル数は、概ね、下記の式（６）に示すＭ（ａ，Ｔ）［−］で与えられる。

Here, assuming that the time width (coherent integration time) of the signal used for coherent integration is T [s], the total fluctuation amount Γ (a, T) [Hz] of the instantaneous Doppler frequency within this time width T is as follows. (4).

Further, the Doppler frequency cell width Δ (T) [Hz] corresponding to the time width T is given by the following equation (5).

Therefore, the number of Doppler cells that move during the time width T is approximately given by M (a, T) [−] shown in the following equation (6).

この関係に基づいて、下記の式（８）に示すように、ドップラーセル数Ｍ（ａ，Ｔ）をコヒーレント積分点数ｋに依存するＭ（ａ，ｋ）の形で表すようにする。

When the pulse repetition frequency is f _p [Hz], the coherent integration point number k is related to the time width T by the following equation (7).

Based on this relationship, the Doppler cell number M (a, T) is expressed in the form of M (a, k) depending on the coherent integration point number k as shown in the following equation (8).

Based on the above, the processing contents of each circuit included in the coherent integration point number setting circuit 3 will be described. In the secondary change information output circuit 2, the secondary change of the phase in the signal acquired by the signal acquisition circuit 1 is explained. Secondary change information indicating the assumed range is output.
The secondary change information output from the secondary change information output circuit 2 is information indicating an assumed range of the secondary change of the phase in the signal. Specifically, the secondary change of the phase in the signal is normally distributed ( For example, information represented by a normal distribution expressed by an average value and a standard deviation defined separately.
FIG. 4 is an explanatory diagram showing an example of the secondary change characteristic of the phase in the signal.

Here, the secondary change information exemplifies information indicating the secondary change of the phase in the signal with a normal distribution. However, if the secondary change information indicates the secondary change of the phase, the information expressed with the normal distribution. For example, it may be a uniform distribution expressed by an average value and a width that are separately defined.
Further, the distribution is a delta function that expresses a secondary change in phase (a delta function distribution that has a value only with a small number of types (for example, one) separately determined as a secondary change in phase). Also good.
A delta function distribution is a value with only a small number of distinctive values, such as the maximum absolute value of the distribution range assumed for the coefficient, values at both ends of the maximum and minimum values, the average value, and the mode value. Is given in the form of having.

When receiving the secondary change information from the secondary change information output circuit 2, the secondary change characteristic setting circuit 11 of the coherent integration point number setting circuit 3 receives the secondary change characteristic of the signal (for example, within an assumed range) from the secondary change information. Are set (step ST1 in FIG. 3).
That is, the secondary change characteristic setting circuit 11 sets the secondary change coefficient range of the signal from the secondary change information as the secondary change characteristic of the signal, calculates the probability density value of the secondary change coefficient range, The probability density value is output to desired signal power improvement ratio calculation circuit 12, S / N improvement ratio calculation circuit 14, and achievement probability calculation circuit 15.
The probability density value may be given as a continuous function p (a) or as a discrete value.
Regarding the probability density distribution p (a), which is a continuous function p (a), a range having a value (not 0) may be assumed to be infinite (for example, a normal distribution). May be set so as to narrow the range of a by regarding the value in a range where p (a) is sufficiently small as zero for the purpose of reducing the processing load at the subsequent stage.
In this case, normalization is performed so that the integral value over the entire range of probability density values is 1.

なお、後段の所望信号電力改善比算出回路１２が、所望信号の電力改善比Ｇ_ｓ（ａ_ｙ，ｋ）を離散系で計算を行う場合には、２次変化特性設定回路１１により設定された２次変化係数ａ_ｙについて、所望信号の電力改善比Ｇ_ｓ（ａ_ｙ，ｋ）が算出される。
一方、所望信号電力改善比算出回路１２が連続系で計算を行う場合には、２次変化特性設定回路１１により算出された確率密度分布ｐ（ａ）が０以外の値を持つａの範囲を含んでいる所望信号の電力改善比Ｇ_ｓ（ａ，ｋ）が算出される。 Further, when the probability density value is given discretely, the probability density value in Y (Y is 1 or more) secondary change coefficients a _y (y = 1, 2,..., Y) is defined as _py , and the following equation Set to satisfy (9).

When the desired signal power improvement ratio calculation circuit 12 in the subsequent stage calculates the power improvement ratio G _s (a _y , k) of the desired signal in a discrete system, it is set by the secondary change characteristic setting circuit 11. For the secondary change coefficient a _y , the power improvement ratio G _s (a _y , k) of the desired signal is calculated.
On the other hand, when the desired signal power improvement ratio calculation circuit 12 performs the calculation in a continuous system, the probability density distribution p (a) calculated by the secondary change characteristic setting circuit 11 is in a range having a value other than 0. A power improvement ratio G _s (a, k) of the desired signal included is calculated.

Hereinafter, an example of setting the secondary change characteristic of the signal by the secondary change characteristic setting circuit 11 will be described.
[Setting example 1]
For example, when the standard deviation σ of the radial acceleration a is obtained as the secondary change information from the secondary change information output circuit 2, the secondary change characteristic of the signal is represented by a normal distribution with an average of 0 and the standard deviation σ. The probability density distribution is set.
When the bias component μ is separately obtained as the secondary change information from the secondary change information output circuit 2 in addition to the standard deviation σ of the radial acceleration a, it is represented by a normal distribution of the average μ and the standard deviation σ. Probability density distribution is set.
Moreover, what is necessary is just to set suitably according to the information, when other information showing a distribution shape is obtained.

[Setting example 2]
When the information representing the distribution shape is not obtained as the secondary change information from the secondary change information output circuit 2, it is assumed that the distribution is a uniform distribution or a normal distribution with an appropriate width. It is possible to substitute for the distribution of the radial acceleration a.
For example, when information about only the average μ is obtained as the secondary change information from the secondary change information output circuit 2, a normal distribution having a width appropriately set around the average μ or a single value is used as the secondary change characteristic of the signal. A method of setting a uniform distribution is conceivable.
In addition, if a rough standard deviation σ is expected, but it is unclear whether the standard deviation σ distribution follows a normal distribution, a method that considers the standard deviation σ distribution as a normal distribution is also a setting example. Enter category 2.

[Setting example 3]
For example, when only the average value μ is obtained as the secondary change information from the secondary change information output circuit 2, a delta function distribution having a value only with the average value μ is set as the secondary change characteristic of the signal. Like that.
The delta function-like distribution is not limited to the average value μ, and may have only other important values.
As other important values, for example, the maximum value a _max of the radial acceleration a expected from the target exercise performance, the mode value, and the like can be considered.
The average value and the mode value are values that most characterize the distribution, and the larger secondary coefficient (the coefficient having a large absolute value) is an important value that limits the upper limit of the coherent integration point. It is a reasonable idea to make the value of be a representative value of the distribution.

[Setting Example 4]
The position of the delta function is not limited to one, and may be set to a plurality of positions.
For example, the maximum value a _max of the radial acceleration a may be set at two points ± a _max in consideration of the sign.

When the secondary change characteristic setting circuit 11 sets the secondary change characteristic of the signal, the desired signal power improvement ratio calculation circuit 12 generates a signal for each radial acceleration a that is a secondary change amount assumed from the secondary change characteristic. The power improvement ratio G _s (a, k) of the desired signal included in the signal when the coherent integration of the signal acquired by the acquisition circuit 1 is performed at each integration point k is calculated (step ST2). ).
The processing for calculating the power improvement ratio G _s (a, k) of the desired signal by the desired signal power improvement ratio calculation circuit 12 will be specifically described below.

Here, the power improvement ratio refers to the value of the ratio (Xout / Xin) between the input power Xin and the output power Xout.
In the case of the power improvement ratio of the desired signal, Xin is the input power of the desired signal, and Xout is the power of the desired signal after coherent integration.
However, the power of the desired signal after the coherent integration indicates the maximum value of the power of the cell in which the signals are correctly stacked in each Doppler cell.

When the signal acquired by the signal acquisition circuit 1 does not include a secondary phase change component, all the k-point signals are accumulated in the same Doppler cell, so the power improvement ratio of the desired signal is k ² . .
However, if a secondary phase change component is included, as described above, it may be accompanied by movement of the Doppler cell, so the power improvement ratio of the desired signal is calculated based on the effect of movement of the Doppler cell. There is a need to.
Hereinafter, calculation methods (1) and (2) of the power improvement ratio of the desired signal will be described.

Calculation method (1)
Even when the signal acquired by the signal acquisition circuit 1 includes a second-order phase change component, the maximum limit value (coherent integration) of the number of integration points where the desired signal is stacked on the same Doppler cell by coherent integration of the signal. Calculate the limit score).
The coherent integration limit score is given as a score k that satisfies the following equation (10). However, for simplification of explanation, the integerization of k is not considered.

Since M (a, k) changes depending on the radial acceleration a, the coherent integration limit number also changes depending on the radial acceleration a.
If the value of M (a, k) is represented by q (a), q (a) is given by the following equation (11).

式（１２）において、ｍｉｎ｛［ｘ，ｙ］｝は、ｘ，ｙのうち、大きくない方の値を取り出すオペレータである。 When the number of coherent integration points k is equal to or less than q (a), the signals at k points are all accumulated in the same Doppler cell, and thus the power improvement ratio of the desired signal is k ² as described above.
However, if the coherent integration point k is larger than q (a), the number of signals accumulated in the same one Doppler cell reaches a peak at q (a), and the remaining signals are transmitted to cells adjacent to the Doppler cell. Pile up. For this reason, it can be considered that the power improvement ratio of the desired signal reaches its peak at q (a) ² .
From the above, the power improvement ratio G _s (a, k) of the desired signal is given by the following equation (12).

In Expression (12), min {[x, y]} is an operator that extracts the smaller value of x and y.

Calculation method (2)
In the calculation method (1), the power improvement ratio G _s (a, k) of the desired signal is calculated based on a signal accumulation model based on the temporal change of the instantaneous Doppler frequency and the Doppler cell width. The desired signal included in the signal acquired by the signal acquisition circuit 1 is Fourier transformed, the signal after Fourier transformation is converted into power, and the desired signal is calculated from the maximum power in the power and the power of the reference signal. The power improvement ratio G _s (a, k) may be calculated.
Specifically, it is as follows.

所望信号ｓ（ａ，ｍ）を下記の式（１４）に示すようにコヒーレント積分（離散フーリエ変換）を実施した後、フーリエ変換後の信号を電力に換算し、それらの電力の中の最大電力を探索することによっても、所望信号の電力改善比Ｇ_ｓ（ａ，ｋ）が得られる。

なお、フーリエ変換に基づく所望信号の電力改善比Ｇ_ｓ（ａ，ｋ）の算出は、上記の離散フーリエ変換の計算に限るものではなく、例えば、連続系のフーリエ変換に基づく式変形や数値積分等でも実施可能である。 For example, a desired signal s (a, m) with power 1 given by the following equation (13) is assumed.

The coherent integration (discrete Fourier transform) is performed on the desired signal s (a, m) as shown in the following equation (14), the signal after the Fourier transform is converted into power, and the maximum power among those powers The power improvement ratio G _s (a, k) of the desired signal can also be obtained by searching for.

Note that the calculation of the power improvement ratio G _s (a, k) of the desired signal based on the Fourier transform is not limited to the above-described calculation of the discrete Fourier transform. For example, formula modification and numerical integration based on the continuous Fourier transform Etc. are also possible.

FIG. 5 is an explanatory diagram showing an example of the power improvement ratio characteristics of the unnecessary signal and the desired signal. In particular, FIG. 5B shows the power improvement ratio G _s (a, k) of the desired signal calculated by the calculation method (1). ) Characteristics. The same tendency can be obtained when the power improvement ratio G _s (a, k) of the desired signal is calculated by the calculation method (2).
In FIG. 5, the horizontal axis represents the number of coherent integration points k, and the vertical axis represents the power improvement ratio [dB] of the desired signal.
In FIG. 5, characteristics for different radial accelerations a [m / s ² ] are overlaid with different line types.
From FIG. 5, it can be confirmed that the increase in the improvement ratio tends to reach its peak with a smaller number of coherent integration points as the radial acceleration a increases.

図５（ａ）は不要信号の電力改善比特性の一例を示しており、図５（ａ）から明らかなように、位相の２次変化成分が含まれている場合の所望信号のような電力改善比の頭打ちは発生しない。 The unnecessary signal power improvement ratio calculation circuit 13 includes an unnecessary signal (for example, receiver noise or the like) included in the signal when the coherent integration of the signal acquired by the signal acquisition circuit 1 is performed at each integration point k. The power improvement ratio G _n (k) of each component is calculated (step ST3).
For example, as the power improvement ratio G _n (k) of the unnecessary signal, the integration point k when the coherent integration of the signal acquired by the signal acquisition circuit 1 is performed is used as shown in the following equation (15). To do.

FIG. 5A shows an example of the power improvement ratio characteristic of the unnecessary signal. As is clear from FIG. 5A, the power like the desired signal when the secondary change component of the phase is included. The improvement ratio will not reach its peak.

In the S / N improvement ratio calculation circuit 14, the desired signal power improvement ratio calculation circuit 12 calculates the power improvement ratio G _s (a, k) of the desired signal for each radial acceleration a, and the unnecessary signal power improvement ratio calculation circuit 13 When the power improvement ratio G _n (k) of the unnecessary signal is calculated, the S / N improvement ratio G (a, k) at each radial acceleration a and coherent integration point number k is calculated as shown in the following equation (16). Calculate (step ST4).

式（１７）より、コヒーレント積分点数ｋがｑ（ａ）以下では、ＳＮ比の改善比がコヒーレント積分点数ｋに比例して増加するが、コヒーレント積分点数ｋがｑ（ａ）より大きくなると、ＳＮ比の改善比がコヒーレント積分点数ｋに反比例する傾向を確認することができる（ｑ（ａ）において、改善比が最大になる）。 Here, by substituting the power improvement ratio G _s (a, k) of the desired signal shown in the equation (12) calculated by the calculation method (1) into the equation (16), the following equation (17) is obtained. It is done.

From equation (17), when the number of coherent integration points k is equal to or less than q (a), the improvement ratio of the SN ratio increases in proportion to the number of coherent integration points k, but when the number of coherent integration points k is greater than q (a), It can be confirmed that the improvement ratio of the ratio is inversely proportional to the number of coherent integration points k (in q (a), the improvement ratio is maximized).

FIG. 6 is an explanatory diagram showing an example of the S / N improvement ratio characteristic.
FIG. 6A shows the characteristic of the S / N improvement ratio with respect to the number of coherent integration points k for each secondary change amount of the representative value of the secondary change, and FIG. 6B shows the S / N improvement ratio characteristic. It is a contour display of the characteristic with respect to the secondary change and the number of coherent integration points.
The coordinate axes in FIG. 6A are the same as those in FIG. 5, the horizontal axis in FIG. 6B is the number of coherent integration points k, and the vertical axis is the assumed radial acceleration a.
FIG. 6 confirms that the improvement ratio tends to be maximized when the number of coherent integration points k is q (a).

［連続系］

The achievement probability calculation circuit 15 is assumed from the secondary change characteristic set by the secondary change characteristic setting circuit 11 when the S / N improvement ratio calculation circuit 14 calculates the S / N improvement ratio G (a, k). The achievement probability of the S / N improvement ratio G (a, k) is calculated for each radial acceleration a that is the secondary change amount (step ST5).
The achievement probability of the S / N improvement ratio G (a, k) gives a distribution indicating how much the assumed S / N improvement ratio can be achieved at each coherent integration point number k.
Assuming that the assumed S / N improvement ratio is ξ, the achievement probability (ζ, k) of the S / N improvement ratio ξ is the S / N improvement ratio G (a, k) for each radial acceleration a and the discrete system ( Alternatively, it is calculated from the probability density distribution p _y (or p (a)) of the continuous system as in the following formula (18) or formula (19).
[Discrete system]

[Continuous system]

In equations (18) and (19), large (x, y) is a function that returns “1” if x ≧ y and “0” if x <y.
Therefore, “1” is returned if the S / N improvement ratio G (a, k) for each radial acceleration a satisfies the assumed S / N improvement ratio ξ, and “0” otherwise. Works to return.
Therefore, the appearance frequency of the radial acceleration a is calculated by multiplying the probability density distribution _py (or p (a)) with respect to the radial acceleration a and adding (or integrating) the large (x, y) with the probability density distribution. For the case according to _py (or p (a)), the probability of satisfying each coherent integration point number k and the assumed S / N improvement ratio ξ is given.

FIG. 7A shows a contour of the achievement probability for each S / N improvement ratio, and FIG. 7B shows an example of the achievement probability at the achievement limit of the S / N improvement ratio.
In FIG. 7A, the horizontal axis represents the number of coherent integration points k, the vertical axis represents the assumed S / N improvement ratio ζ, and the value of ξ (ζ, k) at each ζ, k is displayed in contour. Yes.
For example, hatched hatching indicates a range where ξ (ζ, k) is 0.999 or more, and vertical hatching indicates a range where ξ (ζ, k) is 0.9 or more and less than 0.999, and horizontal hatching. Represents a range where ξ (ζ, k) is 0.001 or more and less than 0.1.
The hatched area of the polka dots shows a range where ξ (ζ, k) is less than 0.001 in the notation of the figure, but this represents a range that cannot be achieved with the set number of coherent integration points (a range of 0). ing. That is, the hatching area of the polka dots and the curve separating the other areas represent the achievement limit of the S / N improvement ratio at each coherent integration point k (when the desired signal is ideally stacked).

From FIG. 7, the achievement limit of the S / N improvement ratio increases as the number of coherent integration points k increases, but the probability that an S / N improvement ratio of the limit degree can be achieved increases as the number of coherent integration points k increases. It turns out that it falls.
Also, from the viewpoint of the probability of achieving the same S / N improvement ratio, it can be seen that if the improvement ratio is within the achievement limit, the achievement probability increases as the number of coherent integration points k decreases.
If the achievement probability is low, even if the achievement limit of the improvement ratio is high, the possibility that it can be achieved is low, so the signal detection probability and the probability of succeeding in extracting information from the signal are also reduced. It can be considered that the performance deteriorates.
Based on the above, it can be said that setting the number of coherent integration points that comprehensively considers both the achievement limit of the S / N improvement ratio and the achievement probability is useful for ensuring noise resistance performance. For the purpose of realizing this, the achievement probability calculation circuit 15 calculates the achievement probability.

Here, although the achievement probability calculation circuit 15 has shown that the achievement probability is calculated in a planar range with respect to each S / N improvement ratio and the number of coherent integration points, the S / N improvement ratio at each coherent integration point number is shown. The achievement probability may be calculated only in a linear range representing the achievement limit. In this case, it is useful from the viewpoint of reducing calculation load.
Considering that the achievement probability for each S / N improvement ratio at each coherent integration point monotonically decreases with respect to the assumed increase in the SN ratio, the achievement probability is also minimized at the achievement limit of the SN ratio.
Therefore, the achievement probability at the achievement limit of the SN ratio is useful as an index for guaranteeing performance in terms of the achievement probability.

［連続系］

The achievement probability at the achievement limit of the S / N ratio is called “S / N improvement ratio achievement limit achievement probability”, which is expressed as 表 す (k), and the S / N improvement ratio achievement limit achievement probability Ξ (k) is (20) and (21).
[Discrete system]

[Continuous system]

FIG. 7B shows a calculation example of the S / N improvement ratio achievement limit achievement probability.
The horizontal axis represents the number of coherent integration points, which is also the improvement limit of the SN ratio. The vertical axis represents the achievement probability with respect to the improvement limit of each SN ratio.
If the coherent integration point k is small and the frequency cell does not move, the achievement probability becomes a high value of 1 (near). However, if the coherent integration point k exceeds the achievement limit, the frequency cell moves. Thereafter, as the number of coherent integration points k increases, the probability of achieving the improvement limit of the SN ratio decreases.

The achievement probability optimization index setting circuit 16 sets an optimization index when the coherent integration point selection circuit 17 selects an optimal integration point (step ST6).
Various optimization indexes can be considered according to restrictions on applications and performance. For example, the following indexes can be considered.
However, in the following description, the index will be explained on the assumption that the larger the value, the more optimal the index will be. However, the smaller the value, the more optimal the index will be, the “large index value” ← → “ Needless to say, it can be used in the same manner with a degree of replacement similar to “small index value”.

式（２２）において、ｘ_１，ｘ_２は重み付けの係数である。 [Optimization index 1]
An index [optimization index 2] indicating that the number of integration points at which the improvement ratio of the SN ratio is the highest is selected under the condition that the achievement probability is equal to or higher than a predetermined value.
An index [optimization index 3] indicating that the number of integration points with the highest achievement probability is selected under the condition that the improvement ratio of the SN ratio is equal to or greater than a predetermined value.
As F (k, ξ) shown in the following equation (22), the index changes depending on both the improvement ratio k of the SN ratio and the achievement probability ξ, and the larger the value, the more desirable index.

In Expression (22), x ₁ and x ₂ are weighting coefficients.

When the achievement probability optimization index setting circuit 16 sets an optimization index, the coherent integration point selection circuit 17 selects a coherent integration performed by the coherent integration circuit 4 from a plurality of coherent integration points k based on the optimization index. The number of coherent integration points is selected (step ST7).
That is, if the optimization index set by the achievement probability optimization index setting circuit 16 is the above optimization index 1, the coherent integration point selection circuit 17 selects the achievement probability calculation circuit from a plurality of coherent integration points k. 15, the S / N improvement ratio G (a, k) calculated by the S / N improvement ratio calculation circuit 14 is the highest under the condition that the achievement probability (ζ, k) calculated by 15 is a predetermined value or more. The number of coherent integration points is selected, and the number of coherent integration points is set in the coherent integration circuit 4.

Further, the coherent integration point selection circuit 17 improves the S / N from the plurality of coherent integration points k if the optimization index set by the achievement probability optimization index setting circuit 16 is the optimization index 2 described above. The achievement probability (ζ, k) calculated by the achievement probability calculation circuit 15 is the highest under the condition that the S / N improvement ratio G (a, k) calculated by the ratio calculation circuit 14 is a predetermined value or more. The number of coherent integration points is selected, and the number of coherent integration points is set in the coherent integration circuit 4.
Further, the coherent integration point number selection circuit 17 determines that the S / N improvement ratio calculation circuit 14 calculates the S / N improvement ratio calculation circuit 14 if the optimization index set by the achievement probability optimization index setting circuit 16 is the above optimization index 3. An index F (k, ξ) is calculated from the N improvement ratio G (a, k) and the achievement probability (ζ, k) calculated by the achievement probability calculation circuit 15, and the index is selected from a plurality of coherent integration points k. The number of coherent integration points with the highest F (k, ξ) is selected, and the number of coherent integration points is set in the coherent integration circuit 4.

Here, no special restriction is provided for the number of coherent integration points. However, when some kind of restriction is additionally provided for the number of coherent integration points (for example, even number is set to a power of 2), the search range is appropriately limited. Should be added.
It is also possible to narrow down the number of coherent integration points for calculating the achievement probability for each S / N improvement ratio and the achievement limit achievement probability of the S / N improvement to a range that satisfies the constraint condition related to the number of coherent integration points in advance. This is useful in terms of reduction.

When the coherent integration point number setting circuit 3 sets the coherent integration point number, the coherent integration circuit 4 performs coherent integration of the signal acquired by the signal acquisition circuit 1 with the coherent integration point number, and outputs the signal after the coherent integration point. The signal is output to the signal analysis circuit 5.
Thereby, the influence of the unnecessary signal included in the signal acquired by the signal acquisition circuit 1 is reduced, and the signal whose SN ratio is improved is given to the signal analysis circuit 5.
The signal analysis circuit 5 analyzes the signal after the coherent integration by the coherent integration circuit 4.
For example, when the signal processing device is mounted on a radar device, processing for detecting a target from a signal after coherent integration, processing for estimating the motion of the target, processing for generating a radar image, and the like are performed. In addition, motion estimation processing for compensating for unnecessary motion components that blur the radar image is also performed.

  As apparent from the above, according to the first embodiment, the coherent integration point number setting circuit 3 is within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit 2. Thus, the improvement ratio of the SN ratio is calculated when the coherent integration of the signal acquired by the signal acquisition circuit 1 is performed at each integration point, and the integration point number of the coherent integration is set based on the improvement ratio. Since it comprised, even if the phase of a signal is changing quadratic, there exists an effect which can improve an S / N ratio.

Specifically, the following effects can be achieved.
(1) Based on the magnitude of the secondary change in the phase of the received signal, it is possible to set the optimum number of coherent integration points in terms of the improvement ratio of the SN ratio and the achievement probability of the improvement ratio of the SN ratio.
(2) Since it is not necessary to perform integration processing with a plurality of coherent integration points, the processing load is reduced.
(3) Since it is not necessary to detect the spread of the signal on the frequency axis, the application environment is not limited by the S / N ratio conditions.
(4) Since it is not necessary to use the spread of the signal on the frequency axis, adverse effects due to factors other than the secondary change related to the spread of the signal on the frequency axis can be avoided.

In the first embodiment, the secondary change information output from the secondary change information output circuit 2 is information indicating the assumed range of the secondary change in the phase of the signal. For example, the signal processing device Is applied to a radar apparatus, the second-order phase change in the signal is often caused by a distance change caused by relative motion between the target to be observed and the radar apparatus, as described above. For this reason, information regarding relative motion may be output as the secondary change information.
This is not limited to the radar device, and movement is an important factor in positioning using GPS signals, mobile communication, and the like.
Examples that fall into this category include targets and motion sensors mounted on transmission and reception platforms.

Also, a general search radar, tracking radar, or the like can be positioned as a sensor that can perform measurement useful for estimating the relative motion of the target and the radar.
A processing device that smoothes the output of these sensors is also useful as a circuit for assisting the motion sensor.
For example, a tracking processor that estimates the true movement trajectory of a target based on measurement values (for example, distance and direction to the target) obtained by the radar apparatus corresponds to this. The characteristics of the secondary change can be estimated from the error distribution of these processors.
Furthermore, not only such sensor information but also rough information linked to the type / category of the moving object (target, transmission / reception platform, etc.) is effective for obtaining secondary change information.
A data storage device including such information (including not only electronic data but also analog information such as paper) can also be configured as the secondary change information output circuit 2.
Based on such data and information on the category of the mobile object specified or estimated separately, information related to secondary change can be obtained.
For example, information may be output such that the acceleration is at most OOm / s ² when the mobile body is a ship category, and △ Δm / s ² when observing an aircraft.

Embodiment 2. FIG.
In the first embodiment, the achievement probability optimization index setting circuit 16 sets an optimization index related to the achievement probability (ζ, k) calculated by the achievement probability calculation circuit 15, and the coherent integration point number selection circuit 17 achieves the achievement probability. Based on the optimization index set by the probability optimization index setting circuit 16, the coherent integration point number selected by the coherent integration circuit 4 is selected from the plurality of coherent integration point numbers k. The probability optimization index setting circuit 16 sets an optimization index related to the S / N improvement ratio achievement limit achievement probability (achievement probability at the achievement limit of the SN ratio improvement ratio) calculated by the achievement probability calculation circuit 15, and performs coherent integration. Based on the optimization index set by the achievement probability optimization index setting circuit 16, the score selection circuit 17 generates a plurality of coherent products. From the number k, may be selected coherent integration number of coherent integration of the coherent integration circuit 4 performs, it is possible to obtain the same advantages as the first embodiment.
Specifically, it is as follows.

The achievement probability optimization index setting circuit 16 sets an optimization index related to the S / N improvement ratio achievement limit achievement probability Ξ (k) calculated by the achievement probability calculation circuit 15 as shown below.
[Optimization index 1]
An index [optimization index 2] indicating that the number of integration points with the highest S / N ratio improvement ratio is selected under the condition that the S / N improvement ratio achievement limit achievement probability is equal to or higher than a predetermined value.
An index [optimization index 3] indicating that the number of integration points at which the S / N improvement ratio achievement limit achievement probability is the highest is selected under the condition that the improvement ratio of the S / N ratio is a predetermined value or more.
Like F (k, ξ) shown in the equation (22), it changes depending on both the improvement ratio k of the S / N ratio and the S / N improvement ratio achievement limit achievement probability ξ. Indicator

When the achievement probability optimization index setting circuit 16 sets an optimization index, the coherent integration point selection circuit 17 selects a coherent integration performed by the coherent integration circuit 4 from a plurality of coherent integration points k based on the optimization index. Select the number of coherent integration points.
That is, if the optimization index set by the achievement probability optimization index setting circuit 16 is the above optimization index 1, the coherent integration point selection circuit 17 selects the achievement probability calculation circuit from a plurality of coherent integration points k. 15 under the condition that the S / N improvement ratio achievement limit achievement probability １５ (k) calculated by 15 is equal to or greater than a predetermined value, the S / N improvement ratio G (a, k) The coherent integration point number with the highest value is selected, and the coherent integration point number is set in the coherent integration circuit 4.

Further, the coherent integration point selection circuit 17 improves the S / N from the plurality of coherent integration points k if the optimization index set by the achievement probability optimization index setting circuit 16 is the optimization index 2 described above. Under the condition that the S / N improvement ratio G (a, k) calculated by the ratio calculation circuit 14 is equal to or greater than a predetermined value, the S / N improvement ratio achievement limit achievement probability Ξ ( k) The coherent integration point number with the highest value is selected, and the coherent integration point number is set in the coherent integration circuit 4.
Further, the coherent integration point number selection circuit 17 determines that the S / N improvement ratio calculation circuit 14 calculates the S / N improvement ratio calculation circuit 14 if the optimization index set by the achievement probability optimization index setting circuit 16 is the above optimization index 3. An index F (k, ξ) is calculated from the N improvement ratio G (a, k) and the S / N improvement ratio achievement limit achievement probability Ξ (k) calculated by the achievement probability calculation circuit 15, and a plurality of coherent integration points k. Then, the number of coherent integration points with the highest index F (k, ξ) is selected, and the number of coherent integration points is set in the coherent integration circuit 4.

Embodiment 3 FIG.
In the first embodiment, the achievement probability calculation circuit 15 and the achievement probability optimization index setting circuit 16 are implemented. However, the achievement probability calculation circuit 15 and the achievement probability optimization index setting circuit 16 are omitted. Thus, the configuration of the coherent integration point number setting circuit 3 may be simplified.
FIG. 8 is a block diagram showing the coherent integration point number setting circuit 3 of the signal processing apparatus according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in FIG.

The coherent integration point selection circuit 18 selects a coherent integration point number of the coherent integration performed by the coherent integration circuit 4 from a plurality of coherent integration points based on the improvement ratio of the S / N ratio calculated by the S / N improvement ratio calculation circuit 14. Perform the process to select.
In other words, the coherent integration point selection circuit 18 selects a coherent integration point that gives the highest improvement ratio of the SN ratio calculated by the S / N improvement ratio calculation circuit 14 from the plurality of coherent integration points, and the number of the coherent integration points Is set in the coherent integration circuit 4.
The coherent integration point number selection circuit 18 constitutes integration point number selection means.

The S / N improvement ratio characteristics for each secondary change amount used for setting the number of coherent integration points are as shown in FIG.
The third embodiment aims to reduce the processing load by omitting the achievement probability calculation circuit 15 and the achievement probability optimization index setting circuit 16, but the main purpose of the third embodiment is as follows. As in the first embodiment, the number of coherent integration points that can achieve the highest possible SN ratio with the highest possible probability is selected.
In order to perform this strictly, processing such as that in the first embodiment using a distribution of secondary changes is required.

By the way, when FIG.6 (b) is seen, when the fluctuation width of the assumed secondary change is comparatively large (for example, the range of -4-4 [m / s < ² >]), in order to achieve a higher achievement probability. It can be seen that the main issue is to increase the achievement probability in the portion where the secondary change is large. In addition, when the range of the assumed secondary change is very small (for example, a range of −0.2 to 0.2, a range of 1.8 to 2.2, etc.), the optimum coherent within the range It can be seen that the number of integration points does not change greatly.
In such a case, it is inefficient to calculate assuming a large number of secondary change coefficients a _y (y = 1, 2,..., Y).
Therefore, in the third embodiment, the number of coherent integration points is set using the S / N improvement ratio characteristics for each secondary change amount with respect to a smaller number of types of secondary change coefficients _ay .
Hereinafter, a specific setting method will be described.

The desired signal power improvement ratio calculation circuit 12 pays attention to the secondary change having the maximum absolute value within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit. The power improvement ratio of the desired signal is calculated.
The unnecessary signal power improvement ratio calculation circuit 13 pays attention to the secondary change having the maximum absolute value within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit. The power improvement ratio of unnecessary signals and signals is calculated.
When the desired signal power improvement ratio calculation circuit 12 calculates the power improvement ratio of the desired signal and the unnecessary signal power improvement ratio calculation circuit 13 calculates the power improvement ratio of the unnecessary signal, the S / N improvement ratio calculation circuit 14 calculates the desired signal power improvement ratio. The S / N improvement ratio is calculated from the power improvement ratio of the unnecessary signal and the power improvement ratio of the unnecessary signal.

When the S / N improvement ratio calculation circuit 14 calculates the S / N improvement ratio, the coherent integration point selection circuit 18 selects a coherent integration point having the highest S / N improvement ratio from the plurality of coherent integration points k. The coherent integration point is set in the coherent integration circuit 4.
In this way, the S / N improvement ratio is calculated by paying attention to the secondary change having the maximum absolute value, and the coherent integration point number at which the S / N improvement ratio is the highest is selected. It becomes possible to avoid failure of signal accumulation due to coherent integration when the absolute value of the second-order change is maximum, and as a result, improvement in the achievement probability is expected.

Here, the S / N improvement ratio is calculated by calculating the power improvement ratio of the desired signal and the unnecessary signal by paying attention to the secondary change having the maximum absolute value within the assumed range of the secondary change. As shown, the S / N improvement ratio may be calculated by calculating the power improvement ratio of the desired signal and the unnecessary signal while paying attention to an arbitrary secondary change within the assumed range of the secondary change. Good.
In this case, the limitation of the application range is relaxed by removing the condition that the absolute value is the maximum secondary change, but as an example of using the secondary change where the absolute value is not the maximum, the secondary change is a process in the previous stage. In some cases, the S / N improvement ratio characteristics are limited to a sufficiently narrow range so that the S / N improvement ratio characteristics can be regarded as the same.
The setting method described here is effectively equivalent to the case where the achievement probability for each S / N improvement ratio with one secondary change coefficient _ay described in the first embodiment is used. The apparatus configuration is simplified and the processing load is reduced by the amount that is not converted to the achievement probability for each / N improvement ratio.

  In the present invention, within the scope of the invention, any combination of the embodiments, or any modification of any component in each embodiment, or omission of any component in each embodiment is possible. .

  DESCRIPTION OF SYMBOLS 1 Signal acquisition circuit, 2nd order change information output circuit, 3 Coherent integration point setting circuit, 4 Coherent integration circuit, 5 Signal analysis circuit, 11 Secondary change characteristic setting circuit, 12 Desired signal power improvement ratio calculation circuit (Power improvement ratio Calculation means), 13 unnecessary signal power improvement ratio calculation circuit (power improvement ratio calculation means), 14 S / N improvement ratio calculation circuit (S / N improvement ratio calculation means), 15 achievement probability calculation circuit (achievement probability calculation means), 16 Achievement probability optimization index setting circuit (integral point selection means), 17, 18 Coherent integration point selection circuit (integration point selection means).

Claims (14)

A signal acquisition circuit for acquiring a signal for performing coherent integration;
A secondary change information output circuit for outputting secondary change information indicating an assumed range of a secondary change in phase in the signal acquired by the signal acquisition circuit;
When coherent integration of the signal acquired by the signal acquisition circuit is performed at each integration point within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit A coherent integration point number setting circuit that calculates an improvement ratio of the signal-to-noise ratio of and sets the integration point number of coherent integration based on the improvement ratio;
A signal processing device comprising: a coherent integration circuit that performs coherent integration of the signal acquired by the signal acquisition circuit with the integration point set by the coherent integration point setting circuit. The coherent integration point setting circuit is
The above when the coherent integration of the signal acquired by the signal acquisition circuit is performed at each integration point within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit A power improvement ratio calculating means for calculating a power improvement ratio of a desired signal included in the signal and calculating a power improvement ratio of an unnecessary signal included in the signal;
An S / N improvement ratio calculation means for calculating an improvement ratio of the signal-to-noise ratio from the power improvement ratio of the desired signal and the unnecessary signal calculated by the power improvement ratio calculation means;
Integration point number selecting means for selecting an integration point number of the coherent integration performed by the coherent integration circuit from the plurality of integration point numbers based on the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculating unit; The signal processing apparatus according to claim 1, comprising: The power improvement ratio calculation means calculates the power improvement ratio of the desired signal and the unnecessary signal for each secondary change amount within the assumed range,
The S / N improvement ratio calculation means calculates an improvement ratio of the signal-to-noise ratio from the power improvement ratio of the desired signal and the unnecessary signal calculated by the power improvement ratio calculation means for each secondary change amount,
The integration point number selecting means performs a coherent integration circuit from among a plurality of integration points based on the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculation means for each secondary change amount. 3. The signal processing apparatus according to claim 2, wherein the number of integration points for coherent integration is selected. The coherent integration point setting circuit is
For each secondary change amount, it comprises an achievement probability calculating means for calculating the achievement probability of the improvement ratio of the signal to noise ratio calculated by the S / N improvement ratio calculating means,
The integration point number selecting means includes, for each secondary change amount, a plurality of values based on the achievement probability calculated by the achievement probability calculating means and the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculating means. 4. The signal processing apparatus according to claim 3, wherein the number of integration points of coherent integration performed by the coherent integration circuit is selected from the number of integration points. The coherent integration point setting circuit is
An achievement probability calculating means for calculating the achievement probability at the achievement limit of the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculating means for each secondary change amount;
The integration point number selecting means includes, for each secondary change amount, a plurality of values based on the achievement probability calculated by the achievement probability calculating means and the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculating means. 4. The signal processing apparatus according to claim 3, wherein the number of integration points of coherent integration performed by the coherent integration circuit is selected from the number of integration points.   The integration point selection means is a signal-to-noise ratio calculated by the S / N improvement ratio calculation means under the condition that the achievement probability calculated by the achievement probability calculation means is equal to or greater than a predetermined value among a plurality of integration points. 6. The signal processing apparatus according to claim 4, wherein the number of integration points at which the improvement ratio is the highest is selected.   The integration point number selection means is calculated by the achievement probability calculation means from the plurality of integration points under the condition that the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculation means is a predetermined value or more. 6. The signal processing apparatus according to claim 4, wherein the number of integration points with the highest achievement probability is selected.   The integration point selection means calculates an integration point selection index for each secondary change amount from the improvement ratio of the signal-to-noise ratio calculated by the S / N improvement ratio calculation means and the achievement probability calculated by the achievement probability calculation means. 6. The signal processing apparatus according to claim 4, wherein the number of integration points of coherent integration performed by the coherent integration circuit is selected from a plurality of integration points based on the selection index. The power improvement ratio calculation means is
Even if the signal acquired by the signal acquisition circuit includes a second-order phase change component, the maximum limit value of the number of integration points at which the desired signal accumulates in the same Doppler cell by coherent integration of the signal is calculated,
When the number of integration points when performing the coherent integration of the signal is less than or equal to the maximum limit value, the square value of the integration point is calculated as the power improvement ratio of the desired signal, and the integration point number is greater than the maximum limit value 9. The signal processing device according to claim 2, wherein a square value of the maximum limit value is calculated as a power improvement ratio of a desired signal.   The power improvement ratio calculation means performs Fourier transform on a desired signal included in the signal acquired by the signal acquisition circuit for each integration point, converts the signal after Fourier transform into power, 9. The signal processing apparatus according to claim 2, wherein a power improvement ratio of a desired signal is calculated from the medium maximum power and the power of the reference signal.   The power improvement ratio calculation means uses the number of integration points when coherent integration of the signal acquired by the signal acquisition circuit is performed as the power improvement ratio of the unnecessary signal. The signal processing device according to claim 1. The power improvement ratio calculation means pays attention to an arbitrary secondary change within an assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit, and generates a desired signal and an unnecessary signal. Calculate the power improvement ratio of
3. The signal according to claim 2, wherein the S / N improvement ratio calculation means calculates the improvement ratio of the signal-to-noise ratio from the power improvement ratio of the desired signal and the unnecessary signal calculated by the power improvement ratio calculation means. Processing equipment. The power improvement ratio calculating means pays attention to the secondary change having the maximum absolute value within the assumed range of the secondary change of the phase indicated by the secondary change information output from the secondary change information output circuit, and outputs the desired signal. And calculate the power improvement ratio of unnecessary signals,
3. The signal according to claim 2, wherein the S / N improvement ratio calculation means calculates the improvement ratio of the signal-to-noise ratio from the power improvement ratio of the desired signal and the unnecessary signal calculated by the power improvement ratio calculation means. Processing equipment. A signal acquisition processing step in which a signal acquisition circuit acquires a signal for coherent integration; and
A secondary change information output processing step in which a secondary change information output circuit outputs secondary change information indicating an assumed range of a secondary change in phase in the signal acquired in the signal acquisition processing step;
The coherent integration point number setting circuit performs coherent integration of the signal acquired in the signal acquisition processing step within the assumed range of the secondary change of the phase indicated by the secondary change information output in the secondary change information output processing step. A coherent integration point setting processing step for calculating an improvement ratio of the signal-to-noise ratio when performed at each integration point, and setting an integration point number of coherent integration based on the improvement ratio;
A coherent integration circuit, wherein the coherent integration circuit performs coherent integration of the signal acquired in the signal acquisition processing step with the number of integration points set in the coherent integration point setting processing step.

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