JP2014192163A - METHOD FOR MANUFACTURING SiC EPITAXIAL WAFER - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing an SiC epitaxial wafer capable of reducing stacking faults in an SiC epitaxial layer.SOLUTION: A method for manufacturing an SiC epitaxial wafer comprises the steps of: (a) preparing an SiC substrate 1 of a first conductivity type; (b) measuring impurity concentration at a plurality of measurement positions 1p on a surface of the SiC substrate 1; (c) calculating a representative value of impurity concentration of the SiC substrate 1 as representative impurity concentration from the measurement results of the step (b); (d) forming an SiC buffer layer 2 in which impurity concentration of an interface with the SiC substrate 1 is not more than the representative impurity concentration and a difference between the impurity concentration and the representative impurity concentration is less than a prescribed value by epitaxial growth on the SiC substrate 1; and (e) forming an SiC drift layer 3 on the SiC buffer layer 2 by epitaxial growth.

Description

  The present invention relates to a method for manufacturing a SiC epitaxial wafer, and particularly to a technique for suppressing stacking faults in an epitaxial layer.

  Silicon carbide (SiC) has a larger band gap than silicon (Si), and has excellent physical properties such as dielectric breakdown field strength, saturation electron velocity and thermal conductivity, and has excellent properties as a semiconductor power device material. Have. In particular, power devices using this SiC can significantly reduce power loss and reduce size and achieve energy savings during power supply power conversion, resulting in higher performance of electric vehicles and higher functions such as solar cell systems. It has the potential to become a key device in realizing a low-carbon society such as

  In manufacturing a SiC power device, it is essential to previously form an active region of a semiconductor device by epitaxial growth on a SiC substrate by a CVD method (thermal chemical vapor deposition method) or the like. Here, the active region refers to a cross-sectional region including a growth direction axis which is formed after the carrier density and film thickness in the crystal are precisely controlled. The reason why such an epitaxially grown layer is required in addition to the substrate is that the carrier concentration and the film thickness are almost specified by the design specifications of the device, and usually control with higher accuracy than the carrier concentration of the substrate. This is because sex is required.

  A wafer in which an epitaxially grown layer is formed on a SiC substrate is hereinafter referred to as an epitaxial wafer. Since SiC devices are manufactured by performing various processes on an epitaxial wafer, the ratio of the number of devices having desired characteristics manufactured from a single wafer, that is, the so-called element yield, is an electrical property of the epitaxial growth layer. It strongly depends on the uniformity of characteristics. That is, if there is a local region in the epitaxial wafer surface where the breakdown electric field is smaller than other regions or a relatively large current flows when a certain voltage is applied, the region is included. The electrical characteristics of the device will be inferior. For example, the withstand voltage characteristics are poor, and so-called leakage current flows even at a relatively small applied voltage. In other words, the factor that primarily defines the device yield is the crystallographic uniformity of the epitaxial wafer. As a factor that hinders the uniformity, the existence of stacking faults caused by defects during epitaxial growth is known.

  A feature of the crystal defects called stacking faults described above is that the periodicity of atomic arrangement in the crystal is locally incomplete along the crystal growth direction. The stacking fault caused by the epitaxial growth of SiC exists inside the epitaxial growth layer, and is known as a device killer defect that causes a fatal fault in the device.

  The SiC crystal has a specific periodicity called a polytype. That is, even when the stoichiometric composition is one-to-one between Si and C and the crystal lattice is a hexagonal close-packed structure, there is another kind of periodicity in the atomic arrangement along the c-axis in this structure. To do. The physical properties of SiC are defined by the periodicity on the atomic scale and the symmetry of the crystal lattice. The SiC crystal currently attracting the most attention from the viewpoint of device application is a type called 4H-SiC. In order to epitaxially grow the same crystal type, the surface of the silicon carbide bulk substrate is set to a plane inclined from a certain plane orientation of the crystal, and is generally 8 ° in the <11-20> direction, for example, from the (0001) plane. Alternatively, it is processed to have a surface inclined by 4 °.

  Several methods for improving the crystallinity of such a silicon carbide bulk substrate and a carbonized epitaxial growth layer have been proposed. In Patent Document 1, an n-type buffer layer (epitaxial layer) having an impurity concentration intermediate between both is formed between a SiC substrate and an n-type SiC active layer (epitaxial layer) thereon, so that the SiC substrate and the epitaxial layer are epitaxially formed. Strain caused by the difference in impurity concentration at the interface of the layers is suppressed, and the flatness of the epitaxial growth layer surface is improved.

  Further, in Patent Document 2, in a SiC substrate having a base substrate and a drift layer having a lower impurity concentration than the base substrate, a basal plane dislocation density is formed by forming a buffer layer having a lower impurity concentration than the drift layer between them. We are trying to reduce it.

  Further, in Patent Document 3, in order to improve the crystal quality of the epitaxial growth layer, a buffer layer having a multilayer structure is formed between the n-type SiC substrate doped with a concentration C and the n-type SiC epitaxial growth layer doped with a concentration lower than that of the substrate. Propose to form. The buffer layer is formed in a multilayer structure in which two or more layers having the same thickness are stacked. When the number of layers in the multilayer structure is N, the doping concentration of the Kth layer from the epitaxial layer side is C · K / (N + 1). It is prescribed.

  Non-Patent Document 1 describes that in a silicon carbide crystal, the lattice constant of the crystal varies depending on the impurity concentration.

JP 2006-066722 A JP 2009-088223 A WO2011-083552

H. Jacobson et al, Doping-induced strain in N-doped 4H-SiC crystals, APPLIED PHYSICS LETTERS, MAY 2003, VOLUME 82, pp3689-3691.

  However, according to the inventions described in Patent Documents 1 and 3, since the in-plane distribution of the impurity concentration of the SiC substrate is not taken into account, distortion caused by lattice mismatch is effectively reduced, and stacking faults are reduced. It was difficult to reduce.

  In addition, according to the invention described in Patent Document 2, lattice mismatch between the drift layer and the SiC base substrate becomes significant, and it is difficult to reduce stacking faults.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method for manufacturing a SiC epitaxial wafer that reduces stacking faults in a SiC epitaxial layer.

  The SiC epitaxial wafer manufacturing method of the present invention includes (a) a step of preparing a first conductivity type SiC substrate, (b) a step of measuring impurity concentrations at a plurality of locations on the surface of the SiC substrate, and (c) step. A step of obtaining a representative value of the impurity concentration of the SiC substrate as a representative impurity concentration by a predetermined calculation process from the measurement result of (b); and (d) the impurity concentration at the interface with the SiC substrate on the SiC substrate is the representative impurity concentration. And a step of forming an SiC buffer layer having a difference from the representative impurity concentration less than a predetermined value by epitaxial growth, and (e) a step of forming an SiC drift layer on the SiC buffer layer by epitaxial growth.

  The SiC epitaxial wafer manufacturing method of the present invention includes (a) a step of preparing a first conductivity type SiC substrate, (b) a step of measuring impurity concentrations at a plurality of locations on the surface of the SiC substrate, and (c) step. A step of obtaining a representative value of the impurity concentration of the SiC substrate as a representative impurity concentration by a predetermined calculation process from the measurement result of (b); and (d) the impurity concentration at the interface with the SiC substrate on the SiC substrate is the representative impurity concentration. And a step of forming an SiC buffer layer having a difference from the representative impurity concentration less than a predetermined value by epitaxial growth, and (e) a step of forming an SiC drift layer on the buffer layer by epitaxial growth. By considering the in-plane distribution of the impurity concentration of the SiC substrate, the impurity concentration of the SiC buffer layer can be set appropriately, so that stacking faults in the SiC buffer layer and the SiC drift layer are suppressed, and the yield of the SiC epitaxial wafer is reduced. Will improve.

It is sectional drawing which shows the structure of a SiC epitaxial wafer. It is a figure which shows the impurity concentration distribution in a SiC substrate surface. It is a top view of the SiC substrate which shows the measurement location of impurity concentration distribution. It is a figure which shows the relationship between the impurity concentration of a buffer layer, and a stacking fault density. It is a flowchart which shows the manufacturing method of an epitaxial wafer. It is a figure which shows the structure of an epitaxial wafer, and the impurity concentration of each layer. It is a figure which shows the structure of the modification of an epitaxial wafer, and the impurity concentration of each layer. It is a figure which shows the structure of the modification of an epitaxial wafer, and the impurity concentration of each layer. It is a figure which shows the structure of the modification of an epitaxial wafer, and the impurity concentration of each layer. It is a figure which shows the structure of the modification of an epitaxial wafer, and the impurity concentration of each layer.

  As a result of intensive studies on the cause of stacking faults that adversely affect the device, the inventors of the present application clearly show that the stacking fault density increases as the difference in impurity concentration between the SiC substrate and the SiC epitaxial growth layer increases. did. Here, the stacking fault density means the number of stacking faults divided by the effective substrate area (the area of the region excluding the edge 3 mm from the entire substrate).

  Further, Non-Patent Document 1 reports that there is a dependency between the impurity concentration and the lattice constant of the SiC crystal, and the lattice constant increases as the impurity concentration decreases. Therefore, it is considered that an essential cause of the stacking fault is a stress caused by strain generated by lattice mismatch between the SiC substrate and the SiC epitaxial growth layer. For this reason, as the SiC substrate increases in diameter to 6 inches and 8 inches in the future, the density of current leakage defects due to stress in the substrate surface may become a serious problem.

<A. Embodiment 1>
FIG. 1 is a cross-sectional view showing the structure of the SiC epitaxial wafer of the first embodiment. The SiC epitaxial wafer includes a SiC substrate 1, a SiC buffer layer 2 formed by epitaxial growth on the Si surface or C surface of the SiC substrate 1, and a SiC drift layer 3 formed by epitaxial growth on the SiC buffer layer 2. Yes.

  The SiC substrate 1 is produced, for example, by slicing and mirror-polishing an ingot grown by a sublimation method, but it is difficult to control the impurity concentration when growing the ingot. It is known as a general problem that the concentration has a large distribution. FIG. 2 shows a typical example of the distribution along the X axis of the impurity concentration of the SiC substrate 1 obtained from the capacitance-voltage characteristics using the Hg probe. From this, it can be seen that the impurity concentration is clearly different between the high concentration region and the low concentration region of the SiC substrate 1. Moreover, as a result of investigating the in-plane distribution of the impurity concentration of a number of SiC substrates 1, it has been found that the position and range of the high-concentration region vary depending on the substrate.

  For this reason, it is very difficult to determine the impurity concentration of SiC buffer layer 2 that can effectively reduce the lattice mismatch at the interface with the SiC substrate corresponding to the impurity concentration distribution of SiC substrate 1. Therefore, as a result of further diligent research by the present inventors, a method for determining the impurity concentration of the SiC buffer layer 2 corresponding to a change in the impurity concentration high concentration region of the SiC substrate 1 has been devised.

<A-1. Method for Determining Impurity Concentration of Buffer Layer>
In the SiC epitaxial wafer manufacturing method of the present embodiment, in order to consider the in-plane impurity concentration distribution of SiC substrate 1, representative impurity concentration N _rep of SiC substrate 1 is obtained, and SiC buffer layer 2 of SiC buffer layer 2 is determined from representative impurity concentration N _rep . Impurity concentration N _buf is determined.

A method for calculating the representative impurity concentration N _rep of SiC substrate 1 will be described. First, a grid-like point on the surface of the SiC substrate 1 shown in FIG. 3 is set as a measurement location 1p, and capacitance-voltage measurement is performed on each measurement location 1p. The interval between adjacent measurement points 1p is, for example, 1 cm in length and width. Then, the maximum value N _max and the minimum value N _min of the impurity concentration in the surface of the SiC substrate 1 are clarified, and an impurity concentration of 90% or more of the maximum value N _max is defined as the high concentration region. When the area of the high concentration region is A and the area of the SiC substrate 1 is B, the representative impurity concentration N _rep of the SiC substrate 1 is N _rep = (A / B) × N _max + (1−A / B) × N _{It is calculated as min} . Although the impurity concentration of 90% or more of the maximum value _Nmax is defined as the high concentration region here, the threshold value that defines the high concentration region may be 80% to 95% of the maximum value _Nmax .

  As a characteristic of the SiC substrate, it is known that there is a correlation between the optical characteristics of the substrate and the impurity concentration. Therefore, instead of the capacitance-voltage measurement, the impurity concentration at each measurement location 1p may be obtained by measuring the optical characteristics of the SiC substrate 1 whose correlation with the impurity concentration is known. If the correlation between the optical characteristics and the impurity concentration is converted into data by photographic analysis or the like, the impurity concentration in the surface of the SiC substrate 1 can be easily obtained from the measurement result of the substrate optical characteristics.

FIG. 4 shows the relationship between stacking faults occurring in the epitaxial layer and the impurity concentration N _buf of the SiC buffer layer 2. The horizontal axis is the difference of representative impurity concentration _{N rep} and impurity concentration of the SiC buffer layer 2 _{N buf} of the SiC substrate 1, the vertical axis indicates the stacking fault density of the epitaxial layer. From FIG. 4, it is necessary to _satisfy (N _rep −N _buf ) ≦ 4.6 × 10 ¹⁸ / cm ^{3 in order} to reduce the stacking fault density to less than 0.2 / cm ² . However, if (N _rep −N _buf ) = 0, the lattice mismatch between the SiC substrate 1 and the SiC buffer layer 2 cannot be relaxed, so at least (N _rep > N _buf ) is required. Therefore, if the impurity concentration N _buf of the SiC buffer layer 2 is set so as to satisfy (N _rep −4.6 × 10 ¹⁸ ) ≦ N _buf <N _rep , an epitaxially grown wafer having a very low stacking fault density can be obtained. If the stacking fault density is 0.2 / cm ² , an extremely high yield of 80% can be obtained when manufacturing a large-area device of 1 cm ² .

<A-2. Manufacturing method>
A SiC epitaxial wafer manufacturing method using the buffer layer impurity concentration N _buf described above will be described with reference to the flowchart shown in FIG.

First, the SiC substrate 1 is prepared (step S1). The SiC substrate 1 is a 4H—SiC n-type substrate doped with nitrogen at an average impurity concentration of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. The substrate thickness is not less than 300 μm and less than 400 μm, and has an inclination angle from the (0001) plane.

  Next, a planarization process is performed on the SiC substrate 1 by mechanical polishing and chemical mechanical polishing (CMP) using a chemical solution showing acidity or alkalinity (step S2).

Thereafter, capacitance-voltage measurement is performed at a plurality of measurement locations 1p on the surface of the SiC substrate 1. The maximum value N _max and the minimum value N _min of the impurity concentration in the surface of the SiC substrate 1 are clarified, and a region where the impurity concentration is 90% or more of the maximum value Nmax is defined as a high concentration region. From the area A of the high concentration region and the area B of the entire SiC substrate, the representative impurity concentration N _rep = (A / B) × N _max + (1−A / B) × N _min of the SiC substrate 1 is obtained. The substrate planarization process (step S1) may be performed after the step of calculating the representative impurity concentration N _rep (step S3). Further, the measurement of the impurity concentration at each measurement location 1p (step S2) may be performed on either the Si surface or the C surface of the SiC substrate 1.

  Once the representative impurity concentration of the SiC substrate 1 is obtained, aqua regia cleaning is performed (step S4). By immersing in a mixed solution of nitric acid and hydrochloric acid (1: 3) for about 30 minutes, metals such as mercury adhering to the surface of the SiC substrate 1 are removed.

  Further, RCA cleaning, that is, cleaning with a mixed solution of hydrofluoric acid and pure water is performed on SiC substrate 1 (step S5).

  After cleaning, the SiC substrate 1 is placed in a reaction furnace of a CVD apparatus and heated to a desired heating temperature. Then, hydrogen is used as a carrier gas and a cleaning gas for the surface of the SiC substrate, and monosilane and propane are used as material gases. Then, nitrogen is introduced as a dopant gas to form SiC epitaxial layers (SiC buffer layer 2 and SiC drift layer 3) (step S6).

The structure and impurity concentration of the SiC epitaxial wafer formed by the above steps are as shown in FIG. The film thickness and concentration of SiC drift layer 3 are determined by the type of device to be produced. The impurity concentration N _buf of the SiC buffer layer 2 has an intermediate value between the SiC substrate 1 and the SiC drift layer 3 and has a relationship of (N _rep −4.6 × 10 ¹⁸ ≦ N _buf <N _rep ). .

  Through the above steps, a SiC epitaxial growth wafer with extremely low density of stacking faults, which are device killer defects, is produced.

<A-3. Modification>
FIG. 6 shows that the impurity concentration of the SiC buffer layer 2 is constant in the thickness direction. However, as shown in FIG. 7, the impurity concentration at the interface with the SiC substrate 1 to the impurity concentration of the SiC drift layer 3 may be reduced gradually or stepwise as the SiC drift layer 3 is approached. Thereby, the stacking fault density can be further reduced.

  Note that a desired profile of the impurity concentration can be obtained by appropriately setting the epitaxial growth conditions in step S6.

Further, although FIG. 7 shows one SiC buffer layer 2, a SiC buffer layer having a multilayer structure as shown in FIG. 8 may be used. When the representative impurity concentration N _rep of the SiC substrate 1 is as high as, for example, 9.2 × 10 ¹⁸ / cm ³ or more, the SiC buffer layer 2 has the impurity concentration of the SiC buffer layer 2 and the SiC drift layer 3. Since the difference becomes large, the lattice mismatch at the interface between the SiC buffer layer 2 and the SiC drift layer 3 cannot be alleviated. Therefore, a two-layer structure of SiC buffer layers 2a and 2b is adopted, and the impurity concentration is reduced in two steps, thereby reducing the difference in impurity concentration between SiC buffer layer 2b and SiC drift layer 3 and stacking in SiC drift layer 3 It is possible to reduce the defect density. In this case, upper SiC buffer layer 2b has the same conductivity type as lower SiC buffer layer 2a, and has a lower carrier concentration than SiC buffer layer 2a.

  Further, the impurity concentration distribution of the upper SiC buffer layer 2b may be gradually decreased toward the SiC drift layer 3 as in the SiC buffer layer 2 of FIG. 7, or may be decreased stepwise. (FIG. 9).

  Further, the SiC buffer layer is not limited to the two-layer structure, and may be formed in a multilayer structure having an arbitrary number of layers. FIG. 10 shows an example in which the SiC buffer layer has a three-layer structure of SiC buffer layers 2a, 2b, and 2c in order from the SiC substrate 1 side. As shown in FIG. 10, the impurity concentration distribution of the uppermost SiC buffer layer 2c may be gradually decreased toward the SiC drift layer 3 side or may be decreased stepwise.

<A-4. Effect>
The SiC epitaxial wafer manufacturing method of the first embodiment includes (a) a step of preparing a first conductivity type SiC substrate 1, and (b) a step of measuring impurity concentrations at a plurality of locations on the surface of the SiC substrate 1, (C) A step of obtaining the representative value of the impurity concentration of the SiC substrate 1 as the representative impurity concentration from the measurement result of the step (b), and (d) the impurity concentration at the interface with the SiC substrate 1 on the SiC substrate 1 is representative. A step of forming an SiC buffer layer 2 (2a, 2b, 2c) having an impurity concentration equal to or lower than the representative impurity concentration and less than a predetermined value by epitaxial growth (for example, CVD); (e) the SiC buffer layer 2 (2b) 2c) forming a SiC drift layer 3 on the first layer by epitaxial growth. The SiC buffer layer 2 is of the first conductivity type. By considering the in-plane distribution of the impurity concentration of the SiC substrate 1 as described above, the impurity concentration of the SiC buffer layer 2 (2a) can be set appropriately, so that the SiC buffer layer 2 (2a, 2b, 2c) And stacking faults in the SiC drift layer 3 are suppressed, and the yield of the SiC epitaxial wafer is improved.

  The step (c) is a step (c1) of measuring the area of the high concentration region by setting a region having an impurity concentration of 90% or more of the maximum value among a plurality of locations on the surface of the SiC substrate 1 as a high concentration region. (C2) A value obtained by multiplying the area ratio of the high concentration region with respect to the SiC substrate 1 by the maximum value of the impurity concentration, and a value obtained by multiplying the area ratio of the region other than the high concentration region with respect to the SiC substrate 1 by the minimum value of the impurity concentration. And a step of setting the value obtained by adding to the representative impurity concentration. By considering the in-plane distribution of the impurity concentration of the SiC substrate 1 as described above, the impurity concentration of the SiC buffer layer 2 (2a) can be set appropriately, so that the SiC buffer layer 2 (2a, 2b, 2c) And stacking faults in the SiC drift layer 3 are suppressed, and the yield of the SiC epitaxial wafer is improved.

  In the step (b), the impurity concentration can be measured from the capacitance-voltage characteristics at a plurality of locations on the surface of the SiC substrate 1.

  Alternatively, in the step (b), the optical characteristics of the SiC substrate 1 whose correspondence relationship with the impurity concentration of the SiC substrate 1 is known are measured, and the impurity concentration is determined from the measurement result of the optical characteristics of the SiC substrate 1 based on the correspondence relationship. May be calculated.

  Further, in the step (d), the impurity concentration of the SiC buffer layer 2 (2a, 2b, 2c) is gradually decreased in a stepped or stepped manner as it goes away from the interface with the SiC substrate 1, or a combination thereof. SiC buffer layer 2 (2a, 2b, 2c) is formed. Thereby, the stacking fault density can be further reduced.

The SiC substrate 1 prepared in the step (a) has a representative impurity concentration obtained in the step (c) of 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. Also, a 4H—SiC SiC substrate 1 is used. By appropriately setting the impurity concentration of the SiC buffer layer 2 (2a) for such a SiC substrate 1, stacking faults in the SiC buffer layer 2 (2a, 2b, 2c) and the SiC drift layer 3 are suppressed. The yield of the SiC epitaxial wafer is improved.

  In addition, in the method of manufacturing an SiC epitaxial wafer according to the present embodiment, the surface of SiC substrate 1 is subjected to chemical mechanical treatment between steps (a) and (b) or between steps (b) and (c). Since the step of planarizing by polishing is provided, it is possible to perform epitaxial growth with high accuracy by performing epitaxial growth from the planarized surface.

  In the present invention, the embodiments can be appropriately modified and omitted within the scope of the invention.

  1 SiC substrate, 1p measurement location, 2, 2a, 2b, 2c buffer layer, 3 drift layer.

Claims (10)

(A) preparing a first conductivity type SiC substrate;
(B) measuring impurity concentrations at a plurality of locations on the surface of the SiC substrate;
(C) obtaining a representative value of the impurity concentration of the SiC substrate from the measurement result of the step (b) as a representative impurity concentration;
(D) forming an SiC buffer layer on the SiC substrate by epitaxial growth having an impurity concentration at the interface with the SiC substrate equal to or lower than the representative impurity concentration and a difference from the representative impurity concentration being less than a predetermined value; ,
(E) forming a SiC drift layer on the SiC buffer layer by epitaxial growth.
Manufacturing method of SiC epitaxial wafer. The step (c)
(C1) A step of setting a region having an impurity concentration of 90% or more of the maximum value among a plurality of locations on the surface of the SiC substrate as a high concentration region, and measuring an area of the high concentration region;
(C2) The value obtained by multiplying the area ratio of the high concentration region with respect to the SiC substrate by the maximum value of the impurity concentration and the area ratio of the region other than the high concentration region with respect to the SiC substrate are multiplied by the minimum value of the impurity concentration. And adding the value obtained by adding the obtained value to the representative impurity concentration,
The manufacturing method of the SiC epitaxial wafer of Claim 1. The step (b) is a step of measuring the impurity concentration from capacitance-voltage characteristics at a plurality of locations on the surface of the SiC substrate.
The manufacturing method of the SiC epitaxial wafer of Claim 1 or 2. The step (b)
(B1) measuring optical characteristics of the SiC substrate whose correspondence with the impurity concentration of the SiC substrate is known;
(B2) calculating the impurity concentration from the measurement result of the optical characteristics of the SiC substrate based on the correspondence relationship,
The manufacturing method of the SiC epitaxial wafer of Claim 1 or 2. The step (d) is a step of forming the SiC buffer layer so that the impurity concentration of the SiC buffer layer decreases gradually, stepwise, or a combination thereof as the distance from the interface with the SiC substrate increases. Is,
The manufacturing method of the SiC epitaxial wafer in any one of Claims 1-4. The step (a) is a step of preparing the SiC substrate in which the representative impurity concentration obtained in the step (c) is 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.
The manufacturing method of the SiC epitaxial wafer in any one of Claims 1-5. The step (d) is a step of forming the SiC buffer layer of the first conductivity type.
The manufacturing method of the SiC epitaxial wafer in any one of Claims 1-6. The step (d) is a step of forming the SiC buffer layer by a CVD method.
The manufacturing method of the SiC epitaxial wafer in any one of Claims 1-7. The step (a) is a step of preparing the SiC substrate of 4H—SiC.
The manufacturing method of the SiC epitaxial wafer in any one of Claims 1-8. (F) The method further includes a step of planarizing the surface of the SiC substrate by chemical mechanical polishing between the steps (a) and (b) or between the steps (b) and (c).
The manufacturing method of the SiC epitaxial wafer in any one of Claims 1-9.

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