JP2014175647A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

A semiconductor device and a method of manufacturing the same that secures a short margin between a contact and a gate electrode and suppresses a short circuit between the contact holes formed by self-alignment technology even when the contact holes are formed with a deviation from a predetermined position. I will provide a.
A semiconductor substrate SUB, a gate electrode GE, an insulating layer IL, and an interlayer insulating film II1 are provided. The gate electrode GE includes a first electrode layer PS and a second electrode layer WS formed on the first electrode layer PS. A contact hole SA having a portion located directly above the gate electrode GE is formed in the interlayer insulating film II1. The insulating layer IL and the interlayer insulating film II1 are made of different materials. The width of the second electrode layer WS is narrower than the width of the insulating layer IL.
[Selection] Figure 6

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Due to high integration and miniaturization, there is an increasing tendency to make a plurality of microelements constituting a semiconductor device overlap in a plan view. Along with the increase in the number of semiconductor devices, a gate electrode of a transistor formed on the surface of a semiconductor substrate and a layer above the transistor are electrically connected by a connection layer called a plug and a conductive layer called a contact. Technology is often used.

  In addition, with high integration and miniaturization, a region between a plurality of transistors formed over the surface of a semiconductor substrate is narrowed. Therefore, depending on the alignment accuracy of processing, there is a high possibility that a contact to be formed immediately above a region between a plurality of transistors is formed at a position shifted from a desired position. If the contact is formed at a shifted position, a short circuit may occur between the contact and the gate electrode adjacent to the contact.

  In order to suppress the above-described problems, the formation of the opening for forming the contact is performed by using the difference in etching selectivity between the materials of the thin film to be formed instead of the conventional normal photolithography technique. Increasing cases are being done by a technique called alignment. A technique for forming an opening by self-alignment is disclosed in, for example, Japanese Patent Application Laid-Open No. 2003-1000076 (Patent Document 1).

  In order to lower the resistance value of the gate electrode, for example, a structure in which two layers of a polycrystalline silicon film and a refractory metal silicide film are laminated is often used. Such a technique is disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-133802 (Patent Document 2).

Japanese Patent Laid-Open No. 2003-1000076 JP 2000-133802 A

  Patent Document 1 describes that the contact hole formed by the self-alignment technique is formed so as to be positioned at the center of a region sandwiched between a pair of adjacent gate electrodes. No consideration is given to the case where the angle is shifted in the left-right direction with respect to the desired position. In Patent Document 1, if the contact hole is formed to be shifted in the left-right direction, the conductive layer in the contact hole and the gate electrode may be short-circuited. Patent Document 2 only describes a two-layer structure of a polycrystalline silicon film and a silicide film, and there is no description about a semiconductor device formed using a self-alignment technique.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes a semiconductor substrate, a gate electrode, an insulating layer, and an interlayer insulating film. The gate electrode includes a first electrode layer and a second electrode layer formed on the first electrode layer. A contact hole having a portion located directly above the gate electrode is formed in the interlayer insulating film. The insulating layer and the interlayer insulating film are made of different materials. The width of the second electrode layer is narrower than the width of the insulating layer.

  According to another embodiment, a method for manufacturing a semiconductor device first includes a first electrode layer and a second electrode layer formed on the first electrode layer on a main surface of a semiconductor substrate. A gate electrode is formed. An insulating layer is formed on the gate electrode, and an interlayer insulating film is formed on the main surface so as to cover the gate electrode and the insulating layer. A contact hole is formed in a portion of the interlayer insulating film located immediately above the gate electrode. The insulating layer and the interlayer insulating film are made of different materials. The width of the second electrode layer is narrower than the width of the insulating layer.

  According to one embodiment and another embodiment, a highly reliable semiconductor device in which a short circuit is suppressed can be provided by using a self-alignment technique.

1 is a schematic plan view of a semiconductor device according to an embodiment. 1 is an equivalent circuit diagram of a memory cell constituting a semiconductor device according to an embodiment. It is a schematic sectional drawing for demonstrating the equivalent circuit of FIG. 2 concretely. Schematic plan view (A) showing the configuration of the same layer as the interlayer insulating film II3 in the memory region, and the overall arrangement of the driver transistor and the access transistor of the interlayer insulating film II3 and the layers below it in the memory region. It is a schematic plan view (B) showing FIG. 5 is a schematic cross-sectional view of the memory region taken along a line VV in FIGS. 3 and 4 when viewed from a direction orthogonal to FIG. 3. It is the schematic sectional drawing which showed the 1st example of the structure of one embodiment more generally than FIG. It is the schematic sectional drawing which showed the 2nd example of the structure of one embodiment more generally than FIG. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in one Embodiment. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in the 1st example shown in FIG. 6 of one embodiment. FIG. 8 is a schematic cross-sectional view showing a third step of the method for manufacturing the semiconductor device in the second example shown in FIG. 7 of the embodiment. FIG. 11 is a schematic cross-sectional view showing a fourth step following FIG. 10 in the method for manufacturing a semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 5th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 6th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 7th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 8th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 9th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 10th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 11th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 12th process of the manufacturing method of the semiconductor device in one embodiment. It is a schematic sectional drawing which shows the 13th process of the manufacturing method of the semiconductor device in one embodiment. It is the schematic sectional drawing which showed the structure of the comparative example more generally than FIG. It is a schematic sectional drawing which shows the process corresponded in FIG. 10 of the manufacturing method of the semiconductor device in a comparative example. It is a schematic sectional drawing which shows the process corresponded in FIG. 12 of the manufacturing method of the semiconductor device in a comparative example. FIG. 3 is a schematic cross-sectional view for defining a width W1 of a tungsten silicide layer and a width W2 of an insulating layer IL. It is a graph which shows the relationship between the width | variety of a tungsten silicide layer, and sheet resistance. It is a schematic sectional drawing which shows the positional relationship of a contact, the gate electrode of a transistor, and an insulating layer.

Hereinafter, an embodiment will be described with reference to the drawings.
Referring to FIG. 1, a semiconductor device DV according to an embodiment is a semiconductor chip in which a plurality of types of circuits are formed on the surface of a semiconductor substrate SUB such as a semiconductor wafer made of silicon single crystal. As an example, the circuit constituting the semiconductor device DV has a memory cell array (memory area), a peripheral circuit area, and a pad area PD.

  The memory cell array is a main memory area of the semiconductor device DV including an SRAM (Static Random Access Memory). A peripheral circuit region and a pad region PD are formed outside the memory cell array in plan view. A plurality of pad regions PD are formed, for example, outside the memory cell array at intervals.

  Next, the structure of the semiconductor device as the present embodiment will be described with reference to the memory cell of FIG.

  Referring to FIG. 2, in the semiconductor device in the present embodiment, an SRAM having a bit line pair BL and ZBL, a word line WL, a flip-flop circuit, and a pair of access transistors T5 and T6 is used as a memory cell. Have.

  The flip-flop circuit has driver transistors T1 and T2 and load transistors T3 and T4. The driver transistor T1 and the load transistor T3 form one CMOS (Complementary Metal Oxide Semiconductor) inverter, and the driver transistor T2 and the load transistor T4 form the other CMOS inverter. The flip-flop circuit is composed of these two CMOS inverters. An SRAM is a semiconductor memory device that has a flip-flop circuit and thus eliminates a process called so-called refresh that restores charges stored as information at a predetermined cycle. The SRAM in the present embodiment further includes capacitors C1 and C2 as DRAMs (Dynamic Random Access Memory).

  Driver transistors T1 and T2 constituting the flip-flop circuit are, for example, n-channel MOS transistors. The load transistors T3 and T4 are, for example, p-channel TFTs (Thin Film Transistors). Access transistors T5 and T6 are, for example, n-channel MOS transistors. As described above, the SRAM of the present embodiment is a so-called Advanced SRAM in which the load transistor is a TFT and a capacitor as a DRAM is added.

  In the flip-flop circuit, the gate electrodes of driver transistor T1 and load transistor T3 and capacitor C1 are electrically connected to each other, and these are electrically connected to source electrode S of access transistor T6. The source electrode S of the access transistor T6 is electrically connected to the drain electrode D of the driver transistor T2 and the load transistor T4, and the region where these are connected functions as a first storage node portion.

  The gate electrodes of driver transistor T2 and load transistor T4 and capacitor C2 are electrically connected to each other, and these are electrically connected to source electrode S of access transistor T5. The source electrode S of the access transistor T5 is electrically connected to the drain electrode D of the driver transistor T1 and the load transistor T3, and the region where these are connected functions as a second storage node portion.

  The source electrodes S of the driver transistors T1 and T2 are electrically connected to the GND potential, and the source electrodes S of the load transistors T3 and T4 are electrically connected to a Vcc wiring (power supply wiring) that applies the voltage Vcc. ing. Further, the capacitors C1 and C2 are electrically connected to a Vcc / 2 wiring that applies a voltage Vcc / 2 that is ½ of the voltage Vcc. Each of the pair of bit lines BL and ZBL is connected to the drain electrodes D of the pair of access transistors T5 and T6.

  Next, a more specific structure of the semiconductor device shown in FIG. 2 will be described with reference to the schematic cross-sectional view of FIG. However, the cross-sectional view of FIG. 3 is not a view showing a cross-sectional aspect in a specific region, but is gathered together to explain the shape of each element such as a transistor and a capacitor shown in FIG. 2 in the semiconductor device. .

  Referring to FIG. 3, the semiconductor device of one embodiment is formed on one main surface of an n-type semiconductor substrate SUB made of, for example, a silicon single crystal.

  A memory region and a peripheral circuit region are formed on the main surface of the semiconductor substrate SUB. The memory area is an area in which the SRAM of FIG. 1 (particularly Advanced SRAM) is formed, and the peripheral circuit area is an area around the area in which the SRAM of FIG. 1 is formed, for example, a signal input / output circuit. It is. Note that the memory region in FIG. 3 is a schematic cross-sectional view taken along the line III-III in FIG. However, as described above, FIG. 3 is merely a collection of each element, and the second contact SC in FIG. 3 and the layers below this are schematically cross-sectional views taken along the line III-III in FIG. Although the figure is faithfully shown, the lower layer wiring 2G in FIG. 3 and each layer above this are not necessarily consistent with the mode of the second contact SC and each layer below this in FIG. Each of the lower layers is shown as an example in which elements such as capacitors existing in each layer are gathered together.

  The memory area has an isolation area and an active area. STI (Shallow Trench Isolation) as an isolation region is formed on a part of the surface of the semiconductor substrate SUB in the memory region. This STI is formed by embedding an insulating layer SI in a groove formed on the surface of the semiconductor substrate SUB.

  A region where no STI is formed other than the isolation region in the memory region is a so-called active region. A plurality of active regions are formed on the surface of the semiconductor substrate SUB, for example, so as to be sandwiched between isolation regions formed on one end side and the other end side opposite to the one end side. . The active region is formed in, for example, a p-type well region PWL into which p-type conductive impurities are implanted. In this case, one active region in the memory region and another active region adjacent to the one active region are electrically connected to each other by an isolation region sandwiched between the one active region and the other active region. Separated.

  A plurality of (n-type) MOS transistors are formed on the surface of the semiconductor substrate SUB in each active region, and the transistor has a pair of source / drain regions S / D. For example, the left and right regions S / D of the memory region in FIG. 3 are the source region S of the access transistor (corresponding to the source electrode S in FIG. 2) and the drain region D of the driver transistor (corresponding to the drain electrode D in FIG. 2). Are overlapping regions, and the access transistor and the driver transistor share the region S / D. These regions S / D correspond to the active regions in FIG. This is apparent by referring to FIGS. 4B and 5 described later. A region D formed in the central active region in FIG. 3 is the drain region D of the access transistors T5 and T6 and is connected to the bit line BL as will be described later, although not shown in FIG.

  An interlayer insulating film II1 made of, for example, a silicon oxide film is formed so as to cover the main surface of the semiconductor substrate SUB on which the insulating layer SI and the like are formed. A plurality of plug conductive layers BS are formed at the same interval as the same layer as the interlayer insulating film II1. Plug conductive layer BS is formed of, for example, polycrystalline silicon to which a conductive impurity is added to fill in an opening formed in a partial region of interlayer insulating film II1. Plug conductive layer BS has, for example, a direction in which a relatively lower region of interlayer insulating film II1 is orthogonal to the main surface so as to reach a pair of source / drain regions S / D on the main surface of semiconductor substrate SUB (FIG. 3). In the vertical direction).

  An interlayer insulating film II2 made of, for example, a silicon oxide film is formed on the interlayer insulating film II1, and an interlayer insulating film II3 made of, for example, a silicon oxide film is formed in contact with the upper surface of the interlayer insulating film II2. . Further thereon, interlayer insulating films II4, II5, II6 made of, for example, silicon oxide films are sequentially formed. Further, an interlayer insulating film I1 made of, for example, a silicon nitride film is formed so as to be in contact with the upper surface of the interlayer insulating film II6. Further, interlayer insulating films II7, II8, II9, and II10 made of, for example, a silicon oxide film are sequentially formed so as to be in contact with the upper surface of the interlayer insulating film I1.

  A plurality of (for example, five) bit lines BL are formed on the interlayer insulating film II2 so as to be in contact with each other (so as to be in contact with the upper surface). The bit line BL extends in the depth direction of the paper surface of FIG. A covering insulating film CL is formed so as to cover the upper surface and side surfaces of the bit line BL, and a wiring structure LE including the bit line BL and the covering insulating film CL (including a side wall insulating film SW described later) is formed. . Bit line BL is electrically connected to drain region D of access transistors T5 and T6 at the center of the memory region of FIG. 3, for example, by a contact conductive layer (not shown).

  The bit line BL is a mixture of what functions as a so-called bit line and what functions as a ground line. For example, five bit lines BL are arranged in FIG. 3, but three of them can function as bit lines and the other two can function as ground lines.

  An interlayer insulating film II3 is formed so as to cover the interlayer insulating film II2 and the wiring structure LE, and a lower layer wiring 2G is formed on the interlayer insulating film II3. The lower layer wiring 2G corresponds to the first and second storage node portions in FIG.

  A first contact 1B and a second contact SC are formed as the same layer as the interlayer insulating films II1 and II2 in the memory region. Here, the first contact 1B and the second contact SC are collectively defined as a contact CT.

  Similar to the plug conductive layer BS, the contact CT is formed of, for example, polycrystalline silicon to which a conductive impurity is added, filling the opening formed in a partial region of the interlayer insulating film II1. Contact CT is formed so as to extend in a direction perpendicular to the main surface in a relatively upper region of interlayer insulating film II1 so as to reach plug conductive layer BS, for example.

  More specifically, the first contact 1B extends from the bit line BL in a direction perpendicular to the main surface so as to pass through the interlayer insulating films II2 and II1 and reach the plug conductive layer BS immediately below. Second contact SC extends in a direction orthogonal to the main surface so as to pass through interlayer insulating films II3, II2 and II1 and reach plug conductive layer BS immediately below from lower layer wiring 2G. The second contact SC passes through a region between a pair of adjacent wiring structures LE in FIG.

  The lower layer wiring 2G is a wiring arranged to electrically connect a capacitor formed in an upper layer and a transistor formed in a lower layer by, for example, the second contact SC. The lower layer wiring 2G is preferably formed in a region that generally overlaps the capacitor in plan view. Lower layer wiring 2G is preferably composed of, for example, a polycrystalline silicon film having impurity ions. When the transistor formed in the lower layer is, for example, an n-channel transistor, the lower layer wiring 2G is made of, for example, polycrystalline silicon containing n-type impurity ions in order to facilitate electrical connection with the transistor TG. It may be configured.

  A polycrystalline silicon layer TP is formed on the interlayer insulating film II4. The polycrystalline silicon layer TP is a semiconductor layer made of polycrystalline silicon into which impurity ions are introduced, and a channel region of a TFT as SRAM load transistors T3 and T4 (see FIG. 2) and a pair of sandwiching the channel region Source / drain regions. The polycrystalline silicon layer TP includes a part of power supply wiring for supplying power to the TFT. The polycrystalline silicon layer TP is preferably formed in a region that generally overlaps the capacitor in plan view.

  A TFT gate electrode layer TD is formed on the interlayer insulating film II5. The gate electrode layer TD is preferably a semiconductor layer containing polycrystalline silicon having impurity ions.

  The electrical connection between the gate electrode layer TD and the lower layer wiring 2G is preferably made by a conductive layer called a data node contact DB. The data node contact DB is in contact with the end portion of the polycrystalline silicon layer TP and is electrically connected to the polycrystalline silicon layer TP while extending from the gate electrode layer TD toward the lower layer wiring 2G. The data node contact DB is a conductive layer for forming an SRAM flip-flop circuit (cross couple), and is formed of a semiconductor layer containing polycrystalline silicon having impurity ions, for example, like the gate electrode layer TD. The data node contact DB is preferably formed so as to extend from the gate electrode layer TD to the lower layer wiring 2G in a direction substantially perpendicular to the surface of the semiconductor substrate SUB so as to penetrate the interlayer insulating film.

  The data node contact DB may be formed to electrically connect a layer above the gate electrode layer TD, for example, the gate electrode layer TD and the capacitor, and a layer below the lower layer wiring 2G, for example, the lower layer wiring 2G. The plug conductive layer BS may be formed so as to be electrically connected. In this case, the data node contact DB may be formed so as to penetrate the gate electrode layer TD, the polycrystalline silicon layer TP, and the lower layer wiring 2G from the capacitor and reach the plug conductive layer BS, for example.

  A capacitor is formed on the interlayer insulating film II6. The capacitor is electrically connected to the data node contact DB by contacting the upper surface of the data node contact DB.

  Metal interconnection MTL is formed above the capacitor, for example, on interlayer insulating film II8 and interlayer insulating film II9. Metal interconnection MTL is preferably made of, for example, aluminum, an aluminum-copper alloy, copper, tungsten, or the like, and its upper and lower surfaces are preferably covered with a barrier metal BRL made of, for example, tantalum, titanium, titanium nitride, or the like. Further, the connection between the metal wirings MTL and the connection between the metal wiring MTL and the bit line BL are preferably made by a metal contact conductive layer MCT made of, for example, copper or tungsten.

  On the other hand, in the peripheral circuit region, for example, an n-type well region NWL into which an n-type conductive impurity is implanted is formed, but this may be a p-type well region PWL. The peripheral circuit region also has an isolation region and an active region like the memory region. An STI made of an insulating layer SI is formed on a part of the surface of the semiconductor substrate SUB in the isolation region. A plurality of (p-type) MOS transistors TG are formed on the surface of the semiconductor substrate SUB in the active region. The transistor TG has a pair of source / drain regions S / D, a gate insulating film GI, a gate electrode GE, and an insulating layer IL. Each of the pair of source / drain regions S / D is formed on the surface of the semiconductor substrate SUB. The gate insulating film GI is formed on the surface of the semiconductor substrate SUB sandwiched between the pair of source / drain regions S / D. The gate electrode GE and the insulating layer IL are formed on the gate insulating film GI, and has a stacked structure in which the gate electrode GE and the insulating layer IL are stacked in this order. The gate electrode GE has, for example, a so-called polycide structure in which a polycrystalline silicon layer PS and a tungsten silicide layer WS are stacked in this order. The insulating layer IL is made of, for example, a silicon oxide film and / or a silicon nitride film, and the gate electrode GE is etched using the insulating layer IL as a mask. A sidewall insulating film SW is formed on the sidewalls of the gate electrode GE and the insulating layer IL. Sidewall insulating film SW is preferably made of, for example, a silicon nitride film, but may be a combination of a silicon oxide film and a silicon nitride film. The insulating film IL and the sidewall insulating film SW serve as etching stopper films when performing the self-alignment technique in the memory cell portion.

  In FIG. 3, the insulating layer IL is formed over the gate electrode GE. However, the gate electrode GE is electrically connected to other wirings in a region extending in the depth direction of the paper not shown in the cross-sectional view of FIG. . Although not described in detail, each transistor TG in the peripheral circuit region includes a metal wiring MTL via a contact conductive layer CTC, a conductive layer as the same layer as the bit line BL, and a metal contact conductive layer MCT. And are electrically connected.

  Next, the aspect of the layer in which the transistor TG is formed in the semiconductor device shown in FIG. 3 will be described in more detail with reference to FIGS.

  Referring to FIGS. 4A and 4B, these illustrate aspects such as bit line BL (wiring structure LE) and plug conductive layer BS in the same region in the memory region of the semiconductor device of FIG. 3 from different viewpoints. It is a thing. Further, within the range shown in the figure, the pattern of each component is arranged so as to be symmetric with respect to a straight line (indicated by a dotted line) extending in the left-right direction at the center in the vertical direction of the figure. In the area below the straight line (shown by a dotted line), the pattern of each component in the unit cell is repeated in a plane with the unit cell surrounded by a rectangle in the figure as a unit.

  FIG. 4B basically shows the configuration of the interlayer insulating film II3 and the layers below it in the memory region, but some of the components are omitted. For example, FIG. 4B does not show the plug conductive layer BS.

  Referring mainly to FIG. 4A, the plurality of bit lines BL extending in the vertical direction in the drawing corresponds to the plurality of bit lines BL extending in the depth direction of the drawing in FIG. By forming the sidewall insulating film SW on the side surface, the wiring structure LE is formed. A plurality of second contacts SC are formed in a region sandwiched between a pair of bit lines BL adjacent to each other in the left-right direction in the figure. Note that the gate electrode GE is also formed in a region overlapping the insulating layer SI (isolation region) in FIG. 3 other than the active region in the memory region, for example. For example, the gate electrode GE in this isolation region is such that the gate electrodes GE of the driver transistors T1, T2 in the active region of FIG. 2 extend to the isolation region in plan view.

  4B and 5, a contact plug conductive layer CG is formed on gate electrode GE in the isolation region. The contact plug conductive layer CG is a conductive layer formed as the same layer as the plug conductive layer BS in the active region, and is formed so as to overlap with the gate electrode GE in the isolation region, so that the gate electrode GE It is used as a contact for taking out to a region. Therefore, the contact plug conductive layer CG is formed in contact with the gate electrode GE. However, since the opening for forming the contact plug conductive layer CG is usually formed not by the self-alignment technique but by the normal photoengraving technique and etching, it slightly deviates from the position of the gate electrode GE. ) Is often formed. In FIG. 5, the contact plug conductive layer CG is formed so as to overlap with the region on the right half of the gate electrode GE (so as to slightly deviate the position in plan view with respect to the gate electrode GE).

  In the isolation region, the second contact SC is formed on the contact plug conductive layer CG so as to planarly overlap the contact plug conductive layer CG. As a result, the second contact SC and the gate electrode GE are electrically connected.

  In FIG. 4A, a plurality of (for example, six) bit lines BL extend (parallel) along the row direction or the column direction with a space therebetween, and a pair of bit lines BL are formed. Five sandwiched areas are shown. Referring also to FIG. 4B, the second contact SC in the center of the five regions sandwiched between the pair of bit lines BL is in the isolation region (insulating layer SI in FIG. 3). In addition, a plurality of second contacts SC in the other regions are formed so as to be electrically connected to the lower layer wiring 2G in FIG.

  Referring mainly to FIG. 4B, a plurality of active regions 1F are formed at intervals on the surface of semiconductor substrate SUB in the memory region. Here, each active region 1F extends substantially in the vertical direction of the drawing (the depth direction of the paper surface in FIG. 3). A plurality of gate electrodes GE are formed spaced apart from each other so as to intersect (for example, orthogonally cross) these active regions 1F in plan view, and these are combined with the insulating layer IL directly above the gate electrodes GE in FIG. The driver transistors T1 and T2 and the access transistors T5 and T6) of FIG. 2 are configured.

  For example, in the unit cell surrounded by a rectangle in FIG. 4, three rows of gate electrodes GE (transistors) are arranged in the vertical direction of the figure. Of these three rows of gate electrodes GE, each of the upper and lower rows of gate electrodes GE is divided into a plurality of gate electrodes GE in the left-right direction in the figure, and an independent driver transistor for each of the divided gate electrodes GE. T1 and T2 are formed. Of the three columns of transistors, the central gate electrode GE is continuous without being divided in the horizontal direction in the figure, and access transistors T5 and T6 are formed therein.

  Specifically, in the driver transistors T1 and T2, the gate electrode GE and the active region 1F, which are surrounded by a circular dotted line in FIG. Formed in the region. Further, the access transistors T5 and T6 are formed in a region surrounded by a circular dotted line in FIG. 4B and in which the gate electrode GE and the active region 1F which are continuous in the horizontal direction of the above figure overlap in a plane. These access transistors T5 and T6 share the gate electrode GE (see FIG. 2).

  The second contact SC is formed between the pair of bit lines BL so as to straddle the pair of driver transistors T1 and T2 and the access transistors T5 and T6 which are adjacent to each other in the active region 1F. The second contact SC is a region where the gate electrode GE of the driver transistors T1 and T2 and the isolation region substantially overlap in the active region 1F, and on the gate electrode GE in the region sandwiched between the pair of bit lines BL. Is also formed.

  The second contact SC is substantially either one of the active region 1F on the side of the gate electrode GE, that is, one of the other in the direction intersecting the extending direction of the gate electrode GE (the vertical direction in FIG. 4B). It is arranged on the side of the. The first contact 1B is generally disposed on the other side surface side in the active region 1F. The first contact 1B extends long in the direction along the extending direction of the gate electrode GE in the plan view (left-right direction in FIG. 4B) and is arranged along the gate electrode GE, whereas the second contact SC Is preferably formed so as to extend long in a direction intersecting the extending direction of the gate electrode GE in a plan view (vertical direction in FIG. 4B) and straddle a pair of adjacent gate electrodes GE.

  The interlayer insulating films II2 and II1 and the lower layers thereof along the active region 1F extending in one unit cell in FIG. 4B are in the mode shown in FIG. Referring to FIG. 5, which is a schematic cross-sectional view taken along the line VV (broken line) in FIG. 4B, in the active region in the unit cell, driver transistors and access transistors are arranged in this order from the left side to the right side. These correspond to driver transistors and access transistors arranged from the upper side to the lower side of the portion along the bent VV line in the unit cell of FIG. 4B.

  The driver transistors T1 and T2 and the access transistors T5 and T6 in FIG. 5 include a source / drain region S / D (partially sharing a pair of adjacent transistors), a gate insulating film GI, a gate electrode GE, And an insulating layer IL and a sidewall insulating film SW. The gate electrode GE has a configuration in which a polycrystalline silicon layer PS and a tungsten silicide layer WS are stacked in this order. A plug conductive layer BS is formed in a region sandwiched between the driver transistor and the access transistor in the active region of FIG.

  The drain region D on the right side of the access transistor in the active region in FIG. 5 corresponds to the drain region D in the memory region in FIG.

  The first contact 1B, which is the contact CT, is formed so as to reach the plug conductive layer BS immediately below the bit line BL in the upper layer. Similarly, the second contact SC, which is the contact CT, is formed so as to reach the plug conductive layer BS immediately below the lower layer wiring 2G. Conversely, the plug conductive layer BS is formed between the contact CT (first contact 1B or second contact SC) and the source / drain region S / D. However, the plug conductive layer BS is omitted in the plan view of FIG.

  In the isolation region of FIG. 5, the gate electrode GE corresponding to the region where the gate electrode GE and the second contact SC (in the region other than the active region 1F) on the VV line in FIG. A plug conductive layer CG is formed, which is a driver transistor having a gate electrode GE (polycrystalline silicon layer PS and tungsten silicide layer WS), a gate insulating film GI, an insulating layer IL, and a sidewall insulating film SW. It is a part of the area. Note that the side surfaces of the gate insulating film GI and the gate electrode GE of the transistor are covered with a stacked structure in which another thin insulating film not shown in FIG. 5 other than the sidewall insulating film SW and the sidewall insulating film SW are stacked in this order. It may be. The other thin insulating film is formed for the purpose of relaxing the electric field in the vicinity of the region, and is preferably formed of a silicon oxide film, for example.

  As described above, the bit line BL connected to the first contact 1B includes one that functions as a bit line and one that functions as a ground line (ground line). For example, the first contact 1B electrically connected to the drain region D on the right side of the access transistor in the active region of FIG. 5 is connected to the bit line, and is electrically connected to the source region S on the left side of the driver transistor in the active region of FIG. The first contact 1B connected to can be connected to a ground line (see FIG. 2).

  Next, although partially overlapping with the above, one embodiment will be described more generally and specifically with reference to FIG. Hereinafter, description will be made using the contact CT including both the first contact 1B and the second contact SC.

  Referring to FIG. 6, in one embodiment, transistor TG is formed on the main surface of p-type well region PWL formed in the active region of semiconductor substrate SUB. Here, the transistor TG may be any of an access transistor, a driver transistor, and a load transistor. The transistor TG includes a pair of source / drain regions S / D, a gate insulating film GI formed on the main surface of the semiconductor substrate SUB, a gate electrode GE, an insulating layer IL over the gate electrode GE, and a sidewall insulating film. SW. Each of the pair of source / drain regions S / D is formed on the surface of the semiconductor substrate SUB. The gate electrode GE has a so-called polycide structure in which a polycrystalline silicon layer PS (first electrode layer) and a tungsten silicide layer WS (second electrode layer) are stacked in this order. The arrangement and form of each component of these transistors TG are basically the same as those of the transistors TG in the peripheral circuit region of FIG.

  An interlayer insulating film II1 is formed so as to cover a part of the main surface where the transistor TG is formed and the gate electrode GE of the transistor TG and the insulating layer IL. A contact hole SA that is an opening of the interlayer insulating film II1 is formed in a part of the interlayer insulating film II1, and the contact CT is formed by filling the contact hole SA with a conductive layer. The contact hole SA and the contact CT are formed so as to have a portion located immediately above the gate electrode GE.

  Interlayer insulating film II1 is made of, for example, a silicon oxide film, and insulating layer IL is made of, for example, a silicon nitride film. Thus, the interlayer insulating film II1 and the insulating layer IL are made of different materials.

  The contact hole SA is formed by a so-called self-alignment technique using a high etching selection ratio between the interlayer insulating film II1 and the insulating layer IL. Here, the interlayer insulating film II1 of the silicon oxide film is etched using etching conditions in which the etching rate of the silicon oxide film is high and the etching rate of the silicon nitride film is low. When the interlayer insulating film II1 is completely etched, the insulating layer IL of the silicon nitride film immediately below it begins to be etched. However, the insulating layer IL is less etched than the interlayer insulating film II1, and serves as an etching stopper. Therefore, the etching is finished when the insulating layer IL immediately below the interlayer insulating film II1 is partially etched, and the contact hole SA is formed.

  When the interlayer insulating film II1 is a silicon oxide film, the insulating layer IL may be a single layer of silicon nitride film as described above, but the silicon oxide film and the silicon nitride film are stacked in this order. It may be a configuration. By forming the insulating layer IL so that the silicon nitride film is an upper layer of the silicon oxide film, the silicon nitride film of the insulating layer IL can function as a stopper for etching by a self-alignment technique.

  By partially etching the insulating layer IL together with the interlayer insulating film II1 using the self-alignment technique, an etching surface ETH is formed on the insulating layer IL. The etching surface ETH is formed by partially removing the insulating layer IL and the sidewall insulating film SW by etching, and the shortest distance B1 in the vertical direction in FIG. 6 between the etching surface ETH and the tungsten silicide layer WS is secured. To be formed. The etching surface ETH has a curved surface shape that is convex on the semiconductor substrate side (the lower side in FIG. 6) with respect to the direction perpendicular to the main surface of the semiconductor substrate SUB (the vertical direction in FIG. 6).

  The etching surface ETH is formed so as to partially scrape not only the insulating layer IL but also the side wall insulating film SW that is usually disposed outside the insulating layer IL. For this reason, the etching surface ETH is also formed in the sidewall insulating film SW in the same manner as the insulating layer IL. The sidewall insulating film SW is also preferably formed of the same material as the insulating layer IL, specifically, a silicon nitride film, and may have a configuration in which a silicon oxide film and a silicon nitride film are stacked in this order.

  The width of the tungsten silicide layer WS in FIG. 6 is narrower than the width of the insulating layer IL. The gate electrode GE in FIG. 6 extends in the depth direction of the paper surface. The dimension in the left-right direction of FIG. 6 that intersects the extending direction of the gate electrode GE is the width here. In FIG. 6, the width of the insulating layer IL is equal to the width of the polycrystalline silicon layer PS. However, referring to the modification of FIG. 7, the width of the polycrystalline silicon layer PS is wider than the width of the insulating layer IL. Also good. To summarize the example of FIG. 6 and the example of FIG. 7, the width of the polycrystalline silicon layer PS is wider than the width of the tungsten silicide layer WS. FIG. 7 differs from FIG. 6 only in the width of the polycrystalline silicon layer PS, and all other components are the same as those in FIG.

  In summary, in the transistor TG, it is preferable that the relationship of the width of the tungsten silicide layer WS <the width of the insulating layer IL ≦ the width of the polycrystalline silicon layer PS is satisfied.

  The insulating layer IL is formed as a mask for patterning the gate electrode GE. The entire upper surface ILS of the insulating layer IL is preferably curved. That is, in the cross-sectional view of FIG. 6, the insulating layer upper surface ILS has a curved line that protrudes upward (interlayer insulating film II2 side), and the insulating layer IL has a curved surface that protrudes upward. Therefore, the insulating layer IL is formed so as to be thick at the center in the left-right direction (width direction) in the figure and thin at both ends in the left-right direction in the figure. The insulating layer upper surface ILS and the sidewall insulating film surface SWS, which is the surface of the sidewall insulating film SW, are smoothly connected, and the sidewall insulating film surface SWS also has a curved surface that protrudes outward in the width direction in the figure, for example. Is preferred.

  Note that the contact CT in FIG. 6 is formed so as to cover the upper surface of the interlayer insulating film II1 and penetrate the region above the interlayer insulating film II1, but as shown in FIGS. Alternatively, it may be formed so as to penetrate through interlayer insulating film II1 and interlayer insulating film II2. As will be described later, the interlayer insulating film II1 may be composed of two layers made of the same material (for example, a silicon oxide film). The interlayer insulating film II1 in FIG. 6 includes the interlayer insulating film II1 and the interlayer insulating film in FIG. It may be considered that it has a two-layer structure including II2.

  Further, in FIG. 6, the contact CT has a structure in which a conductive layer in the contact hole SA of the interlayer insulating film II1 and a conductive layer as a wiring pattern covering the interlayer insulating film II1 are integrated. However, the contact CT is composed of only the conductive layer in the contact hole SA of the interlayer insulating film II1, and even if a conductive layer as a wiring pattern is formed separately from the contact CT on the interlayer insulating film II1 so as to cover the contact CT. Good.

  The interlayer insulating film II1 is basically formed so as to cover the main surface of the semiconductor substrate SUB, but most of the main surface of the active region, particularly the memory region, is mostly the gate electrode GE and the sidewall insulating film SW of the transistor TG. Is covered with a plug conductive layer BS connected to either the region where the gate electrode is formed or the source / drain region S / D. Therefore, the interlayer insulating film II1 is hardly formed so as to directly cover the main surface of the semiconductor substrate SUB in the active region shown in FIG. 6, and most of the interlayer insulating film II1 is formed of the plug conductive layer BS and the transistor TG (insulating). It is formed so as to cover the upper surface ILS of the layer IL and the surface SWS of the sidewall insulating film SW. In the isolation region in the active region and the peripheral circuit region, the main surface of the semiconductor substrate SUB is covered with the interlayer insulating film II1.

  Plug conductive layer BS is formed to cover the upper surface of source / drain region S / D and to be connected to the lower surface of contact CT. That is, the plug conductive layer BS is formed between the source / drain region S / D and the contact CT so as to electrically connect the source / drain region S / D and the contact CT.

  The source / drain region S / D is formed so as to at least partially overlap the contact hole SA in plan view. That is, the source / drain region S / D is formed so as to overlap with at least a part of the contact hole SA (contact CT) immediately in plan view.

  The contact hole SA in FIG. 6 is formed at a position shifted to the left side from the center of the region sandwiched between the two transistors TG in the figure by a self-alignment technique. Therefore, as a result of forming contact hole SA partially overlapping with insulating layer IL, insulating layer IL and sidewall insulating film SW are etched by an amount corresponding to the etching selectivity with interlayer insulating film II1. . For this reason, the left side portion of the contact hole SA forms an etching surface ETH as a curved surface (curved in the sectional view). However, since the right side portion of the contact hole SA is formed by etching only the interlayer insulating film II1, an etching surface as a plane (a straight line in the cross-sectional view) is formed. As described above, the contact hole SA of one embodiment may have an asymmetric cross-sectional shape whose side surface has both a curved surface shape and a planar shape.

  Since the contact hole SA is formed at a position shifted, for example, to the left side from the center of the region sandwiched between the two transistors TG in the drawing, part of the contact hole SA and the contact CT is the gate electrode GE (for example, polycrystalline silicon). It is formed so as to have a portion located directly above the layer PS).

  Since the plug conductive layer BS is formed so as to cover the upper surface of the source / drain region S / D, in particular when a plurality of transistors TG are formed side by side as shown in FIG. A plug conductive layer BS is formed in a region sandwiched between the transistors TG. Plug conductive layer BS is formed so as to partially cover each side wall insulating film surface SWS of a pair of adjacent transistors TG. Specifically, here, the plug conductive layer BS covers all of the side wall insulating film surface SWS directly beside the gate insulating film GI and the gate electrode GE, and covers the lower side of the side wall insulating film surface SWS beside the insulating layer IL.

  In other words, the uppermost surface BST of the plug conductive layer BS is above the uppermost surface (interlayer insulating film II2 side) of the gate electrode GE (tungsten silicide layer WS), and is lower than the uppermost surface of the insulating layer IL (semiconductor). It is preferably located on the substrate SUB side. However, the top surface BST may be formed so as to be located above the top surface of the polycrystalline silicon layer PS and below the top surface of the tungsten silicide layer WS.

  Next, a method for manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. In the following, a method for manufacturing the active region shown mainly in FIG. 6 will be described.

  Referring to FIG. 8, a semiconductor substrate SUB made of, for example, a p-type silicon epitaxial layer having a main surface is prepared, and p-type well region PWL, insulating layer SI, and the like are formed by a generally known method. 8 shows an aspect in which the same portions as those in FIGS. 6 and 7 are viewed from the same direction, the insulating layer SI is not reflected in FIG.

  Next, a gate insulating film GI is formed on the main surface of semiconductor substrate SUB (p-type well region PWL) by a generally known thermal oxidation method, for example. On the gate insulating film GI, a polycrystalline silicon layer PS that is to form the gate electrode GE is formed by a generally known CVD (Chemical Vapor Deposition) method, and the gate electrode GE should be formed on the polycrystalline silicon layer PS. The tungsten silicide layer WS is formed by a generally known method such as sputtering or CVD. Further, an insulating layer IL for forming a mask for patterning the gate electrode GE is formed on the tungsten silicide layer WS by a generally known CVD method. The insulating layer IL may be a single layer of a silicon nitride film, but may have a configuration in which a silicon oxide film and a silicon nitride film are stacked in this order.

  Referring to FIG. 9, patterning is performed so that insulating layer IL has a desired size as a mask by a normal photolithography technique using photoresist PHR and etching.

Referring to FIG. 10, after removing photoresist PHR, tungsten silicide layer WS and polycrystalline silicon layer PS are patterned by etching using insulating layer IL as a mask. In this etching process, a mixed gas of chlorine gas (Cl ₂ ) and fluorine carbide gas (CF ₄ ) is used. By using a gas containing CF ₄ , the etching can be performed so that the etching amount of the tungsten silicide layer WS in the left-right direction (width direction) in the drawing is larger than the etching amount of the polycrystalline silicon layer PS. As a result, as shown in FIG. 10, the side portions of the tungsten silicide layer WS and the polycrystalline silicon layer PS are etched so that the width of the tungsten silicide layer WS is narrower than the widths of the insulating layer IL and the polycrystalline silicon layer PS. Is done.

The use of CF ₄ gas in the etching process, it is possible to increase the component of the isotropic etching in comparison with the case of not using the CF ₄ gas, increasing the amount of etching of the tungsten silicide layer WS about the left-right direction in FIG. Can do. Specifically, for example, if the tungsten silicide layer WS is etched using a mixed gas of ₂₀ ccm of Cl ₂ gas and 40 ccm of CF ₄ gas, the etching of the tungsten silicide layer WS is accelerated by F radicals generated by the CF ₄ gas. can do.

In addition, as a method of processing the width of the tungsten silicide layer WS so as to be narrower than the width of the insulating layer IL, for example, an etching process using a mixed gas further containing oxygen (O ₂ ) gas in the above mixed gas. There is a way to do. Specifically, for example, it is preferable to perform etching using a mixed gas of, for example, 20 ccm of Cl ₂ gas, 40 ccm of CF ₄ gas, and 10 ccm of O ₂ gas. In this way, the separation of the CF ₄ gas is accelerated by the O ₂ gas and the generation of F radicals is promoted, so that the etching of the tungsten silicide layer WS is further accelerated. Further, since the O ₂ gas has a role of suppressing the formation of a deposited film on the sidewall of the tungsten silicide layer WS or the like during etching, the increase in the thickness of the tungsten silicide layer WS is suppressed from this point of view as well. Reduction of width is promoted.

  Furthermore, as another method for processing the tungsten silicide layer WS so that the width of the tungsten silicide layer WS is narrower than the width of the insulating layer IL, for example, the output power of a high-frequency device used for etching may be reduced or the pressure may be increased. . Specifically, for example, in a generally known processing method, the output power of the high-frequency device is 80 W, and the pressure in the device during processing is 0.4 Pa. However, the output power can be lowered or increased. However, it is effective for reducing the width of the tungsten silicide layer WS.

However, among the above four conditions (using CF ₄ gas, using O ₂ gas, lowering the output power, increasing the pressure) and the like, the highly effective conditions vary depending on the purpose of the etching process. Optimal conditions are determined by appropriately combining the above four conditions.

  Through the above processing, a stacked structure of the gate insulating film GI, the gate electrode GE made of the polycrystalline silicon layer PS and the tungsten silicide layer WS, and the insulating layer IL is formed. Next, an n-type impurity region S / D to be a source / drain region is formed on the main surface of the semiconductor substrate SUB in the p-type well region PWL using a normal photolithography technique and ion implantation technique.

  In FIG. 10, as shown in FIG. 6, the width of the polycrystalline silicon layer PS is formed to be substantially equal to the insulating layer IL. However, referring to the modification of FIG. 11, the polycrystalline silicon layer PS may be formed so that the width of the polycrystalline silicon layer PS is wider than the width of the insulating layer IL as shown in FIG. Such a configuration can also be formed by appropriately combining the above four conditions to determine an optimum condition. 11 and 7, the polycrystalline silicon layer PS is shown as a rectangular cross-sectional shape having the same width from the upper surface to the lower surface. However, the polycrystalline silicon layer PS is formed as a trapezoidal cross-sectional shape having a taper at the end of the polycrystalline silicon layer PS so that the width on the lower side (semiconductor substrate SUB side) is wider than the width on the upper side. Also good.

  Referring to FIG. 12, for example, a single layer of a silicon nitride film or a structure in which a silicon oxide film and a silicon nitride film are stacked in this order is formed on the entire main surface of semiconductor substrate SUB. After that, the formed silicon nitride film or the stacked layer of the silicon oxide film and the silicon nitride film is etched back, so that the formed film remains on the side wall of the gate electrode GE and the like, and the cross-sectional shape shown in FIG. The sidewall insulating film SW is formed.

  Referring to FIG. 13, for example, a liner film LF of a silicon nitride film is formed on the entire main surface of semiconductor substrate SUB. Like the insulating layer IL and the sidewall insulating film SW, the liner film LF functions as an etching stopper using an etching selectivity with respect to an interlayer insulating film to be formed later, and on the insulating layer IL and the sidewall insulating film SW. Also formed.

  Referring to FIG. 14, interlayer insulating film II1 made of a silicon oxide film is formed on the entire main surface of semiconductor substrate SUB using, for example, a CVD method. Thereby, the laminated structure including the gate electrode GE and the like is covered with the interlayer insulating film II1. The silicon oxide film of the interlayer insulating film II1 may contain boron or phosphorus impurities such as so-called BPTEOS.

  Referring to FIG. 15, after interlayer insulating film II1 is polished by a chemical mechanical polishing method called CMP (Chemical Mechanical Polishing) so that the upper surface becomes flat, in the region shown in FIG. 15 (FIGS. 6 and 7). Since the whole becomes an opening, a photoresist pattern (not shown) is formed. After the photoresist pattern is formed, the interlayer insulating film II1 is removed in the region shown in FIG. 15 (FIGS. 6 and 7) by etching using a self-alignment technique. The liner film LF, the insulating layer IL, and the silicon nitride film of the sidewall insulating film SW formed immediately below the interlayer insulating film II1 removed at this time are removed by an amount corresponding to the etching selectivity with the interlayer insulating film II1. . When the silicon nitride film is dry-etched by an amount corresponding to the etching selectivity with respect to the interlayer insulating film II1, the etching is completed, so that the silicon nitride film has a rounder cross-sectional shape than the initial one.

  By the dry etching process of the silicon nitride film described above, the surface ILS of the insulating layer IL and the surface SWS of the sidewall insulating film SW are smoothly connected, and these are in a direction opposite to the direction toward the gate electrode GE or the like (the gate electrode GE in the figure). The curved surface is convex in the direction toward the outside. Here, in particular, the entire upper surface of the insulating layer IL is preferably formed to have a curved shape that is convex upward in the drawing. The insulating layer IL is formed so as to be thick at the center in the left-right direction (width direction) in the figure and thin at both ends in the left-right direction in the figure.

  By etching away the interlayer insulating film II1 in a region (region sandwiched between the two gate electrodes GE) other than the region where the gate electrode GE and the sidewall insulating film SW of the transistor TG are formed in the active region in plan view. An opening CV is formed in a region sandwiched between the two transistors TG.

  Since the source / drain region S / D is formed in the region between the two transistors TG in the active region, the source / drain region S / D is exposed by forming the opening CV.

  In FIG. 15, all of interlayer insulating film II1 is removed, but actually, for example, in part of the isolation region of the memory region and part of the peripheral circuit region, interlayer insulating film II1 remains without being etched. Also good. That is, the interlayer insulating film II1 may remain without being etched in a region that is not between the gate electrodes of the pair of transistors and is not directly above the source / drain region S / D. Therefore, as shown in the peripheral circuit region of FIG. 3 and the isolation region of FIG. 5, in these regions, the insulating film IL on the gate electrode GE does not have a round cross-sectional shape, and the liner The film LF may remain partially. For example, in the isolation region, an opening for forming the contact plug conductive layer CG of FIG. 5 is formed as a separate process (at a different timing) from the process of FIG. 15 by a normal photolithography technique and etching. .

  Referring to FIG. 16, a polycrystalline silicon layer BS containing conductive impurities is formed on the main surface of semiconductor substrate SUB by, for example, a CVD method. As a result, the region where the gate electrode GE, the insulating layer IL, and the sidewall insulating film SW of the transistor TG are formed is also covered with the polycrystalline silicon layer BS. Although not shown, the contact plug conductive layer CG is formed by forming a polycrystalline silicon layer also in the opening formed for forming the contact plug conductive layer CG in the isolation region.

  Referring to FIG. 17, an etch back process is performed on the polycrystalline silicon layer formed in the step of FIG. By this process, the polycrystalline silicon layer remains in a region other than the region where the gate electrode GE and the sidewall insulating film SW of the transistor TG are formed in a plan view, that is, in the opening CV. In this manner, plug conductive layer BS made of a polycrystalline silicon layer is formed so as to fill opening CV. Since the plug conductive layer BS is formed so as to cover the upper surface of the source / drain region S / D exposed by the opening CV, the plug conductive layer BS is electrically connected to the source / drain region S / D. It is formed on the main surface of the semiconductor substrate SUB. By the etch back process, the plug conductive layer BS can be formed with high accuracy at a desired position.

  The polycrystalline silicon layer BS formed in the process of FIG. 16 covers the region where the gate electrode GE, the insulating layer IL, and the sidewall insulating film SW of the transistor TG are formed (from the main surface of the semiconductor substrate SUB to the insulating layer IL). Preferably, it is formed so as to have a thickness reaching the uppermost part of the uppermost part of the uppermost surface ILS. After the etch back process is performed on the polycrystalline silicon layer, the plug top surface BST after the etch back is above the top surface of the gate electrode GE (tungsten silicide layer WS), and the top surface ILS (of the insulating layer IL) The etching amount (etching time) of the polycrystalline silicon layer BS is adjusted so that the plug conductive layer BS is formed so as to be located below the uppermost part). However, the plug top surface BST may be formed below the top surface of the tungsten silicide layer WS.

  Referring to FIG. 18, interlayer insulating film II1 is formed on the main surface of semiconductor substrate SUB using, for example, the CVD method so as to cover gate electrode GE and insulating layer IL. As a result, interlayer insulating film II1 is formed so as to cover plug conductive layer BS (plug uppermost surface BST). Here, the interlayer insulating film II1 is preferably formed of a material different from the insulating layer IL (and the sidewall insulating film SW). As described above, the insulating layer IL (and the sidewall insulating film SW) is at least the upper part formed of the silicon nitride film. In this case, the interlayer insulating film II1 is preferably formed of a silicon oxide film that is a material having a high etching selectivity with respect to the silicon nitride film.

  Although not shown in FIG. 18, interlayer insulating film II1 formed in the process of FIG. 18 is in a region where interlayer insulating film II1 formed in the process of FIG. 14 is not removed, such as an isolation region of a memory region or a peripheral circuit region. The interlayer insulating film II1 in the step of FIG. 18 may be formed so as to cover the upper surface of the interlayer insulating film II1 in the step of FIG. That is, in this case, the interlayer insulating film II1 has a two-layer structure.

  Further, from a viewpoint different from the interlayer insulating film II1, the interlayer insulating film including the interlayer insulating film II1 and the interlayer insulating film II2 (see FIG. 3) formed thereon is shown in FIG. It may be considered as II1.

  Referring to FIG. 19, after interlayer insulating film II1 is polished by a normal CMP process so that the upper surface becomes flat, interlayer insulating film II1 is partially etched by self-alignment technique to reach plug conductive layer BS. Thus, a contact hole SA as an opening is formed. As a result, the plug conductive layer BS is disposed so as to remain between the source / drain region S / D and the contact hole SA in the vertical direction of the figure.

  The contact hole SA is displaced in the center in the width direction of the region sandwiched between the region where the gate electrode GE and the sidewall insulating film SW of the pair of adjacent transistors TG are formed (that is, the center of the plug conductive layer BS). Ideally, it should be formed. However, in practice, since the width of the sandwiched region is very narrow due to miniaturization, it is usual that a positional shift occurs in either the left or right direction with respect to the width direction. In FIG. 19, the contact hole SA is formed so as to be biased to the left with respect to the width direction, and the contact hole SA is obtained by (partially) scraping the interlayer insulating film II1 including a portion located immediately above the gate electrode GE. Is formed.

  When the contact hole SA is formed, the interlayer insulating film II1 located immediately above the gate electrode GE is etched, and the silicon nitride insulating layer IL and the sidewall insulating film SW in contact with the lower surface of the interlayer insulating film II1 are The film is partially etched by a thickness corresponding to the etching selectivity with the interlayer insulating film II1. As a result, an etching surface ETH by the contact hole SA is formed in the silicon nitride film immediately above the gate electrode GE. This etching surface ETH has a curved surface shape that protrudes downward (semiconductor substrate side) particularly when the dimension of the etching surface ETH in the horizontal direction in the drawing is small (in other words, the positional displacement of the contact hole SA in the horizontal direction is small). It is formed to become.

  Referring to FIG. 20, polycrystalline silicon thin film PL containing conductive impurities, for example, is filled in contact hole SA. In this process, for example, a CVD method is used, and a polycrystalline silicon thin film PL is also formed on the interlayer insulating film II1.

  Referring to FIG. 21, the polycrystalline silicon thin film PL on the interlayer insulating film II1 remains only above and in the vicinity of the contact hole SA by the normal photoengraving technique and etching, and on the interlayer insulating film II1. Patterning is performed so that the polycrystalline silicon thin film PL in the other region is removed. As a result, the embodiment shown in FIG. 6 having the contact CT in which the conductive layer in the contact hole SA and the wiring pattern immediately above the conductive layer are integrated is formed.

  As described above, the contact CT may have a configuration in which the conductive layer in the contact hole SA of the interlayer insulating film II1 and the conductive layer as a wiring pattern covering the interlayer insulating film II1 are integrated. It may be formed separately in the hole SA and outside the contact hole SA (directly above). The contact CT may be formed so that the thin film PL remains only in a part of the contact hole SA.

  Further, for example, after all of the thin film PL on the interlayer insulating film II shown in FIG. 20 is removed by CMP, the thin film PL is formed again on the interlayer insulating film II, and this is formed by using ordinary photolithography and etching. A conductive layer PL as a separate body may be formed between the inside and outside of the contact hole SA by remaining as a wiring layer at a desired position. Further, as described above, the contact CT here can be considered including the contact SC. Therefore, the contact SC extending to the upper layer from the contact CT is also formed by a procedure similar to the method for forming the contact CT. It can be formed on the basis of SA.

  The description of the method of forming each layer thereafter (interlayer insulating film II2 and higher) is omitted.

  Next, the operation and effect of the embodiment will be described with reference to the comparative examples of FIGS.

  Referring to FIG. 22, in the comparative example, the widths of tungsten silicide layer WS and insulating layer IL constituting gate electrode GE are equal, and the widths of tungsten silicide layer WS, polycrystalline silicon layer PS, and insulating layer IL are equal. Are all equal. However, since FIG. 22 is basically the same as the embodiment of FIG. 6 in other points, the same components as those of FIG. 6 are denoted by the same reference numerals in FIG. 22, and the description thereof will not be repeated. . For example, it is assumed that there is no difference between FIG. 6 and FIG. 22 with respect to the dimension of the plug conductive layer BS in the width direction of the figure and the width of the region surrounded by the sidewall insulating film SW.

  Referring to FIG. 23, as a method of manufacturing the semiconductor device having the configuration of FIG. 22, after the same processing as the steps of FIGS. 8 to 9, the tungsten silicide layer WS, the polycrystalline silicon layer PS, and the insulating layer are processed. Etching is performed so that the widths of IL are all equal. Referring to FIG. 24, sidewall insulating film SW is formed thereafter as in FIG. The subsequent processes are the same as those in FIGS.

  Referring to FIG. 22 again, in FIG. 22, the distance A2 (so-called short margin) in the width direction from the end WSE of the tungsten silicide layer WS to the plug conductive layer BS is narrow, and the tungsten silicide layer WS and the plug conductive layer BS May cause a short circuit. Similarly, in FIG. 22, the distance B2 (short margin) in the vertical direction from the uppermost surface WST of the tungsten silicide layer WS to the contact CT immediately above the tungsten silicide layer WS at the tungsten silicide layer end WSE is narrow, and the tungsten silicide layer WS and the contact CT May cause a short circuit.

  However, in FIG. 6, since the tungsten silicide layer WS is formed thinner than that in FIG. 22 (so as to be thinner than the insulating layer IL), the width of the plug conductive layer BS and the like is assumed to be the same as that in FIG. Then, the short margin A1 in the width direction from the end portion WSE of the tungsten silicide layer WS to the plug conductive layer BS is wider than A2. For this reason, if the tungsten silicide layer WS is thinned as in the embodiment, even if the contact CT is formed so as to have a portion positioned directly above the gate electrode GE by the self-alignment technique. The short circuit between the tungsten silicide layer WS and the plug conductive layer BS can be suppressed.

  In FIG. 6, the tungsten silicide layer end WSE is formed on the inner side in the width direction of the gate electrode GE than in FIG. That is, the short margin B1 in the vertical direction from the uppermost surface WST of the tungsten silicide layer WS to the contact CT immediately above the tungsten silicide layer WS at the tungsten silicide layer end WSE is wider than B2. For this reason, if the tungsten silicide layer WS is thinned as in the embodiment, even if the contact CT is formed so as to have a portion positioned directly above the gate electrode GE by the self-alignment technique. The short circuit between the tungsten silicide layer WS and the contact CT can be suppressed.

  Here, with reference to FIG. 25, how narrow the width W1 of the tungsten silicide layer WS is required as compared with the width W2 of the insulating layer IL (polycrystalline silicon layer PS) will be described below. Here, as an example, a process technique in the case where the gate length of the transistor TG, that is, the width W2 of the polycrystalline silicon layer PS is 140 nm is considered as an example.

  Referring to FIG. 26, the horizontal axis of this graph represents the width W1 of the tungsten silicide layer WS, and the vertical axis represents the sheet resistance of the tungsten silicide layer WS. From FIG. 26, the sheet resistance of the tungsten silicide layer WS when the width W1 is 140 nm is 11.1Ω / □. Here, if the sheet resistance value is allowed to rise up to 15% with respect to the above, the above sheet resistance is allowed up to a maximum of 12.8Ω / □. Since the width W1 of the tungsten silicide layer WS when the sheet resistance is 12.8Ω / □ is 110 nm from the graph, the width W1 needs to be 110 nm or more. This is 79% of the width of the tungsten silicide layer WS, that is, 140 nm when the sheet resistance is 11.1Ω / □. Therefore, W1 needs to be 79% or more of W2.

  Referring to FIG. 27, the width of gate electrode GE is narrower on both the left and right sides of gate electrode GE than the width of insulating layer IL by approximately the dimension in the lateral (width) direction of the right triangle in the drawing. If the width of the gate electrode GE is narrowed by the horizontal dimension of the triangle in the figure, the vertical dimension in the figure, that is, the short margin in the vertical direction between the contact CT and the gate electrode GE is approximately the vertical direction of the triangle in the figure. It becomes wider by the dimension of. Specifically, when the vertical dimension (short margin) of this triangle is required to be 10 nm or more, the lateral dimension of the triangle is 3 nm. When the width W2 is 140 nm, the width W1 needs to be 3 nm or more shorter on both the left and right sides. Therefore, the width W1 needs to be 134 nm or less, and W1 needs to be 95% or less of W2. is there.

From the above, it can be said that the width W1 is preferably 79% or more and 95% or less of the width W2.
The polycrystalline silicon layer PS is a component that is directly related to the determination of the characteristics of the transistor TG having the gate electrode GE. For example, if the width of the polycrystalline silicon layer PS is narrowed similarly to the tungsten silicide layer WS and narrower than the insulating layer IL, for example, when performing an ion implantation technique for forming an impurity region in the step of FIG. If the direction of ion implantation is substantially perpendicular to the main surface of the semiconductor substrate SUB, ion implantation may not be performed in the vicinity of the outer edge of the polycrystalline silicon layer PS. For this reason, the impurity concentration in the portion where ions are not implanted changes, which may cause poor formation of transistors and deterioration of characteristics.

  However, by making the width of the polycrystalline silicon layer PS the same as or larger than the width of the insulating layer IL, it is possible to suppress the occurrence of defects such as the above-mentioned formation defects and characteristic deterioration.

  Since normal gate dimension management is confirmed from above by an inline SEM (Scanning Electron Microscope), and when the width of the polycrystalline silicon layer PS is narrower than the width of the insulating layer IL, the polycrystalline silicon layer PS that determines the transistor characteristics is determined. The width of the can not be managed accurately. However, if the width of the polycrystalline silicon layer PS is greater than or equal to the width of the insulating layer IL, the dimensions of the polycrystalline silicon layer PS can be managed accurately, so that the transistor characteristics can be managed accurately.

  Next, the reason why the short margin B1 is wider than B2 is that the etching surface ETH formed in the insulating layer IL in accordance with the etching selection ratio between the interlayer insulating film II1 and the insulating layer IL becomes convex toward the semiconductor substrate SUB side. This is because it has a curved surface shape, and the etching surface ETH is formed further upward as it goes inside the gate electrode GE.

  The reason why the etching surface ETH is formed on the upper side inside the gate electrode GE is that the entire upper surface of the insulating layer IL has a curved surface shape protruding upward. That is, particularly when the contact CT is formed just above one side (right side) of the uppermost portion (center in the width direction) of the insulating layer IL as shown in FIG. 22, the upper surface of the insulating layer IL is convex upward. In order to have a shape, the upper surface ILS of the insulating layer IL is formed upward as it goes inward (left side) in the region. Since the insulating layer upper surface ILS is formed further upward inside the gate electrode GE, the etching surface ETH is also formed further upward inside the gate electrode GE.

  Next, in the aspect in which the etching surface ETH has a curved surface that protrudes downward (on the semiconductor substrate SUB side) as described above, the displacement of the contact CT is relatively small, and the dimension in the width direction of the etching surface ETH is small. Well realized. If the etching surface ETH has a curved surface shape that protrudes downward, for example, as compared with the case where the etching surface ETH has a curved surface shape that protrudes upward, the tungsten silicide layer WS becomes thinner as described above, so that the short margin B2 The effect of widening can be further enhanced.

  By making the tungsten silicide layer WS narrower than the width of the insulating layer IL, the short margin can be widened and the short circuit can be suppressed, but the width of the polycrystalline silicon layer PS is preferably equal to or larger than the width of the insulating layer IL. As shown, the width of the polycrystalline silicon layer PS may be wider than the width of the insulating layer IL.

  Next, the source / drain region S / D is formed so as to overlap with at least a part of the contact hole SA (contact CT) in plan view, the source / drain region S / D, the plug conductive layer BS, There is a region where the contact CT is aligned with the vertical direction of the figure. Therefore, the source / drain region S / D and the contact CT are electrically connected with a simple structure. The structure in which the source / drain region S / D, the plug conductive layer BS, and the contact CT are aligned in a straight line in the vertical direction in the drawing is such that the plug conductive layer BS is electrically connected to the source / drain region S / D. The contact hole SA is formed so as to reach the plug conductive layer BS. With the above configuration, electrical connection among the contact CT, the plug conductive layer BS, and the source / drain region S / D can be easily performed.

  Next, the plug conductive layer BS and the contact CT are electrically connected by disposing the uppermost surface BST of the plug conductive layer BS above the uppermost surface of the gate electrode GE (tungsten silicide layer WS). It is possible to make the depth of the contact hole SA necessary for the shallower. Therefore, even if the etching amount of the interlayer insulating film II1 for forming the contact hole SA is further reduced, the plug conductive layer BS and the contact CT can be reliably electrically connected.

  The uppermost surface BST of the plug conductive layer BS is disposed below the uppermost surface of the insulating layer IL. In this case, for example, a pair of adjacent plug conductive layers BS exceed the region where the gate electrode GE and the sidewall insulating film SW of the transistor TG arranged next to the plug conductive layer BS are formed (above the region). , The plug conductive layer BS extends so that the pair of plug conductive layers BS are coupled to each other), so that it is possible to suppress the occurrence of an electrical connection (short circuit).

  Although the above description is mainly based on the assumption that it is used in the advanced SRAM, the above configuration is not limited to the advanced SRAM, and may be used in a memory area having another configuration.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  1B 1st contact, BL, ZBL bit line, BS plug conductive layer, BST plug top surface, CG contact plug conductive layer, CT contact, DV semiconductor device, ETH etched surface, II, II1 interlayer insulating film, IL insulating layer, ILS insulating layer upper surface, PD pad region, PL thin film, PS polycrystalline silicon layer, SC second contact, SI insulating layer, SUB semiconductor substrate, SWS sidewall insulating film surface, T1, T2 driver transistor, T3, T4 load transistor, T5 , T6 Access transistor, TG transistor, WS tungsten silicide layer, WSE tungsten silicide layer end, WST tungsten silicide layer top surface.

Claims (14)

A semiconductor substrate having a main surface;
A gate electrode formed on the main surface and including a first electrode layer and a second electrode layer formed on the first electrode layer;
An insulating layer formed on the gate electrode;
An interlayer insulating film formed on the main surface so as to cover the gate electrode and the insulating layer, and having a contact hole having a portion located directly above the gate electrode;
The insulating layer and the interlayer insulating film are different materials,
The semiconductor device, wherein the width of the second electrode layer is narrower than the width of the insulating layer.   The semiconductor device according to claim 1, wherein a width of the first electrode layer is equal to or greater than a width of the insulating layer.   The semiconductor device according to claim 1, wherein the entire upper surface of the insulating layer has a curved shape. The contact hole is formed so as to form an etched surface in the insulating layer by partially scraping the insulating layer,
The semiconductor device according to claim 1, wherein the etching surface has a curved surface shape convex toward the semiconductor substrate with respect to a direction perpendicular to the main surface. An impurity region to be a source / drain region formed on the main surface so as to be located directly under the contact hole;
The semiconductor device according to claim 1, further comprising a plug conductive layer formed between the impurity region and the contact hole.   6. The semiconductor device according to claim 5, wherein an uppermost surface of the plug conductive layer is located above an uppermost surface of the second electrode layer and is located below an uppermost surface of the insulating layer. Preparing a semiconductor substrate having a main surface;
Forming a gate electrode including a first electrode layer and a second electrode layer formed on the first electrode layer on the main surface;
Forming an insulating layer on the gate electrode;
Forming an interlayer insulating film on the main surface so as to cover the gate electrode and the insulating layer;
Forming a contact hole in a portion including a portion located directly above the gate electrode of the interlayer insulating film,
The insulating layer and the interlayer insulating film are formed from different materials,
The method for manufacturing a semiconductor device, wherein the second electrode layer is formed to have a width narrower than a width of the insulating layer.   The method for manufacturing a semiconductor device according to claim 7, wherein a width of the first electrode layer is formed to be equal to or greater than a width of the insulating layer. The entire upper surface of the insulating layer is curved,
The method of manufacturing a semiconductor device according to claim 7, wherein the curved shape is formed by dry etching the insulating layer. The contact hole is formed so as to form an etched surface in the insulating layer by partially scraping the insulating layer,
The method of manufacturing a semiconductor device according to claim 7, wherein the etching surface has a curved shape protruding toward the semiconductor substrate with respect to a direction perpendicular to the main surface. The semiconductor according to claim 7, wherein a side portion of the second electrode layer is etched using a gas containing CF _{4 such} that the width of the second electrode layer is smaller than the width of the insulating layer. Device manufacturing method. Forming an impurity region to be a source / drain region on the main surface;
Forming a plug conductive layer on the main surface so as to be electrically connected to the impurity region,
The method of manufacturing a semiconductor device according to claim 7, wherein the contact hole is formed to reach the plug conductive layer.   In the step of forming the plug conductive layer, the uppermost surface of the plug conductive layer is formed above the uppermost surface of the second electrode layer and below the uppermost surface of the insulating layer. A method of manufacturing a semiconductor device according to claim 12. The step of forming the plug conductive layer includes:
Forming a conductive layer on the main surface so as to cover the gate electrode and the insulating layer;
The method for manufacturing a semiconductor device according to claim 12, further comprising: etching back the conductive layer so as to remain between the impurity region and the contact hole.

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