JP2014175431A - Semiconductor device and electric power conversion system using the same - Google Patents

Abstract

【Task】
Stabilizes the breakdown voltage of the semiconductor device.
[Solution]
FLRs 232 and 234 that are in contact with the auxiliary electrodes 321 and 322 are provided in the N ⁻ layer 112 in the termination region of the semiconductor device 101, and an FLR 233 that is separated from the auxiliary electrode is provided between the FLR 232 and the FLR 234, and this FLR 233. Are covered with auxiliary electrodes 321 and 322.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device and a power conversion device using the same, and more particularly to a high voltage semiconductor device and a large capacity or high reliability power conversion device using the same.

  As high voltage semiconductor devices, PN diodes, Schottky barrier diodes, MOSFETs, insulated gate bipolar transistors and the like are widely used. In FIG. 2, in a high breakdown voltage semiconductor device, a termination region, which is a voltage blocking region, is generally arranged so as to surround an active region through which a main current flows in a plan view.

  Patent Document 1 (Japanese Patent No. 3111827) discloses a technique for realizing a high voltage semiconductor device having a stable voltage blocking characteristic by providing a field plate in an FLR (Field Limiting Ring) as a termination structure.

Japanese Patent No. 3111827

  As for the high breakdown voltage semiconductor device having the field plate as described above, the inventors have studied further stabilization of the blocking breakdown voltage, and found the following problems.

Since the N ⁻ layer having the conventional structure includes a portion not covered with the field plate, the withstand voltage may be deteriorated when the charge of the insulating sealing material such as the module is large.

  In particular, when the semiconductor material constituting the semiconductor device is a wide band gap semiconductor such as silicon carbide (SiC), the dielectric breakdown electric field of the semiconductor device itself is high, so that a high electric field is applied to the insulating sealing material, and the Charge is generated. For this reason, the deterioration of the breakdown voltage becomes remarkable.

  Therefore, an object of the present invention is to increase the breakdown voltage of the semiconductor device and stabilize the voltage blocking characteristics.

  In order to solve the above problems, in the semiconductor device according to the present invention, a plurality of second semiconductor regions in contact with the first auxiliary electrode are provided in the first semiconductor region of the first conductivity type in the termination region. Between the adjacent second semiconductor regions, at least one second conductive type third semiconductor region separated from the first auxiliary electrode is provided, and the surface of the third semiconductor region is the first semiconductor region. Covered by auxiliary electrode.

  Furthermore, in the semiconductor device which is one embodiment of the present invention, an active region in which a main current flows and a termination region located around the active region are provided in the first semiconductor region of the first conductivity type. In this termination region, a plurality of second conductivity type second semiconductor regions are provided so as to surround the active region, and the plurality of first auxiliary electrodes are in contact with these second semiconductor regions. In the termination region, at least one second conductive type third semiconductor region separated from the first auxiliary electrode surrounds the active region between two adjacent second semiconductor regions. Is provided. Furthermore, the surface of the third semiconductor region is covered with the first auxiliary electrodes that are in contact with the two second semiconductor regions.

  The semiconductor device is, for example, a PN diode, a Schottky barrier diode, a MOSFET, an insulated gate bipolar transistor, or the like. The first conductivity type and the second conductivity type are, for example, an N type and a P type, respectively, and are opposite to each other. Further, the second and third semiconductor regions are, for example, FLR (Field Limiting Ring). The first auxiliary electrode preferably comprises a field plate.

  According to the present invention, the breakdown voltage of the semiconductor device can be increased and the voltage blocking characteristic can be stabilized.

  Other objects and other features of the present invention will become apparent from the description of the following specification and the drawings.

FIG. 3 is a cross-sectional view of a termination region of the semiconductor device according to the first embodiment. FIG. 2 is a plan view of the first embodiment. The elements on larger scale of the periphery area | region of FLR separated from the auxiliary electrode. The relationship between the surface density of the charge of the insulating sealing material and the breakdown voltage of the semiconductor device. A modification of the first embodiment. Sectional drawing of the termination area | region of the semiconductor device which is Embodiment 2. FIG. Sectional drawing of the termination area | region of the semiconductor device which is Embodiment 3. FIG. A modification of the third embodiment. The power converter device which is Embodiment 4. FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each embodiment, a field plate extending in the direction from the chip center of the semiconductor device toward the chip end is referred to as a forward field plate, and a field plate extending in the direction from the chip end toward the chip center is referred to as a reverse field plate. The notations N ⁻ , N, and N ⁺ indicate that the conductivity type of the semiconductor layer is N type, and the N-type impurity concentration is relatively high in this order. The notations P ⁻ , P, and P ⁺ indicate that the conductivity type of the semiconductor layer is P type, and the P-type impurity concentration is relatively high in this order.
(Embodiment 1)
1 is a sectional view of a termination region of a semiconductor device according to a first embodiment of the present invention. FIG. 2 shows a plan view of the present embodiment. FIG. 1 shows a longitudinal section taken along line AA ′ in FIG. As shown in FIG. 2, the termination region 103 is located around the active region 102 including the P layer 113 and through which the main current flows in the semiconductor device 101, and a PN junction between the P layer 113, which is the main junction, and the N ⁻ layer 112. The electric field in the part is relaxed to ensure a breakdown voltage.

In the present semiconductor device 101, an N ⁻ layer 112 is formed on a semiconductor substrate 111 that is an N ⁺ layer. Here, the semiconductor substrate 111 is an N ⁺ layer as shown in FIG. 1 in the case of a diode, MOSFET, or NPN transistor, and is a P ⁺ layer in the case of an insulated gate bipolar transistor (hereinafter referred to as IGBT). The semiconductor device 101 has two main surfaces that are opposite to each other, and a main current flows between a main electrode 121 provided on one main surface and a main electrode 122 provided on the other main surface. That is, the semiconductor device 101 of this embodiment is a so-called vertical semiconductor device.

Semiconductor substrate 111 is in contact with one main surface, and N ⁻ layer 112 is in contact with the other main surface. N ^- from the major surface of the layer 112 is in contact, N ^- impurity concentration than the layer 112 higher P layer 113 is provided by an impurity diffusion. Furthermore, FLR (Field Limiting Ring) 231, 232, 233, 234, 235, 236, 237, 238, 239 which are P-type semiconductor layers having an impurity concentration higher than that of the N ⁻ layer 112 so as to surround the P layer 113. Is provided. These FLRs have a nine-fold concentric ring shape surrounding the P layer 113. Further, an N ⁺ layer 114 serving as a channel stopper is provided on the outermost peripheral portion of the semiconductor device 101 so as to surround the nine-fold FLR. Part of N ⁻ layer 112 is interposed between adjacent FLRs, between P layer 113 and FLR 231 and between N ⁺ layer 114 and FLR 239.

Main electrode 121 and main electrode 122 are in electrical contact with semiconductor substrate 111 and P layer 113, respectively. A forward field plate included in the main electrode 122 extends on the surface of an insulating film 130 (for example, a silicon oxide film) provided on the surface of the FLR 231 adjacent to the P layer 113. The forward field plate covers a part of the surface of the N ⁻ layer 112 interposed between the P layer 113 and the FLR 231 and the inner peripheral surface of the FLR 231.

The auxiliary electrodes 321, 322, 323, 324, and 123 are in electrical contact with the FLRs 232, 234, 236, 238 and the N ⁺ layer 114, respectively. That is, in the present embodiment, the auxiliary electrode has a five-fold concentric ring shape. The auxiliary electrodes (321, 322, 323, 324) in contact with the FLR include a forward field plate and a reverse field plate. On the inner peripheral surface of the FLR that is adjacent to the FLR with which the auxiliary electrode contacts and on the outer peripheral side and is not in contact with the auxiliary electrode, and on the surface of a part of the N ⁻ layer 112 interposed between the FLRs Is covered by a forward field plate. In addition, the FLR that is in contact with the auxiliary electrode on the inner peripheral side, is separated from the auxiliary electrode and does not come into contact with the outer peripheral surface of the FLR, and a part of the surface of the N ⁻ layer 112 interposed between both FLRs The top is covered by a reverse field plate. Further, the auxiliary electrode 123 in contact with the N ⁺ layer 114 includes a reverse field plate, and the reverse field plate is adjacent to the N ⁺ layer 114 on the inner peripheral side and is included in the FLR group of nine concentric rings. The outer peripheral side surface of FLR 239 located at the outermost periphery and the surface of a part of N ⁻ layer 112 interposed between N ⁺ layer 114 and FLR 239 are covered. Each field plate extends on an insulating film provided on the surface of each FLR and N ⁺ layer 114 and on the surface of N ⁻ layer 112 interposed between FLRs and between N ⁺ layer 114 and FLR 239.

FIG. 3 is a partially enlarged view of a peripheral region of the FLR 233 separated from the auxiliary electrode in FIG. As shown in FIG. 3, the auxiliary electrode and the main electrode are separated and floated between two FLRs that are in contact with the auxiliary electrode, that is, FLR 232 that is in contact with the auxiliary electrode 321 and FLR 234 that is separated from the auxiliary electrode 322. The state FLR 233 is located. The insulating film 130 is formed on the surface of the FLR 233, on the outer peripheral side of the FLR 232, that is, on the surface on the FLR 233 side, on the inner peripheral side of the FLR 234, that is, on the surface on the FLR 233, and on the surface of the N ⁻ layer 112 interposed between the FLRs. Covered by. The forward field plate of the auxiliary electrode 321 and the reverse field plate of the auxiliary electrode 322 extend on the insulating film 130. That is, the surface of FLR 233 separated from the auxiliary electrode and the surface of N ⁻ layer 112 interposed between FLR 233 and FLRs 232 and 234 adjacent to both sides thereof extend from both sides of FLR 233 through insulating film 130. Covered by the auxiliary electrodes 321 and 322.

Similarly, for FLRs 231, 235, 237, and 239, the surface of the N ⁻ layer 112 interposed between the surface of each FLR and the semiconductor layers (FLR, P layer 113, N ⁺ layer 114) adjacent to both sides thereof , FLRs 231, 235, 237 and 239 are covered with auxiliary electrodes extending from both sides of each FLR. Therefore, in the termination region, the surface of the N ⁻ layer 112 having a low impurity concentration is covered with the insulating film 130 and the auxiliary electrode. Further, the FLR is located under the insulating film 130 that is located between the auxiliary electrodes and is not covered by the auxiliary electrodes.

When the semiconductor device 101 of this embodiment is in a voltage blocking state, a plurality of FLRs cause the depletion layer to spread from the PN junction of the P layer 113 and the N ⁻ layer 112 to the termination region, and the electric field strength of the PN junction is reduced. The Moreover, the voltage borne by each FLR can be equalized by the auxiliary electrode having a plurality of FLRs and forward / reverse field plate portions. Thereby, for example, a high breakdown voltage such as 3300V or 4500V can be obtained. Further, in the present embodiment, in the termination region, the surface of the N ⁻ layer 112 that is easily affected by the surface charge is covered with the auxiliary electrode, and the auxiliary electrode or the region not covered by the main electrode is separated from the auxiliary electrode. FLR is located. Therefore, in the termination region, there is almost no portion where the surface of the N ⁻ layer 112 is exposed. For this reason, the semiconductor device of this embodiment can obtain a stable voltage blocking characteristic as will be described later.

Further, according to the study of the present inventor, the electric field is more likely to concentrate in the lower part of the reverse field plate than in the lower part of the forward field plate. Therefore, the FLR interval below the reverse field plate, that is, the width of a part of the N ⁻ layer 112 covered by the reverse field plate is equal to the FLR interval below the forward field plate, ie, N covered by the forward field plate. ^- it is preferably not more than the size of the portion of the width of the layer 112. That is, in FIG. 1, it is preferable to set D1 ≧ D2, D3 ≧ D4, D5 ≧ D6, D7 ≧ D8.

  FIG. 4 shows the relationship between the surface density of charges of the insulating sealing material and the breakdown voltage of the semiconductor device in Embodiment 1 of the present invention. Note that a semiconductor material constituting the semiconductor device is silicon carbide (SiC). As shown in FIG. 4, according to the first embodiment, a stable breakdown voltage can be obtained without being affected by the charge of the insulating sealing material. It should be noted that a stable breakdown voltage can be similarly obtained in other embodiments and modifications described later.

FIG. 5 shows a modification of the first embodiment. In the present modification, the outermost FLR 239 in FIG. 1 is not provided. That is, in the semiconductor device 101 of FIG. 5, the FLR 238 with which the auxiliary electrode 324 contacts is located on the outermost periphery among the FLRs 231 to 238 forming an eight-fold concentric ring shape. Therefore, the surface of the N ⁻ layer 112 interposed between the N ⁺ layer 114 and the FLR 238 is covered with the forward field plate of the auxiliary electrode 324 and the reverse field plate of the auxiliary electrode 123 through the insulating film 130. In FIG. 1, any one of FLRs 231, 233, 235, and 237 can be omitted.

  In the first embodiment of FIG. 1, there are nine FLRs and five auxiliary electrodes, but the number of FLRs and auxiliary electrodes is set according to the breakdown voltage of the semiconductor device.

(Embodiment 2)
FIG. 6 shows a cross-sectional view of the termination region of the semiconductor device according to the second embodiment of the present invention. Moreover, the planar shape of this embodiment is shown by FIG. 2 similarly to Embodiment 1, and FIG. 6 shows the AA 'longitudinal cross section in FIG.

Unlike the first embodiment, the second embodiment is in contact with the outer peripheral side of the P layer 113 between the P layer 113 and the FLR 231, has a lower impurity concentration than the P layer 113, and is deeper than the P layer 113. A deep P ⁻ layer 131 is provided. Part of the N ⁻ layer 112 is interposed between the P ⁻ layer 131 and the innermost FLR 231. The FLRs 231 to 239 have the same concentration profile as the P ⁻ layer 131.

According to the second embodiment, in addition to the same effects as those of the first embodiment, the electric field concentration on the P layer 113 can be relaxed.
(Embodiment 3)
FIG. 7 shows a cross-sectional view of the termination region of the semiconductor device according to the third embodiment of the present invention. Moreover, the planar shape of this embodiment is shown by FIG. 2 similarly to Embodiment 1, and FIG. 7 shows the AA 'longitudinal cross section in FIG.

In the third embodiment, unlike the first embodiment, two FLRs that do not contact the auxiliary electrode, that is, are separated from the auxiliary electrode, are provided between two FLRs that are in contact with two adjacent auxiliary electrodes. . Two FLRs 231 and 232 separated from the auxiliary electrode are also provided between the P layer 113 and the FLR 233 in contact with the innermost auxiliary electrode 321. Further, two FLRs 240 and 241 separated from the auxiliary electrode are also provided between the FLR 239 and the N ⁺ layer 114 in contact with the auxiliary electrode 323. Of the two FLRs separated from the auxiliary electrode and adjacent to each other, the entire surface of the inner FLR and the inner peripheral surface of the outer FLR are covered by the forward field plate via the insulating film 130. In other words, the outer peripheral surface of the outer FLR is covered with the reverse field plate via the insulating film 130.

  FIG. 8 is a sectional view of a termination region of a semiconductor device that is a modification of the third embodiment.

In this modification, three FLRs separated from the auxiliary electrode are provided between two FLRs in contact with two adjacent auxiliary electrodes. Three FLRs 231, 232, and 233 separated from the auxiliary electrode are also provided between the P layer 113 and the FLR 234 in contact with the innermost auxiliary electrode 321. Further, four FLRs 239, 240, 241, and 242 separated from the auxiliary electrode are provided between the FLR 238 and the N ⁺ layer 114 in contact with the auxiliary electrode 322. Of the three FLRs 235, 236, and 237 separated from the auxiliary electrode and adjacent to each other, the entire surface of the FLR 235 and the inner peripheral surface of the FLR 236 are covered with the forward field plate through the insulating film 130. In other words, the outer peripheral surface of the FLR 236 and the entire surface of the FLR 237 are covered with the reverse field plate via the insulating film 130. Of the three FLRs 231, 232, and 233 that are adjacent to each other between the P layer 113 and the FLR 234 and separated from the auxiliary electrode, the entire surface of the FLR 231 and the inner peripheral surface of the FLR 232 are insulated. The film is covered with the forward field plate through the film 130, and the outer surface of the FLR 232 and the entire surface of the FLR 233 are covered with the reverse field plate through the insulating film 130. Further, among the four FLRs 239, 240, 241, and 242 that are adjacent to each other between the FLR 238 and the N ⁺ layer 114 and separated from the auxiliary electrode, the inner surface of the FLR 240 that is adjacent to the entire surface of the innermost FLR 239. The surface on the peripheral side is covered with the forward field plate through the insulating film 130, and the reverse field is formed on the surface on the outer peripheral side of the FLR 240 and on the entire surface of the FLRs 241 and 242 on the outside thereof through the insulating film 130. Covered by a plate.

As in the third embodiment and its modification, between the semiconductor layers in contact with the auxiliary electrode, by increasing the number of FLRs separated from the auxiliary electrode, the depletion layer is in the chip end direction of the semiconductor device in the voltage blocking state. It is possible to ease the electric field concentration.
(Embodiment 4)
The power converter device which is Embodiment 4 of this invention is demonstrated using FIG.

  This embodiment is a three-phase inverter device, and includes a pair of DC terminals 900 and 901 and the same number of AC phases, that is, three AC terminals 910, 911, and 912. An IGBT 700 is connected as one semiconductor switching element between each DC terminal and each AC terminal, and the entire three-phase inverter device includes six IGBTs. A diode 600 is connected in antiparallel to each IGBT. The number of IGBTs 700 and diodes 600 is appropriately set to a plurality of numbers according to the number of AC phases, the power capacity of the power converter, and the breakdown voltage and current capacity of the semiconductor switching element 700 alone.

  By driving each IGBT 700 and each diode 600 by the gate drive circuit 800, the DC power received from the DC power supply 960 to the DC terminals 900 and 901 is converted into AC power, and the AC power is converted from the AC terminals 910, 911, and 912. Is output. Each AC output terminal is connected to a motor 950 such as an induction machine or a synchronous machine, and the motor 950 is rotationally driven by AC power output from each AC terminal.

  According to the present embodiment, by applying the diodes of the first to third embodiments and the modification described above as the diode 600, the withstand voltage characteristic of the diode can be made high withstand voltage and stable, so that the capacity of the inverter device can be increased. The reliability of the inverter device is improved.

  Although the present embodiment is an inverter device, the semiconductor device and the drive circuit according to the present invention can be applied to other power conversion devices such as converters and choppers, and similar effects can be obtained.

  Needless to say, the present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the technical idea of the present invention. For example, the conductivity type of each semiconductor layer may be reversed in the above-described embodiments. The semiconductor material constituting the semiconductor device is not limited to SiC in the above-described embodiments, but may be other wide gap semiconductors such as GaN (gallium nitride) or Si (silicon).

101 ... Semiconductor device,
102 ... active region,
103 ... Termination area,
111 ... N ⁺ layer,
112 ... N ^- layer,
113 ... P layer,
114 ... N ⁺ layer,
121, 122 ... main electrode,
131 ... P ^- layer,
231,232,233,234,235,236,237,238,239,240,241,242 ... FLR, 123,321,322,323,324 ... auxiliary electrode

Claims (10)

In a semiconductor device comprising a first semiconductor region of a first conductivity type, wherein an active region in which a main current flows and a termination region located around the active region are provided in the first semiconductor region.
The termination region is
A plurality of second semiconductor regions of a second conductivity type provided in the first semiconductor region so as to surround the active region;
A plurality of first auxiliary electrodes in contact with the plurality of second semiconductor regions;
At least one first semiconductor region is provided in the first semiconductor region so as to surround the active region, is positioned between two adjacent second semiconductor regions, and is separated from the first auxiliary electrode. A third semiconductor region of two conductivity types;
With
The semiconductor device, wherein a surface of the third semiconductor region is covered with the first auxiliary electrodes in contact with the two second semiconductor regions.   2. The semiconductor device according to claim 1, wherein a surface of a part of the first semiconductor region interposed between the two second semiconductor regions and the third semiconductor region is the two second semiconductor regions. (2) The semiconductor device is covered with each of the first auxiliary electrodes in contact with the semiconductor region.   2. The semiconductor device according to claim 1, wherein a surface of the third semiconductor region is covered with a forward field plate and a reverse field plate included in each of the first auxiliary electrodes in contact with the two second semiconductor regions. A semiconductor device.   4. The semiconductor device according to claim 3, wherein a surface of a part of the first semiconductor region interposed between the two second semiconductor regions and the third semiconductor region is the forward field plate and the A semiconductor device covered with an inverted field plate.   5. The semiconductor device according to claim 4, wherein a width of a portion covered by the reverse field plate in a part of the first semiconductor region is covered by the forward field plate in a part of the first semiconductor region. A semiconductor device having a width equal to or less than a width. The semiconductor device according to claim 1,
The active region is
A fourth semiconductor region of a second conductivity type provided in the first semiconductor region;
A first main electrode in contact with the fourth semiconductor region;
With
In the termination area,
A fifth semiconductor of a second conductivity type, wherein the first main electrode and the first auxiliary electrode are separated between the fourth semiconductor region and the second semiconductor region adjacent to the fourth semiconductor region. An area is provided,
A surface of the fifth semiconductor region is covered with the first main electrode and the first auxiliary electrode which is in contact with the second semiconductor region adjacent to the fourth semiconductor region.   7. The semiconductor device according to claim 6, wherein an impurity concentration of the second, third, and fifth semiconductor regions is lower than an impurity concentration of the fourth semiconductor region, and the second, third, and fifth semiconductor regions. The depth of the semiconductor device is deeper than the depth of the fourth semiconductor region. The semiconductor device according to claim 1,
The termination region is
A sixth semiconductor region of a first conductivity type provided so as to surround the plurality of second semiconductor regions in the first semiconductor region and having a higher impurity concentration than the first semiconductor region;
A second auxiliary electrode in contact with the sixth semiconductor region;
With
A seventh semiconductor of a second conductivity type, wherein the first auxiliary electrode and the second auxiliary electrode are separated between the sixth semiconductor region and the second semiconductor region adjacent to the sixth semiconductor region. An area is provided,
The semiconductor device, wherein a surface of the seventh semiconductor region is covered with the second auxiliary electrode and the first auxiliary electrode that contacts the second semiconductor region adjacent to the seventh semiconductor region.   2. The semiconductor device according to claim 1, wherein the first semiconductor region is silicon carbide. A pair of DC terminals;
AC terminals with the same number of AC phases,
A plurality of semiconductor switching elements provided between the DC terminal and the AC terminal;
A plurality of diodes connected in antiparallel to the plurality of semiconductor switching elements;
In a power converter comprising:
The power converter according to claim 1, wherein the diode is the semiconductor device according to claim 1.