JP2014135572A - Data communication device and data communication method - Google Patents

Abstract

An object of the present invention is to easily make a transition to a synchronous state when performing data communication.
A transmission side generates synchronization data by a synchronization data generation unit, and generates auxiliary data by an auxiliary data generation unit. Auxiliary data has a one-to-one ratio of 0 and 1 including synchronization data, or the ratio of 0 and 1 including synchronization data is higher than the ratio of 0 and 1 in synchronization data. The data approaches one to one. On the transmission side, the transmitter 4 transmits the synchronization data and auxiliary data. The receiving side receives the synchronization data and auxiliary data by the receiving unit 7 and adjusts the equalizer 8 based on the synchronization data and auxiliary data. The receiving side discards auxiliary data from the data output from the equalizer 8 by the discarding unit 9 and establishes synchronization based on the remaining synchronization data by the synchronization detecting unit 10.
[Selection] Figure 1

Description

  The present invention relates to a data communication apparatus and a data communication method.

  A transmission line that transmits a high-speed signal between devices on a substrate has a characteristic of attenuating a high-frequency component of a signal propagating through the transmission line. As the line length of the transmission line is longer and the frequency is higher, the attenuation amount of the high frequency component is increased, and the intersymbol interference is increased. For this reason, an equalizer may be provided on the receiving side, and the equalizer may compensate for attenuation of high frequency components. In the case of using an equalizer, it is necessary to finely adjust an equalizer feedback coefficient in advance for optimization. In general, the feedback coefficient is optimized by transmitting a training signal without frequency deviation from the transmission side to the reception side and based on the frequency characteristics of the reception signal on the reception side.

  By the way, there has conventionally been an apparatus that prepares two types of bit strings having different polarities for each of a plurality of types of synchronization patterns, and uses the smaller one of the two types of bit strings as a synchronization pattern ( For example, see Patent Document 1).

JP-A-9-91885

  However, in a data communication apparatus having a conventional equalizer, the equalizer feedback coefficient is optimized using a training signal after transition to a synchronous state. At this time, in order to determine the equalizer feedback coefficient as soon as possible, coarse adjustment of the equalizer feedback coefficient may be performed even before the transition to the synchronous state. However, for example, when Serial RapidIO (SRIO, registered trademark) is used as a protocol between devices, if the ratio of 0 to 1 of the synchronization data is not 1: 1, the frequency of the synchronization data is biased, and the equalizer The coarse adjustment of the feedback coefficient may not be performed well. Therefore, there is a possibility that the state cannot be shifted to the synchronous state. There is a similar problem not only in SRIO but also in general high-speed serial communication that performs a transition process to a synchronous state using synchronization data.

  An object of the present invention is to provide a data communication device and a data communication method that can easily make a transition to a synchronous state.

  The data communication apparatus includes a synchronization data generation unit, an auxiliary data generation unit, a transmission unit, a transmission line, a reception unit, an equalizer, a discard unit, and a synchronization detection unit. The synchronization data generation unit generates synchronization data. The auxiliary data generation unit generates auxiliary data. Auxiliary data has a one-to-one ratio of 0 and 1 including synchronization data, or the ratio of 0 and 1 including synchronization data is higher than the ratio of 0 and 1 in synchronization data. The data may be one-to-one. The transmission unit transmits synchronization data and auxiliary data. The transmission line transmits synchronization data and auxiliary data transmitted from the transmission unit. The receiving unit receives synchronization data and auxiliary data transmitted by the transmission line. The equalizer is adjusted based on the synchronization data and auxiliary data received by the receiving unit. The discard unit discards auxiliary data from the synchronization data and auxiliary data output from the equalizer. The synchronization detection unit establishes synchronization based on the synchronization data output from the discard unit.

  The data communication method generates synchronization data and auxiliary data, and transmits the synchronization data and auxiliary data from the transmission side to the transmission line. Auxiliary data has a one-to-one ratio of 0 and 1 including synchronization data, or the ratio of 0 and 1 including synchronization data is higher than the ratio of 0 and 1 in synchronization data. The data may be one-to-one. On the receiving side, the synchronization data and auxiliary data are received from the transmission line, and the equalizer is adjusted based on the synchronization data and auxiliary data. On the receiving side, auxiliary data is discarded from the synchronization data and auxiliary data output from the equalizer, and synchronization is established based on the synchronization data remaining after the auxiliary data is discarded.

  According to the data communication device and the data communication method, there is an effect that the transition to the synchronous state can be easily performed.

FIG. 1 is a diagram illustrating an example of the data communication apparatus according to the embodiment. FIG. 2 is an explanatory diagram showing an example of the flow of data in the data communication apparatus shown in FIG. FIG. 3 is a diagram illustrating an example of the data communication method according to the embodiment. FIG. 4 is a diagram illustrating an example in which the data communication apparatus according to the embodiment is applied to inter-device data communication. FIG. 5 is a diagram showing a first example of the transmission circuit of the data communication apparatus shown in FIG. FIG. 6 is an explanatory diagram showing an example of a data flow in the transmission circuit shown in FIG. FIG. 7 is a diagram showing an example of data transmission timing in the transmission circuit shown in FIG. FIG. 8 is a diagram illustrating an example of a receiving circuit of the data communication apparatus illustrated in FIG. FIG. 9 is an explanatory diagram showing an example of the data flow in the receiving circuit shown in FIG. FIG. 10 is a diagram illustrating a second example of the transmission circuit of the data communication apparatus illustrated in FIG. FIG. 11 is an explanatory diagram showing an example of the data flow in the transmission circuit shown in FIG. 12 is a diagram illustrating an example of data transmission timing in the transmission circuit illustrated in FIG. FIG. 13 is a diagram illustrating another example of data transmission timing in the transmission circuit illustrated in FIG. FIG. 14 is a diagram showing a third example of the transmission circuit of the data communication apparatus shown in FIG. FIG. 15 is an explanatory diagram showing an example of a data flow in the transmission circuit shown in FIG. FIG. 16 is a diagram showing an example of data transmission timing in the transmission circuit shown in FIG. FIG. 17 is a diagram illustrating another example of data transmission timing in the transmission circuit illustrated in FIG.

  Exemplary embodiments of the data communication apparatus and the data communication method will be described below in detail with reference to the accompanying drawings. In the following description of each embodiment, the same components are denoted by the same reference numerals, and redundant descriptions are omitted.

Example of Data Communication Device FIG. 1 is a diagram illustrating an example of a data communication device according to an embodiment. FIG. 2 is an explanatory diagram showing an example of the flow of data in the data communication apparatus shown in FIG. As shown in FIGS. 1 and 2, the data communication apparatus includes a synchronization data generation unit 2, an auxiliary data generation unit 3, and a transmission unit 4 in the transmission side device 1.

  The synchronization data generation unit 2 generates synchronization data. The auxiliary data generation unit 3 generates auxiliary data. The auxiliary data may be data in which the ratio of 0 and 1 in the data including the synchronization data and the auxiliary data is 1: 1. For example, the auxiliary data may be data having a reverse pattern with respect to the pattern of the synchronization data.

  Alternatively, the auxiliary data may be data that makes the ratio of 0 and 1 in the data including the synchronization data and the auxiliary data closer to one-to-one than the ratio of 0 and 1 in the synchronization data. For example, the auxiliary data may be random data.

  The transmission unit 4 is connected to the synchronization data generation unit 2 and the auxiliary data generation unit 3. The transmission unit 4 transmits the synchronization data output from the synchronization data generation unit 2 and the auxiliary data output from the auxiliary data generation unit 3. As a result, the transmission-side apparatus 1 can send a signal with no frequency deviation or a signal with little frequency deviation to the reception-side apparatus 6.

  The data communication apparatus has a transmission line 5. The transmission line 5 is connected to the transmission unit 4 of the transmission side device 1 and the reception unit 7 of the reception side device 6. The transmission line 5 transmits the synchronization data and auxiliary data transmitted from the transmission unit 4 of the transmission side device 1 to the reception side device 6.

  The data communication apparatus includes a reception unit 7, an equalizer 8, a discard unit 9, and a synchronization detection unit 10 in the reception side device 6. The receiving unit 7 receives the synchronization data and auxiliary data transmitted by the transmission line 5.

  The equalizer 8 is connected to the receiving unit 7. The equalizer 8 is adjusted based on the synchronization data and auxiliary data received by the receiving unit 7. The discard unit 9 is connected to the equalizer 8.

  The discard unit 9 discards auxiliary data from the synchronization data and auxiliary data output from the equalizer 8. The synchronization detection unit 10 is connected to the discard unit 9. The synchronization detection unit 10 establishes synchronization based on the synchronization data output from the discard unit 9.

FIG. 3 is a diagram illustrating an example of the data communication method according to the embodiment. The data communication method shown in FIG. 3 may be implemented in, for example, the data communication apparatus shown in FIG. In this embodiment, for example, the data communication apparatus shown in FIG. 1 will be described as performing the data communication method shown in FIG.

  As shown in FIG. 3, when the data communication method is started in the data communication device, the transmission-side device 1 generates synchronization data by the synchronization data generation unit 2. Further, the transmission side device 1 generates auxiliary data by the auxiliary data generation unit 3 (step S1). And the transmission side apparatus 1 transmits the data for a synchronization and auxiliary | assistant data to the transmission line 5 by the transmission part 4 (step S2).

  On the other hand, the receiving side device 6 receives the synchronization data and the auxiliary data from the transmission line 5 by the receiving unit 7 (step S3). Then, the receiving side device 6 starts adjustment of the equalizer 8 based on the synchronization data and the auxiliary data (step S4). The receiving side device 6 discards auxiliary data from the synchronization data and auxiliary data output from the equalizer 8 by the discarding unit 9 (step S5). Then, the receiving side device 6 establishes synchronization based on the synchronization data remaining after the auxiliary data is discarded by the synchronization detection unit 10 (step S6), and ends the series of processing.

  The adjustment of the equalizer 8 started in step S4 may be completed before the synchronization is established in step S6, or may not be completed when the synchronization is established. Alternatively, coarse adjustment of the equalizer 8 may be started in step S4, and the adjustment of the equalizer 8 may be completed by performing fine adjustment of the equalizer 8 after establishment of synchronization in step S6.

  According to the data communication apparatus shown in FIG. 1 or the data communication method shown in FIG. 3, the transmission-side apparatus 1 sends synchronization data and auxiliary data to the reception-side apparatus 6, so that the reception-side apparatus 6 The ratio of 1 to 1 is received, or data in which the ratio of 0 and 1 is closer to 1 than the ratio of 0 and 1 in the synchronization data is received. That is, the receiving side device 6 receives a signal with no frequency deviation or a signal with little frequency deviation. Thereby, adjustment of the feedback coefficient for setting, for example, the characteristics of the equalizer 8 can be started even before the receiving side device 6 transitions to the synchronous state. Therefore, the receiving side device 6 can be easily shifted to the synchronized state.

  The data communication apparatus shown in FIG. 1 can be applied to, for example, high-speed serial communication that performs a transition process to a synchronous state using synchronization data. For example, the data communication apparatus shown in FIG. 1 can be applied when data communication is performed between devices using SRIO as a protocol between the devices. Hereinafter, a case where data communication is performed between devices using SRIO will be described as an example.

Application Example to Interdevice Data Communication FIG. 4 is a diagram illustrating an example in which the data communication apparatus according to the embodiment is applied to interdevice data communication. As illustrated in FIG. 4, for example, a plurality of devices, for example, a device A 22 and a device B 23 may be mounted on a printed board 21. Device A22 and device B23 perform data communication with each other. The protocol between devices may be SRIO.

  The device A22 and the device B23 may be, for example, a large scale integration (LSI, large scale integrated circuit). As an example of an LSI, there is a central processing unit (CPU, central processing unit), a digital signal processor (DSP, digital signal processor), or a field programmable gate array (FPGA, field programmable gate array).

  Device A22 may have a transceiver A24. The transceiver A24 transmits data to other devices or receives data from other devices. The transceiver A24 may include a transmission circuit A25 and a reception circuit A26. The transmission circuit A25 transmits data output from, for example, a processing circuit (not shown) of the device A22 to another device. The reception circuit A26 receives data from another device and sends it to a processing circuit (not shown) of the device A22.

  Device B23 may have a transceiver B27. The transceiver B27 transmits data to other devices or receives data from other devices. The transceiver B27 may include a transmission circuit B29 and a reception circuit B28. The transmission circuit B29 transmits data output from, for example, a processing circuit (not shown) of the device B23 to another device. The receiving circuit B28 receives data from another device and sends it to a processing circuit (not shown) of the device B23.

  For example, the transmission circuit A25 of the device A22 and the reception circuit B28 of the device B23 are connected to each other by the transmission line 30. The transmission line 30 may be formed on the printed circuit board 21, for example. The transmission line 30 has, for example, a pair of signal wirings, and the signal transmitted through the transmission line 30 may be a differential signal. In this case, the transmission circuit A25 of the device A22 outputs data to be transmitted to another device as a differential signal to the transmission line 30. The receiving circuit B28 of the device B23 receives data from other devices by receiving a differential signal from the transmission line 30.

  For example, the transmission circuit B29 of the device B23 and the reception circuit A26 of the device A22 are connected to each other by the transmission line 31. The transmission line 31 may be formed on the printed circuit board 21, for example. The transmission line 31 has, for example, a pair of signal wirings, and the signal transmitted through the transmission line 31 may be a differential signal. In this case, the transmission circuit B29 of the device B23 outputs the data to be transmitted to other devices to the transmission line 31 as a differential signal. The receiving circuit A26 of the device A22 receives data from other devices by receiving differential signals from the transmission line 31.

  In the present embodiment, an encoding method of high-speed serial transfer such as 8B / 10B is adopted, for example, an 8-bit synchronization code K28.5 is used as a comma code, and the synchronization code K28.5 is changed to 10-bit RD + and RD-. A description will be given assuming that each code is encoded. The synchronization code K28.5 is “101 — 11100”, the RD + code is “110000 — 0101”, and the RD− code is “001111 — 1010”. The synchronization code K28.5, the RD + code, and the RD− code are each one of codes defined in the 8B / 10B system. Hereinafter, the RD + code and the RD− code are collectively referred to as an RD + · RD− code.

  For example, the transmission circuit A25 of the device A22 and the transmission circuit B29 of the device B23 may be the same. In the present embodiment, the transmission circuit A25 of the device A22 and the transmission circuit B29 of the device B23 are assumed to be the same, and the transmission circuit A25 will be described as the transmission circuit 25 and the transmission circuit 25 will be described. The transmission circuit 25 is an example of a transmission side device.

First Example of Transmission Circuit FIG. 5 is a diagram illustrating a first example of the transmission circuit of the data communication apparatus illustrated in FIG. FIG. 6 is an explanatory diagram showing an example of a data flow in the transmission circuit shown in FIG. As shown in FIGS. 5 and 6, the transmission circuit 25 includes a buffer 41, a comma code generation unit 42, a switch control circuit A43, and a switch A44. The transmission circuit 25 includes an encoder 45, an inverter 46, a delay circuit 47, an adder circuit 48, a serializer 49, a phase locked loop (PLL) 50, and a driver 51.

  The buffer 41 is connected to the input terminal 56 of the transmission circuit 25. The input terminal 56 is connected to a processing circuit (not shown) provided in the previous stage of the transmission circuit 25. The buffer 41 stores user data passed from the processing circuit via the input terminal 56.

  The comma code generation unit 42 generates a comma code such as a synchronization code K28.5. The comma code is a code for detecting the word boundary of the serial bit string. The synchronization code K28.5 and the comma code are examples of synchronization data. The comma code generation unit 42 is an example of a synchronization data generation unit.

  The switch A44 is connected to the buffer 41 and the comma code generator 42. The switch A44 is either user data output from the buffer 41 or a comma code such as a synchronization code K28.5 output from the comma code generator 42 based on a control signal output from the switch control circuit A43. Select one to output.

  The switch control circuit A43 is connected to the switch A44. The switch control circuit A43 outputs a control signal that controls switching of the switch A44. For the control signal, a comma code such as a synchronization code K28.5 output from the comma code generation unit 42 is selected when synchronization is not established between the transmission circuit 25 and a reception circuit that is a communication partner of the transmission circuit 25. When synchronization is established, this is a signal for selecting user data output from the buffer 41.

  The encoder 45 is connected to the switch A44. The encoder 45 encodes the data output from the switch A44. The encoder 45 may generate an RD + / RD− code for the synchronization code K28.5 output from the switch A44, for example.

  The inverter 46 is connected to the encoder 45. The inverter 46 generates inverted data of data output from the encoder 45. For example, the inverter 46 generates inversion data of the RD + · RD− code output from the encoder 45, that is, reverse pattern data for each pattern of the RD + code and the RD− code.

  The delay circuit 47 is connected to the inverter 46. The delay circuit 47 is output from the inverter 46 so that the inverted data of the RD + / RD− code output from the inverter 46 is input to the serializer 49 following the RD + • RD− code output from the encoder 45. Delay data. For example, the delay circuit 47 delays the inverted data of the RD + · RD− code by at least the data length of the RD + · RD− code.

  The adder circuit 48 is connected to the encoder 45 and the delay circuit 47. The adder circuit 48 receives the data output from the encoder 45 and the data output from the delay circuit 47 when synchronization is not established between the transmission circuit 25 and the reception circuit that is the communication partner of the transmission circuit 25. Are added and output. When synchronization is not established, the adder circuit 48 outputs the inverted data of the RD + .RD- code following the RD + .RD- code.

  The inverter 46, the delay circuit 47, and the addition circuit 48 are examples of the auxiliary data generation unit. When synchronization is established between the transmission circuit 25 and a reception circuit that is a communication partner of the transmission circuit 25, for example, switching between the encoder 45 and the inverter 46 or addition with the delay circuit 47 by switching by a switch (not shown). The circuit 48 may be disconnected. That is, the user data output from the encoder 45 may be input to the serializer 49 without accompanying inverted data of the user data.

  The serializer 49 is connected to the adder circuit 48. The serializer 49 is a parallel-serial conversion circuit, and converts parallel data output from the adder circuit 48 into high-speed serial data based on a high-speed clock signal supplied from the PLL 50.

  The PLL 50 is connected to a serializer 49 and a reference clock input terminal 59. For example, a reference clock is input to the PLL 50 from the reference clock input terminal 59. The PLL 50 is a phase synchronization circuit and outputs, for example, a high-speed clock signal synchronized with a reference clock.

  The + output terminal of the driver 51 is connected to the + output terminal 57 of the transmission circuit 25. The negative output terminal of the driver 51 is connected to the negative output terminal 58 of the transmission circuit 25. The driver 51 is connected to the serializer 49. The transmission line 30 is connected to the + side output terminal 57 and the − side output terminal 58 of the transmission circuit 25. The driver 51 converts the high-speed serial data output from the serializer 49 to the transmission line 30 as a differential signal. The driver 51 is an example of a transmission unit.

FIG. 7 is a diagram illustrating an example of data transmission timing in the transmission circuit illustrated in FIG. 5. FIG. 7 shows an example of the data transmission timing when the synchronization is not established between the transmission circuit 25 and the reception circuit that is the communication partner of the transmission circuit 25.

  As shown in FIG. 7, when synchronization is not established, the switch control circuit A43 causes the switch A44 to select the output data of the comma code generator 42. The comma code generator 42 periodically outputs the synchronization code K28.5_101. The encoder 45 is periodically input with the synchronization code K28.5_101 output from the comma code generator 42. The encoder 45 converts the synchronization code K28.5_101 into the RD + · RD− code 102 and outputs it.

  The inverter 46 generates inverted data of, for example, RD + · RD− code output from the encoder 45. The inversion data 103 of the RD + · RD− code is periodically output from the delay circuit 47 after being delayed by at least the data length of the RD + · RD− code 102. Therefore, the RD + • RD− code 102 and the inverted data 103 of the RD + • RD− code 102 following the RD + • RD− code 102 are periodically input to the serializer 49.

  In the example of the inter-device data communication shown in FIG. 4, for example, the reception circuit B28 of the device B23 and the reception circuit A26 of the device A22 may be the same. In this embodiment, the receiving circuit B28 of the device B23 and the receiving circuit A26 of the device A22 are the same, and the receiving circuit 28 will be described as the receiving circuit 28. The receiving circuit 28 is an example of a receiving side device.

FIG. 8 is a diagram illustrating an example of the receiving circuit of the data communication apparatus illustrated in FIG. FIG. 9 is an explanatory diagram showing an example of the data flow in the receiving circuit shown in FIG. In this embodiment, for example, a 10-bit RD + .RD- code is decoded into an 8-bit synchronization code K28.5.

  As illustrated in FIGS. 8 and 9, the reception circuit 28 includes a receiver 61, an equalizer 62, a deserializer 63, a decoder 64, a detection / discard circuit 65, a comma code detection circuit 66, and a synchronization detection circuit 67. The receiving circuit 28 includes a PLL 68, a duty cycle correlator (DCC) 69, a phase interpolator (PI) 70, and a clock data recovery (CDR) 71.

  The + side input terminal of the receiver 61 is connected to the + side input terminal 76 of the receiving circuit 28. The negative input terminal of the receiver 61 is connected to the negative input terminal 77 of the reception circuit 28. The transmission line 30 is connected to a positive input terminal 76 and a negative input terminal 77 of the reception circuit 28. The receiver 61 returns the differential signal input from the transmission line 30 to high-speed serial data. The receiver 61 is an example of a receiving unit.

  The equalizer 62 is connected to the output terminal of the receiver 61 and the PI 70. The equalizer 62 acquires data output from the receiver 61 at a timing determined by the data strobe signal output from the PI 70. In a state before the synchronization is established, the receiving circuit 28 periodically receives the RD + • RD− code, the RD + • RD− code, and the inverted data of the RD + • RD− code from the transmitting circuit 25 through the transmission line 30. Is input.

  The equalizer 62 starts adjusting the feedback coefficient for setting the characteristics of the equalizer 62 based on the RD + · RD− code and the inverted data of the RD + · RD− code before the synchronization is established. The equalizer 62 may complete the adjustment of the feedback coefficient before the synchronization is established, or may finish the adjustment of the feedback coefficient after the establishment of the synchronization. The equalizer 62 may perform coarse adjustment of the feedback coefficient before synchronization is established, and may perform fine adjustment of the feedback coefficient after establishment of synchronization.

  After synchronization is established, user data is input from the transmission circuit 25 to the reception circuit 28 via the transmission line 30. After the synchronization is established, the equalizer 62 whose feedback coefficient has been adjusted returns the user data signal that deteriorates during propagation on the transmission line 30 to the original transmission signal. For example, the equalizer 62 may compensate for the high frequency component that attenuates when the differential signal propagates through the transmission line 30 by raising the high frequency component of the signal input to the equalizer 62.

  The deserializer 63 is connected to the equalizer 62. The deserializer 63 is a serial / parallel conversion circuit, and converts the high-speed serial data output from the equalizer 62 into low-speed parallel data.

  The decoder 64 is connected to the deserializer 63. The decoder 64 decodes data output from the deserializer 63. For example, the decoder 64 may decode the synchronization code K28.5 from the RD + · RD− code output from the deserializer 63 and may decode the inverted data of the RD + · RD− code.

  The detection / discard circuit 65 is connected to the decoder 64. In the state before the synchronization is established, the detection / discard circuit 65 may detect and discard the data matching the desired pattern from the data output from the decoder 64. For example, the detection / discard circuit 65 may hold a data pattern obtained by decoding the inverted data of the RD + / RD− code.

  For example, the detection / discard circuit 65 obtains data obtained by decoding the inverted data of the synchronization code K28.5 and the RD + · RD− code output from the decoder 64, and the data obtained by decoding the inverted data of the RD + · RD− code. You may compare with the pattern. The detection / discard circuit 65 may detect data that matches the data pattern obtained by decoding the inverted data of the RD + / RD- code, and discard the matching data.

  Alternatively, in the state before the synchronization is established, the detection / discard circuit 65 may detect and discard data that does not match a desired pattern from the data output from the decoder 64. For example, the detection / discard circuit 65 may hold the pattern of the synchronization code K28.5.

  For example, the detection / discard circuit 65 may compare the data obtained by decoding the inverted data of the synchronization code K28.5 and the RD + / RD− code output from the decoder 64 with the pattern of the synchronization code K28.5. Then, the detection / discard circuit 65 may detect data that does not match the pattern of the synchronization code K28.5, and discard the mismatched data.

  In the state after the synchronization is established, the detection / discard circuit 65 may be invalidated by switching with a switch (not shown), for example. That is, the detection / discard circuit 65 may output the user data as it is without comparing the pattern with the user data output from the decoder 64 after synchronization is established. The detection / discard circuit 65 is an example of a discard unit.

  The comma code detection circuit 66 is connected to the detection / discard circuit 65 and the synchronization detection circuit 67. In the state before the synchronization is established, the comma code detection circuit 66 detects the synchronization code K28.5 from the data output from the detection / discard circuit 65 and outputs it to the synchronization detection circuit 67. For example, the comma code detection circuit 66 may hold the pattern of the synchronization code K28.5. For example, the comma code detection circuit 66 may compare the data output from the detection / discard circuit 65 with the pattern of the synchronization code K28.5 and detect data that matches the pattern of the synchronization code K28.5.

  The output terminal of the comma code detection circuit 66 is connected to the output terminal 79 of the reception circuit 28. The output terminal 79 is connected to a processing circuit (not shown) provided at the subsequent stage of the receiving circuit 28. In the state after the synchronization is established, the comma code detection circuit 66 may output the user data output from the detection / discard circuit 65 to a processing circuit (not shown) via the output terminal 79. The comma code detection circuit 66 and the detection / discard circuit 65 may be integrated.

  The synchronization detection circuit 67 is connected to the comma code detection circuit 66. When the synchronization detection circuit 67 detects the synchronization code K28.5 repeatedly given from the comma code detection circuit 66 a predetermined number of times without detecting an illegal code in a state where the synchronization is not established, the synchronization is established. Judge that On the other hand, the synchronization detection circuit 67 determines that synchronization is not established when an invalid code is detected in a state where synchronization is established. For example, the synchronization detection circuit 67 may determine that synchronization is not established when an invalid code is detected within 256 words in a state where synchronization is established. The synchronization detection circuit 67 is an example of a synchronization detection unit.

  The PLL 68 is connected to an input terminal 78 for a reference clock. For example, a reference clock is input to the PLL 68 from the reference clock input terminal 78. The PLL 68 is a phase synchronization circuit and outputs, for example, a high-speed clock signal synchronized with a reference clock.

  The DCC 69 is connected to the PLL 68. The DCC 69 adjusts the rising edge and the falling edge of the high-speed clock signal output from the PLL 68.

  The CDR 71 is connected to the output terminal of the equalizer 62. The CDR 71 reproduces a clock signal from the data output from the equalizer 62.

  The PI 70 is connected to the DCC 69, the CDR 71 and the equalizer 62. The PI 70 generates a data strobe signal by adjusting the phase of the high-speed clock signal output from the DCC 69 based on the clock signal output from the CDR 71.

  According to the data communication apparatus having the transmission circuit 25 shown in FIG. 5 and the reception circuit 28 shown in FIG. 8, the transmission circuit 25 sends the RD + · RD− code and the inverted data of the RD + · RD− code to the reception circuit 28. The receiving circuit 28 receives data in which the ratio of 0 and 1 is 1: 1. That is, the receiving circuit 28 receives a signal with no frequency deviation. Thereby, adjustment of the feedback coefficient for setting the characteristic of the equalizer 62, for example, can be started even before the reception circuit 28 transitions to the synchronous state. Therefore, the receiving circuit 28 can be easily shifted to the synchronous state.

FIG. 10 is a diagram illustrating a second example of the transmission circuit of the data communication apparatus illustrated in FIG. FIG. 11 is an explanatory diagram showing an example of the data flow in the transmission circuit shown in FIG. The transmission circuit 25 shown in FIGS. 10 and 11 switches the output of the adder circuit 48 and the output of the encoder 45 in the transmission circuit 25 shown in FIG. The transmission circuit 25 includes a switch control circuit B81 and a switch B82 in addition to the configuration of the transmission circuit 25 illustrated in FIG.

  The switch B82 is connected to the encoder 45 and the adding circuit 48. The switch B82 selects either the data output from the encoder 45 or the data output from the adder circuit 48 based on the control signal output from the switch control circuit B81 and outputs the selected data to the serializer 49.

  The switch control circuit B81 is connected to the switch B82. The switch control circuit B81 outputs a control signal that controls switching of the switch B82. When the receiving circuit that is the communication partner of the transmitting circuit 25 has a function of discarding the data obtained by decoding the inverted data of the RD + / RD− code as in the receiving circuit 28 shown in FIG. , A signal for selecting data output from the adder circuit 48.

  When the receiving circuit that is the communication partner of the transmitting circuit 25 does not have the function of discarding the data obtained by decoding the inverted data of the RD + / RD− code, the control signal selects the data output from the encoder 45 Signal. Whether the switch control circuit B81 outputs a control signal for selecting the output data of the adder circuit 48 or a signal for selecting the output data of the encoder 45 depends on the type of the receiving circuit that is the communication partner of the transmitting circuit 25. It may be set in advance accordingly.

  The serializer 49 is connected to the switch B82. The serializer 49 converts the parallel data output from the switch B82 into high-speed serial data based on the high-speed clock signal supplied from the PLL 50.

  In the second example of the transmission circuit, the buffer 41, the comma code generation unit 42, the switch control circuit A43, the switch A44, the encoder 45, the inverter 46, the delay circuit 47, the addition circuit 48, the PLL 50, and the driver 51, This is as described in the first example. Therefore, the overlapping description is omitted.

Example of Data Transmission Timing in Second Example of Transmission Circuit FIG. 12 is a diagram illustrating an example of data transmission timing in the transmission circuit shown in FIG. FIG. 12 shows a synchronization between the transmission circuit 25 and the reception circuit when the reception circuit that is the communication partner of the transmission circuit 25 has a function of discarding data obtained by decoding the inverted data of the RD + / RD− code. An example of the data transmission timing when No is established is shown.

  As shown in FIG. 12, when the synchronization is not established, the switch control circuit A43 selects the output data of the comma code generation unit 42 by the switch control circuit A43, and the switch B82 causes the switch B82 to output the output data of the adder circuit 48. select. The data transmission timing in this case is the same as the data transmission timing shown in FIG. Therefore, the overlapping description is omitted.

FIG. 13 is a diagram illustrating another example of the data transmission timing in the transmission circuit illustrated in FIG. 10. In FIG. 13, when the receiving circuit that is the communication partner of the transmitting circuit 25 does not have a function of discarding the data obtained by decoding the inverted data of the RD + / RD− code, the transmitting circuit 25 and the receiving circuit are connected. An example of data transmission timing when synchronization is not established is shown.

  As shown in FIG. 13, when synchronization is not established, the switch control circuit A43 selects the output data of the comma code generator 42 by the switch control circuit A43, and the switch B82 selects the output data of the encoder 45 by the switch control circuit B81. To do. The comma code generator 42 periodically outputs the synchronization code K28.5_101. The encoder 45 is periodically input with the synchronization code K28.5_101 output from the comma code generator 42. The encoder 45 converts the synchronization code K28.5_101 into the RD + · RD− code 102 and outputs it.

  The inverter 46 generates inverted data of, for example, RD + · RD− code output from the encoder 45. The inversion data 103 of the RD + · RD− code is periodically output from the delay circuit 47 after being delayed by at least the data length of the RD + · RD− code 102. However, since the output of the encoder 45 is selected by the switch B 82, the inverted data 103 of the RD + · RD− code 102 output from the delay circuit 47 is not input to the serializer 49. Therefore, the RD + · RD− code 102 output from the encoder 45 is periodically input to the serializer 49.

  According to the data communication apparatus having the transmission circuit 25 shown in FIG. 10, when the reception circuit as the communication partner has a function of discarding data obtained by decoding the inverted data of the RD + / RD− code, It is possible to deal with any of the cases where it is not provided. When the receiving circuit as the communication partner has a function of discarding data obtained by decoding the inverted data of the RD + / RD- code, the data having the transmitting circuit 25 shown in FIG. 5 and the receiving circuit 28 shown in FIG. The same effect as the communication device can be obtained. That is, adjustment of the feedback coefficient for setting the characteristics of the equalizer 62 can be started even before the reception circuit 28 transitions to the synchronous state. Therefore, the receiving circuit 28 can be easily shifted to the synchronous state.

FIG. 14 is a diagram illustrating a third example of the transmission circuit of the data communication apparatus illustrated in FIG. 4. FIG. 15 is an explanatory diagram showing an example of a data flow in the transmission circuit shown in FIG. 14 and 15 includes a buffer 41, a comma code generation unit 42, a switch control circuit A43, and a switch A44. The buffer 41, the comma code generation unit 42, the switch control circuit A43, and the switch A44 are as described in the first example of the transmission circuit. Therefore, the overlapping description is omitted.

  The transmission circuit 25 includes a random burst data generation unit 91, a switch control circuit C92, a switch C93, an encoder 45, a serializer 49, a PLL 50, and a driver 51. The PLL 50 and the driver 51 are as described in the first example of the transmission circuit. Therefore, the overlapping description is omitted.

  The random burst data generation unit 91 generates random burst data with a time length shorter than the transmission interval of the synchronization code K28.5. The random burst data is data in which 0 and 1 are arranged at random. In random burst data, the ratio between 0 and 1 is 1: 1 or close to 1: 1. Random burst data is an example of synchronization data. The random burst data generation unit 91 is an example of an auxiliary data generation unit.

  The switch C93 is connected to the switch A44 and the random burst data generation unit 91. The switch C93 selects either the data output from the switch A44 or the data output from the random burst data generation unit 91 based on the control signal output from the switch control circuit C92, and sends it to the encoder 45. Output.

  The switch control circuit C92 is connected to the switch C93. The switch control circuit C92 outputs a control signal that controls switching of the switch C93. The control signal is a synchronization signal output from the switch A44 at the timing when the synchronization code K28.5 is transmitted in a state where synchronization is not established between the transmission circuit 25 and the reception circuit that is the communication partner of the transmission circuit 25. This is a signal for selecting the code K28.5.

  The control signal selects the random burst data output from the random burst data generation unit 91 at the timing of transmitting the random burst data in a state where synchronization is not established between the transmission circuit 25 and the receiving circuit of the communication partner. Signal. The control signal is a signal for selecting user data output from the switch A44 when synchronization is established between the transmission circuit 25 and the receiving circuit of the communication partner.

  The switch control circuit C92 alternately switches and outputs a control signal for selecting the output data of the switch A44 and a control signal for selecting the output data of the random burst data generation unit 91, or selects the output data of the switch A44. Whether to output the control signal may be set in advance according to the type of the receiving circuit that is the communication partner of the transmitting circuit 25.

  The encoder 45 is connected to the switch C93. The encoder 45 encodes data output from the switch C93. The encoder 45 may generate an RD + / RD- code for the synchronization code K28.5 output from the switch C93, for example. The encoder 45 encodes the random burst data output from the random burst data generation unit 91 and generates encoded data of the random burst data.

  In the encoded data of random burst data, 0 and 1 are randomly arranged, and the ratio of 0 and 1 is a ratio of 1: 1 or close to 1: 1. Accordingly, in the data obtained by combining the RD + / RD- code output from the encoder 45 and the encoded data of the random burst data, the ratio of 0 to 1 is a ratio of 1: 1 or close to 1: 1.

  The serializer 49 is connected to the encoder 45. The serializer 49 converts the parallel data output from the encoder 45 into high-speed serial data based on the high-speed clock signal supplied from the PLL 50.

  For example, the receiving circuit 28 shown in FIG. 8 may be used as the receiving circuit serving as a communication partner of the transmitting circuit 25 shown in FIG. However, in the receiving circuit 28 shown in FIG. 8, the detection / discard circuit 65 detects and discards data that does not match a desired pattern from the data output from the decoder 64 before the synchronization is established.

  For example, the detection / discard circuit 65 may hold the pattern of the synchronization code K28.5. For example, the detection / discard circuit 65 compares the synchronization code K28.5 and random burst data output from the decoder 64 with the pattern of the synchronization code K28.5, and detects data that does not match the pattern of the synchronization code K28.5. May be discarded.

Example of Data Transmission Timing in Third Example of Transmission Circuit FIG. 16 is a diagram illustrating an example of data transmission timing in the transmission circuit shown in FIG. FIG. 16 shows the data transmission timing when synchronization is not established between the transmission circuit 25 and the reception circuit in the case where the reception circuit serving as the communication partner of the transmission circuit 25 has a function of discarding random burst data. An example is shown.

  As shown in FIG. 16, when the synchronization is not established, the switch control circuit A43 causes the switch A44 to select the output data of the comma code generator 42. The switch control circuit C92 causes the switch C93 to alternately select the output data of the switch A44 and the output data of the random burst data generation unit 91.

  The comma code generator 42 periodically outputs the synchronization code K28.5_101. In accordance with the output timing of the synchronization code K28.5_101, the switch C93 selects the output data of the switch A44. The random burst data generation unit 91 periodically outputs the random burst data 104 at a timing between the outputs of successive synchronization codes K28.5_101. In accordance with the output timing of the random burst data 104, the switch C93 selects the output data of the random burst data generation unit 91.

  The encoder 45 is periodically inputted with the synchronization code K28.5_101 and the random burst data 104 following the synchronization code K28.5_101. Although not shown in FIG. 16, the serializer 49 receives the RD + • RD− code generated by encoding the synchronization code K28.5_101 and the RD + • RD− code followed by the encoding of the random burst data 104. Data to be generated is periodically input.

FIG. 17 is a diagram showing another example of data transmission timing in the transmission circuit shown in FIG. 14. FIG. 17 shows the data transmission timing when synchronization is not established between the transmission circuit 25 and the reception circuit when the reception circuit that is the communication partner of the transmission circuit 25 does not have the function of discarding random burst data. An example is shown.

  As shown in FIG. 17, when the synchronization is not established, the switch control circuit A43 causes the switch A44 to select the output data of the comma code generator 42. The switch control circuit C92 causes the switch C93 to select the output data of the switch A44.

  The comma code generator 42 periodically outputs the synchronization code K28.5_101. The random burst data generation unit 91 periodically outputs the random burst data 104 at a timing between the outputs of successive synchronization codes K28.5_101.

  However, since the output of the switch A44 is selected by the switch C93, the random burst data output from the random burst data generation unit 91 is not input to the encoder 45. Therefore, the synchronization code K28.5_101 is periodically input to the encoder 45. Although not shown in FIG. 17, the RD + / RD− code generated by encoding the synchronization code K28.5_101 is periodically input to the serializer 49.

  According to the data communication apparatus having the transmission circuit 25 shown in FIG. 14 and the reception circuit 28 shown in FIG. 8, the transmission circuit 25 sends the RD + · RD− code and encoded data of random burst data to the reception circuit 28. Accordingly, the reception circuit 28 receives data in which the ratio between 0 and 1 is 1: 1, or data whose ratio is closer to 1: 1 than the ratio between 0 and 1 in the RD + .RD- code. That is, the receiving circuit 28 receives a signal with no frequency deviation or with a frequency deviation smaller than the frequency deviation in the RD + · RD− code. Thereby, adjustment of the feedback coefficient for setting the characteristic of the equalizer 62, for example, can be started even before the reception circuit 28 transitions to the synchronous state. Therefore, the receiving circuit 28 can be easily shifted to the synchronous state.

  According to the data communication apparatus having the transmission circuit 25 shown in FIG. 14, the reception circuit as the communication partner can cope with both the case of having a function of discarding random burst data and the case of not having the function. Can do.

  The following additional notes are disclosed with respect to the embodiments including the above-described examples.

(Supplementary Note 1) The synchronization data generation unit for generating the synchronization data and the ratio of 0 and 1 including the synchronization data are set to 1: 1, or 0 and 1 including the synchronization data The auxiliary data generating unit that generates auxiliary data that makes the ratio of 1 to 1 closer to the ratio of 0 and 1 in the synchronization data, the transmission unit that transmits the synchronization data and the auxiliary data, A transmission line for transmitting the synchronization data and the auxiliary data transmitted from the transmission unit, a reception unit for receiving the synchronization data and the auxiliary data transmitted by the transmission line, and the reception unit. An equalizer that is adjusted based on the synchronization data and the auxiliary data, and a break that discards the auxiliary data from the synchronization data and the auxiliary data that are output from the equalizer. Parts and data communication apparatus, characterized in that it comprises a synchronization detector for establishing synchronization based on the synchronization data outputted from the discard portions.

(Supplementary note 2) The data communication device according to supplementary note 1, wherein the auxiliary data is data having a reverse pattern with respect to the pattern of the synchronization data.

(Supplementary Note 3) The auxiliary data generation unit includes an inverter that inverts the synchronization data, a delay circuit that delays data output from the inverter by at least the data length of the synchronization data, and the synchronization data And a data adder that adds the data output from the delay circuit.

(Supplementary Note 4) A switch for switching data output from the adder circuit via the inverter and the delay circuit and data before being input to the inverter and sending the data to the transmission unit, and switching the switch The data communication device according to appendix 3, further comprising a control circuit for controlling.

(Supplementary Note 5) The discard unit compares the data output from the equalizer with the data of the reverse pattern with respect to the pattern of the synchronization data, so that the synchronization is performed from the data output from the equalizer. 5. The data communication apparatus according to any one of appendices 2 to 4, wherein data having a reverse pattern is detected and discarded with respect to the pattern of data for use.

(Supplementary note 6) The data communication device according to supplementary note 1, wherein the auxiliary data is random data.

(Supplementary note 7) A switch for switching the synchronization data output from the synchronization data generation unit and the random data output from the auxiliary data generation unit to send to the transmission unit, and controlling switching of the switch The data communication device according to appendix 6, further comprising:

(Supplementary note 8) The data communication apparatus according to supplementary note 7, wherein the transmission unit burst-transmits the random data at intervals equal to or less than a transmission interval of the synchronization data.

(Additional remark 9) The said discard part compares the data output from the said equalizer with the pattern of the said data for a synchronization, The pattern different from the pattern of the said data for a synchronization out of the data output from the said equalizer The data communication apparatus according to any one of appendices 6 to 8, wherein the data is detected and discarded.

(Supplementary Note 10) The ratio of 0 and 1 including the synchronization data and the synchronization data is set to 1: 1, or the ratio of 0 and 1 including the synchronization data is set in the synchronization data. Auxiliary data that is closer to 1: 1 than the ratio of 0 and 1 is generated, the synchronization data and the auxiliary data are transmitted from the transmission side to the transmission line, and the synchronization data is transmitted from the transmission line on the reception side. Receiving the data and the auxiliary data, adjusting an equalizer based on the synchronization data and the auxiliary data, discarding the auxiliary data from the synchronization data and the auxiliary data output from the equalizer, and A data communication method comprising establishing synchronization based on the synchronization data remaining after discarding data.

(Supplementary note 11) The data communication method according to supplementary note 10, wherein the auxiliary data is data having a reverse pattern with respect to the pattern of the synchronization data.

(Supplementary note 12) The data communication method according to supplementary note 10, wherein the auxiliary data is random data.

DESCRIPTION OF SYMBOLS 1 Transmission side apparatus 2 Synchronization data generation part 3 Auxiliary data generation part 4 Transmission part 5 Transmission line 6 Reception side apparatus 7 Reception part 8,62 Equalizer 9 Discarding part 10 Synchronization detection part 42 Comma code generation part 46 Inverter 47 Delay circuit 48 Adder circuit 51 Driver 61 Receiver 65 Detection / discard circuit 67 Synchronization detection circuit 81, 92 Switch control circuit 82, 93 Switch

Claims (5)

A data generator for synchronization that generates data for synchronization;
The ratio of 0 and 1 including the synchronization data is set to 1: 1, or the ratio of 0 and 1 including the synchronization data is set to 1 rather than the ratio of 0 and 1 in the synchronization data. An auxiliary data generation unit that generates auxiliary data that approaches one-to-one;
A transmission unit for transmitting the synchronization data and the auxiliary data;
A transmission line for transmitting the synchronization data and the auxiliary data transmitted from the transmission unit;
A receiver for receiving the synchronization data and the auxiliary data transmitted by the transmission line;
An equalizer that is adjusted based on the synchronization data and the auxiliary data received by the receiving unit;
A discarding unit that discards the auxiliary data from the synchronization data and the auxiliary data output from the equalizer;
A synchronization detection unit that establishes synchronization based on the synchronization data output from the discard unit;
A data communication apparatus comprising:   The data communication apparatus according to claim 1, wherein the auxiliary data is data having a reverse pattern with respect to the pattern of the synchronization data.   The data communication apparatus according to claim 1, wherein the auxiliary data is random data. The synchronization data and the ratio of 0 and 1 including the synchronization data are set to 1: 1, or the ratio of 0 and 1 including the synchronization data is set to 0 and 1 in the synchronization data. Auxiliary data that is closer to 1: 1 than the ratio of
Sending the synchronization data and the auxiliary data from the transmission side to the transmission line,
On the receiving side, receiving the synchronization data and the auxiliary data from the transmission line,
While adjusting the equalizer based on the synchronization data and the auxiliary data,
Discarding the auxiliary data from the synchronization data and the auxiliary data output from the equalizer;
A data communication method comprising establishing synchronization based on the synchronization data remaining after discarding the auxiliary data.   5. The data communication method according to claim 4, wherein the auxiliary data is data having a reverse pattern with respect to the pattern of the synchronization data.

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