JP2014132512A - Nonvolatile semiconductor memory device and writing method thereof - Google Patents

Abstract

Variations in threshold voltage distribution after programming are minimized, and high-speed rewriting characteristics are obtained.
In a non-volatile semiconductor memory device including a non-volatile memory cell array and a control circuit for controlling writing to the memory cell array, the control circuit performs an erasing process for erasing data of a memory cell to be written. Detecting a program speed when writing to the memory cell array, determining a program start voltage corresponding to the program speed for each block or word line, and storing the determined program start voltage in the memory cell array, A program start voltage is read from the memory cell array and predetermined data is written.
[Selection] Figure 19

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM) such as a flash memory and a writing method thereof.

  2. Description of the Related Art A NAND-type nonvolatile semiconductor memory device is known in which a NAND string is configured by connecting a plurality of memory cell transistors (hereinafter referred to as memory cells) in series between a bit line and a source line to realize high integration. (For example, refer to Patent Documents 1 to 4.)

  In a general NAND type nonvolatile semiconductor memory device, erasing is performed by applying a high voltage of, for example, 20V to the semiconductor substrate and applying 0V to the word line. As a result, electrons are extracted from the floating gate, which is a charge storage layer made of, for example, polysilicon, and the threshold value is made lower than the erase threshold value (for example, −3 V). On the other hand, in writing (programming), 0 V is applied to the semiconductor substrate, and a high voltage of, for example, 20 V is applied to the control gate. As a result, by injecting electrons from the semiconductor substrate into the floating gate, the threshold value is made higher than the write threshold value (for example, 1 V). A memory cell having these threshold values depends on whether a current flows through the memory cell by applying a read voltage (for example, 0 V) between the write threshold value and the read threshold value to the control gate. The state can be determined.

  In the nonvolatile semiconductor memory device configured as described above, when a write operation is performed on a memory cell to be written by a program operation, charges are injected into the floating gate of the memory cell transistor and the threshold voltage rises. As a result, even when a voltage equal to or lower than the threshold is applied to the gate, no current flows, and a state in which data “0” is written is achieved. Generally, the threshold voltage of an erased memory cell varies, and the writing speed also varies due to process variations. Therefore, when a program operation is executed by applying a predetermined write voltage and the threshold voltage is verified to be equal to or higher than the verify level, the threshold voltage of the memory cell after writing has a certain distribution above the verify level. It will be a thing.

  Incidentally, an ISPP (Increment Step Pulse Program) method is used as a method for more effectively writing to a memory having a large writing speed variation due to process variations. That is, when the process variation in the process is large, the threshold voltage distribution after the memory cell is written by one pulse becomes large. Even if the verify technique is simply used for each bit, if the threshold voltage is controlled to be narrow, writing / verification must be repeated finely, resulting in a long time for writing. Therefore, as shown in FIG. 4, a method is used in which the voltage of the program pulse PP is started from the program start voltage Vstart and increased by a predetermined step voltage Vstep and verified for each bit.

JP-A-9-147582 JP 2000-285692 A JP 2003-346485 A JP 2001-028575 A JP 2001-325796 A JP 2010-102751 A JP 2009-283117 A

  Here, in order to obtain a predetermined threshold voltage distribution by programming the NAND flash EEPROM, the program start voltage Vstart is an important parameter as shown below. As shown in FIG. 5, the program start voltage Vstart determines the width of the threshold voltage distribution. Here, in order to narrow the threshold voltage distribution, it is preferable to use a lower program start voltage Vstart. , The program time becomes longer. On the other hand, when a higher program start voltage Vstart is used, the program time is shortened but the threshold voltage distribution is widened. Also, after the program and erase cycles, if the program start voltage Vstart is the same, the threshold voltage distribution becomes wider and the program speed varies depending on the word lines in the memory cell array block. was there. Therefore, optimization of the program start voltage Vstart is an important issue.

  In the prior art, the same program start voltage Vstart is generally used for one chip. Even in the manufacturing process of the applicant, the actual situation is that the variation in the program speed for each block or word line is not taken into consideration for one chip (for example, see Patent Document 6). Further, as described above, when the program speed is high, the threshold voltage distribution is wide for each corresponding block. Therefore, there is a problem that the durability of deterioration of the oxide film itself accompanying data rewriting deteriorates, and it is difficult to obtain a high-speed and many-time rewriting characteristic.

  FIG. 6 is a diagram showing a threshold voltage Vth distribution when the NAND flash EEPROM is programmed using the same program start voltage Vstart when the ISPP (Increment Step Pulse Program) method of FIG. 4 is programmed. . FIG. 11 is a table showing the program start voltage Vstart used in the prior art. As shown in FIG. 11, when programming is performed using the same program start voltage Vstart in each block, there is a problem that the threshold voltage distribution varies as apparent from FIG.

  In order to solve this problem, for example, Patent Document 7 discloses a method of changing the program start voltage. The non-volatile memory device programming method disclosed in Patent Document 7 aims to provide a non-volatile memory device programming method in which the program start voltage is set differently according to the programming speed of each cell. Performing a program operation on a page, counting a program pulse application count until the program operation on the first page is completed, comparing the counted program pulse application count with a threshold value, and a program start voltage And a step of performing a program operation according to the reset program start voltage with respect to the second page.

  In the programming method of the above-mentioned patent document 7, the optimum program start voltage cannot be used on the first page, the writing variation between pages is not corrected, and the threshold voltage is determined only by counting the program pulses. There is a problem that it is difficult to optimize the program start voltage so as to eliminate the variation in distribution.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device and a writing method thereof that can solve the above-described problems, minimize variations in threshold voltage distribution after programming, and obtain high-speed and many-time rewriting characteristics. There is to do.

The nonvolatile semiconductor memory device according to the first invention is
In a nonvolatile semiconductor memory device comprising a nonvolatile memory cell array and a control circuit for controlling writing to the memory cell array,
The control circuit detects a program speed when writing to the memory cell array and applies a program start voltage corresponding to the program speed before applying an erase pulse for an erase process for erasing data of a memory cell to be written. Is determined for each block or each word line, the determined program start voltage is stored in the memory cell array, the program start voltage is read from the memory cell array, and predetermined data is written.

  In the nonvolatile semiconductor memory device, the control circuit is stored in a memory cell on a word line of the memory cell array before applying an erase pulse for erasing processing for erasing data of the memory cell to be written. The program speed is detected using data.

  Alternatively, the control circuit uses the predetermined memory cell on the dummy word line of the memory cell array to increase the program speed before applying an erase pulse for erasing processing for erasing data of the memory cell to be written. It is characterized by detecting.

  Alternatively, the control circuit detects the program speed using a predetermined memory cell on a word line of the memory cell array in a stage before applying an erase pulse for erasing processing for erasing data of the memory cell to be written. It is characterized by doing.

  In the nonvolatile semiconductor memory device, the control circuit detects a program speed using data on only one word line for each erasing process.

  Here, when the program speed is detected using the data on only one word line, the position in the memory cell string of the word line for detecting the program speed is shifted for each erasing process, and a predetermined erase is performed. The number of processes is one cycle.

  Further, in the nonvolatile semiconductor memory device, the program speed detection check is performed by counting the number of times of erasing for each erasing process and storing the information as a flag bit in the same manner as the program speed data. The program speed check is performed when the number of times is reached, and the data is updated.

  Still further, in the nonvolatile semiconductor memory device, the control circuit stores the determined program start voltage in a memory cell on a dummy word line of the memory cell array.

  Still further, in the nonvolatile semiconductor memory device, the control circuit stores the determined program start voltage in a memory cell on a dummy word line of the memory cell array.

  Still further, in the nonvolatile semiconductor memory device, the control circuit stores the determined program start voltage in an additional memory cell on a word line of the memory cell array, and reads the program start voltage from the memory cell. In order to store the determined program start voltage, an N-byte memory area corresponding to the number N of word lines whose program speed is detected is prepared for each word line, and a program corresponding to each erasing process is prepared. The determined program start voltage is stored in a memory cell on a word line used for speed detection.

  Here, in order to store the determined program start voltage, a memory area of at least N bytes corresponding to the number N of word lines whose program speed is detected is prepared for each word line, The determined program start voltage is stored in a memory cell on a word line used in detecting the corresponding program speed.

  Here, when the word line for detecting the program speed also serves as data for at least one word line on both sides of the string, it is not stored on the word line for which the speed has been detected. The memory area of (N + 1) bytes on the word line is used and shifted every erasing process.

  In the nonvolatile semiconductor memory device, the control circuit stores the determined program start voltage in a dummy word line of the memory cell array or a memory cell on the word line. Code) bits are added and writing is performed, and when ECC bits are added and written, writing is performed using three or more bit cells for one bit of data.

  In the nonvolatile semiconductor memory device, the control circuit reads the stored program start voltage in one read cycle, and writes predetermined data using the read program start voltage. To do.

  Further, in the nonvolatile semiconductor memory device, the control circuit reads the stored program start voltage in one read cycle, stores all the read program start voltages in a register, and stores predetermined data If the program processing for writing is within the corresponding block, the program start voltage of the corresponding word line is read from the register and predetermined data is written.

A nonvolatile semiconductor memory device writing method according to a second aspect of the present invention is a nonvolatile semiconductor memory device writing method comprising a nonvolatile memory cell array and a control circuit for controlling writing to the memory cell array.
The control circuit detects a program speed when writing to the memory cell array and applies a program start voltage corresponding to the program speed before applying an erase pulse for an erase process for erasing data of a memory cell to be written. Is determined for each block or each word line, the determined program start voltage is stored in the memory cell array, the program start voltage is read from the memory cell array, and predetermined data is written.

  Therefore, according to the nonvolatile semiconductor memory device and the writing method thereof according to the present invention, the program speed when writing to the memory cell array is detected before or after the erasing process for erasing the data of the memory cell to be written, and the program A program start voltage corresponding to the speed is determined for each block or word line, the determined program start voltage is stored in the memory cell array, the program start voltage is read from the memory cell array, and predetermined data is written. Therefore, variations in the threshold voltage distribution after programming can be minimized, and high-speed and many-time rewriting characteristics can be obtained.

1 is a block diagram showing an overall configuration of a NAND flash EEPROM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration of a memory cell array 10 of FIG. 1 and its peripheral circuits. FIG. 3 is a circuit diagram illustrating a detailed configuration of a page buffer (for two bit lines) in FIG. 2. It is a timing chart showing a writing method when programming a NAND type flash EEPROM using an ISPP (Increment Step Pulse Program) method according to the prior art. FIG. 5 is a diagram showing a threshold voltage Vth distribution when a program start voltage Vstart is changed when programming a NAND flash EEPROM using the ISPP (Increment Step Pulse Program) method of FIG. 4. FIG. 5 is a diagram illustrating a threshold voltage Vth distribution when programming a NAND flash EEPROM using the same program start voltage Vstart when the ISPP (Increment Step Pulse Program) method of FIG. 4 is programmed. It is a three-dimensional conceptual diagram showing the concept of pages and blocks in a general NAND flash EEPROM. FIG. 10 is a threshold voltage Vth distribution diagram showing an operation and effect when a write method for optimizing a program start voltage Vstart for each block or word line is used according to an embodiment of the present invention. FIG. 9 is a threshold voltage Vth distribution diagram showing the effect of the program speed check process used in the writing method of FIG. 8. It is a figure which shows the selection method of the word line for the program speed check process of FIG. It is a table | surface which shows the program start voltage Vstart used with a prior art. It is a table | surface which shows the program start voltage Vstart used in embodiment of this invention. It is a flowchart which shows the program processing which concerns on the 1st Embodiment of this invention. It is a flowchart which shows the program process (S4) which is a subroutine of FIG. 3 is a flowchart illustrating an erasing process that is executed prior to the program process of the first embodiment. It is a flowchart which shows the program speed check process (S21) which is a subroutine of FIG. 6 is a flowchart illustrating an erasing process (Example 2) executed prior to the program process of the first embodiment. It is a flowchart which shows the program speed check process (S42) which is a subroutine of FIG. It is a flowchart which shows the deletion process which concerns on the 2nd Embodiment of this invention. A process according to a modification of the present invention, wherein in the program process, a program start voltage and flag data storage process for storing a program start voltage and flag data using an additional memory cell on a normal word line ( It is a flowchart which shows S23, S43, S65). A process (S61) according to a modification of the present invention, in the program process, shows a program start voltage and flag data reading for reading a program start voltage and flag data from an additional memory cell on a normal word line. It is a flowchart.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component.

  FIG. 1 is a block diagram showing the overall configuration of a NAND flash EEPROM according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of the memory cell array 10 of FIG. 1 and its peripheral circuits. FIG. 3 is a circuit diagram showing the detailed configuration of the page buffer (for two bit lines) in FIG. First, the configuration of the NAND flash EEPROM according to this embodiment will be described below.

  In FIG. 1, a NAND flash EEPROM according to this embodiment includes a memory cell array 10, a control circuit 11 for controlling the operation thereof, a row decoder 12, a high voltage generation circuit 13, a data rewrite / read circuit 14, A column decoder 15, a command register 17, an address register 18, an operation logic controller 19, a data input / output buffer 50, and a data input / output terminal 51 are configured.

  As shown in FIG. 2, the memory cell array 10 includes, for example, 18 stacked gate structure electrically rewritable nonvolatile memory cells MC0 to MC15, MCD0, MCD1 connected in series to NAND cell units NU (NU0, NU1). ,…) Is constructed. Each NAND cell unit NU has a drain side connected to the bit line BL via the selection gate transistor SG1, and a source side connected to the common source line CELSRC via the selection gate transistor SG2. The control gates of the memory cells MC arranged in the row direction are commonly connected to the word line WL, and the gate electrodes of the selection gate transistors SG1 and SG2 are connected to selection gate lines SGD and SGS arranged in parallel with the word line WL. The Here, a dummy word line DWL0 is formed between the selection gate line SGS and the word line WL0 in parallel with each word line, and between the selection gate line SGD and the word line WL15, in parallel with each word line. Thus, the dummy word line DWL1 is formed. A range of memory cells selected by one word line WL is one page as a unit of writing and reading. A range of a plurality of NAND cell units NU in one page or an integral multiple of one page is one block as a data erasing unit. The rewrite / read circuit 14 includes a sense amplifier circuit (SA) and a latch circuit (DL) provided for each bit line in order to write and read data in page units, and is hereinafter referred to as a page buffer.

  The memory cell array 10 in FIG. 2 has a simplified configuration, and a page buffer may be shared by a plurality of bit lines. In this case, the number of bit lines selectively connected to the page buffer at the time of data write or read operation is a unit of one page. FIG. 2 shows a range of the cell array in which data is input / output to / from one input / output terminal 52. In order to select a word line WL and a bit line BL of the memory cell array 10, a row decoder 12 and a column decoder 15 are provided, respectively. The control circuit 11 performs sequence control of data writing, erasing and reading. The high voltage generation circuit 13 controlled by the control circuit 11 generates a boosted high voltage or intermediate voltage used for data rewriting, erasing, and reading.

  The input / output buffer 50 is used for data input / output and address signal input. That is, data is transferred between the input / output terminal 51 and the page buffer 14 via the input / output buffer 50 and the data line 52. An address signal input from the input / output terminal 52 is held in the address register 18 and sent to the row decoder 12 and the column decoder 15 to be decoded. An operation control command is also input from the input / output terminal 52. The input command is decoded and held in the command register 17, whereby the control circuit 11 is controlled. External control signals such as a chip enable signal CEB, a command latch enable CLE, an address latch enable signal ALE, a write enable signal WEB, and a read enable signal REB are taken into the operation logic control circuit 19, and an internal control signal is generated according to the operation mode. Is done. The internal control signal is used for control such as data latch and transfer in the input / output buffer 50, and is further sent to the control circuit 11 for operation control.

  The page buffer 14 includes two latch circuits 14a and 14b, and is configured to be able to switch between a multi-value operation function and a cache function. That is, a cache function is provided when 1-bit binary data is stored in one memory cell, and a cache function is provided when 2-bit quaternary data is stored in one memory cell. However, the cache function can be enabled. FIG. 3 shows a detailed configuration of a specific page buffer 14A (for two bit lines) for realizing such a function.

  In FIG. 3, the page buffer 14A includes a latch L1 composed of two inverters 61 and 62, a latch L2 composed of two inverters 63 and 64, a verifying capacitor 70, a precharging transistor 71, Verify transistors 72 to 75, verify pass / fail judgment transistors 76 and 77, column gate transistors 81 and 82, transfer switch transistors 83 to 85, 88 and 89, bit line select transistors 86 and 87, and latch equalization A transistor 90 and a reset transistor 91 are provided.

  In FIG. 3, two bit lines BLe and BLo are selectively connected to the page buffer 14A. In this case, the bit line select signal 86 or 87 is turned on by the bit line select signal BLSE or BLSO, and either the bit line BLe or the bit line BLo is selectively connected to the page buffer 14A. Note that it is preferable to reduce noise between adjacent bit lines by setting the other bit line in the non-selected state to a fixed ground potential or power supply voltage potential while one bit line is selected.

  The page buffer 14A shown in FIG. 3 includes a first latch L1 and a second latch L2. The page buffer 14A mainly contributes to read, write, and erase operations by predetermined operation control. The second latch L2 is a secondary latch circuit that realizes a cache function in a binary operation, and supplementarily contributes to the operation of the page buffer 14A when the cache function is not used. Realize multi-valued operation.

  The latch L1 is configured by connecting clocked inverters 61 and 62 in antiparallel. The bit line BL of the memory cell array 10 is connected to the sense node N4 via the transfer switch transistor 85, and the sense node N4 is further connected to the data holding node N1 of the latch L1 via the transfer switch transistor 83. A precharge transistor 71 is provided at the sense node N4. Node N1 is connected to temporary storage node N3 for temporarily storing data of node N1 via transfer switch transistors 74 and 75. Further, a precharging transistor 71 for precharging the voltage V1 with respect to the bit line is also connected to the node N4. A capacitor 70 for maintaining the level is connected to the node N4. The other end of the capacitor 70 is grounded.

  Similarly to the first latch L1, the second latch L2 is configured by connecting clocked inverters 63 and 64 in antiparallel. The two data nodes N5 and N6 of the latch L2 are connected to a data line 52 connected to the data input / output buffer 50 via column gate transistors 81 and 82 controlled by a column selection signal CSL. The node N5 is connected to the node N4 via the transfer switch transistor 84.

  FIG. 2 shows a connection relationship between the memory cell array 10, the page buffer 14, and the data input / output buffer 50. The processing unit for reading and writing of the NAND flash EEPROM is a capacity for one page (for example, 512 bytes) selected simultaneously at a certain row address. Since there are eight data input / output terminals 52, there are 512 bits for one data input / output terminal 52, and FIG. 2 shows the configuration for 512 bits.

  When data is written to the memory cell, the write data is fetched from the data signal line 52 into the second latch L2. In order to start the write operation, the write data must be in the first latch L1, and then the data held in the latch L2 is transferred to the latch circuit L1. In the read operation, in order to output data to the data input / output terminal 51, since the read data must be in the latch L2, the data read by the latch L1 needs to be transferred to the latch L2. Accordingly, the transfer switch transistors 83 and 84 are turned on so that data can be transferred between the latch L1 and the latch L2. At this time, the data is transferred after the transfer destination latch circuit is deactivated, and then the transfer destination latch circuit is returned to the active state to hold the data.

  1 to 3, the basic operations for writing and erasing data in the memory cell array 10 are disclosed in, for example, Patent Documents 4 to 5, which are well-known techniques and will not be described in detail.

  The present embodiment proposes a writing method using an improved ISPP method that can obtain a large number of rewrite characteristics at high speed while minimizing variations in the threshold voltage distribution after programming in a NAND flash EEPROM. . Here, the write method according to the present embodiment has a function of changing the program start voltage Vstart for each block or each word line, and after checking the program speed, based on the detection result of the program speed. The program start voltage is determined and stored, and the information is read and predetermined data is written.

  FIG. 7 is a three-dimensional conceptual diagram showing the concept of pages and blocks in a general NAND flash EEPROM (SLC 2G bit). As is apparent from FIG. 7, one page is composed of 2064 bytes × 8 bits, 64 pages constitute one block, and a total of 128K pages. Writing and reading are performed for each page using the page buffer 14, and erasure is performed for each block.

  FIG. 11 is a table showing the program start voltage Vstart used in the prior art, and FIG. 12 is a table showing the program start voltage Vstart used in the embodiment of the present invention. In the prior art, the program start voltage Vstart is the same in each block, but in the present embodiment, as shown in FIG. 12, the optimum program start voltage Vstart is determined and used for each block. In FIG. 12, data in parentheses of the program start voltage Vstart (•) is offset data from a predetermined reference program start voltage Vstart (0). For example, assuming that one unit of offset voltage is 0.3V, Vstart (+2) = Vstart (0) + 2 × 0.3V.

  FIG. 8 is a threshold voltage Vth distribution diagram showing the operation and effect when using the write method for optimizing the program start voltage Vstart for each block or each word line according to the embodiment of the present invention. According to the present embodiment, the program start voltage Vstart is optimized for each block or each word line, and the fluctuation of the threshold voltage distribution is minimized for each block or each word line as shown in FIG. Compared to the conventional example, the durability of the deterioration of the oxide film itself accompanying data rewriting is improved, and the rewriting characteristics can be obtained at high speed and many times.

  FIG. 9 is a threshold voltage Vth distribution diagram showing the effect of the program speed check process used in the writing method of FIG. The program speed check is performed as follows. As shown in FIG. 9, for the test, a program stress is applied to a memory cell of a specific bit (test bit) for each block or each word line, and several voltage levels (4 in FIG. 9) are applied. Is read out by detecting the threshold voltage distribution of the specific bit, and the maximum threshold of the fastest bit among the specific bits for the test is detected. Based on the value voltage, a program start voltage Vstart for the block or the word line is determined. For example, the program start voltage Vstart (0) = 15 to 16V, Vstep = 0.3V and ΔVstep = 0.1V in MLC (Multi Level Cell), and Vstep = 1.1V in SLC (Single Level Cell). ΔVstep = 0.2 to 0.5V.

  For the data of the determined program start voltage Vstart (•), it is preferable to store a corresponding offset value in a memory cell of a specific bit on a dummy word line of each block. For example, bit (110) is associated with program start voltage Vstart (−2), bit (101) is associated with program start voltage Vstart (−1), and bit (100) is associated with program start voltage Vstart (0). ), The bit (011) is associated with the program start voltage Vstart (+1), the bit (010) is associated with the program start voltage Vstart (+2), and stored in the specific bit. Here, since the program start voltage is an important value, no error is allowed. For example, each of the 3 bits may be written using a bit cell of 3 bits or more and read using a majority rule. In addition, for example, a method for determining a majority rule for data of a program start voltage Vstart (•) on a dummy word line is programmed by programming data by a program process with one write pulse using a voltage (Vstart + n × Vstep). It may be configured to use and read and program. In this case, the data of the program start voltage Vstart (•) set for each word line is stored together in the memory cells on the dummy word line of the block. If the data of the determined program start voltage Vstart (•) may be stored in a memory cell of a specific bit on a normal write word line, an additional memory cell for this purpose is required. .

  FIG. 13 is a flowchart showing the program processing according to the first embodiment of the present invention. In FIG. 13, first, in step S1, program data is loaded, and in step S2, data of a specific bit of a block selected for writing is read before applying a program pulse. In this data, Vstart for each block or each word line of the block is stored. Specifically, first, as described above, when the data is stored in the dummy word line, the dummy word line is selected and read, or when the additional word is stored in the normal word line, the predetermined read is performed. After the application word line voltage Vsp is applied to all the word lines, a read process is performed once. Next, a program start voltage and flag data are set in a temporary register (buffer memory) based on the data of a specific bit corresponding to the selected word line. In step S3, program data is set in the buffer memory 14a. Further, in step S4, the program process is executed using the ISPP method using the program start voltage set based on the specific bit. One major requirement for the write method according to this embodiment is not to increase the program time to maintain program throughput, and for this reason, the program speed check process is performed in an erase operation.

  In step S2 of FIG. 13, the program start voltage Vstart (·) is basically determined by reading data from a specific bit of the memory cell. In the case of continuous programming of the word lines WL3 to WL28, Only when the word line WL3 is programmed, data is read from a specific bit of the memory cell, and when the remaining word lines WL4 to WL28 are read, the program start voltage Vstart (·) is read from the temporary register to reduce the extra program time. May be.

  FIG. 14 is a flowchart showing the program processing (S4) which is a subroutine of FIG. In FIG. 14, the program start voltage Vstart (•) set in step S11 is set to the program voltage Vpgm (n), a program pulse having the program voltage Vpgm (n) is applied in step S12, and the program is programmed in step S13. In step S14, it is determined whether or not all memory cells have been passed. If YES, the process returns to the original main routine. If NO, the process proceeds to step S15. In step S15, the program voltage Vpgm (n) is incremented by the increment Vstep to set the program voltage Vpgm (n), and the process returns to step S12.

  FIG. 15 is a flowchart showing the erase process executed prior to the program process of the first embodiment. During this erase process, the program start voltage setting process (Example 1) is executed. In FIG. 15, a program speed check process (FIG. 16) is executed in step S21, and data is erased using an erase pulse in step S22. In step S23, the program start voltage and flag data obtained by the program speed check and set in the temporary register are stored in predetermined specific bits of the memory cell. Specifically, after the program start voltage and flag data stored in the temporary register are set in the page buffer 14, the corresponding word line (or dummy word line) is selected and, for example, normal SLC program processing is executed. Program.

  FIG. 16 is a flowchart showing a program speed check process (S21) which is a subroutine of FIG. In FIG. 16, first, in step S31, data is set in the buffer memory 14 for a specific bit of the memory cell. Specifically, data is read from a specific word line. If it is 1 data, it is a check bit, and if it is 0 data, it is a mask bit. Next, in step S32, program processing is performed using a program pulse. Further, in step S33, the maximum threshold voltage Vth is acquired in the specific bit, the offset data of the program start voltage at that time is stored in the temporary register, and the process returns to the original main routine. Here, in order to obtain the maximum threshold voltage Vth in the specific bit, verify reading is performed while increasing the verify voltage at a predetermined step voltage until all the data bits become 1 data, for example.

  In step S31 of FIG. 16, 1 of the user data is used to obtain the check bit, but the user data does not always include a sufficient number of 1 bits for checking. Therefore, when user data is used in this way, the number of 0 data is counted in step S1 of the program processing shown in FIG. 13, and if the number of 0 data is larger than half the page size, the inversion flag bit Is set and the data is inverted in S3. By this processing, the number of data of 1 can always be more than half of the page size. At the time of reading, of course, if an inversion flag is set in the data, it is inverted and output.

  FIG. 17 is a flowchart showing another form of erasing processing executed prior to the program processing of the first embodiment. In this, the program start voltage setting process (Example 2) is executed. In FIG. 17, first, in step S41, data is erased using an erase pulse, and in step S42, a program speed check process is executed using a soft program process. In step S43, the program start voltage and flag data obtained in the program speed check and set in the temporary register are stored in predetermined specific bits of the memory cell.

  FIG. 18 is a flowchart showing a program speed check process (S42) which is a subroutine of FIG. In FIG. 18, first, in step S51, data is set in the buffer memory 14 for a specific bit on the dummy word line. Next, in step S52, a program process is performed on the specific bit on the dummy word line using a program pulse. Then, in step S53, the verify voltage is changed to verify whether all the data in the specific bit is 1 data, and the maximum threshold voltage Vth is obtained to obtain the program start voltage at that time. Store the offset data in the temporary register and return to the original main routine.

  FIG. 19 is a flowchart showing an erasing process according to the second embodiment of the present invention. In FIG. 19, first, in step S61, old program start voltage and flag data are read from a specific bit of a memory cell. Here, the flag represents a word line for program speed check. Next, a program speed check process is executed in step S62, and data is erased using an erase pulse in step S63. In step S64, the soft program process is executed using the soft program start voltage based on the program start voltage set in the program speed check or a soft program start voltage determined by another predetermined method. Further, in step S65, the set program start voltage and flag data are stored in specific bits, where the modified flag represents the next check word line for program speed check.

  In the program speed check process of FIG. 19, in order to reduce the extra time for the program speed check process, the program speed check process is performed for one specific word line for each erase process. Thus, one cycle of program speed check for a word line is equal to the number of cells in one string. Specifically, user data on the word line is read, 1 bit (or 11 bits) is obtained, and the data is set as a program bit. Then, the program pulse is applied, the verify read is performed while the verify voltage is changed, the maximum threshold voltage Vth is detected, and it is compared with the predicted value, thereby corresponding to the program start voltage Vstart (·). Can be determined.

  FIG. 10 is a diagram showing a word line selection method according to a modification for the program speed check process described above. The program speed check process is executed while shifting every erasure in order for all or some specific word lines. Here, first, (N + 1) bytes are prepared for each word line in order to secure and prepare a data storage location for the program start voltage Vstart. Here, N is the number of word lines for program speed check. The offset value of Vstart (•) is stored in 1 byte. In step S65 of the erase process in FIG. 19, the program start voltage data and the (N + 1) bytes of the word line on which the program speed check has been performed are performed using a normal SLC program using the verify voltage Vread = PV. Flag data is stored. This storage processing flow will be described with reference to FIG. In step S61 for reading the program start voltage data and flag data written in this way, the read word line voltage Vsp (1 V in FIG. 10) is applied to all the word lines, and the previously stored word line is stored. To read the data of the program start voltage Vstart and the flag data storing the number of the word line to be measured this time. Since data is written only in the (N + 1) bytes on one word line, the data can be read out by one read operation.

  Next, the data is decoded using, for example, ECC (Error Correcting Code), and the decoded data is stored in a temporary register. The flow of this reading process will be described with reference to FIG. Further, it is set to the word line of the flag data as a word line for the program speed check process. As an example of the method of selecting the word lines, there is a method of checking the speed of all the word lines. However, since word lines except for the end portions are usually well aligned, for example, WL0, 1, 2, 16, 29 , 30, 31 (both edges and central part of the string) may be selected. WL16 may cover WL3 to 28. This is because the selection of these word lines is determined by program characteristics depending on the word lines. Here, regarding the number of word lines, for example, when storing the program start voltage data in an additional memory cell on a normal word, the number of extra bits is increased, thereby relatively increasing the chip size. Let In reading the program start voltage data, reading and verifying are performed using the verify voltage VpassR = Vread = Vsp in one read cycle, and the flag represents the next check word line for program speed check.

  FIG. 20 shows a process (S65) according to a modification of the present invention. In the erase process, a program start voltage for storing a program start voltage and flag data using an additional memory cell on a normal word line. And it is a flowchart which shows flag data storage processing (S23, S43, S65). In FIG. 20, first, in step S71, the program start voltage and flag data are set from the temporary register to the page buffer 14 for the specific bit of the memory cell. In step S72, the set data is selected as the selected word. By programming the line, the program start voltage and flag data are stored in specific bits of the memory cell. As shown in FIG. 10, since all the cells of the word lines other than the selected word line are in the erased state, there is no problem even if the threshold voltage Vth after writing becomes higher than the read pass voltage (VpassR). It is possible to shorten the program time by reducing the number of write pulses than the program. Specifically, normal SLC writing uses 3 to 4 pulses and takes about 200 [mu] s as a writing time, but this can be halved to about 100 [mu] s by using 1 to 2 pulses.

  FIG. 21 shows a process (S61) according to a modification of the present invention. In the program process, the program start voltage and the flag data for reading the program start voltage and the flag data from the additional memory cells on the normal word line are shown. It is a flowchart which shows reading. In FIG. 21, in step S81, read word line voltage Vsp is set for all word lines. Next, in step S82, data of a specific bit of the memory cell is read, and in step S83, the program start voltage and flag data from the data of the specific bit are set in the temporary register. Before reading the flag data, it is not known which word line contains the program start voltage data and the flag data. Therefore, it is usually necessary to read one word line at a time, but as shown in FIG. Since the memory cells other than the specific bit of the word line are in the erased state, the read voltage Vsp (1 V in FIG. 10) is applied to all the word lines as in S81, and can be read once (about 20 μs). The word line for storing these data may be fixed to, for example, WL16. However, the number of rewrites for each word line can be reduced by shifting each time, so that the reliability can be further improved.

  As described above, according to the present embodiment, a program speed check is performed for each block or each word line to determine an optimum program start voltage, and data is written by changing the program start voltage. Therefore, variation in the threshold voltage distribution after programming can be minimized, and high-speed rewriting characteristics can be obtained.

  In the above description, the program start voltage is set for each block or each word line. Ideally, it is desirable to set the speed check & start voltage for all word lines in all blocks. However, as described above, the write speed of the word line in the middle of the memory cell string is almost the same, and it can be said for the block. Therefore, the program speed check is performed for the block and the word line of the necessary part, respectively. For blocks and word lines that are not performed, the corresponding values may be used. As a result, an increase in the erasure processing time accompanying the program speed check is reduced.

  Further, in FIG. 18, dummy word lines are used as the word lines for checking the program speed. In this case, the program start voltage of each word line is a value calculated based on the initial characteristics or standard characteristics. As a result, the variation is not completely corrected, but the variation between blocks is corrected. In addition, there are mainly a method of using the user data area of the word line and a method of adding an additional bit for checking to the memory cell array.

  Furthermore, in addition to a method in which the program speed check is determined by the maximum threshold voltage Vth after writing, the second highest threshold voltage Vth is set to avoid picking up abnormally fast bit data. The method of adopting is also good. In terms of circuit, 2 to 3 bits are not particularly problematic.

  In addition, as for the bits used for the program speed check, a method of using user data when using a normal word line has been presented. However, the present invention is not limited to this, and all cases where a specific bit of a dummy word line is used. Since it is not written, all can be used. With the configuration of (N + 1) bytes × majority bits described above, all the bits of the word line for which the program speed is to be checked are in the erased state, and can be used as they are. Thus, it is not always necessary to use user data.

  Further, the memory cell for storing the program start voltage data has the dummy bit line or the additional bit of the normal word line as in the embodiment, but the dummy word line has the additional bit region without the additional bit. In addition, it is possible to select whether to use a dummy word line on the selection gate line SGD side or a dummy word line on the selection gate line SGS side. Therefore, the selection gate line SGS side may be divided for storage, and the selection gate line SGD side may be divided for program speed check.

  Further, in the above description, the method for shifting the program speed check one by one at the time of each erasing process is described assuming that the program speed check is one, and the program speed check is performed for the word lines 0, 1, 2, 16, 29, 30, 31. Although the embodiment has been described, the present invention is not limited to this, and if the speed check is performed for all word lines, one cycle of the speed check period is 32 times, but only seven word lines are used as described above. When the speed check is performed, in addition to setting one cycle to seven times as it is, there is a method in which the word lines 3 to 15 and 17 to 28 are only counted (only flag bits are updated) and one cycle is set to 32 times. It can be said that this is a preferable method for suppressing the deterioration of reliability due to the number of rewrites of the memory cell, together with the method of performing the storage while shifting the word line to 3 to 28. Similarly, when the program speed check is performed with a dummy word line as shown in FIG. 18, the number of erase processes is similarly counted and stored as a flag bit, so that one cycle of the speed check is set to a predetermined suitable number of 32 times. can do.

  Although the NAND flash EEPROM has been described in the above embodiments, the present invention is not limited to this, and is widely applied to nonvolatile semiconductor memory devices capable of writing data to a floating gate such as a NOR flash EEPROM. it can.

  As described above in detail, according to the nonvolatile semiconductor memory device and the writing method thereof according to the present invention, the program speed check is performed for each block or each word line to determine the optimum program start voltage, and the program Since data is written by changing the start voltage, variation in the threshold voltage distribution after programming can be minimized and high-speed rewrite characteristics can be obtained.

10: Memory cell array,
11 ... control circuit,
12 ... row decoder,
13. High voltage generation circuit,
14, 14A ... Data rewriting and reading circuit (page buffer),
14a, 14b ... latch circuit,
15 ... column decoder,
17 ... Command register,
18 ... Address register,
19 ... Operation logic controller,
50: Data input / output buffer,
51: Data input / output terminal,
52 ... Data line,
L1, L2 ... Latch.

Claims (13)

In a nonvolatile semiconductor memory device comprising a nonvolatile memory cell array and a control circuit for controlling writing to the memory cell array,
The control circuit detects a program speed when writing to the memory cell array and applies a program start voltage corresponding to the program speed before applying an erase pulse for an erase process for erasing data of a memory cell to be written. Is determined for each block or word line, the determined program start voltage is stored in the memory cell array, the program start voltage is read from the memory cell array, and predetermined data is written.
The control circuit uses the data stored in the memory cells on the word lines of the memory cell array to increase the program speed before applying an erase pulse for erasing processing for erasing data in the memory cell to be written. A non-volatile semiconductor memory device, characterized by detecting.   2. The non-volatile semiconductor memory device according to claim 1, wherein the control circuit detects a program speed by using data on only one word line for each erasing process.   When the program speed is detected using the data on only one word line, the position of the word line for detecting the program speed in the memory cell string is shifted for each erase process, and the predetermined number of erase processes is performed. 3. The nonvolatile semiconductor memory device according to claim 2, wherein one cycle is used.   The program speed detection check counts the number of erases for each erase process and stores the information as flag bits in the same manner as the program speed data. When the erase count reaches a predetermined number, the program speed check is performed. 4. The nonvolatile semiconductor memory device according to claim 2, wherein the data is updated.   The nonvolatile semiconductor memory according to claim 1, wherein the control circuit stores the determined program start voltage in a memory cell on a dummy word line of the memory cell array. apparatus.   The non-volatile semiconductor according to claim 1, wherein the control circuit stores the determined program start voltage in an additional memory cell on a word line of the memory cell array. Storage device.   In order to store the determined program start voltage, a memory area of at least N bytes corresponding to the number N of word lines for which the program speed is detected is prepared for each word line, and a program corresponding to each erasing process is prepared. 7. The nonvolatile semiconductor memory device according to claim 6, wherein said determined program start voltage is stored in a memory cell on a word line used for speed detection.   The control circuit detects the program speed by selecting a word line at the center in the arrangement direction of a plurality of word lines as a word line for detecting the program speed, and is positioned respectively on both sides of the word line at the center. 8. The nonvolatile semiconductor memory device according to claim 7, wherein the nonvolatile semiconductor memory device is used as a program speed of a plurality of word lines.   The control circuit detects the program speed by using the word line for detecting the program speed as the word line in the central portion, and positions the program start voltage data corresponding to the detected data on both sides of the word line. 9. The nonvolatile memory according to claim 8, wherein when writing to one of a plurality of word lines, each word line is selected while being shifted one by one for each erasing process for erasing data in a memory cell. Semiconductor memory device.   The control circuit uses a 3-bit bit cell for 1 bit of data of the program start voltage when storing the determined program start voltage in a dummy word line of the memory cell array or a memory cell on the word line. The nonvolatile semiconductor memory device according to claim 1, wherein writing is performed by majority logic.   11. The control circuit according to claim 1, wherein the control circuit reads the stored program start voltage in one read cycle, and writes predetermined data using the read program start voltage. The nonvolatile semiconductor memory device according to claim 1.   The control circuit reads the stored program start voltage in one read cycle, stores all the read program start voltages in a register, and writes a predetermined data in the corresponding block. 12. The nonvolatile semiconductor memory device according to claim 1, wherein the program start voltage of the corresponding word line is read from the register and predetermined data is written. In a writing method of a nonvolatile semiconductor memory device comprising a nonvolatile memory cell array and a control circuit for controlling writing to the memory cell array,
The control circuit detects a program speed when writing to the memory cell array and applies a program start voltage corresponding to the program speed before applying an erase pulse for an erase process for erasing data of a memory cell to be written. Is determined for each block or word line, the determined program start voltage is stored in the memory cell array, the program start voltage is read from the memory cell array, and predetermined data is written.
The control circuit uses the data stored in the memory cells on the word lines of the memory cell array to increase the program speed before applying an erase pulse for erasing processing for erasing data in the memory cell to be written. A non-volatile semiconductor memory device writing method, comprising: detecting a non-volatile semiconductor memory device;

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