JP2014117063A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output circuit capable of preventing the occurrence of a through-current.SOLUTION: The output circuit in an embodiment comprises: a diode D1 in which an input voltage VDIN is applied to the drain terminal of an output-use NMOS transistor N100, an LC circuit and a regenerative diode D are connected to a source terminal OUT, and an anode terminal is connected to the gate terminal of the output-use NMOS transistor N100; an NMOS transistor N1 having its drain terminal connected to the cathode terminal of the diode D1 and its source terminal connected to a ground potential terminal GND; and an NMOS transistor N2 and an NMOS transistor N3 connected in series between the gate terminal and the source terminal of the output-use NMOS transistor N100. When the output-use NMOS transistor N100 is non-conductive, a control circuit 1 establishes electrical continuity between the NMOS transistor N2 and the NMOS transistor N3, and establishes electrical continuity to the NMOS transistor N1 for a period shorter than this conduction period.

Description

  Embodiments described herein relate generally to an output circuit.

  In a diode rectification step-down switching regulator, a MOS transistor whose conduction is controlled by a switching control signal input to a gate terminal is used for an output circuit that applies a charging current to an LC circuit composed of an inductor and a capacitor. At this time, the input voltage is applied to the drain terminal of the MOS transistor, and the LC circuit and the diode are connected to the source terminal.

  Conventionally, a PMOS transistor is often used as the MOS transistor, but in recent years, an NMOS transistor excellent in switching characteristics has been used. However, when an NMOS transistor is used, a voltage higher than the input voltage needs to be applied to the gate terminal, so that a booster circuit that boosts the switching control signal is required.

  When an NMOS transistor is used in the output circuit, when the input voltage to the gate terminal becomes 0V and the NMOS transistor is turned off, the energy accumulated in the inductor of the LC circuit flows to the diode as a regenerative current, and the source of the NMOS transistor The terminal may be negative. As a result, a voltage difference is generated between the gate and the source of the NMOS transistor, a through current from the input power source flows through the NMOS transistor, and the conversion efficiency of the step-down switching regulator is deteriorated.

JP 10-336006 A

  The problem to be solved by the present invention is to provide an output circuit capable of preventing the occurrence of a through current.

  In the output circuit of the embodiment, the input voltage is applied to the drain terminal, the output NMOS transistor in which the LC circuit and the regenerative diode are connected to the source terminal, and the switching control signal is boosted to a voltage higher than the input voltage. A PMOS transistor applied to the gate terminal of the output NMOS transistor. The output circuit includes a diode having an anode terminal connected to the gate terminal of the output NMOS transistor, a first NMOS having a drain terminal connected to the cathode terminal of the diode, and a source terminal connected to a ground potential terminal. A transistor, and a second NMOS transistor and a third NMOS transistor connected in series between the gate terminal and the source terminal of the output NMOS transistor, and a control circuit includes the output NMOS transistor Is turned off, the second NMOS transistor and the third NMOS transistor are turned on, and the first NMOS transistor is turned on for a period shorter than the conduction period.

FIG. 3 is a circuit diagram showing an example of the configuration of the output circuit of the embodiment. The figure which shows the phase relationship of the control signal of the output circuit of embodiment. The wave form diagram which shows the example of operation | movement of the output circuit of embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment)
FIG. 1 is a circuit diagram illustrating an example of a configuration of an output circuit according to the embodiment.

  The output circuit of this embodiment is a circuit that constitutes the output stage of a diode rectification step-down switching regulator, in which an input voltage VDIN is applied to the drain terminal, and an inductance L and a capacitor C are provided to the source terminal OUT. An output NMOS transistor N100 to which the LC circuit and the regenerative diode D are connected, a control signal generator 100 that adjusts the phase of the switching control signal SWC and outputs the switching control signal SWP and the switching control signal SWN, and a switching control signal A level shifter 200 that outputs a switching control signal SWPH obtained by boosting and inverting SWP to a voltage VDH higher than the input voltage VDIN, and switching control in which conduction is controlled by the switching control signal SWPH and boosted to the high voltage VDH. Has a PMOS transistor P100, the applying a No. SG to the gate terminal of the output NMOS transistor N100.

  Here, when the switching control signal SWP becomes “1”, the switching control signal SWPH becomes “0”, the PMOS transistor P100 becomes conductive, and the level of the switching control signal SG becomes the high voltage VDH. As a result, the output NMOS transistor N100 becomes conductive and outputs a charging current to the LC circuit.

  The output circuit of the present embodiment has a diode D1 whose anode terminal is connected to the gate terminal of the output NMOS transistor N100, a drain terminal connected to the cathode terminal of the diode D1, and a source terminal connected to the ground potential terminal GND. NMOS transistor N1, NMOS transistor N2 and NMOS transistor N3 connected in series between the gate terminal and source terminal of output NMOS transistor N100, and NMOS transistor N2 when output NMOS transistor N100 is non-conductive And a control circuit 1 for conducting the NMOS transistor N3 and conducting the NMOS transistor N1 for a period shorter than the conduction period.

  A protective diode DP for clamping the gate voltage is inserted between the source terminal and the gate terminal of the NMOS transistor N2 and the NMOS transistor N3.

  As an example of the configuration of the control circuit 1, in FIG. 1, the switching control signal SWN output from the control signal generation unit 100 is inverted to generate the control signal SW1 to be applied to the gate terminals of the NMOS transistor N2 and the NMOS transistor N3. An inverter IV1, a delay circuit 11 that delays the control signal SW1, an inverter IV2 that inverts the output of the delay circuit 11, an AND operation of the control signal SW1 and the output signal DLY of the inverter IV2, and a gate terminal of the NMOS transistor N1 And an AND gate AND that generates a control signal SW2 to be applied to.

  FIG. 2 shows the phase relationship between the switching control signal SWC and each signal generated by the control signal generator 100 and the control circuit 1.

  The control signal generator 100 adjusts the phase of the switching control signal SWC so that no through current flows during switching in the PMOS transistor P100 and the NMOS transistor N1, and outputs the switching control signal SWP and the switching control signal SWN.

  Here, when the power supply voltage of the logic circuit is VDD, the switching control signal SWPH is a signal obtained by level-shifting the VDD level switching control signal SWP to the high voltage VDH and inverting it.

  The control signal SW1 output from the control circuit 1 is an inverted signal of the switching control signal SWN.

  The control signal SW2 is an AND gate output of the control signal SW1 and the signal DLY. That is, the control signal SW2 is a signal that rises simultaneously with the control signal SW1 and falls earlier than the control signal SW1.

  In the present embodiment, when the switching control signal SWPH is “1” and the output NMOS transistor N100 is turned off by the control of the control circuit 1, the control signal SW1 becomes “1”. At this time, when the voltage of the source terminal OUT of the output NMOS transistor N100 is lowered to the power supply voltage VDD, the NMOS transistor N2 and the NMOS transistor N3 are turned on, and between the gate terminal and the source terminal OUT of the output NMOS transistor N100. A short-circuit path is formed by the NMOS transistor N2 and the NMOS transistor N3.

  Therefore, even if the output NMOS transistor N100 becomes non-conductive, the energy accumulated in the inductor L of the LC circuit flows to the diode D as a regenerative current, and even if the source terminal OUT of the output NMOS transistor N100 becomes a negative potential, The gate terminal of the output NMOS transistor N100 also has the same negative potential.

  On the other hand, the control signal SW2 is “1” simultaneously with the control signal SW1, and the NMOS transistor N1 is conductive. As a result, the NMOS transistor N1 performs an operation of extracting charges from the gate terminal of the output NMOS transistor N100.

  However, when a short circuit path is formed by the NMOS transistor N2 and the NMOS transistor N3 and the gate terminal of the output NMOS transistor N100 becomes a negative potential, the diode D1 is reverse-biased. Therefore, no current flows through the diode D1, and the operation of extracting the charge from the gate terminal of the output NMOS transistor N100 by the NMOS transistor N1 is not performed.

  Therefore, the gate terminal of the output NMOS transistor N100 remains at a negative potential, no potential difference is generated between the output NMOS transistor N100 and the source terminal OUT, and no through current from the input voltage VDIN power supply flows through the output NMOS transistor N100.

  FIG. 3 is a waveform diagram showing an example of the operation of the output circuit of this embodiment.

  When the switching control signal SWPH changes from “0” to “1”, the PMOS transistor P100 becomes non-conductive. As a result, the output NMOS transistor N100 changes from the “conductive state” to the “nonconductive state”.

  At this time, when the energy accumulated in the inductor L of the LC circuit flows through the diode D as a regenerative current, the potential of the source terminal OUT of the output NMOS transistor N100 changes from the input voltage VDIN to the negative potential Vm.

  Here, when the control signal SW1 output from the control circuit 1 changes from “0” to “1”, the NMOS transistor N2 and the NMOS transistor N3 are turned on, and the gate terminal and the source terminal OUT of the output NMOS transistor N100 are connected. A short circuit path is formed between them.

  As a result, the potential SG of the gate terminal of the output NMOS transistor N100 becomes the same negative potential Vm as that of the source terminal OUT.

  On the other hand, the NMOS transistor N1 to which the control signal SW2 is input performs an operation of extracting charges from the gate terminal of the output NMOS transistor N100.

  However, when the NMOS transistor N2 and the NMOS transistor N3 become conductive and a short-circuit path is formed between the gate terminal of the output NMOS transistor N100 and the source terminal OUT, the potential SG of the gate terminal of the output NMOS transistor N100 is The negative potential Vm is the same as that of the source terminal OUT.

  As a result, the diode D1 connected to the NMOS transistor N1 is reverse-biased, and the operation of extracting the charge from the gate terminal of the output NMOS transistor N100 by the NMOS transistor N1 is blocked.

  Therefore, the gate voltage SG of the output NMOS transistor N100 remains at the negative potential Vm, and no potential difference occurs between the source terminal OUT and the source terminal OUT. Therefore, no current flows through the drain current In of the output NMOS transistor N100.

  The gate voltage SG of the output NMOS transistor N100 is kept at the negative potential Vm until the switching control signal SWPH changes to “0” next time.

  On the other hand, as reference waveforms in FIG. 3, the waveforms of the potential SG ′ of the gate terminal of the output NMOS transistor N100 and the drain current In ′ flowing through the output NMOS transistor N100 when the diode D1 is not connected are shown. Show.

  When the diode D1 is not connected, the potential SG ′ of the gate terminal of the output NMOS transistor N100 becomes the ground potential GND during the period when the control signal SW2 is “1”, and passes through the drain current In ′ of the output NMOS transistor N100. Current flows.

  According to the present embodiment as described above, it is possible to prevent a through current from flowing through the output NMOS transistor N100 while the output of the output NMOS transistor N100 is at a negative potential. Thereby, the switching power loss can be greatly improved as an output stage of the switching regulator.

  According to the output circuit of the embodiment described above, generation of a through current can be prevented.

  Moreover, the described embodiment is presented as an example, and is not intended to limit the scope of the invention. The novel embodiment can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

DESCRIPTION OF SYMBOLS 1 Control circuit 11 Delay circuit N1-N3 NMOS transistor D1 Diode IV1, IV2 Inverter AND AND gate N100 Output NMOS transistor P100 PMOS transistor 100 Control signal generation part 200 Level shifter

Claims (2)

An output NMOS transistor in which an input voltage is applied to the drain terminal and an LC circuit and a regenerative diode are connected to the source terminal;
An output circuit having a PMOS transistor that boosts a switching control signal to a voltage higher than the input voltage and applies the switching control signal to a gate terminal of the output NMOS transistor;
A diode having an anode terminal connected to the gate terminal of the output NMOS transistor;
A first NMOS transistor having a drain terminal connected to the cathode terminal of the diode and a source terminal connected to a ground potential terminal;
A second NMOS transistor and a third NMOS transistor connected in series between the gate terminal and the source terminal of the output NMOS transistor;
A control circuit for conducting the second NMOS transistor and the third NMOS transistor when the output NMOS transistor is non-conducting and conducting the first NMOS transistor for a period shorter than the conducting period. An output circuit characterized by. The control circuit comprises:
A first inverter that inverts the switching control signal to generate a first control signal to be applied to gate terminals of the second NMOS transistor and the third NMOS transistor;
A delay circuit for delaying the first control signal;
A second inverter for inverting the output of the delay circuit;
An AND gate that performs a logical product operation of the first control signal and the output signal of the second inverter, and generates a second control signal to be applied to the gate terminal of the first NMOS transistor. The output circuit according to claim 1.

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