JP2014103282A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that allows high-speed operation.SOLUTION: A semiconductor device includes: a pad connected to a first node; a first output buffer circuit including a first transistor having one end connected to the first node; a second node electrically connected to the first node; and a second output buffer circuit including a second transistor having one end electrically connected to the second node. The distance from a contact to a gate of the second transistor is shorter than the distance from a contact to a gate of the first transistor.

Description

Embodiments described herein relate generally to a semiconductor device and, for example, to a protection circuit from electrostatic discharge (ESD) of a semiconductor chip or a package containing a semiconductor chip.

In order to protect the internal circuit from ESD, the semiconductor device has an ESD protection pad on the semiconductor chip.
A protection circuit for protection is connected. By connecting this protection element to the pad, the pin capacitance is increased. When the pin capacitance increases, the signal propagation speed decreases, and it becomes difficult to perform high-speed operation.

JP 2010-206021 A

  The present embodiment is intended to provide a semiconductor device capable of high-speed operation.

One aspect of the semiconductor device of this embodiment includes a first output buffer circuit having a pad connected to a first node, a first transistor having one end connected to the first node, and the first
A second node electrically connected to the node; and a second output buffer circuit having a second transistor having one end electrically connected to the second node; and from a contact of the second transistor The distance between the gates is smaller than the distance between the contact of the first transistor and the gate.

1 is a block diagram showing an example of a configuration of a NAND flash memory. FIG. 3 is a circuit diagram illustrating an example of a circuit configuration of a memory cell array. The block diagram which shows an example of the buffer which concerns on 1st Embodiment. FIG. 3 is a circuit diagram illustrating an example of a buffer unit according to the first embodiment. The figure which shows an example of the layout of the transistor arrange | positioned at an output buffer circuit. The circuit diagram which shows an example of the 2nd modification of a buffer part. The circuit diagram which shows an example of the 3rd modification of a buffer part. The figure which shows an example of the semiconductor device which concerns on 2nd Embodiment. The circuit diagram showing an example of the buffer part of the 2nd semiconductor chip concerning a 2nd embodiment. The circuit diagram showing an example of the modification of the buffer part of the 2nd semiconductor chip concerning a 2nd embodiment. The figure which shows an example of the 1st modification of the semiconductor device which concerns on 2nd Embodiment. The figure which shows an example of the semiconductor device which concerns on 3rd Embodiment. The figure which shows an example of the 1st modification of the semiconductor device which concerns on 3rd Embodiment. The figure which shows an example of the semiconductor device which concerns on 4th Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings.

(First embodiment)
Embodiments of the present invention will be described below with reference to the drawings.

First, referring to FIGS. 1 and 2, as an example of a semiconductor device applicable to this embodiment, NAN
The configuration of the D-type flash memory will be described as an example.

FIG. 1 is a block diagram showing an example of the configuration of a NAND flash memory. NAND
The type flash memory 100 includes a memory cell array 1 in which memory cells MC for storing data are arranged in a matrix. The memory cell array 1 includes a plurality of bit lines B
L, a plurality of word lines WL, a source line SRC, and a plurality of memory cells MC. Memory cell MC can store data of n bits (n is a natural number of 1 or more) in one memory cell.

Various commands CMD, addresses ADD, and data DT for controlling the operation of the NAND flash memory supplied from the host or the memory controller HM are input to the buffer 4. The write data input to the buffer 4 is supplied to the bit line BLs selected by the bit line control circuit 2. Various commands CMD and address ADD are:
Input to the control circuit 5, the control circuit 5 controls the booster circuit 6 and the driver 7 based on the command CMD and the address ADD. The buffer 4 also receives control signals ALE (address latch enable), CLE (command latch enable), WE (write enable), and RW (read enable). The control circuit 5 can control an output buffer circuit and the like disposed in the buffer 4.

The booster circuit 6 generates a voltage necessary for writing, reading, and erasing under the control of the control circuit 5 and supplies the voltage to the driver 7. The driver 7 supplies these voltages to the bit line control circuit 2 and the word line control circuit 3 under the control of the control circuit 5. The bit line control circuit 2 and the word line control circuit 3 read data from the memory cell MC by these voltages, write data to the memory cell MC, and erase data in the memory cell MC.

The memory cell array 1 includes a bit line control circuit 2 for controlling the voltage of the bit line BL,
A word line control circuit 3 for controlling the voltage of the word line WL is connected. Also,
The bit line control circuit 2 and the word line control circuit 3 are connected to a driver 7.

That is, the driver 7 controls the bit line control circuit 2 based on the address ADD, and reads the data of the memory cell MC in the memory cell array 1 via the bit line BL. Further, the driver 7 controls the bit line control circuit 2 based on the address ADD, and writes data in the memory cell MC in the memory cell array 1 via the bit line BL.

Further, the bit line control circuit 2, the word line control circuit 3, the driver 7, and the control circuit 5 may be collectively referred to as “control circuit”.

FIG. 2 shows an example of the circuit configuration of the memory cell array 1 shown in FIG. A plurality of memory cells are arranged in the memory cell array 1. One NAND string NS includes, for example, a memory string composed of 64 memory cells MC connected in series in the bit line direction, and
The selection transistors SD and SS are configured. Note that dummy memory cells DMC may be arranged between the memory string and the selection transistor SD and between the memory string and the selection transistor SS.

A plurality of NAND strings NS are arranged in the word line direction (m + 1 in the example of FIG. 2), one of the bit lines BL is connected to one end of the NAND string NS, and a common source line CELSRC is connected to the other end. It is connected. It can be said that a plurality of NAND strings NS are arranged in the word line direction, one end of the plurality of bit lines BL is connected to one end of the NAND string NS, and a common source line CELSRC is connected to the other end. The selection transistors SD and SS are connected to selection gate lines SGD and SGS, respectively. here,
A unit in which a plurality of NAND strings NS are arranged in the word line direction is referred to as a block.

The word line WL extends in the word line direction and commonly connects memory cells MC arranged in the word line direction. One page is composed of memory cells MC connected in the word line direction. Memory cell M
Writing to C is performed in units of pages.

  FIG. 3 is a block diagram showing an example of the buffer 4 of the NAND flash memory.

A plurality of pads PA are arranged in the buffer 4. Bonding wires, through-hole vias and the like are connected to these pads PA. Signals such as data DT are input to the pads PA from the host or the memory controller HM via bonding wires, through-hole vias, or the like. Here, data DT, command CMD, address AD
Pads to which D and the like are input are pads PA-1 to PA-k (k is an integer of 1 or more), and pads to which control signals such as a write enable signal and a chip enable signal are input are pads PA-
Let C1 and C2. Two or more pads PA-C1 and C2 may be arranged.

Buffer parts BF-1 to BF-k are connected to the pads PA-1 to k, respectively. Pad P
Buffer sections BF-C1 and C2 are connected to A-C1 and C2, respectively.

Note that the NAND flash memory 100 includes a pad to which the ground voltage VSS and the external voltage VEXT are supplied. Here, a protection element can be connected to a pad for supplying an external voltage in order to form a current path for releasing a surge.

FIG. 4 is a circuit diagram illustrating an example of the buffer unit BF-k. The buffer unit BF-1 to BF-1
The buffer unit BF-k of k will be described as a representative example. The remaining buffer units BF-1 to (k
-1) can be configured similarly. The buffer unit BF-k is connected to the pad PA-k via the node N1.

The buffer unit BF-k includes an input buffer unit IB and two types of output buffer circuits OB1 and OB.
2 has. The input buffer IB and the output buffer circuit OB1 are connected to the node N1. The output buffer circuit OB2 is also connected to the node N1 and connected to the output buffer circuit OB1 via the node N1.

The input buffer unit IB has a protection resistor IBR and an input buffer IBA. The input buffer IBA is connected to the node N1 through the protective resistor IBR. The protective resistance IBR is
Among a plurality of metal wiring layers (not shown) arranged in the NAND flash memory, for example, the wiring resistance of the metal wiring formed in the lowermost layer has a resistance value of, for example, about 300Ω.

The output buffer circuit OB1 has one p-type transistor OB1TP and one n-type transistor OB1TN. One end of the p-type transistor OB1TP is connected to the node N1, and the other end is connected to the power supply voltage VEXT. One end of the n-type transistor OB1TN is connected to the node N1, and the other end is connected to the ground voltage VSS. The control circuit 5 controls the gate electrodes (control lines) of the p-type transistor OB1TP and the n-type transistor OB1TN, respectively, and switches the p-type transistor OB1TP and the n-type transistor OB1TN between a conductive state and a non-conductive state. it can.

The output buffer circuit OB2 has one p-type transistor OB2TP and one n-type transistor OB2TN. One end of the p-type transistor OB2TP is connected to the node N2, and the other end is connected to the power supply voltage VEXT. One end of the n-type transistor OB2TN is connected to the node N3, and the other end is connected to the ground voltage VSS. The node N2 has a resistance R
2 and connected to the node N1. Node N3 is connected to node N1 via resistor R3.

Here, the resistors R2 and R3 are, for example, the lowermost wiring resistors. Note that metal wiring, polysilicon, or the like can be used for the wiring. The NAND flash memory has a plurality of layers of wiring that connect circuit elements. Here, the lowermost wiring often has the highest resistance value. Therefore, when connecting from the node N1 to the nodes N2 and N3, the connection is made through the lowermost wiring. For example, the node N1 is the uppermost layer wiring, and the node N1 is connected to the lowermost layer wiring by a contact or the like. The lowermost wiring is extended by a certain distance, and a contact CT2 of a p-type transistor OB2TP, which will be described later, and an n-type transistor OB2T which is a node N3.
Connect to N contacts CT2.

The resistors R2 and R3 can be a resistance element using a gate electrode or a resistance element including an element region.

FIG. 5 shows n-type transistors OB1TN arranged in the output buffer circuits OB1 and OB2.
It is drawing which shows an example of the layout of OB2TN. Note that the n-type transistor has been described as an example, but the p-type transistors OB1TP and OB2TP can have the same configuration.

The n-type transistor OB1TN has an element region AA1 that is isolated by an element isolation insulating film STI, a gate electrode GT1, and a contact CT1. The gate electrode GT1 extends in the Y direction and is arranged so as to separate the element region AA in the X direction. Diffusion layers are formed in the element region AA separated in the X direction, which become a source region and a drain region, respectively. A plurality of contacts CT1 are arranged in each of the source region and the drain region. Contacts CT1 are arranged in a line in the Y direction. Here, the distance between the gate electrode GT1 and the contact CT1 is a distance d1.

The n-type transistor OB2TN has an element region AA2 that is element-isolated by an element isolation insulating film STI, a gate electrode GT2, and a contact CT2. The gate electrode GT2 extends in the Y direction and is arranged so as to separate the element region AA in the X direction. Diffusion layers are formed in the element region AA separated in the X direction, which become a source region and a drain region, respectively. A plurality of contacts CT2 are arranged in each of the source region and the drain region. The contacts CT2 are arranged in a line in the Y direction. Here, the distance between the gate electrode GT2 and the contact CT2 is a distance d2.

The distance d1 is larger than the distance d2. That is, the n-type transistor OB1TN
And n-type transistor OB2TN have substantially the same diffusion layer capacitance per unit area, n-type transistor OB1TN has a diffusion layer capacitance larger than that of n-type transistor OB2TN. As a result, the function as a protection element is higher in the n-type transistor OB1TN than in the n-type transistor OB2TN.

The p-type transistors OB1TP and OB2TP have a similar relationship. That is, if the p-type transistor OB1TP and the p-type transistor OB2TP have substantially the same diffusion layer capacitance, the p-type transistor OB1TP has a larger diffusion layer capacitance than the p-type transistor OB2TP. As a result, the function as a protection element is the p-type transistor OB1T.
P is higher than the p-type transistor OB2TP.

That is, it can be said that the output buffer circuit OB1 has not only a function of the output buffer but also a function as a protection element.

Note that the width of the gate electrode GT1 and the width of the gate electrode GT2 may be the same or different.
(effect)
By connecting the output buffer circuit OB1 to the node N1 connected to the pad PA-k, the breakdown voltage against surge of the semiconductor device can be increased. On the other hand, it can be said that the output buffer circuit OB2 is connected to the output buffer circuit OB1 via the resistors R2 and R3. That is, when a surge occurs in the pad PA-1k, the node N2 is generated by the resistors R2 and R3.
, N3 time constant increases. As a result, the surge is applied to the output buffer circuit OB1 before a large electrical stress is applied to the n-type transistor OB2TN and the p-type transistor OB2TP.
To power supply voltage or ground voltage. As a result, no large electrical stress is applied to the n-type transistor OB2TN and the p-type transistor OB2TP. Therefore, the n-type transistor OB2TN and the p-type transistor OB2TP can be reduced in size. Only one of the resistors R2 and R3 may be arranged.

If it is considered that the output buffer circuit OB2 is replaced with the output buffer circuit OB1 so as to satisfy the product standard, the operation of the semiconductor device becomes slow. That is, since all the output buffers are output buffer circuits OB1 having a large diffusion layer capacity, the pin capacity is increased, and the operation of the semiconductor device is delayed.

Therefore, the diffusion layer capacitance of the output buffer circuit OB1 arranged at a position close to the pad PA-k is increased, and the function as a protection element is enhanced, while being connected to the pad PA-k via the resistors R2 and R3. The diffusion layer capacitance of the output buffer circuit OB2 can be reduced and the pin capacitance can be reduced. As a result, it is possible to provide a semiconductor device capable of high-speed operation without weakening protection from ESD.

The adjustment of the diffusion layer capacitance is not limited to changing the distance between the gate electrode and the contact. For example, the diffusion layer capacitance can be adjusted by changing the capacitance value by changing the impurity concentration of the diffusion layer.

Note that the size may be different between the n-type transistor and the p-type transistor. in this case,
If the relationship of distance d1> distance d2 is satisfied between n-type transistor OB1TN and n-type transistor OB2TN, and the relationship of distance d1> distance d2 is satisfied between p-type transistor OB1TP and p-type transistor OB2TP. good.

(Second modification)
FIG. 6 is a circuit diagram illustrating an example of a second modification of the buffer unit BF. In addition, the same code | symbol is attached | subjected to the same part as the previous figure.

As shown in FIG. 6, a plurality of output buffer circuits OB1-1 to OB1-m (m is an integer of 2 or more) are arranged to constitute an output buffer circuit group B1. Output buffer circuit OB1-
1-OB1-m are connected in series to the node N1. Each output buffer circuit OB1-1 ~
OB1-m has p-type transistors OB1TP-1 to OB1TP-m and n-type transistors OB1TN-1 to OB1TN-m, respectively.

One end of each of the p-type transistors OB1TP-1 to OB1TP-m is connected to the node N1, and the other end is connected to the power supply voltage VEXT. Each n-type transistor OB1
One end of TN-1 to OB1TN-m is connected to the node N1, and the other end is connected to the ground voltage VSS. The control circuit 5 includes p-type transistors OB1TP-1 to OB1TP-m, n
The gate electrodes (control lines) of the n-type transistors OB1TN-1 to OB1TN-m are respectively controlled, and the p-type transistors OB1TP-1 to OB1TP-m and the n-type transistors OB1TN-
1-OB1TN-m can be switched between a conductive state and a non-conductive state.

Here, it can be said that the p-type transistors OB1TP-1 to OB1TP-m are connected in parallel to the node N1, and the n-type transistors OB1TN-1 to OB1TN-m are connected to the node N1.
It can be said that they are connected in parallel.

Further, a plurality of output buffer circuits OB2-1 to OB2-n (n is an integer of 2 or more) are arranged to constitute an output buffer circuit group B2. Output buffer circuits OB2-1 to OB2-
n is connected in series to the node N1. The output buffer circuits OB2-1 to OB2-n include p-type transistors OB2TP-1 to OB2TP-n and n-type transistors OB2T, respectively.
N2-OB2TN-n.

One end of each of the p-type transistors OB2TP-1 to OB2TP-n has a power supply voltage VEX.
Connected to T. One end of each of the n-type transistors OB2TN2 to OB2TN-n is connected to the ground voltage VSS. The other ends of the p-type transistors OB2TP-1 to OBn of the output buffer circuits OB2-1 to OB2-n are connected to a node N1 via resistors RP1 to RPn, respectively.
It is connected to the. N-type transistor OB2 of output buffer circuits OB2-1 to OB2-n
The other ends of TN-1 to TN are connected to the node N1 via resistors RN1 to RNn, respectively. Here, the resistors RP <b> 1 to RPn and RN <b> 1 to RNn are, for example, lowermost wiring resistances.
Further, the resistors RP1 to RPn and RN1 to RNn can be resistor elements using an upper layer wiring resistance or a gate electrode.

The control circuit 5 controls the gate electrodes (control lines) of the p-type transistors OB2TP-1 to OB2TP-n and the n-type transistors OB2TN2 to OB2TN-n, respectively, and the p-type transistors OB2TP-1 to OB2TP-n and n-type transistors Transistors OB2TN2 to OB2TN
-N can be switched between a conducting state and a non-conducting state.

Here, it can be said that the p-type transistors OB2TP-1 to OB2TP-n are connected in parallel to the node N1, and the n-type transistors OB2TN2 to OB2TN-n are connected in parallel to the node N1.

The p-type transistors OB1TP-1 to OB1TP-m and OB2TP-1 to OB2T
P-n can be said to be connected in parallel to the node N1, and the n-type transistor OB1TN-
It can be said that 1 to OB1TN-m and OB2TN-1 to OB1TN-n are connected in parallel to the node N1.

Further, the p-type transistors O arranged in the output buffer circuits OB1-1 to OB1-m
B1TP-1 to OB1TP-m and n-type transistors OB1TN-1 to OB1TN-m
The layout of is the same as that of the n-type transistor OB1TN (OB1TP) shown in FIG. The p-type transistors OB2TP-1 to OB2TP-n and the n-type transistors OB2TN-1 to OB2TN- disposed in the output buffer circuits OB2-1 to OB2-n are also provided.
The layout of n is the same as that of the n-type transistor OB2TN (OB1TP) shown in FIG.

(effect)
The second modification can obtain the same effects as those of the first embodiment.

Further, the user may adjust the output after the product is shipped. In that case, the host or memory controller HM prevents the control circuit 5 from operating some of the output buffer circuits OB2-1 to OB2-n. For example, when the output buffer circuit OB2-n is not operated, the host or the memory controller HM turns off the transistors to the control lines of the n-type transistor OB2TN-n and the p-type transistor OB2TP-n with respect to the control circuit 5. Send a signal.

Further, resistors are connected between one end of the transistor and the node N1 for each of the p-type transistors OB2TP-1 to OB2TP-n. That is, for each output buffer circuit OB2-1 to OB2-n, the resistor RP1 is connected between the node N1 and the power supply voltage VEXT.
~ RPn will be connected. As a result, the distance d between the gate electrode GT2 and the contact CT2 of the p-type transistors OB2TP-1 to OB2TP-n by the resistances RP1 to RPn.
Even if 2 is shortened, it is possible to maintain the resistance against the surge of the output buffer circuits OB2-1 to OB2-n. As a result, the p-type transistors OB2TP-1 to OB2TP-n can be reduced.

Similarly, a resistor is connected between one end of the transistor and the node N1 for each of the n-type transistors OB2TN-1 to OB2TN-n. That is, for each output buffer circuit OB2-1 to OB2-n, the resistor RN is connected between the node N1 and the power supply voltage VEXT.
1 to RNn are connected. As a result, even if the distance d2 between the gate electrode GT2 of the n-type transistors OB2TN-1 to OB2TN-n and the contact CT2 is shortened by the resistances RN1 to RNn, the output buffer circuits OB2-1 to OB2-n are protected from surges. Resistance can be maintained. As a result, the n-type transistors OB2TN-1 to OB2TN-n can be reduced. Further, only one of the resistors RP1 to RPn or the resistors RN1 to RNn may be arranged.

  Note that the magnitude relationship between the integers m and n may be either larger or the same value.

(Third Modification)
FIG. 7 is a circuit diagram showing an example of a third modification of the buffer unit BF. In addition, the same code | symbol is attached | subjected to the same part as the previous figure.

The output buffer circuits OB2-1 to OB2-n of the third modification are connected in substantially the same manner as the output buffer circuit OB2 shown in FIG. p-type transistors OB2TP-1 to OB2TP
One end of -n is connected to the power supply voltage VEXT, and the other end is connected to the node N2. One end of the n-type transistors OB2TN-1 to OB2TN-n is connected to the ground voltage VSS, and the other end is connected to the node N3. The node N2 is connected to the node N1 via the resistor R2. Node N3 is connected to node N1 via resistor R3.

For example, p-type transistors OB2TP-1 to OB2TP-n and n-type transistor OB
2TN-1 to OB2TN-n and the nodes N2 and N3 are connected by an upper layer wiring having a small wiring resistance. On the other hand, the node N1 and the nodes N2 and N3 are connected by a lower layer wiring having a large wiring resistance.

(effect)
The second modification can obtain the same effects as those of the first embodiment and the second modification. Further, resistors R2 and R3 are arranged in the vicinity of the connection between the node N1 and the nodes N2 and N3. As a result, the number of resistors can be reduced, and the NAND flash memory 100 can be reduced in size.

In addition, the n-type transistor OB2TN and the p-type transistor OB2TP have a breakdown voltage relationship.
In many cases, they are arranged at distant positions. Therefore, node N1 and node N which are branch points of the wiring
2, resistors R2 and R3 are arranged together in the vicinity of N3. As a result, the first embodiment,
In addition to the first modification, the wiring layout can be facilitated. Resistor R2
, R3 may be arranged in only one of them.

(Second Embodiment)
The second embodiment relates to a semiconductor device in which a plurality of semiconductor chips are stacked. FIG.
3 shows an example of a semiconductor device according to the second embodiment.

As shown in FIG. 8, in the semiconductor device 200 according to the second embodiment, the first semiconductor chip 101 arranged on the base KD and the plurality of second semiconductor chips 102 to 108 are shifted by a constant interval. Are stacked. The base KD is provided with input pin connection pads 30 connected to the input pins. First semiconductor chip 101 and a plurality of second semiconductor chips 102 to 108
Have the same size when viewed from above. Further, the first of the plurality of semiconductor chips.
The semiconductor chip 101 is disposed in the lowermost layer. Note that the semiconductor device 200 described as an example includes eight semiconductor chips, but it is sufficient that there is one first semiconductor chip and one second semiconductor chip.

For example, the first semiconductor chip 101 and the plurality of second semiconductor chips 102 to 108 are the NAND flash memory 100 described in the first embodiment. Further, the first semiconductor chip 101 and the plurality of second semiconductor chips 102 to 108 have substantially the same configuration. However, the second semiconductor chips 102 to 108 are different from the first semiconductor chip 101 in the buffer portion B.
Instead of F1 to k, buffer units BF1L to kL are provided.

Here, the first semiconductor chip 101 is, for example, a NAND flash memory having the buffer unit described with reference to FIGS.

Here, the second semiconductor chips 102 to 108 are, for example, the buffer unit BF shown in FIG.
A NAND flash memory having −kL. Here, FIG. 9 is a circuit diagram illustrating an example of the buffer unit BF-kL of the second semiconductor chips 102 to 108.

Here, the buffer unit BF-kL among the buffer units BF-1L to BF-kL will be described as a representative example. The remaining buffer units BF-1L to BF- (k-1) L can have the same configuration. The buffer unit BF-kL is obtained by replacing the buffer units BF-1 to BF-k shown in FIG.

The buffer unit BF-kL is not provided with the output buffer circuit OB1 with respect to the buffer unit BF-k. The output buffer circuit OB2 is connected to the pad PA-k via the node N12.

The output buffer circuit OB2 includes a p-type transistor OB2TP and an n-type transistor OB2T.
N. The p-type transistor OB2TP has one end connected to the power supply voltage and the other end connected to the node N12. The n-type transistor OB2TN has one end connected to the node N12 and the other end connected to the ground voltage. The layout of the p-type transistor OB2TP and the n-type transistor OB2TN is the same as that shown in FIG.

As shown in FIG. 8, in the semiconductor device 200, the buffer 4-101 included in the first semiconductor chip 101 has a high function as a protection element, but has a relatively large pin capacitance. On the other hand, the buffers 4-102 to 4-108 included in the second semiconductor chips 102 to 108 have a low function as a protection element but a small pin capacitance.

The first semiconductor chip 101 and the second semiconductor chips 102 to 108 configured as described above are shown in FIG.
As shown in FIG. 4, the pads PA of each chip are exposed by stacking them with a certain interval. For example, bonding wires 29 are successively and sequentially bonded to the exposed pad PA.

That is, for example, the bonding wire 29 is first disposed on the base KD and bonded to the input pad 30 to which the input pin is connected. This input pad 30 is formed by stacking the first
The second semiconductor chips 101 and 102 to 108 are connected to external circuits.

Next, the bonding wire 29 bonded to the input pad 30 is bonded to the pad PA of the first semiconductor chip 101 and bonded to the pad PA of the second semiconductor chips 102 to 108. In this way, the input pad 30, the pad PA of the first semiconductor chip 101, and the pads PA of the second semiconductor chips 102 to 108 are electrically connected.

In the first semiconductor chip 101 and the second semiconductor chips 102 to 108, the pad PA connected by the bonding wire 29 is a pad PA having the same function.
For example, the pad PA-k to which the data DT of the first semiconductor chip is input is connected to the pad PA-k of the second semiconductor chips 102 to 108, respectively.

(effect)
Here, the pad PA-k will be described as an example. In the second embodiment, the bonding wire 29 is connected to the pad PA-k of the first semiconductor chip 101 and the plurality of pads PA-k of the second semiconductor chips 102 to 108. Here, an output buffer circuit having a high function as a protection element is an output buffer circuit OB1 arranged in the first semiconductor chip 101.
Only. This is because only the output buffer circuit OB2 having a small pin capacitance is arranged in the second semiconductor chips 102 to 108. For this reason, the capacitance connected to the bonding wire 29 and the input pad 30 can be reduced, and a decrease in signal propagation speed can be prevented.

In addition, the first semiconductor chip 10 to which data DT and the like are first input from the input pad 30
1 is provided with an output buffer circuit OB1. On the other hand, the second semiconductor chips 102 to 108 to which data DT or the like is input after the first semiconductor chip 101 are output buffer circuits O.
B1 is not arranged. However, the function of the protective element of the first semiconductor chip 101 to which the surge is most strongly applied is enhanced. On the other hand, the function of the protection element of the second semiconductor chips 102 to 108 to which the surge is not applied so strongly may be low. As a result, it is possible to provide a semiconductor device that has sufficient protection against the surge of the semiconductor device 200, can prevent a decrease in signal propagation speed due to the protection circuit, and can operate at high speed.

(Modification of the second semiconductor chip)
FIG. 10 is a circuit diagram illustrating an example of a first modification of the buffer unit BF-kL of the second semiconductor chips 102 to 108. In addition, the same code | symbol is attached | subjected to the same part as the previous figure.

The buffer unit BF-kL illustrated in FIG. 10 is obtained by omitting the output buffer circuit group B1 from the buffer unit BF-k illustrated in FIG. The output buffer circuit group B2 is the same as that shown in FIG. The layout of the p-type transistor OB2TP and the n-type transistor OB2TN is the same as that shown in FIG.

(effect)
The first modification can obtain the same effects as those of the second embodiment and the second modification of the first embodiment. Also in the second semiconductor chips 102 to 108, the user can adjust the output after product shipment. Therefore, by configuring the output buffer for adjustment with the output buffer circuit OB2 having a small diffusion layer capacity, the user can adjust the output after product shipment,
A semiconductor device with a small pin capacity can be provided.

(First modification)
FIG. 11 shows an example of a first modification of the semiconductor device according to the second embodiment. A semiconductor device 210 illustrated in FIG. 11 is obtained by applying the semiconductor device 200 to a so-called TSV method.
Through vias (to the first semiconductor chip 101 and the plurality of second semiconductor chips 102 to 108 (
TSV (Through Silicon Via) 41a to 48a are formed, and these through vias 41a to 4a are formed.
The first semiconductor chip 101 and the plurality of second semiconductor chips 102 to 108 are stacked on the base KD by bringing the 8a into contact with each other and electrically connecting them. The through vias 41 a to 48 a are formed in portions corresponding to the pads PA-k of the first semiconductor chip 101 and the PA-k of the second semiconductor chips 102 to 108. The first semiconductor chip 101 is stacked on the top layer.

In the above configuration, the first semiconductor chip 101 and the plurality of second semiconductor chips 10
2 to 108 are sequentially laminated so as to overlap when viewed from above. Therefore, the through via 48a
To the first semiconductor chip 101 and the plurality of second semiconductor chips 102 to
The pad PA of 108 is electrically connected.

In this state, the through via 41 a (pad PA-k) of the first semiconductor chip 101 and the input pad 50 are connected by the bonding wire 51.

(effect)
The second modification can obtain the same effects as those of the second embodiment. Here, the pad PA-k of the first semiconductor chip 101 and the plurality of pads PA of the second semiconductor chips 102 to 108.
-K is connected by through vias 48a-41a. Here, the output buffer circuit having a high function as the protection element is only the output buffer circuit OB1 arranged in the first semiconductor chip 101. The second semiconductor chips 102 to 108 have an output buffer circuit O having a small pin capacitance.
This is because only B2 is arranged. For this reason, the capacitance connected to the bonding wire 29 and the input pad 30 can be reduced, and a decrease in signal propagation speed can be prevented.

In addition, the first semiconductor chip 10 to which data DT and the like are first input from the input pad 50.
1 is provided with an output buffer circuit OB1. On the other hand, the second semiconductor chips 102 to 108 to which data DT or the like is input after the first semiconductor chip 101 are output buffer circuits O.
B1 is not arranged. Here, the function of the protective element of the first semiconductor chip 101 to which the surge is most strongly applied is enhanced. On the other hand, the function of the protection element of the second semiconductor chips 102 to 108 to which the surge is not applied so strongly may be low. As a result, it is possible to provide a semiconductor device that has sufficient protection against the surge of the semiconductor device 210, can prevent a decrease in signal propagation speed due to the protection circuit, and can operate at high speed.

Further, since the pads PA of each semiconductor chip are connected by through vias, the parasitic capacitance is small. Therefore, the data communication speed can be greatly improved.

Moreover, the modification of the second semiconductor chip of the second embodiment described above can be applied to this modification.

(Third embodiment)
The third embodiment relates to a semiconductor device in which a plurality of semiconductor chips having different metal wirings are stacked. FIG. 15 shows an example of a semiconductor device according to the third embodiment.

As shown in FIG. 12, in the semiconductor device 300 according to the third embodiment, the first semiconductor chip 111 arranged on the base KD and the plurality of second semiconductor chips 112 to 118 are shifted by a predetermined interval. Are stacked. The base KD is provided with input pin connection pads 30 connected to the input pins. First semiconductor chip 111 and a plurality of second semiconductor chips 112 to 11
8 has the same size when viewed from above. Of the plurality of semiconductor chips, the first semiconductor chip 111 is disposed in the lowest layer.

Here, the first semiconductor chip 111 and the second semiconductor chips 112 to 118 have buffer portions BF1 to k and buffer portions BF1L to kL, respectively. Here, in the first semiconductor chip 111, the pads PA-1 to PA-k are buffer portions BF1 to BF1 by the metal wiring MH.
connected to k. On the other hand, in the second semiconductor chips 112 to 118, the pads PA-1 to PA-k are connected to the buffer portions BF1L to kL by the metal wiring ML.

Here, the metal wirings MH and ML are, for example, metal wirings in the uppermost layer of the semiconductor chip. That is, it can be said that the first semiconductor chip 111 and the second semiconductor chips 112 to 118 have the same structure except for the layout of the uppermost metal wiring.

Further, in the first semiconductor chip 111, the buffer units BF1 to kk function, and the buffer units BF1L to kL do not function. On the other hand, in the second semiconductor chips 112 to 118, the buffer units BF1L to kL function, and the buffer units BF1 to kk do not function.

  Since other configurations are the same as those of the second embodiment, description thereof is omitted.

(effect)
The third embodiment can obtain the same effect as the second embodiment. Moreover, the 1st semiconductor chip 111 and the 2nd semiconductor chips 112-118 can be manufactured only by changing 1 layer of a metal wiring layer. As a result, the first semiconductor chip 111 and the second semiconductor chip 112-
118 has many common parts and can improve design efficiency and production efficiency.

Further, a modification of the second semiconductor chip of the second embodiment described above can be applied to this embodiment.

(First modification)
FIG. 13 shows an example of a first modification of the semiconductor device according to the third embodiment. A semiconductor device 310 illustrated in FIG. 13 is obtained by applying the semiconductor device 300 to a so-called TSV method.
As a result, the same effect as the third embodiment can be obtained. Also, each semiconductor chip pad PA
Are connected by through vias, the parasitic capacitance is small. Therefore, the data communication speed can be greatly improved.

Moreover, it is also possible to apply the modification of the 2nd semiconductor chip of 2nd Embodiment to this modification.

(Fourth embodiment)
The fourth embodiment relates to a semiconductor device in which semiconductor chips are stacked. FIG. 14 shows an example of a semiconductor device according to the fourth embodiment.

As shown in FIG. 14, in the semiconductor device 400 according to the fourth embodiment, the first semiconductor chip 121 arranged on the base KD and the plurality of second semiconductor chips 122 to 128 are shifted by a predetermined interval. Are stacked. The base KD is provided with input pin connection pads 30 connected to the input pins. First semiconductor chip 121 and a plurality of second semiconductor chips 122 to 128
Have the same size when viewed from above. Further, the first of the plurality of semiconductor chips.
The semiconductor chip 121 is disposed in the lowermost layer.

Here, the first semiconductor chip 121 and the second semiconductor chips 122 to 128 have the same configuration. That is, the first semiconductor chip 121 and the second semiconductor chips 122-1
28 has pads PA-1 to k connected to the buffer units BF-1 to k, respectively, and pads PA-1L to kL in the buffer units BF-1L to kL, respectively.

The first semiconductor chip 121 and the second semiconductor chips 122 to 128 configured as described above are shown in FIG.
As shown in FIG. 4, the pads PA of each chip are exposed by stacking them with a certain interval. For example, bonding wires 29 are successively and sequentially bonded to the exposed pad PA.

The bonding wire 29 bonded to the input pad 30 is bonded to the pad PA-k of the first semiconductor chip 101 and bonded to the pad PA-kL of the second semiconductor chips 102 to 108. In this way, the input pad 30, the pad PA-k of the first semiconductor chip 101, and the pad PA-kL of the second semiconductor chips 102 to 108 are electrically connected.

In the first semiconductor chip 121 and the second semiconductor chips 122 to 128, the pad PA connected by the bonding wire 29 is a pad PA having the same function except for the buffer unit BF.

That is, the bonding word line is connected to the first semiconductor chip 121 so that the buffer unit BF-k functions, and the second semiconductor chips 122 to 128 are connected to the buffer unit BF-k.
Bonding wires are connected so that kL functions.

(effect)
The fourth embodiment can obtain the same effects as those of the second embodiment. Further, the same effect as that of the second embodiment can be obtained only by changing the connection of the bonding wire 29. As a result, the first
The semiconductor chip 111 and the second semiconductor chips 112 to 118 can be made the same semiconductor chip, and design efficiency and production efficiency can be increased.

Moreover, it is also possible to apply the modification of the 2nd semiconductor chip of 2nd Embodiment to this embodiment.

In addition, the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Moreover, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

DESCRIPTION OF SYMBOLS 100 ... Semiconductor chip, PA ... Pad, BF ... Buffer part, OB1, OB2 ... Output buffer circuit, OB1TN, OB2TN ... N-type transistor, OB1TP, OB2TP ... P-type transistor, B1, B2 ... Output buffer group, 200, 210, 300, 310, 400
... Semiconductor device.

Claims (6)

A pad connected to the first node;
A first output buffer circuit having a first transistor having one end connected to the first node;
A second node electrically connected to the first node;
A second output buffer circuit having a second transistor having one end electrically connected to the second node;
The distance between the contact of the second transistor and the gate is smaller than the distance between the contact of the first transistor and the gate. A third node electrically connected to the first node;
The first output buffer further includes a third transistor connected to the first node;
The second output buffer further includes a fourth transistor connected to a third node;
The first transistor and the second transistor are p-type transistors,
The third transistor and the fourth transistor are n-type transistors,
The other ends of the first transistor and the second transistor are each connected to a power supply voltage,
2. The semiconductor device according to claim 1, wherein the other ends of the third transistor and the fourth transistor are connected to a ground voltage. A pad connected to the first node;
A first output buffer circuit having a first transistor having one end connected to the first node and a third transistor having one end connected to the first node;
A second output buffer circuit having a second transistor having one end electrically connected to the first node and a fourth transistor having one end electrically connected to the first node;
The distance from the contact of the second transistor to the gate is smaller than the distance from the contact of the first transistor to the gate;
The first transistor and the second transistor are p-type transistors,
The third transistor and the fourth transistor are n-type transistors,
The other ends of the first transistor and the second transistor are each connected to a power supply voltage,
The other ends of the third transistor and the fourth transistor are each connected to a ground voltage,
A semiconductor device, wherein a resistor is disposed between at least one of the first node and the second transistor or between the first node and the fourth transistor. 3. The semiconductor device according to claim 2, wherein a resistor is disposed between at least one of the first node and the second node or between the first node and the third node. 5. The semiconductor device according to claim 1, wherein an input buffer is connected to the first node. 6. The semiconductor device according to claim 1, wherein a plurality of the first output buffers are arranged, and a plurality of the second output buffers are arranged.

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