JP2014075744A - Oscillator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oscillation circuit that precisely outputs an oscillation signal of a desired frequency.SOLUTION: According to an embodiment, an oscillation circuit 1 is an oscillation circuit including a pulse generation section 10, and the pulse generation section 10 includes a comparator 103 for comparing a voltage Ve1 with a reference voltage Vref to output a comparison result Ve3 in a normal operation mode and setting a voltage at a non-inverting input terminal at the level of the reference voltage Vref in an initialization mode, and a comparator 104 for comparing a voltage Vf1 with the reference voltage Vref to output a comparison result Vf3 in the normal operation mode and setting a voltage at a non-inverting input terminal at the level of the reference voltage Vref in the initialization mode.

Description

  The present invention relates to an oscillation circuit, for example, an oscillation circuit suitable for accurately outputting an oscillation signal having a desired frequency.

  In recent years, an oscillation circuit that outputs an oscillation signal having a desired frequency with high accuracy is required. A related technique is disclosed in Patent Document 1. The oscillation circuit disclosed in Patent Document 1 includes first and second capacitors, first and second comparison circuits, an RS flip-flop circuit, and first and second charge / discharge control circuits. .

  The first and second capacitors are charged or discharged by the current generated by the constant current source. The first comparison circuit compares the first voltage V1 corresponding to the amount of electric charge stored in the first capacitor and the first reference voltage Vst, and the first voltage V1 is the first reference voltage. A first signal indicating that the voltage Vst has been reached is output. The second comparison circuit compares the second voltage V2 corresponding to the amount of electric charge stored in the second capacitor and the second reference voltage Vst, and the second voltage V2 is the second reference voltage. A second signal indicating that the voltage Vst has been reached is output.

  The RS flip-flop circuit is set by one of the first signal and the second signal, and is reset by the other. The first charge / discharge control circuit sets the first capacitor in a charged state when the RS flip-flop circuit is in a set state and in a discharged state when the RS flip-flop circuit is in a reset state. The second charge / discharge control circuit sets the second capacitor in a charged state when the RS flip-flop circuit is in a reset state and in a discharged state when the RS flip-flop circuit is in a set state.

  Here, in this oscillation circuit, ideally, the logic of the output signal of the RS flip-flop circuit is the same as the first voltage V1 exceeds the reference voltage Vst or the second voltage V2 exceeds the reference voltage Vst. The value changes. However, in reality, the logical value of the output signal (oscillation signal) of the RS flip-flop circuit changes when the first voltage V1 exceeds the reference voltage Vst or when the second voltage V2 changes the reference voltage Vst. This is after the elapse of the delay time Td caused by the operation delay of each of the first or second comparison circuit and the RS flip-flop circuit. For this reason, this oscillation circuit has a problem that when the delay time Td changes due to fluctuations in temperature and power supply voltage, the frequency of the oscillation signal fluctuates accordingly. That is, this oscillation circuit has a problem that an oscillation signal having a desired frequency cannot be output with high accuracy. In particular, when the bias current supplied to the first and second comparison circuits is lowered to reduce the power consumption, the delay time Td increases, and this problem becomes significant.

  A solution to such a problem is disclosed in Non-Patent Document 1. The oscillation circuit disclosed in Non-Patent Document 1 includes a pulse generation unit that generates a control signal Vctrl having a pulse width corresponding to the delay time Td, and controls the frequency of the oscillation signal based on the control signal. As a result, the oscillation circuit outputs an oscillation signal having a desired frequency without being affected by fluctuations in the delay time Td.

JP 2007-243922 A

T. Tokairin, K. Nose, K. Takeda, K. Noguchi, T. Maeda, K. Kawai and M. Mizuno, "A 280nW, 100kHz, 1-Cycle Start-up Time, On-chip CMOS Relaxation Oscillator Employing a Feedforward Period Control Scheme ", 2012 Symposium on VLSI Circuits Digest of Technical Papers, 2012, pp.16-17

  As apparent from FIG. 5 (a) in the literature, the oscillation circuit of the related technology includes capacitors C5 and C6 in the pulse generation unit. Therefore, the nodes Vc5 and Vc6 are once set to the initial value voltage Vcl. Then, it is sufficient to charge only the amount changed due to the leakage current, and the initial value voltage Vcl can be set with high speed and low power consumption. However, in the related art oscillation circuit, the signal at the input node of the comparator is attenuated by the ratio between the capacitors C5 and C6 and the gate capacitance of the comparator connected to them, so that the nodes Vc3 and Vc4 must be charged extra. Therefore, an error occurs between the rising speed of the voltages Vc1 and Vc2 of the oscillation circuit and the rising speed of the voltages Vc3 and Vc4 of the pulse generator, and accordingly, the oscillation frequency of each of the oscillation circuit and the pulse generator is changed. An error will occur. As a result, the related art oscillation circuit has a problem that it cannot accurately generate an oscillation signal having a desired frequency. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to an embodiment, the oscillation circuit includes a pulse generation unit, and the pulse generation unit is configured to perform a first operation according to the charge accumulated in the third capacitor in a first period in which the third capacitor is charged. The third voltage is compared with the reference voltage, and the second set signal is output. In the second period other than the first period, the voltage of the input terminal to which the third voltage is supplied is set to the reference voltage level. In a third period in which the third comparator and the fourth capacitor are charged, a fourth voltage corresponding to the charge accumulated in the fourth capacitor is compared with the reference voltage, and a second reset signal is output. In a fourth period other than the third period, a fourth comparator sets the voltage of the input terminal to which the fourth voltage has been supplied to the reference voltage level.

  According to one embodiment, the oscillation circuit includes a first capacitor, and charges or discharges the first capacitor at a charge rate corresponding to the control signal based on the first trigger signal. A first comparator that compares the discharge unit, a first voltage corresponding to the charge accumulated in the first capacitor, and a reference voltage and outputs a first comparison result; and the first voltage is greater than the reference voltage. A first pulse output as the first trigger signal by delaying the timing of the change from the first logical value to the second logical value of the first comparison result indicating that the state has changed from a large state to a state below the reference voltage An adjustment unit; a frequency divider that generates a first output signal having a period corresponding to the first trigger signal; and a pulse generation unit, wherein the pulse generation unit includes a second capacitor, and the control signal Based on the second condition A second charge charging / discharging unit that controls whether or not to charge the second capacitor, and a second voltage corresponding to the charge accumulated in the second capacitor and the reference in a first period during which the second capacitor is charged. A second comparator that compares the voltage and outputs a second comparison result, and sets the voltage of the input terminal to which the second voltage has been supplied to the reference voltage level in a second period other than the first period; And a control circuit for outputting the control signal based on the second comparison result and the first trigger signal.

  According to the embodiment, it is possible to provide an oscillation circuit that can generate an oscillation signal having a desired frequency with high accuracy.

1 is a diagram illustrating a configuration example of an oscillation circuit according to a first embodiment; 3 is a diagram illustrating a configuration example of a pulse generation unit provided in the oscillation circuit according to the first embodiment; FIG. 3 is a diagram illustrating a configuration example of a comparator according to the first embodiment; FIG. 3 is a timing chart showing an operation of the oscillation circuit according to the first exemplary embodiment; 3 is a timing chart showing the operation of the pulse generator according to the first exemplary embodiment; FIG. 3 is a diagram illustrating a configuration example of an oscillation circuit according to a second embodiment. 6 is a diagram illustrating a configuration example of a pulse generation unit provided in an oscillation circuit according to a second embodiment; FIG. 6 is a timing chart illustrating an operation of a pulse generation unit according to the second exemplary embodiment; FIG. 6 is a diagram illustrating a configuration example of a part of an oscillation circuit according to a third embodiment; FIG. 6 is a diagram illustrating a configuration example of a comparator according to a third embodiment. 6 is a timing chart illustrating an operation of the oscillation circuit according to the third exemplary embodiment; FIG. 6 is a diagram illustrating a configuration example of an oscillation circuit according to a fourth embodiment. FIG. 10 is a diagram illustrating a configuration example of a pulse width adjustment unit 44 according to a fourth embodiment. FIG. 10 is a diagram illustrating a configuration example of a pulse width adjustment unit 404 according to the fourth embodiment. FIG. 9 is a diagram illustrating a configuration example of a control circuit according to a fourth embodiment. 6 is a timing chart illustrating an operation of the oscillation circuit according to the fourth embodiment; FIG. 10 is a diagram illustrating a modification of the oscillation circuit according to the fourth embodiment. FIG. 10 is a diagram illustrating a configuration example of a bias voltage generation unit according to a fifth embodiment; FIG. 10 is a diagram illustrating a configuration example of a bias voltage generation unit according to a fifth embodiment; FIG. 10 is a diagram illustrating a configuration example of a clock generation circuit according to a sixth embodiment; FIG. 10 is a diagram illustrating a configuration example of a clock generation circuit according to a seventh embodiment; FIG. 10 is a diagram illustrating a configuration of a PLL according to an eighth embodiment. FIG. 10 illustrates a configuration of a semiconductor integrated circuit according to a ninth embodiment. It is a figure which shows the structure of the oscillation circuit concerning the concept before reaching embodiment. It is a timing chart which shows operation | movement of the oscillation circuit concerning the concept before reaching embodiment. It is a figure which shows the structure of the oscillation circuit concerning the concept before reaching embodiment. FIG. 26 is a diagram illustrating a configuration of a pulse generation unit provided in the oscillation circuit illustrated in FIG. 25. It is a figure which shows the structural example of SW control circuit provided in the pulse generation part shown in FIG. 26 is a timing chart showing an operation of the oscillation circuit shown in FIG. It is a timing chart which shows the operation | movement of the pulse generation part shown in FIG.

<Preliminary examination by the inventors>
Prior to the description of the embodiments, the contents examined in advance by the present inventors will be described.

<Oscillation circuit 500 according to the concept before reaching the embodiment>
FIG. 23 is a diagram illustrating a configuration of a relaxation oscillation circuit 500 according to the concept before reaching the embodiment. An oscillation circuit 500 illustrated in FIG. 23 includes an RS flip-flop 501, a charge charge / discharge unit 502, a comparator 503, a comparator 504, and a reference voltage generation unit 505.

  The RS flip-flop 501 outputs output signals Q and QB based on input signals (comparison results Vx2 and Vy2) supplied to the input terminals S and R, respectively. For example, if the input signal supplied to the input terminal S rises when the input signal supplied to the input terminal R is L level, the RS flip-flop 501 raises the output signal Q and lowers the output signal QB. On the other hand, when the input signal supplied to the input terminal R rises when the input signal supplied to the input terminal S is at the L level, the RS flip-flop 501 raises the output signal Q and raises the output signal QB. The RS flip-flop 501 oscillates the output signals Q and QB when input signals supplied to the input terminal R and the input terminal S rise alternately. The output signals Q and QB are also referred to as oscillation signals.

  The charge charging / discharging unit 502 is a unit that charges or discharges the capacitors C1 and C2 in a complementary manner based on the output signals Q and QB. The charge charging / discharging unit 502 includes a constant current source circuit B5 that supplies a constant current, switches SW1 to SW4, a capacitor C1, and a capacitor C2. The switches SW1 to SW4 are also referred to as switch units. Here, a case where the capacitance value of the capacitor C1 and the capacitance value of the capacitor C2 are substantially the same will be described as an example.

  In the charge / discharge unit 502, the input terminal of the constant current source circuit B5 is connected to a high potential side power supply terminal (hereinafter referred to as a power supply voltage terminal VDD) to which the power supply voltage VDD is supplied. The output terminal of the constant current source circuit B5 is connected to one end of the switch SW1 and one end of the switch SW3. The other end of the switch SW1 is connected to one end of the switch SW2 via the node X1. The other end of the switch SW2 is connected to a low potential side power supply terminal (hereinafter referred to as a ground voltage terminal GND) to which the ground voltage GND is supplied. The other end of the switch SW3 is connected to one end of the switch SW4 via the node Y1. The other end of the switch SW4 is connected to the ground voltage terminal GND.

  The capacitor C1 is provided in parallel with the switch SW2 between the node X1 and the ground voltage terminal GND. The capacitor C2 is provided in parallel with the switch SW4 between the node Y1 and the ground voltage terminal GND.

  On / off of the switches SW1 and SW4 is controlled based on the output signal QB of the RS flip-flop 501. On the other hand, ON / OFF of the switches SW2 and SW3 is controlled based on the output signal Q of the RS flip-flop 501.

  For example, when the output signal Q is L level and the output signal QB is H level, the switches SW1 and SW4 are turned on and the switches SW2 and SW3 are turned off. In this case, since one end (node X1 side) of the constant current source circuit B5 and the capacitor C1 becomes conductive, electric charge is gradually accumulated at one end of the capacitor C1 due to the current flowing through the constant current source circuit B5. Thereby, the voltage Vx1 of the node X1 gradually increases. Further, since the ground voltage terminal GND and one end of the capacitor C2 (on the node Y1 side) are conducted, the charge stored at one end of the capacitor C2 is rapidly released. Thereby, the voltage Vy1 at the node Y1 rapidly decreases to the ground voltage level (L level).

  On the other hand, when the output signal Q is H level and the output signal QB is L level, the switches SW1 and SW4 are turned off and the switches SW2 and SW3 are turned on. In this case, since one end (node Y1 side) of the constant current source circuit B5 and the capacitor C2 becomes conductive, electric charge is gradually accumulated at one end of the capacitor C2 due to the current flowing through the constant current source circuit B5. Thereby, the voltage Vy1 gradually increases. Further, since the ground voltage terminal GND and one end of the capacitor C1 (on the node X1 side) are conducted, the charge stored at one end of the capacitor C1 is rapidly released. Thereby, the voltage Vx1 rapidly decreases to the ground voltage level (L level).

  Thus, the capacitor C1 and the capacitor C2 are charged or discharged in a complementary manner by the output signals Q and QB of the RS flip-flop.

  The reference voltage generation unit 505 is a unit that generates a reference voltage Vref having a stable voltage level. The reference voltage generation unit 505 includes a constant current source circuit B3 that supplies a constant current and a resistance element R1.

  The constant current source circuit B3 and the resistance element R1 are provided in series between the power supply voltage terminal VDD and the ground voltage terminal GND. More specifically, the input terminal of the constant current source circuit B3 is connected to the power supply voltage terminal VDD. The output terminal of the constant current source circuit B3 is connected to one end of the resistance element R1 through the node N1. The other end of the resistance element R1 is connected to the ground voltage terminal GND. Here, the voltage level of the node N1 is determined based on the current value of the current output from the constant current source circuit B3 and the resistance value of the resistance element R1. The reference voltage generation unit 505 outputs the voltage at the node N1 as the reference voltage Vref.

  The comparator 503 compares the reference voltage Vref and the voltage Vx1, and outputs a comparison result Vx2 to the node X2. In the example of FIG. 23, the comparator 503 outputs an H level comparison result Vx2 when the voltage Vx1 is greater than the reference voltage Vref, and outputs an L level comparison result Vx2 when the voltage Vx1 is equal to or lower than the reference voltage Vref.

  The comparator 504 compares the reference voltage Vref and the voltage Vy1, and outputs a comparison result Vy2 to the node Y2. In the example of FIG. 23, the comparator 504 outputs an H level comparison result Vy2 when the voltage Vy1 is greater than the reference voltage Vref, and outputs an L level comparison result Vy2 when the voltage Vy1 is less than or equal to the reference voltage Vref.

  For example, when the output signal Q is L level and the output signal QB is H level, the switches SW1 and SW4 are turned on and the switches SW2 and SW3 are turned off as described above. Thereby, since the capacitor C1 is charged, the voltage Vx1 gradually increases. When the voltage Vx1 exceeds the level of the reference voltage Vref, the comparator 503 raises the comparison result Vx2. At this time, since the capacitor C2 is discharged, the voltage Vy1 is equal to or lower than the reference voltage Vref (L level). Therefore, the comparator 504 outputs the L level comparison result Vy2. Thereby, the RS flip-flop 501 raises the output signal Q and falls the output signal QB.

  Since the output signal Q becomes H level and the output signal QB becomes L level, the switches SW1 and SW4 are turned off and the switches SW2 and SW3 are turned on. Thereby, since the capacitor C2 is charged, the voltage Vy1 gradually increases. When the voltage Vy1 exceeds the level of the reference voltage Vref, the comparator 504 raises the comparison result Vy2. At this time, since the capacitor C1 is discharged, the voltage Vx1 is equal to or lower than the reference voltage Vref (L level). For this reason, the comparator 503 outputs the L level comparison result Vx2. Thereby, the RS flip-flop 501 falls the output signal Q and raises the output signal QB. Such an operation is repeated.

  Thus, the comparison results Vx2 and Vy2 of the comparators 503 and 504 rise alternately. The RS flip-flop 501 oscillates the output signals Q and QB by alternately rising input signals (comparison results Vx2 and Vy2) supplied to the input terminal R and the input terminal S, respectively.

  Here, in the oscillation circuit 500 shown in FIG. 23, ideally, when the voltage Vx1 exceeds the level of the reference voltage Vref or when the voltage Vy1 exceeds the level of the reference voltage Vref, the RS flip-flop 501 The output signals Q and QB change in logical value. However, in reality, the logical values of the output signals Q and QB of the RS flip-flop 501 change from the time when the voltage Vx1 exceeds the level of the reference voltage Vref or the time when the voltage Vy1 exceeds the level of the reference voltage Vref. After the delay time Td caused by the operation delay of the comparators 503 and 504 and the RS flip-flop 501 has elapsed (see FIG. 24).

  In addition, the change speed (slew rate) of the voltage Vx1 or the voltage Vy1 in the ideal state is expressed as the following formula (1). However, V represents the voltage Vx1 or the voltage Vy1, I represents the current value of the current flowing through the constant current source circuit B5, and C represents the capacitance value of the capacitor C1 or the capacitor C2.

  dV / dt = I / C (1)

  Further, the reference voltage Vref is expressed as the following equation (2). Here, R1 represents the resistance value of the resistance element R1, and Ib represents the current value of the current flowing through the constant current source circuit B3.

  Vref = R1 · Ib (2)

  Here, assuming that the current value I and the current value Ib are the same, the pulse widths Tp of the output signals Q and QB in the ideal state are expressed by the following equation (3) from the equations (1) and (2). It is expressed as

  Tp = C · Vref / Ib = R1 · C (3)

  However, actually, the pulse widths Tp of the output signals Q and QB are expressed as follows due to the influence of the operation delay of the comparators 503 and 504 and the RS flip-flop 501 as described above.

  Tp = R1 · C + Td (4)

  Therefore, the oscillation circuit 500 shown in FIG. 23 has a problem that when the delay time Td changes due to changes in temperature and power supply voltage, the oscillation frequencies of the output signals Q and QB change accordingly. That is, the oscillation circuit 500 shown in FIG. 23 has a problem that an oscillation signal (output signals Q and QB) having a desired frequency cannot be output with high accuracy.

<Oscillation circuit 600 according to the concept before reaching the embodiment>
FIG. 25 is a diagram showing a configuration of a relaxation oscillation circuit 600 according to the concept before reaching the embodiment. An oscillation circuit 600 illustrated in FIG. 25 includes an RS flip-flop 601, a charge charge / discharge unit 602, comparators 603 and 604, a reference voltage generation unit 605, an initial value generation unit 606, and a pulse generation unit 700. . The RS flip-flop 601, the charge charging / discharging unit 602, the comparators 603, 604, and the reference voltage generating unit 605 correspond to the RS flip-flop 501, the charge charging / discharging unit 502, the comparators 503, 504, and the reference voltage generating unit 505, respectively. To do.

  The charge / discharge unit 602 includes a variable current source circuit B1, switches SW1 to SW4, and capacitors C1 and C2. That is, the charge charging / discharging unit 602 includes a variable current source circuit B1 instead of the constant current source circuit B5, as compared with the charge charging / discharging unit 502. The variable current source circuit B1 flows a current corresponding to the control signal Vctrl output from the pulse generation unit 700. For example, when the control signal Vctrl is at L level, a current having a current value I flows through the variable current source circuit B1. On the other hand, when the control signal Vctrl is at the H level, a current having a current value 2I (twice the current value I) flows through the variable current source circuit B1. The rising speeds (slew rates) of the voltages Vx1 and Vy1 of the nodes X1 and Y1 when the current of the current value 2I flows through the variable current source circuit B1 are the same as when the current of the current value I flows through the variable current source circuit B1. This is twice the rising speed (slew rate) of the voltages Vx1 and Vy1.

  The initial value generation unit 606 is a unit that generates an initial value voltage Vcl and supplies it to the pulse generation unit 700. For example, the initial value voltage Vcl indicates a voltage level slightly lower than the reference voltage Vref.

  The pulse generation unit 700 is a unit that generates a control signal Vctrl having substantially the same pulse width as the delay time Td in synchronization with changes in the logical values of the output signals Q and QB. In other words, the pulse generator 700 raises the control signal Vctrl in synchronization with changes in the logical values of the output signals Q and QB, and falls after the delay time Td has elapsed.

(Specific Configuration Example of Pulse Generation Unit 700)
FIG. 26 is a diagram illustrating a specific configuration example of the pulse generation unit 700. 26 includes an RS flip-flop 701, a charge charge / discharge unit 702, a comparator 703, a comparator 704, a SW control circuit 705, capacitors C3D and C4D, and switches SW5D and SW6D. Have. The RS flip-flop 701, the charge charging / discharging unit 702, and the comparators 703, 704 correspond to the RS flip-flop 601, the charge charging / discharging unit 602, and the comparators 603, 604, respectively.

  The pulse generator 700 is configured such that the RS flip-flop 701 outputs output signals (oscillation signals) QD and QBD having substantially the same frequency as the output signals Q and QB. In addition, the pulse generator 700 is configured such that the delay time caused by the operation delay of the comparators 703 and 704 and the RS flip-flop 701 is the delay time Td caused by the operation delay of the comparators 603 and 604 and the RS flip-flop 601. It is comprised so that it may become substantially the same. Therefore, for example, the comparators 703 and 704 and the RS flip-flop 701 have the same configuration as the comparators 603 and 604 and the RS flip-flop 601, respectively.

  The RS flip-flop 701 receives an output signal QD from the output terminal Q based on an input signal (comparison result Ve3 described later) supplied to the input terminal S and an input signal (comparison result Vf3 described later) supplied to the input terminal R. And an output signal QBD (an inverted signal of the output signal QD) is output from the output terminal QB. The basic operation of the RS flip-flop 701 is the same as that of the RS flip-flop 601.

  The SW control circuit 705 outputs the switching signals S1 to S4 and the control signal Vctrl based on the output signals QD and QBD of the RS flip-flop 701 and the output signals Q and QB of the RS flip-flop 601.

  FIG. 27 is a diagram illustrating a specific configuration example of the SW control circuit 705. The SW control circuit 705 illustrated in FIG. 27 includes logical product circuits (hereinafter simply referred to as AND circuits) 7051 to 7054 and logical sum circuits (hereinafter simply referred to as OR circuits) 7055. The AND circuit 7051 outputs a logical product of the output signal QBD and the output signal Q as the switching signal S1. The AND circuit 7052 outputs a logical product of the output signal QD and the output signal Q as the switching signal S2. The AND circuit 7053 outputs a logical product of the output signal QD and the output signal QB as the switching signal S3. The AND circuit 7054 outputs a logical product of the output signal QBD and the output signal QB as the switching signal S4. Then, the OR circuit 7055 outputs a logical sum of the switching signal S1 and the switching signal S3 as the control signal Vctrl.

  Returning to FIG. 26, the charge charging / discharging unit 702 is a unit that charges or discharges the capacitors C1D and C2D in a complementary manner based on the switching signals S1 to S4 from the SW control circuit 705. The charge / discharge unit 702 includes a constant current source circuit B1D that allows a constant current to flow, switches SW1D to SW4D, and capacitors C1D and C2D.

  The input terminal of the constant current source circuit B1D is connected to the power supply voltage terminal VDD. The output terminal of the constant current source circuit B1D is connected to one end of the switch SW1D and one end of the switch SW3D. The other end of the switch SW1D is connected to one end of the switch SW2D via the node E1. The other end of the switch SW2D is connected to the ground voltage terminal GND. The other end of the switch SW3D is connected to one end of the switch SW4D via the node F1. The other end of the switch SW4D is connected to the ground voltage terminal GND.

  The capacitor C1D is provided in parallel with the switch SW2D between the node E1 and the ground voltage terminal GND. Capacitor C2D is provided in parallel with switch SW4D between node F1 and ground voltage terminal GND.

  On / off of the switches SW1D to SW4D is controlled based on the switching signals S1 to S4, respectively. A current having a current value I flows through the constant current source circuit B1D. Further, the capacitance values of the capacitors C1D and C2D are the same as those of the capacitors C1 and C2. The basic operation of the charge / discharge unit 702 is the same as that of the charge / discharge unit 602.

  Hereinafter, a case where the on / off of the switches SW1D to SW4D is controlled based on the switching signals S1 to S4 will be described as an example, but the present invention is not limited thereto. The switches SW1D to SW4D may be configured to be controlled based on the switching signal S1, the inverted signal of the switching signal S1, the switching signal S3, and the inverted signal of the switching signal S3 (hereinafter referred to as configuration B).

  The capacitor C3D is provided between the node E1 and the node E2. Capacitor C4D is provided between nodes F1 and F2. A switch SW5D and a switch SW6D are provided in series between the node E2 and the node F2. On / off of the switch SW5D is controlled based on the output signal QB. On / off of the switch SW6D is controlled based on the output signal Q. An initial value voltage Vcl is supplied to a node between the switches SW5D and SW6D. For example, when the output signal Q is H level and the output signal QB is L level, the switch SW5D is turned off and the switch SW6D is turned on, so that the initial value voltage Vcl is supplied to the node F2 side. On the other hand, when the output signal Q is L level and the output signal QB is H level, the switch SW5D is turned on and the switch SW6D is turned off, so that the initial value voltage Vcl is supplied to the node E2.

  For example, the initial value voltage Vcl indicates a voltage level slightly lower than the reference voltage Vref. Accordingly, the comparator 703 maintains the comparison result Ve3 at the L level when the voltage Ve1 is at the ground voltage level, and switches the comparison result Ve3 to the H level when the voltage Ve1 slightly increases. Similarly, the comparator 704 maintains the comparison result Vf3 at the L level when the voltage Vf1 is at the ground voltage level, and switches the comparison result Vf3 to the H level when the voltage Vf1 slightly increases.

  The comparator 703 compares the reference voltage Vref with the voltage Ve2 at the node E2, and outputs a comparison result Ve3 to the node E3. In the example of FIG. 26, the comparator 703 outputs an H level comparison result Ve3 when the voltage Ve2 is greater than the reference voltage Vref, and outputs an L level comparison result Ve3 when the voltage Ve2 is equal to or lower than the reference voltage Vref.

  The comparator 704 compares the reference voltage Vref and the voltage Vf2 at the node F2, and outputs a comparison result Vf3 to the node F3. In the example of FIG. 26, the comparator 704 outputs an H level comparison result Vf3 when the voltage Vf2 is greater than the reference voltage Vref, and outputs an L level comparison result Vf3 when the voltage Vf2 is less than or equal to the reference voltage Vref.

  Since other configurations and operations of the oscillation circuit 600 are the same as those of the oscillation circuit 500, description thereof is omitted.

(Timing chart)
Subsequently, the operation of the oscillation circuit 600 will be described with reference to FIGS.

  First, the operation of the oscillation circuit 600 will be described with reference to FIG. FIG. 28 is a timing chart showing the operation of the oscillation circuit 600. In the example of FIG. 28, since the output signal Q is at the H level and the output signal QB is at the L level at time t0, the switches SW1 and SW4 are turned off and the switches SW2 and SW3 are turned on. Therefore, the voltage Vy1 (second voltage) continues to rise. On the other hand, the voltage Vx1 (first voltage) indicates the ground voltage level (L level).

  When the voltage Vy1 exceeds the reference voltage Vref (time t1), the comparator 604 raises the comparison result Vy2 with a slight delay. At this time, the comparator 603 outputs an L level comparison result Vx2. Thereby, the RS flip-flop 601 falls the output signal Q and raises the output signal QB (time t2). In other words, when the voltage Vy1 exceeds the reference voltage Vref (time t1), after the elapse of the delay time Td caused by the operation delay of the comparator 604 and the RS flip-flop 601, the output signal Q falls and the output signal QB becomes Stand up (time t2).

  Since the output signal Q is at the L level and the output signal QB is at the H level, the switches SW1 and SW4 are turned on and the switches SW2 and SW3 are turned off (time t2). Thereby, the voltage Vx1 starts to rise. On the other hand, the voltage Vy1 indicates the ground voltage level (L level). Here, the pulse generation unit 700 raises the control signal Vctrl in synchronization with the change in the logical value of the output signals Q and QB (time t2). Then, the pulse generator 700 causes the control signal Vctrl to fall after the delay time Td has elapsed (time t3). That is, the pulse generator 700 outputs the control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with the change in the logical value of the output signals Q and QB.

  During the period in which the control signal Vctrl is at the H level (time t2 to t3), the current of the current value 2I flows through the variable current source circuit B1, so that the voltage Vx1 rises at twice the normal speed (slew rate). After the control signal Vctrl falls (time t3 to t5), the current of the normal current value I flows through the variable current source circuit B1, so that the voltage Vx1 increases at a normal speed (slew rate).

  When the voltage Vx1 exceeds the reference voltage Vref (time t4), the comparator 603 raises the comparison result Vx2 with a little delay. At this time, the comparator 604 outputs the L level comparison result Vy2. Thereby, the RS flip-flop 601 raises the output signal Q and falls the output signal QB (time t5). In other words, when the voltage Vx1 exceeds the reference voltage Vref (time t4), the output signal Q rises and the output signal QB rises after the elapse of the delay time Td caused by the operation delay of the comparator 603 and the RS flip-flop 601. Decrease (time t5).

  Here, the value of the voltage Vx1 at the time (time t3) when the control signal Vctrl falls is expressed by the following equation (5). However, C1 shows the capacitance value of the capacitor C1.

  Vx1 = 2I · Td / C1 (5)

  The difference voltage between the reference voltage Vref and the voltage Vx1 at this time is expressed as the following equation (6).

  Vref−Vx1 = Vref−2I · Td / C1 (6)

  Therefore, a period Tx from when the logical value of the output signals Q and QB changes at time t2 to when the logical value changes again at time t5 is expressed by the following equation (7).

Tx = Td + C1 / I. (Vref-2I.Td/C1) + Td
= C1 · Vref / I = RC1 (7)

  As is clear from Equation (7), the period Tx is determined without depending on the delay time Td.

  Subsequently, since the output signal Q is at the H level and the output signal QB is at the L level, the switches SW1 and SW4 are turned off and the switches SW2 and SW3 are turned on (time t5). Thereby, the voltage Vy1 starts to rise. On the other hand, the voltage Vx1 indicates the ground voltage level (L level). Here, the pulse generator 700 raises the control signal Vctrl in synchronization with the change in the logic value of the output signals Q and QB (time t5). Then, the pulse generator 700 causes the control signal Vctrl to fall after the delay time Td has elapsed (time t6). That is, the pulse generator 700 outputs the control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with the change in the logical value of the output signals Q and QB.

  During the period in which the control signal Vctrl is at the H level (time t5 to t6), the current of the current value 2I flows through the variable current source circuit B1, so that the voltage Vy1 rises at twice the normal speed (slew rate). After the control signal Vctrl falls (time t6 to t8), a current having a normal current value I flows through the variable current source circuit B1, so that the voltage Vy1 increases at a normal speed (slew rate).

  When the voltage Vy1 exceeds the reference voltage Vref (time t7), the comparator 604 raises the comparison result Vy2 with a slight delay. At this time, the comparator 603 outputs an L level comparison result Vx2. Thereby, the RS flip-flop 601 falls the output signal Q and raises the output signal QB (time t8). In other words, when the voltage Vy1 exceeds the reference voltage Vref (time t7), after the elapse of the delay time Td caused by the operation delay of the comparator 604 and the RS flip-flop 601, the output signal Q falls and the output signal QB becomes Stand up (time t8). Such an operation is repeated.

  Here, the period Ty from when the logic value of the output signals Q and QB changes at time t5 to when the output signal Q and QB change again at time t8 is expressed by the following equation with reference to equations (5) to (7). It is expressed as (8). However, C2 shows the capacitance value of the capacitor C2.

Ty = Td + C2 / I. (Vref-2I.Td/C2) + Td
= C2 · Vref / I = RC2 (8)

  As apparent from the equation (8), the period Ty is determined without depending on the delay time Td.

  As described above, the timing of changing the logical values of the output signals Q and QB is determined without depending on the delay time Td. That is, in the oscillation circuit 600, even when the delay time Td generated due to the operation delay of the comparator or the RS flip-flop changes due to the change in temperature or the power supply voltage, the oscillation circuit 600 is not affected by the change in the delay time Td. It is possible to output the frequency output signals (oscillation signals) Q and QB with high accuracy.

  Next, the detailed operation of the pulse generation unit 700 will be described with reference to FIG. FIG. 29 is a timing chart showing the operation of the pulse generator 700. In the example of FIG. 29, at time t0, the output signal Q is H level, the output signal QB is L level, the output signal QD is H level, and the output signal QBD is L level. Therefore, the SW control circuit 705 outputs an H level switching signal S2, outputs L level switching signals S1, S3, and S4, and outputs an L level control signal Vctrl. In this case, since the switch SW1D is turned off and the switch SW2D is turned on, the voltage Ve1 is lowered to the L level. On the other hand, since the switches SW3D and SW4D are both turned off, the node F1 is in a floating state and maintains the L level. (Note that when the above configuration B is adopted, the switch SW3D is turned off and the switch SW4D is turned on, so that the voltage Vf1 of the node F1 is reduced to the L level.) Also, since the switch SW5D is turned off, the node E2 is in a floating state and maintains the voltage level of the initial value voltage Vcl. On the other hand, since the switch SW6D is turned on, the node F2 is precharged to the voltage level of the initial value voltage Vcl. Therefore, the comparators 703 and 704 output L level comparison results Ve3 and Vf3, respectively.

  When the output signal Q falls and the output signal QB rises, the SW control circuit 705 outputs an H level switching signal S3, outputs L level switching signals S1, S2, S4, and an H level control signal Vctrl. Is output (time t2). Thereby, the switch SW3D is turned on and the switch SW4D is turned off, so that the voltage Vf1 starts to rise. On the other hand, since the switches SW1D and SW2D are both turned off, the node E1 enters a floating state and maintains the L level. (Note that when the above configuration B is adopted, the switch SW1D is turned off and the switch SW2D is turned on, so the voltage Ve1 of the node E1 is maintained at the L level.) Also, the output signal Q falls and the output signal QB Rises, the switch SW5D is turned on and the switch SW6D is turned off (time t2). Thereby, the node E2 is precharged to the voltage level of the initial value voltage Vcl. On the other hand, the node F2 enters a floating state and maintains the voltage level of the initial value voltage Vcl.

  Here, the voltage Vf2 increases as the voltage Vf1 increases. More specifically, the node F2 indicates a voltage level obtained by adding an increase of the voltage Vf1 to the initial value voltage Vcl. When the voltage Vf2 rises slightly from the initial value voltage Vcl (near time t2), the comparator 704 raises the comparison result Vf3 with a slight delay. At this time, the comparator 703 outputs an L level comparison result Ve3. Thereby, the RS flip-flop 701 falls the output signal QD and raises the output signal QBD (time t3). In other words, after the voltage Vf2 slightly rises from the initial value voltage Vcl (near time t2), the output signal QD rises after the elapse of the delay time Td caused by the operation delay of the comparator 704 and the RS flip-flop 701. The output signal QBD rises (time t3). Since the initial value voltage Vcl is approximately equal to or slightly lower than the reference voltage Vref, the voltage Vf2 is set to the comparison result Vf3 at the H level immediately after the logical values of the output signals Q and QB change, that is, at time t2. It can be considered that the voltage level has reached a level that can be switched to.

  When the output signal QD falls and the output signal QBD rises, the SW control circuit 705 outputs an H level switching signal S4, outputs L level switching signals S1 to S3, and outputs an L level control signal Vctrl. (Time t3). As a result, the switch SW3D is turned off and the switch SW4D is turned on, so that the voltage Vf1 drops to the L level. Accordingly, the voltage Vf2 also decreases to the level of the initial value voltage Vcl. On the other hand, since the switches SW1D and SW2D are both turned off, the node E1 enters a floating state and maintains the L level. (Note that when the above configuration B is adopted, the switch SW1D is turned off and the switch SW2D is turned on, so that the voltage Ve1 at the node E1 is maintained at the L level.) The voltage Ve2 is also maintained at the level of the initial value voltage Vcl. .

  As described above, the pulse generator 700 raises the control signal Vctrl in synchronization with the logical value change of the output signals Q and QB (time t2), and lowers the control signal Vctrl after the delay time Td has elapsed (time t3). ). That is, the pulse generator 700 outputs the control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with the change in the logical value of the output signals Q and QB.

  Thereafter, when the output signal Q rises and the output signal QD falls, the SW control circuit 705 outputs an H level switching signal S1, outputs L level switching signals S2 to S4, and outputs an H level control signal Vctrl. Is output (time t5). Thereby, the switch SW1D is turned on and the switch SW2D is turned off, so that the voltage Ve1 starts to rise. On the other hand, since the switches SW3D and SW4D are both turned off, the node F1 enters the floating state and maintains the L level. (Note that when the above configuration B is adopted, the switch SW3D is turned off and the switch SW4D is turned on, so that the voltage Vf1 of the node F1 is maintained at the L level.) The output signal Q rises and the output signal QB When falling, the switch SW5D is turned off and the switch SW6D is turned on (time t5). Thereby, the node F2 is precharged to the voltage level of the initial value voltage Vcl. On the other hand, the node E2 is in a floating state and maintains the voltage level of the initial value voltage Vcl.

  Here, the voltage Ve2 increases as the voltage Ve1 increases. More specifically, the node E2 indicates a voltage level obtained by adding an increase of the voltage Ve1 to the initial value voltage Vcl. When the voltage Ve2 rises slightly from the initial value voltage Vcl (near time t5), the comparator 703 raises the comparison result Ve3 with a slight delay. At this time, the comparator 704 outputs an L level comparison result Vf3. Thereby, the RS flip-flop 701 raises the output signal QD and falls the output signal QBD (time t6). In other words, when the voltage Ve2 rises slightly from the initial value voltage Vcl (near time t5), the output signal QD rises after the elapse of the delay time Td caused by the operation delay of the comparator 703 and the RS flip-flop 701, and the output The signal QBD falls (time t6). Since the initial value voltage Vcl is equal to or slightly lower than the reference voltage Vref, the voltage Ve2 is set to the comparison result Ve3 at the H level immediately after the logical values of the output signals Q and QB change, that is, at time t5. It can be considered that the voltage level has reached a level that can be switched to.

  When the output signal QD rises and the output signal QBD falls, the SW control circuit 705 outputs an H level switching signal S2, outputs L level switching signals S1, S3, S4, and an L level control signal Vctrl. Is output (time t6). As a result, the switch SW1D is turned off and the switch SW2D is turned on, so that the voltage Ve1 drops to the L level. Accordingly, the voltage Ve2 decreases to the level of the initial value voltage Vcl. On the other hand, since the switches SW3D and SW4D are both turned off, the node F1 enters the floating state and maintains the L level. (Note that, when the above configuration B is adopted, the switch SW3D is turned off and the switch SW4D is turned on, so that the voltage Vf1 of the node F1 maintains the L level.) The voltage Vf2 also maintains the level of the initial value voltage Vcl. . Such an operation is repeated.

  As described above, the pulse generator 700 raises the control signal Vctrl in synchronization with the change in the logic value of the output signals Q and QB (time t5), and lowers the control signal Vctrl after the delay time Td has elapsed (time t6). ). That is, the pulse generator 700 outputs the control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with the change in the logical value of the output signals Q and QB.

  Here, since the oscillation circuit 600 includes the capacitors C3D and C4D in the pulse generation unit 700, once the nodes E2 and F2 are set to the initial value voltage Vcl, after that, if only the amount changed due to the leakage current is charged. It can be set to the initial value voltage Vcl at high speed and with low power consumption. However, in this configuration, the signals Ve2 and Vf2 of the input nodes E2 and F2 of the comparators 703 and 704 are attenuated by the ratio between the capacitors C3D and C4D and the gate capacitances of the comparators 703 and 704, so that the nodes E1 and F1 are redundant. An error occurs between the rising speeds of the voltages Vx1 and Vy1 of the oscillation circuit 600 and the rising speeds of the voltages Ve1 and Vf1 of the pulse generation unit 700, and accordingly, the oscillation circuit 600 and the pulse generation unit An error occurs in each oscillation frequency of 700. In addition, if the capacitors C3D and C4D are made sufficiently larger than the gate capacities of the comparators 703 and 704 so that the extra charge must be ignored, then the parasitic capacitances of the capacitors C3D and C4D can be ignored. Thus, the gate capacitance of the comparators 703 and 704 or the error of the capacitors C1D and C2D is effectively generated. Therefore, there is a problem that the oscillation circuit 600 cannot accurately generate an oscillation signal having a desired frequency.

  On the other hand, as another configuration of the pulse generation unit 700, a configuration in which the capacitors C3D and C4D and the switches SW2D and SW4D are deleted from the pulse generation unit 700 and the nodes E1 and F1 are directly set to the initial value voltage Vcl can be considered. However, this configuration has a problem that power consumption increases because the initial value generation unit 606 needs to repeatedly charge and discharge the nodes E1 and F1. That is, with the configuration of the oscillation circuit 600, it has been difficult to achieve both improvement in oscillation frequency accuracy and reduction in power consumption.

  Furthermore, since the oscillation circuit 600 needs to include the initial value generation unit 606, there is a problem that the circuit scale increases.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a diagram illustrating a configuration example of a relaxation type oscillation circuit 1 according to the first embodiment. The oscillation circuit 1 according to the present embodiment includes a comparator that performs a comparison operation in the normal operation mode and sets the voltage of the non-inverting input terminal to the reference voltage level in the initial setting mode. As a result, the oscillation circuit 1 according to the present embodiment does not need to be provided with a level shift capacitor in front of the comparator, so that an error in the oscillation frequency of the oscillation circuit and the pulse generation unit can be suppressed and a desired value can be obtained. An oscillation signal having a frequency can be generated with high accuracy. This will be specifically described below.

  An oscillation circuit 1 shown in FIG. 1 includes an RS flip-flop (first RS flip-flop) 11, a charge charge / discharge unit (first charge charge / discharge unit) 12, a comparator (first comparator) 13, and a comparator (second comparator). ) 14, a reference voltage generation unit 15, and a pulse generation unit 10. The RS flip-flop 11, the charge charging / discharging unit 12, the comparators 13 and 14, the reference voltage generating unit 15 and the pulse generating unit 10 are respectively an RS flip-flop 601, a charge charging / discharging unit 602, comparators 603 and 604, and a reference voltage. This corresponds to the generation unit 605 and the pulse generation unit 700.

  The RS flip-flop 11 outputs output signals (first output signals) Q and QB based on input signals (comparison results Vx2 and Vy2) supplied to the input terminals S and R, respectively. Details of the RS flip-flop 11 are the same as those of the RS flip-flop 601, and thus the description thereof is omitted.

  The charge charging / discharging unit 12 is a unit that complementarily charges or discharges the capacitors (first and second capacitors) C1 and C2 based on the output signals Q and QB of the RS flip-flop 11. The rising speed (slew rate) of the voltages Vx1 and Vy1 when the current having the current value 2I flows through the variable current source circuit B1 is the same as that of the voltages Vx1 and Vy1 when the current having the current value I flows through the variable current source circuit B1. It is twice ascending speed (slew rate). The details of the charge / discharge unit 12 are the same as those of the charge / discharge unit 602, and thus the description thereof is omitted.

  The reference voltage generation unit 15 is a unit that generates a reference voltage Vref having a stable voltage level. The reference voltage generation unit 15 includes a constant current source circuit (second constant current source circuit) B3 and an N-channel MOS transistor (hereinafter simply referred to as a transistor) MN1. The transistor MN1 is also referred to as a fifth transistor.

  The input terminal of the constant current source circuit B3 is connected to the power supply voltage terminal VDD, and the output terminal of the constant current source circuit B3 is connected to the node N1. In the transistor MN1, the source is connected to the ground voltage terminal GND, and the drain and gate are connected to the node N1. That is, the transistor MN1 is diode-connected. Then, the reference voltage generation unit 15 outputs the voltage at the node N1 indicating the threshold voltage of the transistor MN1 as the reference voltage Vref.

  In the present embodiment, a case where the constant current source circuit B3 is configured by a P-channel MOS transistor (hereinafter simply referred to as a transistor) MP3 will be described as an example. In the transistor MP3, the source is connected to the power supply voltage terminal VDD, the drain is connected to the node N1, and the bias voltage is supplied to the gate.

  The comparator 13 compares the reference voltage Vref with the voltage Vx1 (first voltage) and outputs a comparison result Vx2 to the node X2. For example, the comparator 13 outputs the comparison result Vx2 of the H level (first logic value) when the voltage Vx1 is greater than the reference voltage Vref, and the L level (second logic value) when the voltage Vx1 is less than or equal to the reference voltage Vref. The comparison result Vx2 (first set signal) is output.

  The comparator 14 compares the reference voltage Vref and the voltage Vy1 (second voltage) and outputs a comparison result Vy2 to the node Y2. For example, the comparator 14 outputs an H level comparison result Vy2 when the voltage Vy1 is greater than the reference voltage Vref, and outputs an L level comparison result Vy2 (first reset signal) when the voltage Vy1 is less than or equal to the reference voltage Vref. To do.

  The pulse generation unit 10 is a unit that generates a control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with changes in the logical values of the output signals Q and QB. In other words, the pulse generator 10 raises the control signal Vctrl in synchronization with changes in the logical values of the output signals Q and QB, and falls after the delay time Td has elapsed.

(Specific configuration example of the pulse generator 10)
FIG. 2 is a diagram illustrating a specific configuration example of the pulse generation unit 10. 2 includes an RS flip-flop (second RS flip-flop) 101, a charge charge / discharge unit (second charge charge / discharge unit) 102, a comparator (third comparator) 103, and a comparator (fourth). Comparator) 104 and SW control circuit (control circuit) 105. The RS flip-flop 101, the charge charging / discharging unit 102, and the comparators 103, 104 correspond to the RS flip-flop 11, the charge charging / discharging unit 12, and the comparators 13, 14, respectively.

  The pulse generator 10 is configured so that the RS flip-flop 11 outputs output signals (oscillation signals) QD and QBD having substantially the same frequency as the output signals Q and QB. In addition, the pulse generator 10 determines that the delay time caused by the operation delay of the comparators 103 and 104 and the RS flip-flop 101 is the delay time Td caused by the operation delay of the comparators 13 and 14 and the RS flip-flop 11. It is comprised so that it may become substantially the same. Therefore, for example, the comparators 103 and 104 and the RS flip-flop 101 have the same configuration as the comparators 13 and 14 and the RS flip-flop 11, respectively.

  The RS flip-flop 101 outputs output signals (second output signals) QD and QBD based on input signals (comparison results Ve3 and Vf3) supplied to the input terminals S and R, respectively. Details of the RS flip-flop 101 are the same as in the case of the RS flip-flop 701, and a description thereof will be omitted.

  The SW control circuit 105 outputs switching signals S1 and S3 and a control signal Vctrl based on the output signals QD and QBD of the RS flip-flop 11 and the output signals Q and QB of the RS flip-flop 11. The details of the SW control circuit 105 are the same as in the case of the SW control circuit 705, and thus the description thereof is omitted.

  The charge charging / discharging unit 102 is a unit that charges or discharges the capacitors C1D and C2D in a complementary manner based on the switching signals S1 and S3 from the SW control circuit 105. The charge / discharge unit 102 includes a constant current source circuit (third constant current source circuit) B1D for supplying a constant current, switches SW1D and SW3D, and capacitors (third and fourth capacitors) C1D and C2D. That is, the charge / discharge unit 102 does not have the switches SW2D and SW4D as compared with the charge charge / discharge unit 702. Since the other circuit configuration of the charge / discharge unit 102 is the same as that of the charge / discharge unit 702, description thereof is omitted.

  In the normal operation mode, the comparator 103 compares the reference voltage Vref with the voltage Ve1 (third voltage) of the node E1 and outputs a comparison result Ve3 (second set signal) to the node E3. For example, the comparator 103 outputs an H level comparison result Ve3 when the voltage Ve1 is higher than the reference voltage Vref, and outputs an L level comparison result Ve3 when the voltage Ve1 is equal to or lower than the reference voltage Vref. Further, in the initial setting mode, the comparator 103 sets the voltage level of the non-inverting input terminal to the level of the reference voltage Vref and sets the voltage level of the output terminal to the ground voltage level (L level).

  In the normal operation mode, the comparator 104 compares the reference voltage Vref and the voltage Vf1 (fourth voltage) of the node F1 and outputs a comparison result Vf3 (second reset signal) to the node F3. For example, the comparator 104 outputs an H level comparison result Vf3 when the voltage Vf1 is greater than the reference voltage Vref, and outputs an L level comparison result Vf3 when the voltage Vf1 is equal to or lower than the reference voltage Vref. Further, in the initial setting mode, the comparator 104 sets the voltage level of the non-inverting input terminal to the level of the reference voltage Vref and sets the voltage level of the output terminal to the ground voltage level (L level).

(Specific configuration example of the comparators 103 and 104)
FIG. 3 is a diagram illustrating a specific configuration example of the comparator 103. The comparator 103 shown in FIG. 3 includes P-channel MOS transistors (hereinafter simply referred to as transistors) MP11 and MP12, N-channel MOS transistors (hereinafter simply referred to as transistors) MN11 and MN12, switches SW11 to SW13, and a constant current. Source circuit (first constant current source circuit) B2.

  The transistors MP11 and MP12 are also referred to as first and second transistors, respectively. The transistors MN11 and MN12 are also referred to as third and fourth transistors, respectively. The switches SW11 to SW13 are also referred to as first to third transistors, respectively.

  The input terminal of the constant current source circuit B2 is connected to the power supply voltage terminal VDD, and the output terminal of the constant current source circuit B2 is connected to the node N12. In the transistor MP11, the source is connected to the node N12, the drain is connected to the node N11, and the gate is connected to the non-inverting input terminal of the comparator 103. In the transistor MN11, the source is connected to the ground voltage terminal GND, and the drain and gate are connected to the node N11. In the transistor MP12, the source is connected to the node N12, the drain is connected to the node N13 via the switch SW12, and the gate is connected to the inverting input terminal of the comparator 103. In the transistor MN12, the source is connected to the ground voltage terminal GND, the drain is connected to the node N13, and the gate is connected to the node N11. Further, a switch SW11 is provided between the gate of the transistor MP11 (non-inverting input terminal of the comparator 103) and the node N11. A switch SW13 is provided between the node N13 and the ground voltage terminal GND. On / off of the switch SW12 is controlled by the switching signal S1. On / off of the switches SW11 and SW13 is controlled by an inverted signal of the switching signal S1.

  In the present embodiment, an example will be described in which the constant current source circuit B2 is a P-channel MOS transistor (transistor) MP2. In the transistor MP2, the source is connected to the power supply voltage terminal VDD, the drain is connected to the node N12, and a bias voltage is supplied to the gate. In the present embodiment, the size ratio of the transistor MN11 and the transistor MN1 in the reference voltage generation unit 15 is equal to the size ratio of the transistor MP2 constituting the constant current source circuit B2 and the transistor MP3 constituting the constant current source circuit B3. The case where they are substantially the same will be described as an example.

  For example, when the switching signal S1 is at the H level (in the normal operation mode), the switch SW12 is turned on and the switches SW11 and SW13 are turned off. Thereby, the comparator 103 performs a normal comparison operation. Specifically, the comparator 103 outputs an H level comparison result Ve3 when the voltage Ve1 is higher than the reference voltage Vref, and outputs an L level comparison result Ve3 when the voltage Ve1 is equal to or lower than the reference voltage Vref. On the other hand, when the switching signal S1 is at the L level (in the initial setting mode), the switch SW12 is turned off and the switches SW11 and SW13 are turned on. Thereby, the comparator 103 sets the voltage level of the non-inverting input terminal to the voltage level of the node N11 and sets the voltage level of the output terminal to the ground voltage level (L level).

  Here, as described above, the size ratio of the transistor MN11 and the transistor MN1 in the reference voltage generation unit 15 is equal to the size ratio of the transistor MP2 constituting the constant current source circuit B2 and the transistor MP3 constituting the constant current source circuit B3. It is almost the same. Therefore, in the initial setting mode, the voltage at the node N11 and the voltage at the node N1 (reference voltage Vref) are substantially the same. Thereby, in the initial setting mode, the comparator 103 sets the voltage level of the non-inverting input terminal to the level of the reference voltage Vref, and sets the voltage level of the output terminal to the ground voltage level (L level).

  The specific configuration of the comparator 104 is the same as that of the comparator 103. However, in the comparator 104, ON / OFF of the switch SW12 is controlled by the switching signal S3, and ON / OFF of the switches SW11, SW13 is controlled by an inverted signal of the switching signal S3.

  The specific configuration of each comparator 13, 14 is preferably the same as that of the comparator 103. However, in this case, both the comparators 13 and 14 need to be controlled so as to always operate in the normal operation mode. In the present embodiment, a case where the specific configuration of each of the comparators 13 and 14 is the same as that of the comparator 103 will be described as an example.

  Further, in the transistors MP11 and MP12 constituting the input differential pair, the size (W / L ratio) of the transistor MP11 connected to the non-inverting input terminal (positive side terminal) is connected to the inverting input terminal (negative side terminal). Further, it is preferable to be configured to be larger than the size of the transistor MP12.

  For example, when the sizes of the transistors MP11 and MP12 are the same, the comparators 13 and 14 have already started to raise the comparison results Vx2 and Vy2 when the voltages Vx1 and Vy1 reach the reference voltage Vref. That is, the comparison results Vx2 and Vy2 indicate intermediate potentials. On the other hand, the comparators 103 and 104 provided in the pulse generator 10 still maintain the comparison results Ve3 and Vf3 at the ground voltage level when the initial setting mode is shifted to the normal operation mode. For this reason, the delay time caused by the operation delay of the comparators 13 and 14 and the RS flip-flop 11 is different from the delay time caused by the operation delay of the comparators 103 and 104 and the RS flip-flop 101. As a result, the frequency accuracy of the oscillation signal may be reduced.

  On the other hand, when the size of the transistor MP11 is larger than the size of the transistor MP12, the rise of the comparison results Vx2 and Vy2 is delayed. Thereby, the comparators 13 and 14 can keep the comparison results Vx2 and Vy2 close to the ground voltage level even when the voltages Vx1 and Vy1 reach the reference voltage Vref. Thereby, an error between the delay time caused by the operation delay of the comparators 13 and 14 and the RS flip-flop 11 and the delay time caused by the operation delay of the comparators 103 and 104 and the RS flip-flop 101 is suppressed. As a result, a decrease in frequency accuracy of the oscillation signal is suppressed.

(Timing chart)
Subsequently, the operation of the oscillation circuit 1 will be described with reference to FIGS. 4 and 5. FIG. 4 is a timing chart showing the operation of the oscillation circuit 1. FIG. 5 is a timing chart showing the operation of the pulse generator 10 provided in the oscillation circuit 1. Note that the timing chart of the oscillation circuit 1 illustrated in FIG. 4 is the same as the timing chart of the oscillation circuit 600 illustrated in FIG. Therefore, the detailed operation of the pulse generator 10 will be described below with reference to FIG.

  In the example of FIG. 5, at time t0, the output signal Q is H level, the output signal QB is L level, the output signal QD is H level, and the output signal QBD is L level. Therefore, the SW control circuit 105 outputs the L level switching signals S1 and S3 and the L level control signal Vctrl.

  At this time, the switch SW1D is turned off by the L level switching signal S1. Further, in response to the L level switching signal S1, the comparator 103 sets the voltage Ve1 of the non-inverting input terminal (node E1) to the level of the reference voltage Vref and sets the voltage Ve3 of the output terminal (node E3) to the ground voltage level ( L level). On the other hand, the switch SW3D is turned off by the L level switching signal S3. Further, in response to the L level switching signal S3, the comparator 104 sets the voltage Vf1 of the non-inverting input terminal (node F1) to the level of the reference voltage Vref and sets the voltage Vf3 of the output terminal (node F3) to the ground voltage level ( L level).

  When the output signal Q falls and the output signal QB rises, the SW control circuit 105 outputs an L level switching signal S1, an H level switching signal S3, and an H level control signal Vctrl (time t2).

  At this time, the switch SW3D is turned on by the rise of the switching signal S3, and the comparator 104 shifts from the initial setting mode to the normal operation mode. Thereby, the voltage Vf1 starts to rise from the level of the reference voltage Vref. The comparator 104 raises the comparison result Vf3 as the voltage Vf1 increases. On the other hand, since the switching signal S1 remains at the L level, the voltage Ve1 maintains the level of the reference voltage Vref, and the voltage Ve3 maintains the L level. Thereby, the RS flip-flop 101 falls the output signal QD and raises the output signal QBD (time t3). In other words, after the voltage Vf1 starts to rise (time t2), after the elapse of the delay time Td caused by the operation delay of the comparator 104 and the RS flip-flop 101, the output signal QD falls and the output signal QBD becomes Stand up (time t3).

  When the output signal QD falls and the output signal QBD rises, the SW control circuit 105 outputs the L level switching signals S1 and S3 and the L level control signal Vctrl (time t3).

  At this time, the switch SW3D is turned off by the fall of the switching signal S3, and the comparator 104 shifts from the normal operation mode to the initial setting mode. Thereby, the comparator 104 sets the voltage Vf1 of the non-inverting input terminal (node F1) to the level of the reference voltage Vref, and sets the voltage Vf3 of the output terminal (node F3) to the ground voltage level (L level). On the other hand, since the switching signal S1 remains at the L level, the voltage Ve1 maintains the level of the reference voltage Vref, and the voltage Ve3 maintains the L level.

  In this way, the pulse generator 10 raises the control signal Vctrl in synchronization with the change in the logical value of the output signals Q and QB (time t2), and lowers the control signal Vctrl after the delay time Td has elapsed (time). t3). That is, the pulse generator 10 outputs the control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with the change in the logical value of the output signals Q and QB.

  Thereafter, when the output signal Q rises and the output signal QD falls, the SW control circuit 105 outputs an H level switching signal S1, an L level switching signal S3, and an H level control signal Vctrl (time t5). .

  At this time, the switch SW1D is turned on by the rising edge of the switching signal S1, and the comparator 103 shifts from the initial setting mode to the normal operation mode. As a result, the voltage Ve1 starts to rise from the level of the reference voltage Vref. The comparator 103 raises the comparison result Ve3 as the voltage Ve1 increases. On the other hand, since the switching signal S3 remains at the L level, the voltage Vf1 maintains the level of the reference voltage Vref, and the voltage Vf3 maintains the L level. Thereby, the RS flip-flop 101 raises the output signal QD and falls the output signal QBD (time t6). In other words, after the voltage Ve1 starts to rise (time t5), the output signal QD rises and the output signal QBD rises after the delay time Td caused by the operation delay of the comparator 103 and the RS flip-flop 101 has elapsed. Decrease (time t6).

  When the output signal QD rises and the output signal QBD falls, the SW control circuit 105 outputs the L level switching signals S1 and S3 and the L level control signal Vctrl (time t6).

  At this time, the switch SW1D is turned off by the fall of the switching signal S1, and the comparator 103 shifts from the normal operation mode to the initial setting mode. Thereby, the comparator 103 sets the voltage Ve1 of the non-inverting input terminal (node E1) to the level of the reference voltage Vref and sets the voltage Ve3 of the output terminal (node E3) to the ground voltage level (L level). On the other hand, since the switching signal S3 remains at the L level, the voltage Vf1 maintains the level of the reference voltage Vref, and the voltage Vf3 maintains the L level. Such an operation is repeated.

  In this way, the pulse generation unit 10 raises the control signal Vctrl in synchronization with the change in the logical value of the output signals Q and QB (time t5), and lowers the control signal Vctrl after the delay time Td has elapsed (time). t6). That is, the pulse generator 10 outputs the control signal Vctrl having a pulse width substantially the same as the delay time Td in synchronization with the change in the logical value of the output signals Q and QB.

  In the example of FIG. 5, the comparator 103 operates in the normal operation mode during the period during which the capacitor C1D is charged (first period), and enters the initial setting mode during the other period (second period). Works. In addition, the comparator 104 operates in the normal operation mode during the period during which the capacitor C2D is charged (third period), and operates in the initial setting mode during the other period (fourth period).

  As described above, the oscillation circuit 1 according to the present embodiment includes the comparator that performs the comparison operation in the normal operation mode and sets the voltage of the non-inverting input terminal to the reference voltage level in the initial setting mode. As a result, the oscillation circuit 1 according to the present embodiment does not need to include a level shift capacitor in front of the comparator, so that the rising speeds of the voltages Vx1, Vy1 and the rising speeds of the voltages Ve1, Vf1 of the oscillation circuit 1 are eliminated. The oscillation signal having a desired frequency can be generated with high accuracy by suppressing the error between the oscillation frequency and the oscillation frequency of the oscillation circuit and the pulse generation unit. In addition, since the oscillation circuit 1 according to the present embodiment does not need to repeatedly charge and discharge the nodes E1 and F1 by the initial value generation unit, an increase in power consumption can be suppressed. That is, the oscillation circuit 1 according to the present embodiment can realize both improvement in the oscillation frequency accuracy and reduction in power consumption.

  Furthermore, since the oscillation circuit 1 according to the present embodiment does not need to include an initial value generation unit, an increase in circuit scale can be suppressed.

  Furthermore, since the oscillation circuit 1 according to the present embodiment can operate without being subjected to suppression of fluctuations in the delay time Td from the initial stage of oscillation (for example, the first cycle), it can oscillate the output signals Q and QB. It can be stabilized at high speed. Thereby, the oscillation circuit 1 according to the present embodiment can repeatedly execute and stop the operation efficiently, for example.

  Although the case where the reference voltage generation unit 15 includes the constant current source circuit B3 and the transistor MN1 has been described as an example in the present embodiment, the present invention is not limited thereto. The reference voltage generation unit 15 can be appropriately changed to a configuration further including a P-channel MOS transistor corresponding to the transistor MP11 between the constant current source circuit B3 and the transistor MN1. Thereby, the voltage level of the node N11 in the initial setting mode can be made closer to the level of the reference voltage Vref.

<Embodiment 2>
FIG. 6 is a diagram illustrating a configuration example of the relaxation type oscillation circuit 2 according to the second embodiment. The oscillation circuit 2 illustrated in FIG. 6 includes a pulse generation unit 20 instead of the pulse generation unit 10 as compared with the oscillation circuit 1 illustrated in FIG.

  FIG. 7 is a diagram illustrating a specific configuration example of the pulse generation unit 20. The pulse generation unit 20 illustrated in FIG. 7 includes an RS flip-flop 101, a charge charge / discharge unit 202, a comparator 103, a comparator 104, a SW control circuit 205, and capacitors C3D and C4D. The RS flip-flop 101, the charge charging / discharging unit 202, and the comparators 103, 104 correspond to the RS flip-flop 11, the charge charging / discharging unit 12, and the comparators 13, 14, respectively.

  The SW control circuit 205 outputs switching signals S1 to S4 and a control signal Vctrl based on the output signals QD and QBD of the RS flip-flop 101 and the output signals Q and QB of the RS flip-flop 11. The details of the SW control circuit 205 are the same as in the case of the SW control circuit 705, and thus the description thereof is omitted.

  The charge charging / discharging unit 202 is a unit that charges or discharges the capacitors C1D and C2D in a complementary manner based on switching signals S1 to S4 from the SW control circuit 205. The charge / discharge unit 202 includes a constant current source circuit B1D that allows a constant current to flow, switches SW1D to SW4D, and capacitors C1D and C2D. The details of the charge / discharge unit 202 are the same as in the case of the charge / discharge unit 702, and thus the description thereof is omitted.

  In the case of the charge charging / discharging unit 202, as in the case of the charge charging / discharging unit 702, the switches SW1D to SW4D are switched to the switching signal S1, the inverted signal of the switching signal S1, the switching signal S3, and the inverted signal of the switching signal S3, respectively. The structure controlled based on may be sufficient.

  The capacitor C3D is provided between the node E1 and the node E2. Capacitor C4D is provided between nodes F1 and F2. In the normal operation mode, the comparator 103 compares the reference voltage Vref and the voltage Ve2 at the node E2, and outputs a comparison result Ve3 to the node E3. The comparator 104 compares the reference voltage Vref with the voltage Vf2 at the node F2 and outputs the comparison result Vf3 to the node F3 in the normal operation mode.

  The other configuration of the pulse generation unit 20 is the same as that of the pulse generation unit 10, and thus the description thereof is omitted.

(Timing chart)
Next, the operation of the oscillation circuit 2 will be described. FIG. 8 is a timing chart showing the operation of the pulse generator 20 provided in the oscillation circuit 2.

  In the pulse generator 700, the switches SW5D and SW6D are alternately turned on and off, so that the voltages Ve2 and Vf2 of the nodes E2 and F2 are alternately set to the level of the initial value voltage Vcl (see FIG. 29). On the other hand, in the pulse generation unit 20, the comparators 103 and 104 alternately shift to the initial setting mode, whereby the voltages Ve2 and Vf2 of the nodes E2 and F2 are alternately set to the level of the reference voltage Vref (see FIG. 8). ). Since other operations of the oscillation circuit 2 are the same as those of the oscillation circuit 600, description thereof is omitted.

  Thereby, the oscillation circuit 2 according to the present embodiment can achieve the same effect as the oscillation circuit 1 according to the first embodiment. Here, since the oscillation circuit 2 according to the present embodiment includes the capacitors C3D and C4D, once the nodes E2 and F2 are set to the initial value voltage Vcl, only the amount changed by the leakage current is charged thereafter. The initial value voltage Vcl can be set at high speed and with low power consumption. As described above, the oscillation circuit 2 according to the present embodiment can reduce the bias current of the comparators 103 and 104, and is therefore particularly suitable when low power consumption is required.

<Embodiment 3>
FIG. 9 is a diagram illustrating a configuration example of a part of the relaxation type oscillation circuit 3 according to the third embodiment. Compared with the oscillation circuit 1 shown in FIG. 1, the oscillation circuit 3 shown in FIG. 9 includes comparators 33 and 34 instead of the comparators 13 and 14, and a comparator 303 instead of the comparators 103 and 104 in the pulse generation unit 10. , 304.

  A specific configuration example of each of the comparators 33, 34, 303, and 304 will be described. Since these comparators have the same configuration in this example, a specific configuration example of the comparator 33 will be described below as a representative.

  FIG. 10 is a diagram illustrating a specific configuration example of the comparator 33. Compared to the comparator 13, the comparator 33 shown in FIG. 10 further includes a switch (fourth switch) SW31 between the constant current source circuit B2 and the transistors MP11 and MP12. Since the other configuration of the comparator 33 is the same as that of the comparator 13, the description thereof is omitted.

  Note that the switch SW31 provided in each of the comparators 303 and 304 is always controlled to be on. On the other hand, on / off of the switch SW31 provided in the comparator 33 is controlled by the output signal QB of the RS flip-flop 11. On / off of the switch SW31 provided in the comparator 34 is controlled by the output signal Q of the RS flip-flop 11.

  FIG. 11 is a timing chart showing the operation of the oscillation circuit 3. As shown in FIG. 11, the switch SW31 in the comparator connected to the discharged capacitor among the comparators 33 and 34 is controlled to be off. In other words, of the comparators 33 and 34, the comparator connected to the discharged capacitor stops operating. Thereby, power consumption is further reduced.

<Embodiment 4>
FIG. 12 is a diagram illustrating a configuration example of the relaxation type oscillation circuit 4 according to the fourth embodiment. Compared with the oscillation circuit 1 shown in FIG. 1, the oscillation circuit 4 shown in FIG. 12 generates an oscillation signal using one charge / discharge path and one comparator instead of two charge / discharge paths and two comparators. ing. This will be specifically described below.

  The oscillation circuit 4 shown in FIG. 12 includes a pulse generation unit 40, a frequency divider 41, a charge / discharge unit (first charge charge / discharge unit) 42, a comparator (first comparator) 43, and a pulse width adjustment unit ( First pulse width adjustment unit) 44. The charge / discharge unit 42 includes a variable current source circuit B4, a switch SW7, and a capacitor (first capacitor) C5. The pulse generation unit 40 includes a charge charging / discharging unit (second charge charging / discharging unit) 402, a comparator (second comparator) 403, a pulse width adjusting unit (second pulse width adjusting unit) 404, a control circuit 405, Have The charge / discharge unit 402 includes a constant current source circuit B4D, a switch SW7D, and a capacitor C5D. In the present embodiment, a case where both the comparators 43 and 403 have the same configuration as that shown in FIG. 3 will be described as an example. In this case, the comparator 43 is controlled so as to always operate in the normal operation mode.

  In the variable current source circuit B4, the input terminal is connected to the power supply voltage terminal VDD, and the output terminal is connected to the node G1. In the switch SW7, one end is connected to the node G1, and the other end is connected to the ground voltage terminal GND. In the capacitor C5, one end is connected to the node G1, and the other end is connected to the ground voltage terminal GND. The on / off state of the switch SW7 is controlled based on the signal Vrst1 output from the pulse width adjustment unit 44.

  For example, when the signal Vrst1 is at L level, the switch SW7 is turned off. In this case, electric charge is gradually accumulated at one end (node G1 side) of the capacitor C5 due to the current flowing through the variable current source circuit B4. Thereby, the voltage Vg1 (first voltage) of the node G1 gradually increases. On the other hand, when the signal Vrst1 is at the H level, the switch SW7 is turned on. In this case, the electric charge stored at one end (node G1 side) of the capacitor C5 is released. Thereby, the voltage Vg1 rapidly decreases to the ground voltage level (L level). Thus, the capacitor C5 is charged or discharged by the signal Vrst1.

  Further, the variable current source circuit B4 flows a current corresponding to the control signal Vctrl output from the pulse generation unit 40. For example, when the control signal Vctrl is at L level, a current having a current value I flows through the variable current source circuit B4. On the other hand, when the control signal Vctrl is at the H level, a current having a current value 2I (twice the current value I) flows through the variable current source circuit B4. The rising speed (slew rate) of the voltage Vg1 when the current having the current value 2I flows through the variable current source circuit B4 is equal to the rising speed (through) of the voltage Vg1 when the current having the current value I flows through the variable current source circuit B4. Rate).

  The comparator 43 compares the reference voltage Vref and the voltage Vg1 of the node G1, and outputs a comparison result Vg2 (first comparison result) to the node G2. For example, the comparator 43 outputs an H level comparison result Vg2 when the voltage Vg1 is higher than the reference voltage Vref, and outputs an L level comparison result Vg2 when the voltage Vg2 is equal to or lower than the reference voltage.

  The pulse width adjustment unit 44 adds a delay larger than the rise to the fall of the comparison result Vg2, and outputs the result as a signal (first trigger signal) Vrst1. The frequency divider 41 changes the logic value of the clock signal (first output signal) CLK in synchronization with the rise of the signal Vrst1.

  The pulse generator 40 generates a control signal Vctrl having substantially the same pulse width as the delay time Td in synchronization with the falling edge of the signal Vrst1. In other words, the pulse generator 40 raises the control signal Vctrl in synchronization with the fall of the signal Vrst1, and falls after the delay time Td has elapsed. Details will be described below.

  In the charge / discharge unit 402, in the constant current source circuit B4D, the input terminal is connected to the power supply voltage terminal VDD, and the output terminal is connected to one end of the switch SW7D. The other end of the switch SW7D is connected to the node P1. Capacitor C5D has one end connected to node P1 and the other end connected to ground voltage terminal GND. The on / off state of the switch SW7D is controlled based on the control signal Vctrl.

  In the normal operation mode, the comparator 403 compares the reference voltage Vref and the voltage Vp1 of the node P1, and outputs a comparison result Vp2 (second comparison result) to the node P2. For example, the comparator 403 outputs an H level comparison result Vp2 (second voltage) when the voltage Vp1 is greater than the reference voltage Vref, and outputs an L level comparison result Vp2 when the voltage Vp1 is equal to or lower than the reference voltage Vref. . Further, in the initial setting mode, the comparator 403 sets the voltage level of the non-inverting input terminal to the level of the reference voltage Vref and sets the voltage level of the output terminal to the ground voltage level (L level). In this embodiment, an example will be described in which the comparator 403 shifts to the initial setting mode when the control signal Vctrl is at the L level and shifts to the normal operation mode when the control signal Vctrl is at the H level.

  For example, when the control signal Vctrl is at the H level, the switch SW7D is turned on and the comparator 403 shifts to the normal operation mode. In this case, electric charge is gradually accumulated at one end (node P1 side) of the capacitor C5D by the current flowing through the constant current source circuit B4D. Thereby, the voltage Vp1 of the node P1 gradually increases. On the other hand, when the control signal Vctrl is at the L level, the switch SW7D is turned off, and the comparator 403 shifts to the initial setting mode. In this case, the electric charge stored at one end (node P1 side) of the capacitor C5D is released. As a result, the voltage Vp1 rapidly decreases to the level of the reference voltage Vref. Thus, the capacitor C5D is charged or discharged by the control signal Vctrl.

  The pulse width adjustment unit 404 adds a delay larger than the falling to the rising edge of the comparison result Vp2, and outputs it as a signal (second trigger signal) Vrst2. The pulse width adjusting unit 404 adds a delay to the rising edge of the comparison result Vp2 in response to the pulse width adjusting unit 44 adding a delay to the falling edge of the comparison result Vg2. Therefore, when the falling delay of the comparison result Vg2 does not affect the frequency of the clock signal CLK, the pulse width adjustment unit 404 may not be provided.

  The control circuit 405 generates a control signal Vctrl based on the signals Vrst1 and Vrst2. Specifically, the control circuit 405 raises the control signal Vctrl in synchronization with the fall of the signal Vrst1 after the delay time Ta elapses after the signal Vrst1 rises, and outputs the control signal Vctrl in synchronization with the rise of the signal Vrst2. Fall down.

(Specific configuration example of the pulse width adjustment unit 44)
FIG. 13A is a diagram illustrating a specific configuration example of the pulse width adjustment unit 44. The pulse width adjustment unit 44 illustrated in FIG. 13A includes inverters IV0 to IV5 and NAND circuits (hereinafter simply referred to as NAND circuits) ND1 to ND4.

  The inverter IV0 outputs an inverted signal of an external input signal (comparison result Vg2). NAND circuit ND1 outputs a negative logical product of the output signals of inverter IV0. Inverter IV1 outputs an inverted signal of the output of NAND circuit ND1. NAND circuit ND2 outputs a negative logical product of the outputs of inverters IV0 and IV1. Inverter IV2 outputs an inverted signal of the output of NAND circuit ND2. NAND circuit ND3 outputs a negative logical product of the outputs of inverters IV0 and IV2. Inverter IV3 outputs an inverted signal of the output of NAND circuit ND3. NAND circuit ND4 outputs a negative logical product of the outputs of inverters IV0 and IV3. Inverter IV4 outputs an inverted signal of the output of NAND circuit ND4. Then, inverter IV5 outputs an inverted signal (signal Vrst1) of the output of inverter IV4 to the outside.

  With such a circuit configuration, the pulse width adjustment unit 44 outputs little delay with respect to the rising edge of the input signal and adds a large delay with respect to the falling edge of the input signal. Note that the number of stages of logic gates can be arbitrarily changed. Further, the pulse width adjustment unit 44 can be appropriately changed to another circuit configuration capable of realizing a function equivalent to the circuit shown in FIG. 13A.

(Specific configuration example of the pulse width adjustment unit 404)
FIG. 13B is a diagram illustrating a specific configuration example of the pulse adjustment unit 404. The pulse width adjustment unit 404 illustrated in FIG. 13B includes inverters INV6 and INV7 on the input side and the output side of the configuration of the pulse width adjustment unit 44, respectively.

  With such a circuit configuration, the pulse width adjustment unit 404 adds little delay to the falling edge of the input signal and outputs a large delay to the rising edge of the input signal. Note that the number of stages of logic gates can be arbitrarily changed. Further, the pulse width adjustment unit 404 can be appropriately changed to another circuit configuration capable of realizing a function equivalent to the circuit illustrated in FIG. 13B.

  When the influence of the delays of the inverters INV6 and INV7 cannot be ignored in the pulse width adjustment unit 404 shown in FIG. 13B, the inverters INV5 and INV7 on the output side of the pulse width adjustment unit 404 may be deleted.

(Specific configuration example of the control circuit 405)
FIG. 14 is a diagram illustrating a specific configuration example of the control circuit 405. The control circuit 405 illustrated in FIG. 14 includes an RS flip-flop FF1 and a negative OR circuit (hereinafter simply referred to as a NOR circuit) NR1.

  The RS flip-flop FF1 outputs an intermediate signal QM from the output terminal Q based on the signal Vrst2 supplied to the input terminal S and the signal Vrst1 supplied to the input terminal R. The NOR circuit NR1 outputs a negative logical sum of the intermediate signal QM and the signal Vrst1 as a control signal Vctrl.

(Timing chart)
Next, the operation of the oscillation circuit 4 will be described with reference to FIG. FIG. 15 is a timing chart showing the operation of the oscillation circuit 4. In the following description, it is assumed that the pulse width adjustment unit 44 outputs the input signal without adding a delay, and adds the delay of the delay time Ta to the falling of the input signal. Here, the description will be made assuming that the pulse width adjusting unit 404 outputs the input signal without adding a delay, and adds the delay of the delay time Ta to the rising of the input signal.

  In the example of FIG. 15, at time t0, the signals Vrst1 and Vrst2 indicate the L level, and the control signal Vctrl indicates the L level. Therefore, the switch SW7 is turned off, and a current having a current value I flows through the variable current source circuit B4. As a result, the voltage Vg1 continues to rise. Further, the switch SW7D is turned off, and the comparator 403 has shifted to the initial setting mode. Thereby, the voltage Vp1 indicates the reference voltage Vref level.

  When the voltage Vg1 exceeds the reference voltage Vref (time t1), the comparator 43 raises the comparison result Vg2 with a little delay (time t2). In other words, when the voltage Vg1 exceeds the reference voltage Vref (time t1), the comparison result Vg2 rises after the elapse of the delay time Td caused by the operation delay of the comparator 43 (time t2). The pulse width adjustment unit 44 raises the signal Vrst1 almost simultaneously with the rise of the comparison result Vg2 (time t2). When the signal Vrst1 rises, the frequency divider 41 raises the clock signal CLK (time t2).

  Further, when the signal Vrst1 rises, the switch SW7 is switched from OFF to ON (time t2). Thereby, the voltage Vg1 rapidly decreases to the ground voltage level. Since the voltage Vg1 falls below the reference voltage Vref level, the comparator 43 causes the comparison result Vg2 to fall (near time t2). The pulse width adjustment unit 44 causes the signal Vrst1 to fall after the delay time Ta has elapsed from the fall of the comparison result Vg2 (time t3). As a result, the switch SW7 switches from on to off again after the voltage Vg1 has completely dropped to the ground voltage level. Thus, by expanding the pulse width of the signal Vrst1 using the pulse width adjustment unit 44, it is possible to prevent the voltage Vg1 from starting to rise before it completely decreases to the ground voltage level.

  When the signal Vrst1 falls, the control circuit 405 raises the control signal Vctrl in synchronization with the signal Vrst1 (time t3). When the control signal Vctrl rises, the switch SW7D is turned on, and the comparator 403 shifts from the initial setting mode to the normal operation mode. Thereby, the voltage Vp1 starts to rise from the reference voltage Vref level (time t3). A current I flows through the constant current source circuit B4D. The comparator 403 raises the comparison result Vp2 as the voltage Vp1 rises (time t4). In other words, the comparison result Vp2 rises (time t4) after the delay time Td caused by the operation delay of the comparator 403 has elapsed after the voltage Vp1 starts to rise (time t3). The pulse width adjustment unit 404 raises the signal Vrst2 after the delay time Ta has elapsed from the rise of the comparison result Vp2 (time t4). When the signal Vrst2 rises, the control circuit 405 causes the control signal Vctrl to fall (time t4). That is, the pulse generator 40 outputs the control signal Vctrl having a pulse width of time Td + Ta in synchronization with the falling of the signal Vrst1.

  During the period in which the control signal Vctrl is at the H level (time t3 to t4), the current of the current value 2I flows through the variable current source circuit B4, so that the voltage Vg1 rises at twice the normal speed (slew rate). After the control signal Vctrl falls (time t4 to t6), since the current of the current value I flows through the variable current source circuit B4, the voltage Vg1 rises at a normal speed (slew rate). Further, after the control signal Vctrl falls (time t4 to t6), the switch SW7D is turned off, and the comparator 403 shifts to the initial setting mode. Therefore, the voltage Vp1 indicates the reference voltage Vref level. Therefore, the comparison result Vp2 and the signal Vrst2 indicate L level.

  After time t5, the operations from time t1 to time t5 are repeated.

  As described above, the oscillation circuit 4 according to the present embodiment, like the oscillation circuit 1 according to the first embodiment, accurately outputs the clock signal CLK having a desired frequency without being affected by the variation in the delay time Td. Can be output. Here, since the oscillation circuit 4 according to the present embodiment can generate the clock signal CLK using a small number of charge / discharge paths and comparators, an increase in power consumption and an increase in circuit scale can be suppressed.

  In addition, the oscillation circuit 4 according to the present embodiment performs the comparison operation in the normal operation mode, and the voltage of the non-inverting input terminal is set to the reference voltage level in the initial setting mode, like the oscillation circuit 1 according to the first embodiment. The pulse generator is provided with a comparator to be set. As a result, the oscillation circuit 4 according to the present embodiment does not need to include a level shift capacitor in the previous stage of the comparator, and therefore, between the rising speed of the voltage Vg1 and the rising speed of the voltage Vp1 of the oscillation circuit 4 Thus, an oscillation signal having a desired frequency can be generated with high accuracy (inhibiting errors in the oscillation frequencies of the oscillation circuit and the pulse generation unit). In addition, since the oscillation circuit 4 according to the present embodiment does not need to repeatedly charge and discharge the node P1 by the initial value generation unit, an increase in power consumption can be suppressed. That is, the oscillation circuit 4 according to the present embodiment can realize both improvement in the oscillation frequency accuracy and reduction in power consumption.

  Furthermore, since the oscillation circuit 4 according to the present embodiment does not need to include an initial value generation unit, an increase in circuit scale can be suppressed.

  Since the oscillation circuit 4 according to the present embodiment has a configuration in which mismatch between comparators and capacitors does not occur in principle, the clock signal CLK with a duty ratio of 50% can be output with high accuracy. Note that the delay time Ta of the delay added by the pulse width adjustment unit is negligibly small compared to the delay time Td caused by the operation delay of the comparator.

(Modification of the oscillation circuit 4)
FIG. 16 is a diagram showing a modification of the oscillation circuit 4 as the oscillation circuit 4a. Compared with the oscillation circuit 4 shown in FIG. 12, the oscillation circuit 4a shown in FIG. 16 includes general comparators 46 and 406 instead of the comparators 43 and 403 capable of mode switching. Accordingly, the oscillation circuit 4a shown in FIG. 16 further includes switches SW8D and SW9D and a capacitor C6D. This will be specifically described below.

  The switch SW8D is provided between the node P1 and the ground voltage terminal GND. Capacitor C6D is provided between node P1 and the non-inverting input terminal of comparator 406. The switch SW9D is provided between the non-inverting input terminal of the comparator 406 and the initial value voltage input terminal to which the initial value voltage Vcl is supplied. Note that the switch SW8D, the switch SW9D, and the capacitor C6D correspond to the switch SW2D, the switch SW5D, and the capacitor C3D, respectively.

  The oscillation circuit 4a shown in FIG. 16 needs to supply the initial value voltage Vcl to the pulse generation unit, but can still generate the clock signal CLK using a small number of charge / discharge paths and comparators. And the increase in circuit scale can be suppressed.

<Embodiment 5>
In the present embodiment, a specific configuration of a bias voltage generation unit that generates a bias voltage to be supplied to current source circuits (B1 to B4, B1D, B4D, etc.) will be described.

  When the threshold voltage of the transistor MN1 provided in the reference voltage generation unit 15 varies due to the influence of characteristic variation or the like, the reference voltage Vref also varies accordingly. As a result, the timing at which the voltage Vx1 and the reference voltage Vref match and the timing at which the voltage Vy1 and the reference voltage Vref match each vary. As a result, the frequency of the oscillation signal may change unintentionally.

  Therefore, the bias voltage generation unit according to the present embodiment generates a bias voltage corresponding to the threshold voltage (reference voltage Vref) of the transistor MN1, thereby changing the output current of each current source circuit to a current corresponding to the reference voltage Vref. Adjust to the value. Thereby, the fluctuation | variation of the timing when the voltage Vx1 and the reference voltage Vref correspond, and the timing when the voltage Vy1 and the reference voltage Vref correspond are suppressed. As a result, fluctuations in the frequency of the oscillation signal are suppressed.

(First Specific Configuration Example of Bias Voltage Generation Unit)
FIG. 17 is a diagram illustrating a first specific configuration example of the bias voltage generation unit. The bias voltage generator shown in FIG. 17 includes P-channel MOS transistors (hereinafter simply referred to as transistors) MP21 and MP22, N-channel MOS transistors (hereinafter simply referred to as transistors) MN21 and MN22, and a resistance element R2. Have.

  In the transistor (ninth transistor) MP21, the source is connected to the power supply voltage terminal VDD, and the drain and gate are connected to the node N21. In the transistor (sixth transistor) MP22, the source is connected to the power supply voltage terminal VDD, the drain is connected to the node N22, and the gate is connected to the node N21. In the transistor (eighth transistor) MN21, the source is connected to the node N23, the drain is connected to the node N21, and the gate is connected to the node N22. In the transistor (seventh transistor) MN22, the source is connected to the ground voltage terminal GND, the drain is connected to the node N22, and the gate is connected to the node N23. One end of the resistor element R2 is connected to the ground voltage terminal GND, and the other end of the resistor element R2 is connected to the node N23. Then, the bias voltage generation unit shown in FIG. 17 outputs the voltage at the node N21 as the bias voltage Vbias1. The bias voltage Vbias1 is supplied to each current source circuit (B1 to B4, B1D, B4D, etc.).

  Here, the voltage level of the node N23 indicates the level of the threshold voltage Vth of the transistor MN22. Therefore, when the threshold voltage of the transistor MN22 varies due to the influence of characteristic variation or the like, the voltage level of the node N23 also varies. Accordingly, the current I flowing between the source and drain of the transistor MP21 varies. As a result, the bias voltage Vbias1 also varies.

  As described above, the bias voltage generation unit illustrated in FIG. 17 generates the bias voltage Vbias1 corresponding to the threshold voltage of the transistor MN22. Since the transistors MN22 and MN1 are assumed to vary in the same manner, it can be said that the bias voltage generation unit illustrated in FIG. 17 generates the bias voltage Vbias1 corresponding to the threshold voltage (reference voltage Vref) of the transistor MN1.

  The size ratio between the transistor MN22 and the transistor MN1 in the reference voltage generation unit 15 is preferably substantially the same as the size ratio between the transistor MP22 and the transistor MP3 constituting the constant current source circuit B3. Thereby, fluctuations in the frequency of the oscillation signal are further suppressed.

  The threshold voltage of the transistor MN21 is preferably as small as possible. Thereby, fluctuations in the frequency of the oscillation signal are further suppressed. Further, since the transistor MN21 is easily turned on, it is not necessary to provide a separate startup circuit. Thereby, an increase in power consumption and an increase in circuit scale are suppressed. As the transistor MN21, for example, a transistor whose threshold voltage is reduced by increasing the W / L ratio or a transistor of a device having a low threshold voltage is used.

(Second Specific Configuration Example of Bias Voltage Generation Unit)
FIG. 18 is a diagram illustrating a second specific configuration example of the bias voltage generation unit. The bias voltage generator shown in FIG. 18 includes P-channel MOS transistors (hereinafter simply referred to as transistors) MP21 to MP24, N-channel MOS transistors (hereinafter simply referred to as transistors) MN21 to MN26, and a resistance element R2. Have.

  The gate of transistor MP22 is connected to node N25 instead of node N21. In other words, the voltage (bias voltage) Vbias2 of the node N25 is supplied to the gate of the transistor MP22.

  In the transistor MP23, the source is connected to the power supply voltage terminal VDD, the drain is connected to the node N24, and the gate is connected to the node N21. In the transistor MN23, the source is connected to the ground voltage terminal GND, and the drain and gate are connected to the node N24. In the transistor (twelfth transistor) MP24, the source is connected to the power supply voltage terminal VDD, and the drain and gate are connected to the node N25. In the transistor (tenth transistor) MN24, the source is connected to the ground voltage terminal GND, the drain is connected to the node N25, and the gate is connected to the node N24. In the transistor (13th transistor) MN25, the source is connected to the drain of the transistor MN26, the drain is connected to the node N25, and the gate is connected to the node N24. In the transistor (eleventh transistor) MN26, the source and the gate are connected to the ground voltage terminal GND.

  The bias voltage generator shown in FIG. 18 outputs the voltage at the node N21 as the bias voltage (second bias voltage) Vbias1, and outputs the voltage at the node N25 as the bias voltage (first bias voltage) Vbias2. The bias voltage Vbias1 is supplied to a current source circuit (B1, B1D, B4, B4D, etc.) provided in the charge / discharge unit. The bias voltage Vbias2 is supplied to the current source circuit B3 provided in the reference voltage generation unit 15 and the current source circuit B2 provided in each comparator.

  For example, when the threshold voltage of the transistor MN22 decreases due to a temperature rise, the current flowing through the transistor MP21 decreases. Thereby, the bias voltage Vbias1 decreases. As the current flowing through the transistor MP21 decreases, the current flowing through the transistor MN24 also decreases. On the other hand, the leakage current flowing through the transistor MN26 increases due to the temperature rise. Here, the current flowing through the transistor MP24 is the sum of the current flowing through the transistor MN24 and the leak current flowing through the transistor MN26. Therefore, the current flowing through the transistor MP24 decreases with a reduction width smaller than the reduction width of the current flowing through the transistor MP21. Therefore, the bias voltage Vbias2 does not decrease much as compared with the case of the bias voltage Vbias1. That is, the variation range of the bias voltage Vbias2 is smaller than the variation range of the bias voltage Vbias1. As a result, fluctuations in the delay time Td caused by each comparator are suppressed, so that the frequency accuracy of the oscillation signal is improved.

  Note that the transistor MN25 has a role of limiting a leakage current flowing through the transistor MN26. Therefore, if it is not necessary to limit the leakage current flowing through the transistor MN26, the transistor MN25 may not be provided.

<Embodiment 6>
In the present embodiment, a case will be described in which a plurality of oscillation circuits according to the above embodiments share a bias voltage generation unit and a reference voltage generation unit. FIG. 19 is a diagram illustrating a configuration example of a clock generation circuit (semiconductor integrated circuit) 5 including a plurality of oscillation circuits.

  The clock generation circuit 5 illustrated in FIG. 19 includes a reference voltage generation unit 15, a bias voltage generation unit 16, and oscillation circuits 1a and 1b that share the reference voltage generation unit 15 and the bias voltage generation unit 16. The oscillation circuit 1a, the reference voltage generation unit 15, and the bias voltage generation unit 16 realize a configuration equivalent to that of the oscillation circuit 1. In addition, the oscillation circuit 1b, the reference voltage generation unit 15, and the bias voltage generation unit 16 realize a configuration equivalent to that of the oscillation circuit 1.

  The oscillation circuit 1a outputs an oscillation signal as the clock signal CLKA. The oscillation circuit 1b outputs an oscillation signal having a frequency different from that of the clock signal CLKA as the clock signal CLKB.

  As described above, the clock generation circuit 5 according to the present embodiment can suppress an increase in power consumption by sharing a bias voltage generation unit and a reference voltage generation unit by a plurality of oscillation circuits, and can be reduced in circuit scale. Can be suppressed.

  Although the case where a plurality of configurations of the oscillation circuit 1 are provided has been described in the present embodiment, the present invention is not limited to this. It is possible to appropriately change to a configuration in which a plurality of oscillation circuit configurations according to other embodiments are provided.

  In addition, when the frequency accuracy required for one clock signal is low, the bias voltage generation unit and the oscillation circuit according to any of the above embodiments and a general oscillation circuit that does not have a pulse generation unit The configuration can be appropriately changed to a configuration in which the reference voltage generation unit is shared.

<Embodiment 7>
In the present embodiment, a case will be described in which a plurality of oscillation circuits according to the above embodiments share a bias voltage generation unit. FIG. 20 is a diagram illustrating a configuration example of a clock generation circuit (semiconductor integrated circuit) 6 including a plurality of oscillation circuits.

  The clock generation circuit 6 illustrated in FIG. 20 includes reference voltage generation units 15c and 15d, a bias voltage generation unit 16, and oscillation circuits 1c and 1d that share the bias voltage generation unit 16. The oscillation circuit 1c, the reference voltage generation unit 15c, and the bias voltage generation unit 16 realize a configuration equivalent to that of the oscillation circuit 1. Further, the oscillation circuit 1d, the reference voltage generation unit 15d, and the bias voltage generation unit 16 realize a configuration equivalent to that of the oscillation circuit 1.

  The oscillation circuit 1c outputs an oscillation signal as a clock signal CLKC. The oscillation circuit 1d outputs an oscillation signal having a frequency different from that of the clock signal CLKC as the clock signal CLKD.

  As described above, the clock generation circuit 6 according to the present embodiment can suppress an increase in power consumption and a circuit scale by sharing a bias voltage generation unit among a plurality of oscillation circuits. be able to. Note that, unlike the clock generation circuit 5, the clock generation circuit 6 according to the present embodiment includes reference voltage generation units 15c and 15d for the oscillation circuits 1c and 1d, respectively. As a result, fluctuations in the reference voltage caused by noise sneaking between the oscillation circuits are suppressed.

  Although the case where a plurality of configurations of the oscillation circuit 1 are provided has been described in the present embodiment, the present invention is not limited to this. It is possible to appropriately change to a configuration in which a plurality of oscillation circuit configurations according to other embodiments are provided.

  In addition, when the frequency accuracy required for one clock signal is low, the bias voltage generation unit includes any of the oscillation circuits according to the above embodiment and a general oscillation circuit that does not have a pulse generation unit. It can be changed as appropriate to the shared configuration.

<Eighth embodiment>
FIG. 21 is a block diagram showing a PLL to which the oscillation circuit according to the above embodiment is applied. In this embodiment, the case where the oscillation circuit 1 shown in FIG. 1 is applied to a PLL will be described as an example. However, the oscillation circuit according to another embodiment may be applied.

  A PLL 70 shown in FIG. 21 includes an oscillation circuit 1, a phase comparator (PFD) 71, a charge pump 72, a loop filter 73, a voltage controlled oscillator (VCO) 74, and a frequency divider 75. The phase comparator 71 and the charge pump 72 are also referred to as a phase difference detection unit.

  The oscillation circuit 1 outputs an oscillation signal as a reference clock signal. The phase comparator 71 detects the phase difference between the reference clock signal from the oscillation circuit 1 and the divided clock signal from the frequency divider 75. The charge pump 72 generates an output voltage corresponding to the phase difference detected by the phase comparator 71. The loop filter 73 converts the output voltage of the charge pump 72 into a DC signal and outputs it as a control voltage. The voltage controlled oscillator 74 outputs a clock signal having a frequency corresponding to the control voltage. The frequency divider 75 divides the clock signal from the voltage controlled oscillator 74 and outputs it as a divided clock signal.

  As described above, the PLL 70 according to this embodiment can generate a higher-speed clock signal with high accuracy by multiplying the reference clock signal (oscillation signal) output from the oscillation circuit 1.

<Embodiment 9>
FIG. 22 is a block diagram showing a semiconductor integrated circuit (LSI) to which the oscillation circuit according to the above embodiment is applied. In this embodiment, the case where the oscillation circuit 1 shown in FIG. 1 is applied to a semiconductor integrated circuit as the clock source 1 will be described as an example. However, the oscillation circuit according to another embodiment may be applied.

  A semiconductor integrated circuit 80 shown in FIG. 22 includes a clock source 1, an internal circuit 81 including a logic circuit and a memory, and a power supply 82. The power supply 82 supplies a power supply voltage to the clock source 1 and the internal circuit 81. The clock source 1 operates when an activation signal from the outside is activated, and outputs a clock signal (oscillation signal) having a preset frequency. The internal circuit 81 operates in synchronization with the clock signal supplied from the clock source 1.

  As described above, the semiconductor integrated circuit 80 according to the present embodiment operates in synchronization with the highly accurate clock signal output from the oscillation circuit (clock source) 1, and thus can realize a stable operation. In particular, the semiconductor integrated circuit 80 according to the present embodiment can stabilize the clock signal at high speed using the oscillation circuit (clock source) 1, so that the startup time can be shortened.

  As described above, the oscillation circuit according to the embodiment includes the comparator in the pulse generation unit that performs the comparison operation in the normal operation mode and sets the voltage of the non-inverting input terminal to the reference voltage level in the initial setting mode. As a result, the oscillation circuit according to the above embodiment does not need to be provided with a level shift capacitor in front of the comparator. Therefore, it is possible to suppress an error in the oscillation frequency of each of the oscillation circuit and the pulse generation unit. An oscillation signal having a frequency can be generated with high accuracy. In addition, since the oscillation circuit according to the above embodiment does not need to repeatedly charge and discharge the nodes E1, F1, and the like by the initial value generation unit, an increase in power consumption can be suppressed. That is, the oscillation circuit according to the above embodiment can realize both improvement in oscillation frequency accuracy and reduction in power consumption.

  Furthermore, since the oscillation circuit according to the above embodiment does not need to include an initial value generation unit, an increase in circuit scale can be suppressed.

  In the above embodiment, the case where the pulse width of the control signal Vctrl (in this example, the period of the H level) is substantially the same as the delay time Td has been described as an example, but the present invention is not limited to this. The pulse width of the control signal Vctrl can be appropriately changed within a range in which the amount of change in the periods Tx and Ty due to the variation in the delay time Td is small. As a result, the oscillation circuit may operate under the influence of fluctuations in the delay time Td, but the influence can be reduced.

  In the above embodiment, an example in which twice the normal current flows in the variable current source circuit B1 when the control signal Vctrl is activated (in this example, the control signal Vctrl is at the H level) will be described. However, it is not limited to this. When the control signal Vctrl is activated, the current value of the current flowing through the variable current source circuit B1 can be appropriately changed within a range in which the amount of change in the periods Tx and Ty due to the variation in the delay time Td is small. In this case, the oscillation circuit may operate under the influence of the fluctuation of the delay time Td, but the influence can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  A part or all of the above embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A first charge charging / discharging unit that has a first capacitor and charges or discharges the first capacitor at a charging rate according to a control signal based on a first trigger signal;
A first comparator that compares a first voltage corresponding to the charge accumulated in the first capacitor and a reference voltage and outputs a first comparison result;
The timing of the change from the first logic value to the second logic value of the first comparison result indicating that the first voltage has changed from a state greater than the reference voltage to a state below the reference voltage is delayed to the first voltage. A first pulse adjustment unit that outputs as one trigger signal;
A frequency divider for generating a first output signal having a period according to the first trigger signal;
A pulse generation unit,
The pulse generator
A second charge / discharge unit that has a second capacitor and controls whether to charge the second capacitor based on the control signal;
In the first period during which the second capacitor is charged, the second voltage corresponding to the electric charge accumulated in the second capacitor is compared with the reference voltage and a second comparison result is output, and the first period is output. A second comparator that sets the voltage of the input terminal to which the second voltage has been supplied to the reference voltage level in a second period other than
An oscillation circuit comprising: a control circuit that outputs the control signal based on the second comparison result and the first trigger signal.

(Appendix 2)
The control circuit determines that the timing of the change of the first trigger signal from the first logic value to the second logic value and that the second voltage has changed from a state below the reference voltage to a state greater than the reference voltage. The oscillation circuit according to appendix 1, wherein the control signal having a pulse width determined by the timing of the change from the second logic value to the first logic value of the second comparison result is output.

(Appendix 3)
The second comparator is
First and second transistors constituting an input differential pair;
A first constant current source circuit for supplying a constant current to the input differential pair;
A third transistor provided in series with the first transistor;
A fourth transistor, which is provided in series with the second transistor and through which a current corresponding to a current flowing through the third transistor flows;
A first switch provided between the input terminal connected to the gate of the first transistor and a node between the first and third transistors;
The oscillation circuit according to appendix 1, wherein a comparison result corresponding to a difference between currents flowing through the second and fourth transistors is output from an output terminal.

(Appendix 4)
The second comparator is
A second switch provided between the second transistor and the output terminal, the ON / OFF of which is controlled complementarily to the first switch;
The oscillation circuit according to appendix 3, further comprising: a third switch provided between the output terminal and the ground voltage terminal and controlled to be turned on / off complementarily with the second switch.

(Appendix 5)
Each of the first and second comparators is
First and second transistors constituting an input differential pair;
A first constant current source circuit for supplying a constant current to the input differential pair;
A third transistor provided in series with the first transistor;
A fourth transistor, which is provided in series with the second transistor and through which a current corresponding to a current flowing through the third transistor flows;
A first switch provided between the input terminal connected to the gate of the first transistor and a node between the first and third transistors;
A comparison result corresponding to a difference in current flowing through each of the second and fourth transistors is output from an output terminal;
The oscillation circuit according to appendix 1, wherein the first switch of the first comparator is always controlled to be off.

(Appendix 6)
Each of the first and second comparators is
A second switch provided between the second transistor and the output terminal, the ON / OFF of which is controlled complementarily to the first switch;
The oscillation circuit according to appendix 5, further comprising: a third switch provided between the output terminal and the ground voltage terminal and controlled to be turned on / off complementarily with the second switch.

(Appendix 7)
The oscillation circuit according to appendix 5, wherein in each of the first and second comparators, the size of the first transistor is larger than the size of the second transistor.

(Appendix 8)
Second timing is delayed by delaying the timing of the change from the second logic value to the first logic value of the second comparison result indicating that the second voltage has changed from a state below the reference voltage to a state greater than the reference voltage. A second pulse adjustment unit that outputs as a trigger signal;
The oscillation circuit according to appendix 1, wherein the control circuit outputs the control signal based on the first and second trigger signals.

(Appendix 9)
A reference voltage generator for generating the reference voltage;
The reference voltage generator is
A second constant current source circuit having the same circuit configuration as the first constant current source circuit;
A fifth transistor connected in series with the second constant current source circuit and diode-connected with the same conductivity type as the third transistor;
The oscillation circuit according to appendix 3, wherein a voltage at a node between the second constant current source circuit and the fifth transistor is output as the reference voltage.

(Appendix 10)
Appendix 9 The size ratio of the transistors constituting the first constant current source circuit and the transistor constituting the second constant current source circuit is substantially the same as the size ratio of the third transistor and the fifth transistor. The oscillation circuit described in 1.

(Appendix 11)
A bias voltage generator for generating a bias voltage and supplying the bias voltage to each gate of a transistor constituting each of the first and second constant current source circuits;
The bias voltage generator is
A sixth transistor having the same conductivity type as the transistor constituting the second constant current source circuit, wherein the bias voltage is supplied to the gate;
A seventh transistor provided in series with the sixth transistor and having the same conductivity type as the fifth transistor;
An eighth transistor of the same conductivity type as the seventh transistor, the source and gate of which are connected to the gate and drain of the seventh transistor, respectively;
A resistance element provided between a node between the source of the eighth transistor and the gate of the seventh transistor and a ground voltage terminal;
A ninth transistor provided between the drain of the eighth transistor and a power supply voltage terminal and diode-connected with the same conductivity type as the sixth transistor;
The oscillation circuit according to appendix 9, wherein the drain voltage of the ninth transistor is output as the bias voltage.

(Appendix 12)
The size ratio of the transistor constituting the first constant current source circuit, the transistor constituting the second constant current source circuit, and the sixth transistor, the third transistor, the fifth transistor, and the seventh transistor The oscillation circuit according to appendix 11, wherein the transistor size ratio is substantially the same.

(Appendix 13)
The oscillation circuit according to appendix 11, wherein a threshold voltage of the eighth transistor is smaller than a threshold voltage of the seventh transistor.

(Appendix 14)
A bias voltage generator for generating a first bias voltage and supplying the first bias voltage to each gate of a transistor constituting each of the first and second constant current source circuits;
The bias voltage generator is
A sixth transistor having the same conductivity type as the transistor constituting the second constant current source circuit, wherein the first bias voltage is supplied to the gate;
A seventh transistor provided in series with the sixth transistor and having the same conductivity type as the fifth transistor;
An eighth transistor of the same conductivity type as the seventh transistor, the source and gate of which are connected to the gate and drain of the seventh transistor, respectively;
A resistance element provided between a node between the source of the eighth transistor and the gate of the seventh transistor and a ground voltage terminal;
A ninth transistor connected between the drain of the eighth transistor and a power supply voltage terminal and diode-connected with the same conductivity type as the sixth transistor;
A tenth transistor in which a current corresponding to a current flowing in the ninth transistor flows;
An eleventh transistor provided in parallel with the tenth transistor and supplied with a fixed potential at the gate;
A twelfth transistor provided in series with the tenth and eleventh transistors and diode-connected,
The oscillation circuit according to appendix 9, wherein the drain voltage of the twelfth transistor is output as the first bias voltage.

(Appendix 15)
The first charge charging / discharging unit includes:
A variable current source circuit that generates an output current according to the control signal;
Charging the first capacitor at a charging rate according to the output current of the variable current source circuit;
The second charge charging / discharging unit includes:
A third constant current source circuit for generating a constant current;
Charging the second capacitor at a charging rate according to a constant current of the third constant current source circuit;
The bias voltage generation unit generates the drain voltage of the ninth transistor as a second bias voltage, and supplies the second bias voltage to the gates of the transistors constituting the variable current source circuit and the third constant current source circuit, respectively. The oscillation circuit according to appendix 14.

(Appendix 16)
The bias voltage generator is
15. The oscillation circuit according to appendix 14, further comprising a thirteenth transistor having the same conductivity type as the tenth transistor, provided in series with the eleventh transistor and having a gate connected to the gate of the tenth transistor.

(Appendix 17)
The size ratio of the transistor constituting the first constant current source circuit, the transistor constituting the second constant current source circuit, and the sixth transistor, the third transistor, the fifth transistor, and the seventh transistor 15. The oscillation circuit according to appendix 14, wherein the size ratio of the transistors is substantially the same.

(Appendix 18)
15. The oscillation circuit according to appendix 14, wherein a threshold voltage of the eighth transistor is smaller than a threshold voltage of the seventh transistor.

(Appendix 19)
The oscillation circuit according to any one of appendices 1 to 18, and
A phase difference detector that detects a phase difference between the first output signal of the oscillation circuit and a feedback signal;
A loop filter that generates a control voltage according to a detection result of the phase difference detection unit;
A voltage-controlled oscillation circuit that generates a clock signal having a frequency according to the control voltage;
A frequency divider that divides the clock signal to generate the feedback signal.

(Appendix 20)
The oscillation circuit according to any one of appendices 1 to 19 that outputs the first output signal as a clock signal;
An internal circuit that operates in synchronization with the clock signal.

1 to 4 Oscillation circuits 1a to 1d, 4a Oscillation circuits 5, 6 Clock generation circuit 10, 20, 40 Pulse generation unit 11, 101 RS flip-flop 12, 42, 102, 202, 402 Charge charge / discharge unit 13, 14, 33 , 34, 43, 46 Comparator 103, 104, 303, 304, 403, 406 Comparator 15, 15c, 15d Reference voltage generator 16 Bias voltage generator 41 Divider 44, 404 Pulse width adjuster 70 Semiconductor integrated circuit 71 PFD
72 charge pump 73 loop filter 74 VCO
75 frequency divider 80 semiconductor integrated circuit 81 internal circuit 82 power supply 105, 205 SW control circuit 405 control circuit B1, B4 variable current source circuit B1D, B2, B3, B4D constant current source circuit C1, C2, C5 capacitors C1D to C6D capacitors FF1 RS flip-flop IV0 to IV7 Inverter MN1, MN11, MN12, MN21 to MN26 Transistor MP11, MP12, MP21 to MP24 Transistor ND1 to ND4 NAND circuit NR1 NAND circuit R1, R2 Resistive elements SW1 to SW4, SW7 Switch SW1D ~ SW9D switch SW11, SW12, SW13, SW31 switch

Claims (20)

A first RS flip-flop that generates a first output signal based on the first set signal and the first reset signal;
A first charge charging unit configured to charge or discharge a capacitor selected by the first output signal in a complementary manner by the first output signal at a charge rate according to a control signal. A discharge part;
A first comparator that compares a first voltage corresponding to the charge accumulated in the first capacitor with a reference voltage and outputs the first set signal;
A second comparator that compares the second voltage corresponding to the charge accumulated in the second capacitor and the reference voltage and outputs the first reset signal;
A pulse generation unit,
The pulse generator
A second RS flip-flop that generates a second output signal based on the second set signal and the second reset signal;
A control circuit for outputting a switching signal and the control signal based on the first and second output signals;
A second charge charging / discharging unit having a third and a fourth capacitor and controlling whether to charge each of the third and fourth capacitors based on the switching signal;
In a first period in which the third capacitor is charged, a third voltage corresponding to the charge accumulated in the third capacitor is compared with the reference voltage to output the second set signal, and the first set signal is output. In a second period other than the period, a third comparator that sets the voltage of the input terminal to which the third voltage was supplied to the reference voltage level;
In a third period in which the fourth capacitor is charged, a fourth voltage corresponding to the charge accumulated in the fourth capacitor is compared with the reference voltage, and the second reset signal is output, and the third capacitor is output. An oscillation circuit comprising: a fourth comparator that sets the voltage of the input terminal to which the fourth voltage has been supplied to the reference voltage level in a fourth period other than the period. Each of the third and fourth comparators is
First and second transistors constituting an input differential pair;
A first constant current source circuit for supplying a constant current to the input differential pair;
A third transistor provided in series with the first transistor;
A fourth transistor, which is provided in series with the second transistor and through which a current corresponding to a current flowing through the third transistor flows;
A first switch provided between the input terminal connected to the gate of the first transistor and a node between the first and third transistors;
The oscillation circuit according to claim 1, wherein a comparison result corresponding to a difference between currents flowing through the second and fourth transistors is output from an output terminal. Each of the third and fourth comparators is
A second switch provided between the second transistor and the output terminal, the ON / OFF of which is controlled complementarily to the first switch;
The oscillation circuit according to claim 2, further comprising: a third switch provided between the output terminal and a ground voltage terminal and controlled to be turned on / off complementarily with the second switch. Each of the first to fourth comparators is
First and second transistors constituting an input differential pair;
A first constant current source circuit for supplying a constant current to the input differential pair;
A third transistor provided in series with the first transistor;
A fourth transistor, which is provided in series with the second transistor and through which a current corresponding to a current flowing through the third transistor flows;
A first switch provided between the input terminal connected to the gate of the first transistor and a node between the first and third transistors;
A comparison result corresponding to a difference in current flowing through each of the second and fourth transistors is output from an output terminal;
The oscillation circuit according to claim 1, wherein the first switch of each of the first and second comparators is always controlled to be off. Each of the first to fourth comparators is
A second switch provided between the second transistor and the output terminal, the ON / OFF of which is controlled complementarily to the first switch;
5. The oscillation circuit according to claim 4, further comprising: a third switch provided between the output terminal and the ground voltage terminal and controlled to be turned on / off complementarily with the second switch. Each of the first to fourth comparators is
A fourth switch for controlling whether or not to supply a constant current of the first constant current source circuit to the input differential pair;
ON / OFF of the fourth switch of each of the first and second comparators is complementarily controlled based on the first output signal,
The oscillation circuit according to claim 4, wherein the fourth switch of each of the third and fourth comparators is always controlled to be on.   5. The oscillation circuit according to claim 4, wherein in each of the first to fourth comparators, a size of the first transistor is larger than a size of the second transistor. A reference voltage generator for generating the reference voltage;
The reference voltage generator is
A second constant current source circuit having the same circuit configuration as the first constant current source circuit;
A fifth transistor connected in series with the second constant current source circuit and diode-connected with the same conductivity type as the third transistor;
The oscillation circuit according to claim 2, wherein a voltage at a node between the second constant current source circuit and the fifth transistor is output as the reference voltage.   The size ratio of the transistors constituting the first constant current source circuit and the transistor constituting the second constant current source circuit is substantially the same as the size ratio of the third transistor and the fifth transistor. 9. The oscillation circuit according to 8. A bias voltage generator for generating a bias voltage and supplying the bias voltage to each gate of a transistor constituting each of the first and second constant current source circuits;
The bias voltage generator is
A sixth transistor having the same conductivity type as the transistor constituting the second constant current source circuit, wherein the bias voltage is supplied to the gate;
A seventh transistor provided in series with the sixth transistor and having the same conductivity type as the fifth transistor;
An eighth transistor of the same conductivity type as the seventh transistor, the source and gate of which are connected to the gate and drain of the seventh transistor, respectively;
A resistance element provided between a node between the source of the eighth transistor and the gate of the seventh transistor and a ground voltage terminal;
A ninth transistor provided between the drain of the eighth transistor and a power supply voltage terminal and diode-connected with the same conductivity type as the sixth transistor;
The oscillation circuit according to claim 8, wherein the drain voltage of the ninth transistor is output as the bias voltage.   The size ratio of the transistor constituting the first constant current source circuit, the transistor constituting the second constant current source circuit, and the sixth transistor, the third transistor, the fifth transistor, and the seventh transistor The oscillation circuit according to claim 10, wherein the size ratio of the transistors is substantially the same.   The oscillation circuit according to claim 10, wherein a threshold voltage of the eighth transistor is smaller than a threshold voltage of the seventh transistor. A bias voltage generator for generating a first bias voltage and supplying the first bias voltage to each gate of a transistor constituting each of the first and second constant current source circuits;
The bias voltage generator is
A sixth transistor having the same conductivity type as the transistor constituting the second constant current source circuit, wherein the first bias voltage is supplied to the gate;
A seventh transistor provided in series with the sixth transistor and having the same conductivity type as the fifth transistor;
An eighth transistor of the same conductivity type as the seventh transistor, the source and gate of which are connected to the gate and drain of the seventh transistor, respectively;
A resistance element provided between a node between the source of the eighth transistor and the gate of the seventh transistor and a ground voltage terminal;
A ninth transistor connected between the drain of the eighth transistor and a power supply voltage terminal and diode-connected with the same conductivity type as the sixth transistor;
A tenth transistor in which a current corresponding to a current flowing in the ninth transistor flows;
An eleventh transistor provided in parallel with the tenth transistor and supplied with a fixed potential at the gate;
A twelfth transistor provided in series with the tenth and eleventh transistors and diode-connected,
The oscillation circuit according to claim 8, wherein the drain voltage of the twelfth transistor is output as the first bias voltage. The first charge charging / discharging unit includes:
A variable current source circuit that generates an output current according to the control signal;
Charging the first and second capacitors at a charge rate according to the output current of the variable current source circuit;
The second charge charging / discharging unit includes:
A third constant current source circuit for generating a constant current;
Charging the third and fourth capacitors at a charge rate according to a constant current of the third constant current source circuit;
The bias voltage generation unit generates the drain voltage of the ninth transistor as a second bias voltage, and supplies the second bias voltage to the gates of the transistors constituting the variable current source circuit and the third constant current source circuit, respectively. The oscillation circuit according to claim 13. The bias voltage generator is
The oscillation circuit according to claim 13, further comprising a thirteenth transistor having the same conductivity type as the tenth transistor, provided in series with the eleventh transistor and having a gate connected to a gate of the tenth transistor.   The size ratio of the transistor constituting the first constant current source circuit, the transistor constituting the second constant current source circuit, and the sixth transistor, the third transistor, the fifth transistor, and the seventh transistor The oscillation circuit according to claim 13, wherein the size ratio of the transistors is substantially the same.   The oscillation circuit according to claim 13, wherein a threshold voltage of the eighth transistor is smaller than a threshold voltage of the seventh transistor. A first charge charging / discharging unit that has a first capacitor and charges or discharges the first capacitor at a charging rate according to a control signal based on a first trigger signal;
A first comparator that compares a first voltage corresponding to the charge accumulated in the first capacitor and a reference voltage and outputs a first comparison result;
The timing of the change from the first logic value to the second logic value of the first comparison result indicating that the first voltage has changed from a state greater than the reference voltage to a state below the reference voltage is delayed to the first voltage. A first pulse adjustment unit that outputs as one trigger signal;
A frequency divider for generating a first output signal having a period according to the first trigger signal;
A pulse generation unit,
The pulse generator
A second charge / discharge unit that has a second capacitor and controls whether to charge the second capacitor based on the control signal;
In the first period during which the second capacitor is charged, the second voltage corresponding to the electric charge accumulated in the second capacitor is compared with the reference voltage and a second comparison result is output, and the first period is output. A second comparator that sets the voltage of the input terminal to which the second voltage has been supplied to the reference voltage level in a second period other than
An oscillation circuit comprising: a control circuit that outputs the control signal based on the second comparison result and the first trigger signal. The oscillation circuit according to any one of claims 1 to 18,
A phase difference detector that detects a phase difference between the first output signal of the oscillation circuit and a feedback signal;
A loop filter that generates a control voltage according to a detection result of the phase difference detection unit;
A voltage-controlled oscillation circuit that generates a clock signal having a frequency according to the control voltage;
A frequency divider that divides the clock signal to generate the feedback signal. The oscillation circuit according to any one of claims 1 to 19, which outputs the first output signal as a clock signal;
An internal circuit that operates in synchronization with the clock signal.

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